SAR ADC circuit facing temperature sensor

Abstract

The invention discloses an SAR ADC circuit facing a temperature sensor. The circuit comprises a CDAC array, a comparator, an SAR logic module and a temperature mode switching circuit. The front temperature sensor utilizes the temperature characteristic of base-emitter voltage of a triode to generate double-end voltage of which the voltage difference linearly changes along with the temperature. According to the invention, through an SARADC structure, the inherent offset voltage of a temperature-sensing pre-stage circuit is compensated firstly, then the difference value of the double-end voltage which is generated by a front temperature sensor and changes along with the temperature is converted into an 8-bit binary digital signal, and the quantized digital signal represents a temperature signal. According to the invention, by switching the reference voltage module of the ADC, the temperature range of ADC quantization is changed. According to the invention, when the temperature changes by 1 DEG C, the difference value of the output voltages at the two ends of the temperature sensor changes by 0.0039 V; and one LSB value of the SARADC is also 0.0039 V, that is, the change of a unit output digital signal of the SARADC corresponds to the temperature change of 1 DEG C, so that the efficiency of quantifying the temperature is effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital converters, and more specifically, to a SARADC circuit for a temperature sensor. Background Art

[0002] Analog-to-Digital Converter (ADC) is an electronic device that converts analog signals into digital signals. This conversion is essential for modern electronic systems because digital electronic devices (such as computers, smartphones, and digital signal processors) can only process digital signals. Analog-to-digital conversion technology continues to advance with the development of electronic technology. Early ADCs had slow conversion speeds and low precision. With the development of semiconductor technology, modern ADCs can perform conversions very quickly and accurately. The classification and advantages and disadvantages of ADCs are as follows: successive approximation register (SAR), integral type, voltage-frequency conversion type, etc., which are mainly used in medium-speed or low-speed, medium-precision data acquisition and intelligent instruments. Hierarchical and pipeline ADCs are mainly used in transient signal processing, fast waveform storage and recording, high-speed data acquisition, video signal quantization, and high-speed digital communication technology under high-speed conditions.

[0003] As one of the most important physical quantities in daily life, temperature is closely related to human production and life, and accurate temperature measurement is also of great significance. Uneven temperature distribution in the chip may lead to abnormalities in the overall chip, so it is necessary to place a temperature sensor in the chip to monitor the temperature. The ADC is responsible for processing the analog voltage signal generated by the temperature sensor that changes with temperature. Since various types of temperature sensors are different and the signals generated are also different, the existing ADC cannot meet the application requirements of the output voltage for temperature sensors. In addition, the operating range of most chips is -40℃ to 125℃. How to leave enough margin in the design so that even if the temperature deviates from this range, a relatively accurate temperature value can still be read through the ADC is also a problem that needs to be solved by the ADC for temperature sensors. Summary of the invention

[0004] The purpose of the present invention is to design a SARADC circuit for a temperature sensor, which can process and quantize a temperature-related two-terminal signal generated by the temperature sensor, thereby outputting a temperature value in a larger temperature range more accurately and better meeting the needs of practical applications.

[0005] The present invention provides a SARADC circuit for a temperature sensor, comprising: 1. A SARADC circuit for a temperature sensor, characterized in that it comprises:

[0006] A CDAC array, for receiving a differential input signal from a temperature sensor, including 8-bit capacitance values, wherein the capacitance values ​​are configured based on binary weights, and are capacitances of C0, C0, 2C0, 4C0, 8C0, 16C0, 32C0, and 64C0, respectively; wherein each bit of capacitance corresponds to a CDAC unit module; wherein C0 is a unit capacitance;

[0007] a comparator, including a preamplifier and a latch, for comparing the voltage signal from the CDAC array and outputting a comparison result;

[0008] A SAR logic module, used to control the CDAC array and the comparator to perform a successive approximation process to generate a digital output representing the temperature; the SAR logic module includes: a sampling signal generation module, a timing generation module, and a result transmission module;

[0009] The temperature mode switching circuit is used to select different working modes based on the output signal of the temperature sensor, wherein the different working modes are used to adapt to different temperature ranges.

[0010] As an optional implementation, the CDAC array is two groups of identical 8-bit capacitor arrays, respectively connected to two ends of the comparator;

[0011] Each bit capacitor of the CDAC array is set to an initial state by presetting a voltage during the conversion phase, so as to reduce the number of successive approximation comparison steps and the required number of capacitors;

[0012] Wherein, applying a preset voltage to the highest bit capacitor is equivalent to presetting the highest bit to 1, and applying preset voltages to the remaining bits of capacitors in sequence until the lowest bit;

[0013] When comparing the lowest bit, a portion of the preset voltage is applied to the corresponding capacitor.

[0014] As an optional implementation manner, the SAR logic module is further used for:

[0015] Generate the clock signal and control signal required by the circuit to control the operation of the CDAC array during sampling and conversion;

[0016] Perform an initial comparison to determine the value of the most significant bit;

[0017] Based on the output result of the comparator, the switching of the reference voltage is controlled, and the comparison and assignment of the remaining bits are performed in sequence.

[0018] As an optional implementation, the timing generation module includes:

[0019] A plurality of D flip-flops connected in sequence, each D flip-flop having a data input terminal, a clock input terminal, a data output terminal, a reverse output terminal and a reset terminal;

[0020] The reset terminal is connected to the reverse signal of the sampling control signal. When the reverse signal is at a low level, the D flip-flop is reset and no data transmission is performed; when the reverse signal is at a high level, the D flip-flop works normally.

[0021] Under normal working conditions, the rising edge of the clock signal triggers each D flip-flop in turn, so that:

[0022] The first D flip-flop transmits a high level to the first control signal output terminal at the first rising edge of the clock signal and maintains a high level state;

[0023] At each subsequent clock rising edge, the subsequent D flip-flop sequentially transfers the high level of the previous control signal output terminal to the next control signal output terminal until all control signal output terminals are at high level until the next reset signal arrives;

[0024] Through the above steps, the timing generation module generates control signals that are triggered in sequence, which are used for comparison and assignment of each bit in the successive approximation process.

[0025] As an optional implementation, the result transmission module includes:

[0026] A plurality of independent D flip-flops, each of which has a data input terminal, a clock input terminal, a data output terminal, a reverse output terminal and a reset terminal;

[0027] The reset terminal is connected to the reverse signal of the sampling control signal. When the reverse signal is at a low level, the D flip-flop is reset and no data transmission is performed; when the reverse signal is at a high level, the D flip-flop works normally.

[0028] During the period when the reverse signal is at a high level, the clock signal generated in the successive approximation process is connected to the clock input terminal of each D flip-flop in sequence, so that:

[0029] As the rising edges of the clock signal arrive in sequence, the data signal input end of the D flip-flop reads the output signal of the comparator in sequence to realize the transmission and storage of the SARADC result.

[0030] As an optional implementation, it is characterized in that the temperature mode switching circuit includes: two modules for generating different reference voltages, wherein each module for generating a reference voltage includes:

[0031] Enable signal input terminal, used to control the working state of the module;

[0032] When the enable signal is at the first level, the module works normally and generates a corresponding reference voltage; when the enable signal is at the second level, the module stops working;

[0033] An operational amplifier, used for clamping the voltage at the positive input terminal to a preset reference voltage;

[0034] The control switch is used to control the enabling of two reference voltage generating modules based on the mode selection signal to provide different reference voltages to adapt to different temperature measurement ranges.

[0035] As an optional implementation, the temperature mode switching switch includes:

[0036] A comparator, whose non-inverting input terminal is connected to a preset reference voltage, whose inverting input terminal is connected to the output signal of the temperature sensor, and has an enable terminal. When the enable signal is at a first level, the comparator works normally; when the enable signal is at a second level, the comparator stops working;

[0037] The D flip-flop has a set terminal connected to a fixed level and is always in normal working state, and a clock input terminal connected to a clock signal generated by a logic circuit;

[0038] When the output signal of the temperature sensor is higher than the preset reference voltage, the comparator outputs a first logic level, and the D flip-flop transmits the logic level as a mode selection signal at the rising edge of the clock signal to control the temperature mode to the first mode; when the output signal is lower than the reference voltage, the comparator outputs a second logic level to control the temperature mode to the second mode.

[0039] As an optional implementation, in both temperature modes, the common mode voltage is kept constant to provide a stable operating point;

[0040] The difference in the initial reference voltage is adjusted based on the selected temperature mode to offset the inherent offset voltage of the temperature sensor and to preset the voltage of the highest-order capacitor.

[0041] As an optional implementation, it also includes:

[0042] In the second temperature mode, the difference in the initial reference voltage is reduced by a predetermined voltage value relative to the first temperature mode, corresponding to a specific temperature range;

[0043] When the capacitor modules are respectively connected to the adjusted reference voltage, it is equivalent to applying additional voltage compensation on the capacitors, so as to expand the range of temperature measurement.

[0044] As an optional implementation, in the successive approximation process, when determining the value of each bit capacitance, the preset voltage of the current bit is directly eliminated by adjusting the reference voltage to replace the initial reference voltage, and the value is assigned based on the result of the comparator.

[0045] Compared with the prior art, the beneficial effects of the present invention include:

[0046] First, the present invention designs a temperature mode switching circuit, and the voltage difference between the two modes is 0.25V; the voltage size of 0.25V corresponds to 64°C, that is, in mode 1, -42°C corresponds to the 8-bit digital signal 00000000, and in mode 2, -106°C corresponds to the 8-bit digital signal 00000000, and the temperature mode switching circuit contains a switch, when the temperature is less than 60°C, mode 2 is adopted, and when the temperature is greater than 60°C, mode 1 is adopted; the mode switching operation broadens the temperature range of the chip operation.

[0047] Second, the traditional 8-bit SAR ADC design generally contains 9-bit capacitors, that is, 256 unit capacitors are required on one side, the first 8 bits are used for comparison and feedback reset respectively, and the lowest bit only serves to provide voltage; while the 8-bit SAR ADC module designed by the present invention adopts a preset method and only uses 128 unit capacitors, saving half the area of ​​the capacitor array and achieving the same effect.

[0048] In summary, the present invention can effectively complete temperature detection in a wider temperature range, and compared with the traditional SAR ADC structure, the area is greatly reduced, and has good practical application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A SARADC circuit structure diagram for a temperature sensor provided in an embodiment of the present disclosure;

[0050] Figure 2 A CDAC array circuit diagram provided by an embodiment of the present disclosure;

[0051] Figure 3 A circuit diagram and simulation results of a timing generation module provided by an embodiment of the present disclosure;

[0052] Figure 4 A circuit diagram of a result output module provided by an embodiment of the present disclosure;

[0053] Figure 5 A circuit diagram of a module for generating different reference voltages provided by an embodiment of the present disclosure;

[0054] Figure 6 A temperature mode switching switch circuit diagram provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part rather than all of the embodiments of the present disclosure. Components of the embodiments of the present disclosure described and illustrated herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure is not intended to limit the scope of the present disclosure claimed, but merely represents selected embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0056] The present invention discloses a SAR ADC circuit for a temperature sensor. Please refer to Figure 1 , Figure 1 which is a structural diagram of a SAR ADC circuit for a temperature sensor provided by an embodiment of the present disclosure.

[0057] Among them, cdac is a CDAC array;

[0058] SAR_comp is a comparator in the entire SAR ADC circuit, responsible for comparing the input signal during the successive approximation process. SAR_comp includes a preamplifier and a latch to achieve high-precision and high-speed comparison functions. Among them, compp receives the voltage signal from the positive end of the CDAC array (i.e., the signal after the positive output of the temperature sensor is processed by the CDAC), and compn receives the voltage signal from the negative end of the CDAC array (i.e., the signal after the negative output of the temperature sensor is processed by the CDAC); abc_en is a control signal used to enable or disable the target module; the vcm port in the comparator is used to receive the common-mode voltage signal, provide a reference voltage for the differential input signal, and guide the signals at the comparator input terminals compp and compn to a stable operating point. By comparing the differential input signal with respect to vcm, the common-mode noise of the input signal can be effectively reduced, and the symmetry of the input signal can be maintained.

[0059] In a specific implementation, when compp > compn, the output comp_out is high, and when compp < compn, the output comp_out is low;

[0060] SAR_logic is a SAR logic module, including a sampling signal generation module, a timing generation module, and a result transmission module, responsible for generating the clock signals required for the entire circuit;

[0061] Among them, the sampling signal generation module is used to generate a control signal to control the sampling of the CDAC array. When the sampling signal is at a high level, the CDAC array samples the differential input signal; when the sampling signal is at a low level, the sampling ends and the capacitor maintains the sampled voltage. Timing generation module: The timing generation module generates a timing signal for successive approximation logic control based on the input clock signal. The clock signal controls the timing of the output result of each comparator to ensure that the comparison results of the successive approximation are transmitted on time. Result transmission module: The result transmission module receives the digital signal output by the comparator and sequentially transmits the 8-bit successive approximation result to the D flip-flop for storage. After the successive approximation is completed, the 8-bit digital signal is output through the dout<7:0> port to represent the measurement result of the temperature sensor.

[0062] Among them, d<7:0> (input data port): used to receive the comparison result signal output by the comparator during the successive approximation process. This port receives one comparison result at a time, and finally forms an 8-bit digital signal, which represents the quantized temperature value of the temperature sensor. set<7:0> (control signal port): the signal that controls the successive approximation logic, assigns and compares each bit in turn, ensures the step-by-step processing from the highest bit to the lowest bit, and finally determines the 8-bit digital signal. dout<7:0> (output data port): after the successive approximation is completed, the final 8-bit digital signal is output through this port, representing the quantized output result of the temperature sensor. sample (sampling control signal port): used to control the sampling process. When sample is high, the CDAC array samples the input signal; when sample is low, the sampling ends and enters the comparison stage of the successive approximation. clk (clock signal port): used to control the timing of the successive approximation process. Whenever the rising edge of the clock signal arrives, the SAR_logic module controls the comparator to perform bit-level comparison and determine the value of the digital signal bit by bit.

[0063] Vref_gen_adc_choice is a temperature mode switching circuit, which is used to generate and switch different reference voltages in the SARADC circuit of the present invention. This module ensures that the SARADC performs accurate temperature signal quantization in different temperature ranges by providing different reference voltages. The design of this module expands the range of temperature measurement and improves measurement accuracy through mode switching.

[0064] gen_choice is a temperature mode switching switch. By comparing inn with the 1.8V reference voltage, it outputs a Vref_sel signal to the temperature mode switching circuit, and switches between the two temperature modes according to the high and low levels of the Vref_sel signal.

[0065] See also Figure 2 , Figure 2 A CDAC array circuit diagram provided in an embodiment of the present disclosure.

[0066] The specific structure of the CDAC array at the inn end of the receiving signal is as follows Figure 2 As shown, the CDAC array structure of the receiving signal inp end is Figure 2 The same, the difference is that all the connected inverting terminal signals are switched to the non-inverting terminal; taking C0 as the unit capacitor, the 8-bit capacitance values ​​of C0~C7 are C0, C0, 2C0, 4C0, 8C0, 16C0, 32C0, 64C0, and the upper and lower plates of C0~C6 capacitors are the same as C7; the full scale voltage of the capacitor array is 1V, so when the corresponding digital signal is set to 1, the corresponding voltage values ​​of C7~C0 are 0.5V, 0.25V, 0.125V, 0.0625V, 0.03125V, 0.015625V, 0.0078125V, 0.0078125V, and each bit of capacitor corresponds to a CDAC unit module; when the sampling control signal sample is high, the upper plate of the capacitor is connected to the input signal V in , the lower plate is connected to the common mode signal V CM ; When the sampling control signal is converted to low, the lower plate floats, the charge is conserved, and the upper plate is connected to V CMN , at this time the lower plate potential is V CM -V in +V CMN ; When the voltage difference between the two terminals of the front temperature sensor is 1V, the corresponding temperature is -42℃. For every 1℃ change, the voltage changes by 0.0039V; V CMP 2.5V+0.5V+0.25V, V CMN 2.5V-0.5V-0.25V, V CMP -V CMN 1V in the difference can offset the difference in the temperature sensor output voltage at -42℃. In addition, 0.5V can be equivalent to presetting the highest capacitor to high. At this time, if the comparator output is high, that is, V CM -V ip +V CMP >V CM -V in +V CMN , then transfer V CMP V refph , transfer V CMN V refnl ; If the comparator output is low, V CM -V ip +V CMP <V CM -V in +V CMN , then transfer V CMP V refpl , transfer V CMN Vrefnh ;

[0067] After the above operation is completed, it is equivalent to the highest bit being set to 1 or 0, that is, at this moment, only the last seven capacitors have a preset value of 0.5V, which is equivalent to setting the second capacitor to 1; then the remaining seven capacitors are compared and assigned values ​​in turn; in addition, after the seventh bit is assigned, the preset voltage of 0.5V is only added to the last capacitor, which is equivalent to presetting half of the voltage value of the last bit, that is, 0.0039V, thereby completing the comparison and assignment of the eighth bit, and then accurately reaching the voltage accuracy of 1°C;

[0068] Thus, compared with the traditional 8-bit SAR ADC, the present invention adopts a preset mode, so that only 128 unit capacitors are needed for a single end, thus saving the area of ​​the capacitor array.

[0069] See also Figure 3 , Figure 3 A timing generation module circuit diagram and simulation results provided by an embodiment of the present disclosure;

[0070] As an optional implementation, the timing generation module may include 8 identical D flip-flops, wherein the d terminal is a signal input terminal, the clk terminal is a clock input terminal, the q terminal is a data output terminal, the qn terminal is logically opposite to the q terminal, and the nr terminal is a reset terminal of the D flip-flop;

[0071] Combination Figure 3 From the simulation results of the clock signal in the figure, we can see that the sampleb signal is the reverse of the sample signal. The sampleb signal is connected to the nr terminal. When the sampleb signal is low, the D flip-flop is reset and does not play a role in data transmission. When the sampleb signal is high, the D flip-flop can work normally. In the interval where the sampleb signal is high, when the clock clk_sar signal rises, the first D flip-flop transmits the power supply voltage avdd to the set <7> , so that after this moment, set <7> Keep it high; when the next clock rising edge arrives, the second D flip-flop will set <7> The high voltage is transmitted to the set <6> Until it is passed to set <0> , set<7:0> are all high until the next reset signal arrives; the logical result of generating the clock signal is as follows Figure 3 shown.

[0072] See also Figure 4 , Figure 4A circuit diagram of a result transmission module provided by an embodiment of the present disclosure; as an optional implementation, the result transmission module includes eight identical and independent D flip-flops, wherein the d terminal is a signal input terminal, the clk terminal is a clock input terminal, the q terminal is a data output terminal, the qn terminal is logically opposite to the q terminal, and the nr terminal is a reset terminal of the D flip-flop; the sampleb signal is the reverse of the sample signal, and the sampleb signal is connected to the nr terminal. When the sampleb signal is low, the D flip-flop is reset and does not play a role in data transmission. When the sampleb signal is high, the D flip-flop can work normally; in the interval where the sampleb signal is high, Figure 3 It is known that set<7:0> is eight clock signals whose rising edges arrive in sequence. Set<7:0> is connected to the clock signal terminals of eight D flip-flops respectively. Therefore, as the rising edges of the clocks of set<7:0> arrive in sequence, d<7:0> also reads out the output signals of the comparators at the rising edges of the clocks in sequence, thereby realizing the transmission of SARADC results.

[0073] See also Figure 5 , Figure 5 A circuit diagram of a module for generating different reference voltages provided in an embodiment of the present disclosure; the temperature mode switching circuit in the present disclosure includes two modules for generating different reference voltages and a control switch; as an optional implementation, one of the modules for generating different reference voltages is as follows Figure 5 As shown, the en signal can control whether this module generates a reference voltage. If the en signal is high, the Q2 tube is cut off and the circuit works normally. If the en signal is low, the Q2 tube is turned on, the gates of the Q1 and Q3 tubes are raised to vdd, the Q1 and Q3 tubes are cut off, and the circuit does not work. When the en signal is high, the operational amplifier Vref_op clamps the voltage at the positive input terminal to the reference voltage 1.2V. At this time, the current flowing through R1 and R2 is determined by the resistance value of R2. Q1 and Q3 have the same width and length, forming a current mirror, and copying the current to the Q3 branch. The resistors have a size relationship of R1+R2=R3+R4+R5+R6+R7+R8+R9+R10, and the voltage division value is proportional to the resistance value. By designing the resistance values ​​of R3~R10, the desired voltages vrefph, vcmp, vrefpl, vcm, vrefnh, Vref_1p8, vcmn, and vrefnl can be obtained more accurately.

[0074] In addition, the difference between the two modules for generating reference voltages in different temperature ranges is that the vrefph, vcmp, vrefpl, vrefnh, vcmn, and vrefnl they generate are different, which is reflected in the circuit as different resistance values ​​of R3 to R10.

[0075] See also Figure 6 , Figure 6A temperature mode switching switch circuit diagram provided by an embodiment of the present disclosure; as an optional implementation, the control switch of the temperature mode switching circuit can be composed of a comparator and a D flip-flop; the en terminal is connected to the en_temp signal, which is the enable terminal of the comparator. When the en_temp signal is low, the comparator does not work, and when the en_temp signal is high, the comparator works normally; the in-phase terminal of the comparator is connected to the Vref_1p8 signal, that is, the reference voltage of 1.8V, and the inverting terminal of the comparator is connected to the inn signal generated by the temperature sensor; the set terminal of the D flip-flop is always vdd, and the D flip-flop works normally all the time; the clk_temp signal is the clock signal generated by the logic in the circuit, which will be After the output of the temperature sensor stabilizes, a rising edge is generated. When the rising edge of the clk_temp signal arrives, the result of the comparator is transmitted to Vref_sel; inn is related to temperature. The higher the temperature, the lower the inn signal value. According to the properties of the front temperature sensor, when the temperature is lower than 60℃, the inn signal is greater than 1.8V, and when the temperature is higher than 60℃, the inn signal is less than 1.8V; when the inn signal is greater than 1.8V, the comparator generates a logic low, which is transmitted to the Vref_sel signal, thereby controlling the temperature mode to mode 1; when the inn signal is less than 1.8V, the comparator generates a logic high, which is transmitted to the Vref_sel signal, thereby controlling the temperature mode to mode 2.

[0076] In both modes, V CM Constant at 2.5V, providing a stable static operating point; in mode 1, V CMP -V CMN is 1.5V, so the capacitor module is connected to V CMP and V CMN When the temperature sensing circuit is set to 1V, the offset voltage inherent in the pre-stage circuit can be offset, and the highest level capacitance can be preset to 1. The V CMP -V CMN is 1.25V, Mode 2 is higher than Mode 1 V CMP -V CMN The voltage is reduced by 0.25V. The voltage of 0.25V corresponds to 64℃. In mode 2, the capacitor module is connected to V CMP and V CMN When the temperature sensor is set to 0,420℃, the offset voltage of 1V inherent in the temperature sensing pre-stage circuit is offset and the highest level capacitance is preset to 1. It is equivalent to connecting a voltage of -0.25V to the upper plate of the single-ended 8-bit capacitor, and the 0.25V voltage can quantify a temperature range of 64℃. That is, in mode 1, -42℃ corresponds to 00000000 of the 8-bit digital signal, while in mode 2, -106℃ corresponds to 00000000 of the 8-bit digital signal, which broadens the operating temperature range of the chip.

[0077] In both modes, V refph VCMP High 0.25V, V refpl V CMP 0.25V low, V refnh V CMN High 0.25V, V refnl V CMN 0.25V lower, when the timing reaches the point where a certain level of capacitance is judged to be set to 1 or 0, V refph or V refpl Replace V CMP 、V refnh or V refnl Replace V CMN , the preset voltage of the current level can be directly cancelled and the current level can be assigned according to the comparator result; the temperature mode switching circuit contains a switch, when the temperature is less than 60°C, mode 2 is used, and when the temperature is greater than 60°C, mode 1 is used. That is, the temperature mode used in different temperature ranges is controlled by the above method, thereby greatly expanding the temperature range that SARADC can detect, which has good practical application value.

[0078] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A SARADC circuit for a temperature sensor, characterized in that: include: A CDAC array, for receiving a differential input signal from a temperature sensor, including 8-bit capacitance values, wherein the capacitance values ​​are configured based on binary weights, and are capacitances of C0, C0, 2C0, 4C0, 8C0, 16C0, 32C0, and 64C0, respectively; wherein each bit of capacitance corresponds to a CDAC unit module; wherein C0 is a unit capacitance; a comparator, including a preamplifier and a latch, for comparing the voltage signal from the CDAC array and outputting a comparison result; A SAR logic module, used to control the CDAC array and the comparator to perform a successive approximation process to generate a digital output representing the temperature; the SAR logic module includes: a sampling signal generation module, a timing generation module, and a result transmission module; The temperature mode switching circuit is used to select different working modes based on the output signal of the temperature sensor, wherein the different working modes are used to adapt to different temperature ranges.

2. The SARADC circuit for temperature sensor according to claim 1, characterized in that: The CDAC arrays are two groups of identical 8-bit capacitor arrays, respectively connected to the two ends of the comparator; Each bit capacitor of the CDAC array is set to an initial state by presetting a voltage during the conversion phase, so as to reduce the number of successive approximation comparison steps and the required number of capacitors; Wherein, applying a preset voltage to the highest bit capacitor is equivalent to presetting the highest bit to 1, and applying preset voltages to the remaining bits of capacitors in sequence until the lowest bit; When comparing the lowest bit, a portion of the preset voltage is applied to the corresponding capacitor.

3. The SARADC circuit for temperature sensor according to claim 1, characterized in that: The SAR logic module is also used for: Generate the clock signal and control signal required by the circuit to control the operation of the CDAC array during sampling and conversion; Perform an initial comparison to determine the value of the most significant bit; Based on the output result of the comparator, the switching of the reference voltage is controlled, and the comparison and assignment of the remaining bits are performed in sequence.

4. The SARADC circuit for temperature sensor according to claim 1, characterized in that: The timing generation module comprises: A plurality of D flip-flops connected in sequence, each D flip-flop having a data input terminal, a clock input terminal, a data output terminal, a reverse output terminal and a reset terminal; The reset terminal is connected to the reverse signal of the sampling control signal. When the reverse signal is at a low level, the D flip-flop is reset and no data transmission is performed; when the reverse signal is at a high level, the D flip-flop works normally. Under normal working conditions, the rising edge of the clock signal triggers each D flip-flop in turn, so that: The first D flip-flop transmits a high level to the first control signal output terminal at the first rising edge of the clock signal and maintains a high level state; At each subsequent clock rising edge, the subsequent D flip-flop sequentially transfers the high level of the previous control signal output terminal to the next control signal output terminal until all control signal output terminals are at high level until the next reset signal arrives; Through the above steps, the timing generation module generates control signals that are triggered in sequence, which are used for comparison and assignment of each bit in the successive approximation process.

5. The SARADC circuit for temperature sensor according to claim 1, characterized in that: The result transmission module includes: A plurality of independent D flip-flops, each of which has a data input terminal, a clock input terminal, a data output terminal, a reverse output terminal and a reset terminal; The reset terminal is connected to the reverse signal of the sampling control signal. When the reverse signal is at a low level, the D flip-flop is reset and no data transmission is performed; when the reverse signal is at a high level, the D flip-flop works normally. During the period when the reverse signal is at a high level, the clock signal generated in the successive approximation process is connected to the clock input terminal of each D flip-flop in sequence, so that: As the rising edges of the clock signal arrive in sequence, the data signal input end of the D flip-flop reads the output signal of the comparator in sequence to realize the transmission and storage of the SARADC result.

6. The SARADC circuit for temperature sensor according to any one of claims 1 to 5, characterized in that: The temperature mode switching circuit includes: two modules for generating different reference voltages, wherein each module for generating a reference voltage includes: Enable signal input terminal, used to control the working state of the module; When the enable signal is at the first level, the module works normally and generates a corresponding reference voltage; when the enable signal is at the second level, the module stops working; An operational amplifier, used for clamping the voltage at the positive input terminal to a preset reference voltage; The control switch is used to control the enabling of two reference voltage generating modules based on the mode selection signal to provide different reference voltages to adapt to different temperature measurement ranges.

7. The SARADC circuit for temperature sensor according to claim 6, characterized in that: The temperature mode switching switch comprises: A comparator, whose non-inverting input terminal is connected to a preset reference voltage, whose inverting input terminal is connected to the output signal of the temperature sensor, and has an enable terminal. When the enable signal is at a first level, the comparator works normally; when the enable signal is at a second level, the comparator stops working; The D flip-flop has a set terminal connected to a fixed level and is always in normal working state, and a clock input terminal connected to a clock signal generated by a logic circuit; When the output signal of the temperature sensor is higher than the preset reference voltage, the comparator outputs a first logic level, and the D flip-flop transmits the logic level as a mode selection signal at the rising edge of the clock signal to control the temperature mode to the first mode; when the output signal is lower than the reference voltage, the comparator outputs a second logic level to control the temperature mode to the second mode.

8. The SARADC circuit for temperature sensor according to claim 7, characterized in that: In both temperature modes, the common-mode voltage remains constant to provide a stable operating point; The difference in the initial reference voltage is adjusted based on the selected temperature mode to offset the inherent offset voltage of the temperature sensor and to preset the voltage of the highest-order capacitor.

9. The SARADC circuit for temperature sensor according to claim 8, characterized in that: Also includes: In the second temperature mode, the difference in the initial reference voltage is reduced by a predetermined voltage value relative to the first temperature mode, corresponding to a specific temperature range; When the capacitor modules are respectively connected to the adjusted reference voltage, it is equivalent to applying additional voltage compensation on the capacitors, so as to expand the range of temperature measurement.

10. The SARADC circuit for temperature sensor according to claim 9, characterized in that: In the successive approximation process, when determining the value of each bit capacitance, the preset voltage of the current bit is directly eliminated by adjusting the reference voltage to replace the initial reference voltage, and the value is assigned based on the result of the comparator.

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