Component carrier and method for manufacturing same

Abstract

A component carrier (100) and a method of manufacturing the same are described wherein the component carrier (100) comprises a stack (101) comprising a plurality of electrically insulating layer structures (110, 120) and at least one electrically conductive layer structure (104), i) wherein at least one electrically insulating layer structure (110) of the electrically insulating layer structures comprises a main material portion (112), the main material portion of the electrically insulating layer structures has a filler (111) embedded therein, ii) wherein one further electrically insulating layer structure (120) of the electrically insulating layer structures is arranged on one of the main surfaces (115) of at least one of the electrically insulating layer structures (110), and iii) wherein on the main surface (115), the filler (111) is arranged in the filler (111). The filling material (111) of the electrically insulating layer structure (110) is exposed and the material portion (122) of the further electrically insulating layer structure (120) is embedded in the space between the exposed filling material (111).

Description

Technical Field

[0001] The invention relates to a component carrier having a stack with an electrically insulating layer structure with a filler and a further electrically insulating layer structure located on top, wherein material sections of the further electrically insulating layer structure are embedded in the spaces between the exposed fillers.

[0002] Furthermore, the invention relates to a method for producing a component carrier.

[0003] Thus, the present invention may relate to the technical field of manufacturing component carriers, such as printed circuit boards or IC substrates. Background Art

[0004] In the context of the increasing product functionality of component carriers equipped with one or more electronic components, the progressive miniaturization of these electronic components and the increasing number of electronic components to be mounted on component carriers, such as printed circuit boards, increasingly powerful array-like components or packages with a plurality of electronic components are used, which have a plurality of contacts or connections, wherein the spacing between these contacts is increasingly smaller. Removing the heat generated by these electronic components and the component carriers themselves during operation is becoming an increasing problem. In addition, effectively preventing electromagnetic interference is also becoming an increasing problem. At the same time, the component carrier should be mechanically strong and electrically and magnetically reliable in order to be able to operate even under adverse conditions.

[0005] For example, a so-called decontamination process can be applied during the manufacture of the component carrier. This process can be used to clean the surface and the boreholes of the component carrier preform (the so-called panel), in particular by removing resin smears. This process can provide the surface roughness that may be required to improve the adhesion of another layer, such as a copper layer, to the surface to be decontaminated. However, sometimes the increased surface roughness may not improve the adhesion, but may lead to problems with copper residues.

[0006] Typically, the decontamination process is performed as a wet process, in particular by etching the surface of the component carrier preform (e.g. using permanganate). However, in the case where the component carrier layer located at the surface to be etched includes embedded particles, a number of disadvantages may occur. For example, etching can affect resin materials that are (significantly) stronger than filler materials. In the case of silica (SiO2) filler particles, the silica filler particles are usually not affected by etching, while the resin in which the silica filler particles are embedded is removed by etching.

[0007] Figure 4A and Figure 4BA conventional joint 251 of a circuit board 200 is shown separately. Conventional circuit board 200 includes two insulating layers stacked one above the other, wherein each insulating layer includes filler particles embedded in a matrix material. There is poor adhesion between the lower surface of the upper layer and the upper surface of the lower layer caused by poor adhesion between the resin / filler material of the upper layer and the filler of the lower layer. In particular, after a surface treatment process, such as a decontamination process, the filler particles of the lower layer even protrude higher from the matrix material or are at least partially exposed on the outer surface, thereby providing a high surface roughness, which results in even weaker adhesion to the upper layer due to more resin being etched and the presence of more filler particles without roughening the surface of the filler particles exposed to the joint. In addition, due to the high roughness, the joint of the resin may become weaker, thereby being more prone to rupture, and therefore the adhesion also becomes weaker.

[0008] Figure 4A : Due to the weak adhesion, after cutting or dicing the product, there is a gap (visible as a black line) at the joint 250 between the two insulating layers.

[0009] Figure 4B : Further, due to the weak adhesion, delamination portions 251 appear between the insulating layers, thereby significantly reducing the quality of the circuit board 200. Summary of the invention

[0010] There is a need to provide effective and strong joints between electrically insulating layer structures of component carriers.

[0011] Component carriers and methods of manufacture are provided.

[0012] According to an aspect of the invention, a component carrier (eg a printed circuit board or an IC substrate) is described, wherein the component carrier comprises a (multi-layer) stack comprising a plurality of (at least two) electrically insulating layer structures and at least one electrically conductive layer structure.

[0013] i) at least one of the electrically insulating layer structures comprises a main material portion (matrix material, such as a resin) having a filler (such as filler particles, such as SiO2) embedded in the main material portion (preferably distributed non-uniformly in the main material portion);

[0014] ii) a further electrically insulating layer structure of the electrically insulating layer structure (in particular, the further electrically insulating layer structure comprises a further main material portion or an insulating material without a filler, the further main material portion having a further filler embedded in the further main material portion) is arranged on one of the main surfaces of the at least one electrically insulating layer structure; and

[0015] iii) on the main surface, fillers of the electrically insulating layer structure (at least some of the fillers) are exposed (protruding beyond the outer surface of the main material portion), and (part of) another material portion (e.g., resin and / or filler) of the other electrically insulating layer structure is embedded in the space between the exposed fillers.

[0016] According to a further aspect of the invention, a method of manufacturing a component carrier is described, the component carrier comprising a stack comprising a plurality of electrically insulating layer structures and at least one electrically conductive layer structure, the method comprising:

[0017] i) providing at least one of the electrically insulating layer structures, the at least one electrically insulating layer structure comprising a main material portion having a filler embedded in the main material portion;

[0018] ii) providing a further electrically insulating layer structure, wherein one of the main surfaces of the electrically insulating layer structure (for example a main surface by a desmear treatment and / or a plasma treatment) is treated such that the filler is at least partially exposed; and

[0019] iii) arranging a further electrically insulating layer structure on said main surface of the electrically insulating layer structure such that material portions of the further electrically insulating layer structure are embedded in the spaces between the exposed fillers.

[0020] In the context of this document, the term "filler" may particularly refer to a material suitable for being embedded in an electrically insulating material (e.g., a resin). The filler may be configured to provide a specific function in the insulating material, such as mechanical stability for the product, and the filler may also affect the dielectric properties of the insulating material, such as Dk, Df in terms of electrical properties. In an example, the filler may be configured as particles, such as beads. Although the filler may be slightly spherical in the example, in another example, the filler may be formed as a fiber-like piece. In a preferred embodiment, the spherical filler is applied to an insulating (resin) material. A specific example of an electrically insulating layer structure may be an Ajinomoto laminated film (ABF) or a solder resist film or solder resist ink, in which the spherical particles are embedded in a resin layer. In another example, the filler material may be (substantially) unaffected by a wet decontamination process, particularly etching. In a specific example, the filler material includes silica. The filler may be solid or hollow. The filler may include a coating or may not include a coating.

[0021] In the context of this document, the term "main material part" may particularly refer to a matrix material suitable for embedding fillers as described above. Preferably, the main material part is an insulating material part, such as a resin part, for example an epoxy resin part.

[0022] In the context of the present document, the term "component carrier" may particularly denote any supporting structure capable of accommodating one or more components on and / or in the component carrier to provide mechanical support and / or electrical connection and / or thermal conduction. In other words, the component carrier may be configured as a mechanical carrier and / or electronic carrier, as well as a thermal carrier for the components. In particular, the component carrier may be one of a printed circuit board, an organic interposer, a metal core substrate, an inorganic substrate and an IC (integrated circuit) substrate. The component carrier may also be a hybrid board combining different component carriers of the above-mentioned types of component carriers. The component carrier may include at least one electrically insulating structure and an electrically conductive structure.

[0023] The term "component carrier preform" (in manufacturing) may refer to a semi-finished product which will form the final component carrier after multiple processing steps. A preform may for example be a plate comprising multiple (semi-finished) component carriers which will be separated in further manufacturing steps.

[0024] In the context of this document, the term "embedded in the space between..." can be understood in particular as a structural feature in which the material portion of the additional electrically insulating layer structure (e.g., resin and / or filler) is embedded / arranged between the fillers of the electrically insulating layer structure (i.e., the space between the fillers) at the joining area of ​​the two electrically insulating layer structures, the electrically insulating layer structure and the material of the additional electrically insulating layer structure. In other words, the filler of the electrically insulating layer structure extends / protrudes beyond the outer surface of the main material portion (matrix) and enters into the material portion of the additional electrically insulating layer structure. Similar to in a peak-and-valley surface, there are spaces (valley-shaped portions) between the protruding fillers (peak-shaped portions). The additional material portion of the additional electrically insulating layer structure can occupy (in particular, completely occupy) these spaces. This structural feature can achieve high adhesion between the electrically insulating layer structures at the joining area. This structure can be formed by bonding between two dielectric layers by chemical bonding.

[0025] According to exemplary embodiments, the present invention may be based on the idea that an effective and strong joint may be provided between electrically insulating layer structures of a component carrier when the joint between electrically insulating layer structures of a component carrier is configured such that a material portion of one of the electrically insulating layer structures is embedded in a space between exposed / protruding fillers of the other electrically insulating layer structure (similar to being located in a valley of a peak-to-valley surface). The inventors have found that in this particular arrangement, the material portion of the other electrically insulating layer structure may be attached to the exposed filler surface of the electrically insulating layer structure in a stable manner.

[0026] Usually (see above Figure 4A and Figure 4BIn the case of a laminated electrically insulating layer structure (e.g., a laminated electrically insulating layer structure having a plurality of layers) there may still be gaps or even delaminations between the stacked electrically insulating layer structures due to the poor adhesion, in particular when at least one of the stacked insulating layer structures comprises embedded filler particles. This effect may be even more pronounced when a decontamination process is performed which may further expose the filler particles (which typically have a material that is more stable than the embedding matrix).

[0027] In contrast, the component carrier described has a joining region in which the filler of one electrically insulating layer structure protrudes into the material portion of the other electrically insulating layer structure, thereby providing a dense and compact connection that can significantly enhance the adhesion between the layers. The adhesion can be further enhanced when, for example, the material portion of the other electrically insulating layer structure is pressed / arranged under a portion of the exposed filler (undercut). In a specific example, a plasma treatment step is applied (in particular after a decontamination process and before a lamination step) to optimize the filler surface in order to achieve the described advantageous adhesion effects.

[0028] Exemplary Implementations

[0029] According to an embodiment, the further electrically insulating layer structure is attached to the electrically insulating layer structure by means of a material portion of the further electrically insulating layer structure embedded in the space between the exposed fillers. In this way, the material portion of the further electrically insulating layer structure in the space between the fillers can be used as an anchoring portion to achieve a stable and reliable interconnection between the layers at the joining area.

[0030] According to a further embodiment, at least 50%, in particular at least 75%, of the surface of the (further) material portion of the further electrically insulating layer structure attached to the main surface of the electrically insulating layer structure is in (physical) contact with the exposed surface of the filler. By bringing such a large amount of material of the further electrically insulating layer structure into contact with the exposed filler surface (in other words: located in the space), a particularly high adhesion (anchoring function) can be achieved.

[0031] According to another embodiment, the total volume of the filler occupies a ratio of 40% to 80%, in particular between 60% and 80%, more particularly about 75% (e.g. between 70% and 80%) of the entire volume of the electrically insulating layer structure. Such a large amount of filler can provide higher stability (in particular anti-warping) and better electrical properties (low loss, high frequency) in terms of dielectric properties, and can be achieved, for example, by ABF. A large amount of filler can further increase the adhesion, because more and smaller spaces are provided between the exposed fillers. Therefore, the material of the additional electrically insulating layer structure can be attached to more exposed surfaces, thereby increasing the overall stability.

[0032] According to a further embodiment, the further electrically insulating layer structure comprises a (further) main material portion having a further filler (similar to or different from the filler) embedded in the main material portion. Thus, stability advantages may also be provided for the further electrically insulating layer structure. Furthermore, the filler of the further electrically insulating layer structure may also move downwards to the electrically insulating layer (e.g. ABF) during processing (e.g. by hot pressing). Thus, the fillers of the two layers may fuse into each other in the junction of the two layers.

[0033] According to a further embodiment, the total volume ratio occupied by the further filler in the further electrically insulating layer structure is (equal to or) less than the total volume ratio occupied by the filler in the electrically insulating layer structure (e.g. 75% or more, in particular 80% or more). In other words, the further filler is smaller and / or there is a smaller amount of further filler than the filler. This can provide the following advantages: there can be more further main material parts and the spaces between the fillers can be penetrated even more effectively to achieve the anchoring function. In an example, the filler can move more easily towards the further electrically insulating material during processing (e.g. hot pressing) and fuse more into the further electrically insulating material to allow the two layers to be better attached.

[0034] According to another embodiment, the main surface of the electrically insulating layer structure (and / or another electrically insulating layer structure) comprises a surface having a roughness defined at least in part by peaks and / or valleys or point-to-point variations in surface flatness. In particular, the peaks are realized by exposed fillers, while the valleys are spaces between the exposed fillers, thereby exposing the outer surface of the main material portion (matrix). Such a peak-to-valley (rough) surface can enable another main material portion to invade into the valleys to increase adhesion. The process can be similar to a rough metal (copper) surface that enables insulating material to attach to the valleys.

[0035] According to another embodiment, undercuts are formed in some of the valley-shaped portions (the spaces therebetween). In the present context, the term "undercut" may particularly refer to an area of ​​the electrical insulating layer structure at the junction between the filler and the main material portion of the electrical insulating layer structure in the vertical direction (z, along the thickness direction of the stack). In other words, the undercut may be the space between the exposed filler and the outer surface of the associated main material portion. In an embodiment, the undercut is filled with the (additional main) material portion of another electrical insulating layer structure. This may provide the advantage of further enhancing the adhesion (particularly the anchoring function of another electrical insulating layer structure material). For example, such an undercut structure may be intentionally obtained by selecting a specific shape of the filler or by increasing the exposure of the filler (e.g., through a decontamination process).

[0036] According to a further embodiment, the material portion of the further electrically insulating layer structure embedded in the space between the exposed fillers is (at least) partially embedded in the undercut (see above).

[0037] According to another embodiment, the further electrically insulating layer structure may be formed by ink, wherein the ink is coated or screened on the electrically insulating material (e.g., ABF layer). In particular, by coating or screen printing, the ink may be (completely) filled into the spaces between the exposed fillers, e.g., by roll coating or screen printing.

[0038] According to a further embodiment, the component carrier comprises a joint penetration between the electrically insulating layer structure and the further electrically insulating layer structure, in particular wherein at least one joint penetration structure (at the joint penetration) is at least 50 nm, in particular at least 300 nm, more particularly at least 600 nm.

[0039] According to a further embodiment, a joint penetration is formed between two electrically insulating layer structures after applying temperature / pressure (e.g. hot pressing; lamination) on the further insulating material. Such a joint penetration can be formed, for example, when heat is applied to the further insulating material or when a material is laminated on the insulating material. As a result, the fillers in the two electrically insulating layer structures move towards each other and the resins of the layer structures fuse together due to the forces and reaction forces in the (vacuum) lamination of the two materials.

[0040] According to further embodiments, the exposed filler and the material portion embedded (in the space) are configured to avoid separation of the electrically insulating layer structure and the further electrically insulating layer structure in a non-destructive manner (avoid delamination).

[0041] According to a further embodiment, the filler comprises a non-fibrous filler, in particular, the filler comprises filler particles, more particularly, the filler comprises a non-fibrous filler having a spherical shape and / or an oval shape. In an example, the diameter of the filler may be in the range of 0.1 μm to 5 μm, in particular in the range of 0.5 μm to 5 μm. Compared to a fibrous filler, a non-fibrous filler (e.g. spherical particles) may achieve a higher flexibility (bendability) of the electrically insulating layer structure. In addition, the non-fibrous particles may achieve an improved surface attachment of the (further main) material portion of the further electrically insulating layer structure.

[0042] According to further embodiments, the filler has a diameter in the range of 10 nm to 15 μm. This range can be particularly effective for stabilizing the insulating material but allowing a certain flexibility / bendability. In an example, the maximum filler size can be about 10 μm or slightly higher, depending on the molding (matrix) material. Considering the nanofiller ABF, the filler size range can be in the range of 10 nm to 15 μm.

[0043] According to a further embodiment, the main surface comprises a surface of roughness at least partially defined by rounded peaks and / or rounded valleys. In an example, at least 70% of the surface is defined by rounded peaks and / or rounded valleys, in particular, at least 80% of the surface is defined by rounded peaks and / or rounded valleys, more in particular, at least 95% of the surface is defined by rounded peaks and / or rounded valleys. The rounded peaks may be realized by round (in particular spherical) filler particles. The rounded valleys may be formed during a processing (e.g. decontamination) process, and / or the rounded valleys may be formed by round filler particles falling out of the rounded valleys. The rounded shape at the main surface may improve the adhesion of further electrically insulating layer structures.

[0044] According to a further embodiment, the material portion of the further electrically insulating layer structure embedded in the space between the exposed fillers is positioned at a depth in the range of 50 nm to 700 nm along the thickness direction (z) of the stack. Such a depth allows for particularly robust interconnection and adhesion.

[0045] According to another embodiment, the main surface of the electrically insulating layer structure comprises a roughness that is higher than the roughness of the opposite main surface. In other words, the size / shape / number of fillers at the main surface is different. For example, compared with the electrically insulating layer structure, the other electrically insulating layer structure may not include fillers or include fewer fillers or include smaller fillers. Therefore, the roughness of the surface, in particular the peak-and-valley structure, may be different. By providing the other electrically insulating layer structure with a lower roughness, the intrusion of the material portion into the space between the exposed fillers can be improved.

[0046] According to a further embodiment, the exposed filler forms a protrusion which fuses from the electrically insulating layer structure and extends away from the main surface of the electrically insulating layer structure. Thus, the protruding filler can be positioned deep into the further material of the further electrically insulating layer structure and thus enhance the anchoring function at the joint.

[0047] According to a further embodiment, the protrusion extends in a linear direction, in particular, the protrusion extends in a direction perpendicular to the orientation of the main surface, ie in a vertical direction z. Furthermore, by this means, the anchoring function at the joint can be enhanced.

[0048] According to a further embodiment, the material part of the electrically insulating layer structure comprises an organic material, in particular an epoxy resin. Thus, established and highly industrially relevant materials and their production processes can be directly implemented.

[0049] According to a further embodiment, the filler comprises or consists of an inorganic material (eg ceramic or silicon / glass). In this way, established and highly reliable materials (and their manufacturing processes) can be directly applied.

[0050] Filler includes silicon dioxide or other inorganic materials (combination compound) (inorganic filler can be used alone or in any ratio with two or more inorganic materials combined use, thus can make the thermal expansion coefficient of the cured material obtained by curing the resin combination reduced and can control warping). Filler particles can make the depth of the concave part of the polished surface of the resin smaller and can make the dielectric loss tangent of the cured material obtained by curing the resin combination reduced. In addition, this can contribute to reduce the tensile elastic modulus of the cured material. In addition, preferably, filler particles can be surface treated by suitable surface treatment, because surface treatment can suppress the aggregation of the particles of the filler or the separation of the particles of the filler and the polished surface, and surface treatment can obtain better uniformity on the resin sheet surface and improve the corrosion resistance and dispersibility of particle filler. Surface treatment can also contribute to changing the characteristics of the material surface, so that the adhesion between two different layers is better. The material can effectively stabilize the insulating material, but in the decontamination etching process, defects (see above) can be caused, and the dielectric properties of the insulating material in terms of electrical properties will be affected by having different materials or having different shapes or even having fillers of different sizes inside. However, by treating the exposed surface portions of the silica filler together with the insulating material, in particular by laser ablation, the advantages of higher stability and surface roughness consistency can be combined.

[0051] In other embodiments, the filler may include conductive particles, for example, the interior of the conductive particles is plastic and the exterior of the conductive particles is coated with a conductive metal, such as gold, nickel, or the like.

[0052] According to a further embodiment, the further electrically insulating layer structure (the further main material part) comprises an organic material, in particular an epoxy resin. More particularly, the organic material (e.g. epoxy resin) is embedded between the spaces of the protruding parts (exposed filler particles). Preferably, the organic materials of the two electrically insulating layer structures are different (or similar). The resin material may be at least partially viscous during the lamination process, so that the further main material part can be arranged in an easy but effective way into the spaces between the protruding fillers.

[0053] According to a further embodiment, the further electrically insulating layer structure comprises a photosensitive layer or consists of a photosensitive layer. Thus, the structuring / patterning of the layer can be achieved in a defined manner. For example, the further electrically insulating layer structure can be used as a solder resist layer and should therefore be patterned to cover only certain areas of the component carrier surface.

[0054] According to a further embodiment, the electrically insulating layer structure is a layer of a (layer stack of component carrier) build-up structure and / or wherein the further electrically insulating layer structure is an outer surface layer, in particular a solder resist layer and / or a surface treatment layer. Such an outer surface layer may be important for the protection of the component carrier, so that the described enhanced adhesion may be very advantageous.

[0055] According to a further embodiment, the treatment of the main surface of the electrically insulating layer structure comprises a decontamination treatment. This established process can improve the quality of the main surface. In particular, after the decontamination process, the exposed filler particles can protrude more from the matrix material.

[0056] In the context of this document, the term "decontamination process / treatment" may particularly denote a process in which a decontamination operation is applied in component carrier manufacturing, i.e. a surface cleaning and / or roughening of a component carrier preform. In particular, resin surfaces and drilled holes may be cleaned and the surface may be roughened to improve the attachment properties. The decontamination process may include wet decontamination and / or dry decontamination. Wet decontamination uses chemicals to treat the surface, while dry decontamination may use gases to attack the surface.

[0057] According to a further embodiment, the treatment of the main surface of the electrically insulating layer structure comprises a plasma treatment, in particular after decontamination of the main surface (and before lamination of the further electrically insulating layer structure). The plasma treatment can be performed according to a predetermined procedure and can preferably improve the surface adhesion of the exposed filler by treating the filler surface.

[0058] According to another embodiment, the treatment of the main surface of the electrically insulating layer structure comprises an excimer treatment. By means of the excimer treatment, the roughness of the insulating material surface can be made more consistent, or the desired roughness can be obtained by means of a pre-designed mask applied together with the excimer. In addition, the protrusion of the filler inside the insulating material can be controlled as required, and the penetration with the further insulating material can be predetermined. Thus, the adhesion between the two layers can be significantly improved.

[0059] In an embodiment, the component carrier is formed as a plate. This contributes to a compact design, wherein the component carrier nevertheless provides a large base for mounting components on the component carrier. Furthermore, in particular a bare chip as an example of an embedded electronic component can be conveniently embedded in a thin plate, such as a printed circuit board, due to the small thickness of the bare chip.

[0060] In an embodiment, the component carrier is configured as one of a printed circuit board, a substrate (in particular an IC substrate) and an interposer.

[0061] In the context of the present application, the term "printed circuit board" (PCB) may particularly denote a plate-like component carrier formed by laminating a plurality of electrically conductive layer structures with a plurality of electrically insulating layer structures, the lamination being performed, for example, by applying pressure and / or by supplying thermal energy. As a preferred material for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may comprise, for example, resin and / or glass fibers, so-called prepregs or FR4 materials, PID or ABF. The individual electrically conductive layer structures may be connected to one another in a desired manner by forming holes through the laminate, for example by laser drilling or mechanical drilling, and by partially or completely filling the holes with an electrically conductive material, in particular copper, thereby forming vias or any other through-hole connections. A filled hole connecting the entire stack, (the through-hole connection extending through a plurality of layers or the entire stack), or a filled hole connecting at least two electrically conductive layers, is referred to as a via. Similarly, an optical interconnect may be formed through the various layers of the stack to receive an electro-optical circuit board (EOCB). In addition to one or more components that can be embedded in the printed circuit board, the printed circuit board is generally configured to accommodate one or more components on one surface or two opposite surfaces of the plate-shaped printed circuit board. The one or more components can be connected to the corresponding main surface by welding. The dielectric portion of the PCB may include a resin with reinforcing fibers (such as glass fibers).

[0062] In the context of the present application, the term "substrate" can particularly refer to a small component carrier. Relative to a PCB, a substrate can be a relatively small component carrier on which one or more components can be installed, and can be used as a connection medium between one or more chips and another PCB. For example, a substrate can have a size roughly the same as a component (especially an electronic component) to be mounted on the substrate (for example, in the case of a chip-scale package (CSP)). In another embodiment, the substrate can be significantly larger than the assigned components (for example, a flip chip ball grid array (FCBGA) configuration). More specifically, a substrate can be understood as a component carrier for a carrier for an electrical connector or an electrical network and a component carrier for a connector that is comparable to a printed circuit board (PCB) but has a relatively high density of lateral and / or vertical arrangements. The lateral connector is, for example, a conductive path, and the vertical connector can be, for example, a drill hole. These lateral connectors and / or vertical connectors are arranged in the substrate and can be used to provide an electrical connection, thermal connection, and / or mechanical connection between a contained component or an uncontained component (such as a bare wafer), especially an IC chip and a printed circuit board or an intermediate printed circuit board. Therefore, the term "substrate" also includes "IC substrate." The dielectric part of the substrate may include a resin with reinforcement particles, such as reinforcement spheres, in particular glass spheres.

[0063] The substrate or interposer may include or be composed of at least a glass layer, silicon (Si), and / or a photoimageable or dry-etchable organic material such as an epoxy-based laminate material (e.g., an epoxy-based laminate film), or a polymer composite such as polyimide or polybenzoxazole (the polymer composite may or may not include photosensitive and / or heat-sensitive molecules).

[0064] In an embodiment, at least one electrically insulating layer structure comprises at least one of the following: a resin or polymer, such as an epoxy resin, a cyanate resin, a benzocyclobutene resin, a bismaleimide triazine resin, a polyphenyl derivative (e.g. based on polyphenylene ether, PPE), a polyimide (PI), a polyamide (PA), a liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE) and / or a combination thereof. A reinforcing structure, such as a mesh, a fiber, a sphere or other types of filler particles, made, for example, of glass (multilayer glass) to form a composite material may also be used. A semi-cured resin combined with a reinforcing agent, such as a fiber impregnated with the above resin, is called a prepreg. These prepregs are usually named after their properties, such as FR4 or FR5 to describe their flame retardant properties. Although prepregs, especially FR4, are usually preferred for rigid PCBs, other materials, especially epoxy-based laminated materials (such as laminated films) or photoimageable dielectric materials may also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers and / or cyanate resins may be preferred. In addition to these polymers, low temperature co-fired ceramics (LTCC) or other low-DK materials, relatively low-DK materials or ultra-low-DK materials can be used as electrically insulating layer structures in the component carrier.

[0065] In an embodiment, at least one electrically conductive layer structure comprises at least one of copper, aluminum, nickel, silver, gold, palladium, tungsten, magnesium, carbon, (particularly doped) silicon, titanium and platinum. Although copper is generally preferred, other materials or other types of coatings thereof are also possible, in particular coated with superconducting materials or conducting polymers, such as graphene or poly (3,4-ethylenedioxythiophene) (PEDOT), respectively.

[0066] At least one further component may be embedded in the stack and / or surface mounted on the stack. The component and / or the at least one further component may be selected from: a non-conductive inlay, a conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (such as a heat pipe), an optical waveguide element (such as an optical waveguide or optical conductor connector), an electronic component or a combination thereof. The inlay may, for example, be a metal block with or without an insulating material coating (IMS-inlay), which may be embedded or surface mounted to promote heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W / mK. Such materials are typically based on, but not limited to, metals, metal oxides and / or ceramics, such as copper, aluminum oxide (Al2O3) or aluminum nitride (AlN). In order to increase the heat exchange capacity, other geometric structures with increased surface area are also often used. Furthermore, the component may be an active electronic component (implementing at least one pn junction), a passive electronic component such as a resistor, an inductor or a capacitor, an electronic chip, a memory device (e.g., a DRAM or other data memory), a filter, an integrated circuit (e.g., a field programmable gate array (FPGA), a programmable array logic (PAL), a general purpose array logic (GAL), and a complex programmable logic device (CPLD)), a signal processing component, a power management component (e.g., a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), a junction field effect transistor (JFET), or an insulated-gate field effect transistor (GFET). In the invention, the invention relates to a power management device, a gate electrode (IGFET), the power management components are all based on semiconductor materials, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), indium phosphide (InP) and / or any other suitable inorganic compound), optoelectronic interface elements, light emitting diodes, optocouplers, voltage converters (such as DC / DC converters or AC / DC converters), cryptographic components, transmitters and / or receivers, electromechanical transducers, sensors, actuators, microelectromechanical systems (MEMS), microprocessors, capacitors, resistors, inductors, batteries, switches, cameras, antennas, logic chips and energy collection units. However, other components can be embedded in the component carrier. For example, a magnetic element can be used as a component. Such a magnetic element can be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, such as a ferrite core), or such a magnetic element can be a paramagnetic element. However, the component can also be, for example, an IC substrate, an intermediate layer or another component carrier in a board-in-board configuration. The component can be surface mounted on the component carrier and / or can be embedded in the interior of the component carrier.In addition, other components can also be used as components, in particular those components that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment.

[0067] In an embodiment, the component carrier is a laminated component carrier. In such an embodiment, the component carrier is a composite of multiple layers that are stacked and connected together by applying pressure and / or heat.

[0068] After processing the internal layer structure of the component carrier, one or more further electrically insulating layer structures and / or electrically conductive layer structures can be coated symmetrically or asymmetrically on one or both opposite main surfaces of the processed layer structure, in particular by lamination. In other words, the layering can be continued until the desired number of layers is obtained.

[0069] After the formation of the stack of electrically insulating layer structures and electrically conductive layer structures has been completed, the obtained layer structure or component carrier can be subjected to a surface treatment.

[0070] In particular, with regard to surface treatment, an electrically insulating solder resist may be applied to one or both of the opposite main surfaces of a layer stack or component carrier. For example, such a solder resist may be formed over the entire main surface and the layer of solder resist may be subsequently patterned to expose one or more electrically conductive surface portions that are used to electrically connect the component carrier to an electronic peripheral. Surface portions of the component carrier that remain covered with the solder resist, in particular surface portions containing copper, may be effectively protected from oxidation or corrosion.

[0071] As far as the surface treatment is concerned, a surface treatment can also be selectively applied to the exposed electrically conductive surface portions of the component carrier. Such a surface treatment can be an electrically conductive covering material on the exposed electrically conductive layer structures (such as pads, conductive traces, etc., including or consisting of copper in particular) on the surface of the component carrier. If such exposed electrically conductive layer structures are not protected, the exposed electrically conductive component carrier material (especially copper) may oxidize, making the component carrier less reliable. The surface treatment can then be formed as a joint between, for example, a surface mounted component and a component carrier. The surface treatment has the function of protecting the exposed electrically conductive layer structures (especially copper circuits) and realizing a joining process with one or more components, for example by soldering. Examples of suitable materials for the surface treatment are organic solderability preservatives (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), electroless nickel electroless palladium immersion gold (ENEPIG), gold (especially hard gold), chemical tin (chemical and electroplated), nickel-gold, nickel-palladium, etc. Particularly for high-speed applications, nickel-free materials for the surface treatment can also be used. Examples are ISIG (immersion silver-immersion gold) and EPAG (electroless palladium-autocatalytic gold). BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.

[0073] Figure 1 A cross section through a component carrier according to an exemplary embodiment of the invention is shown.

[0074] Figure 2 A microscopic image of a joint of a component carrier according to an exemplary embodiment of the present invention is shown.

[0075] FIG. 3A to FIG. 3C A method for producing a component carrier according to an exemplary embodiment of the invention is shown.

[0076] Figure 4A and Figure 4B Conventional joints of the circuit boards are shown respectively.

[0077] Figure 5A , Figure 5B and Figure 6 Detailed microscopic images of a joint of a component carrier according to an exemplary embodiment of the present invention are respectively shown. DETAILED DESCRIPTION

[0078] The illustrations in the drawings are schematic. In different drawings, similar or identical elements are provided with the same reference signs.

[0079] Figure 1 A component carrier 100 according to an exemplary embodiment of the invention is shown. The component carrier 100 comprises a stack 101 having a plurality of electrically insulating layer structures 110, 120 (two layers are shown in this example) and at least one electrically conductive layer structure 104 (which is arranged below the electrically insulating layer structures 110, 120 in this example).

[0080] The lower electrical insulating layer structure 110 includes a main material portion 112 having a filler 111 embedded in the main material portion 112. In this example, the filler 111 is filler particles that are non-uniformly distributed in the main material portion (matrix) 112. The filler 111 is a non-fibrous filler having a spherical and / or oval shape. The total volume of the filler 111 occupies a ratio of 40% to 80% of the entire volume of the electrical insulating layer structure 110.

[0081] The further (upper) electrically insulating layer structure 120 is arranged on the upper main surface 115 of the (lower) electrically insulating layer structure 110 and comprises a further main material portion 122 having a further filler 121 embedded in the further main material portion 122. The ratio of the total volume occupied by the further filler 121 in the further electrically insulating layer structure 120 is smaller than the ratio of the total volume occupied by the filler 111 in the electrically insulating layer structure 110. In other words, the electrically insulating layer structure 110 comprises more (in terms of size, may be larger, smaller or the same) filler than the further electrically insulating layer structure 120.

[0082] Between the electrically insulating layer structures 110 , 120 , a joining region 150 is provided, which extends in a horizontal direction (x, y plane) perpendicular to the stacking direction (z).

[0083] On the main surface 115, at the bonding region 150, the fillers 111 of the (lower) electrically insulating layer structure 110 are exposed, i.e. the fillers 111 of the (lower) electrically insulating layer structure 110 extend / protrude beyond the main surface 115 of the main material portion 112. Therefore, a portion of the main material portion 122 of the further electrically insulating layer structure 120 is embedded in the space between the exposed fillers 111 of the (lower) electrically insulating layer structure 110. In other words, the exposed fillers 111 of the electrically insulating layer structure 110 extend / protrude into the further electrically insulating layer structure 120, whereas the further fillers 121 of the further electrically insulating layer structure 120 extend / protrude into the electrically insulating layer structure 110.

[0084] The further electrically insulating layer structure 120 is attached to the electrically insulating layer structure 110 by means of a material portion 122 of the further electrically insulating layer structure 120 embedded in the space between the exposed fillers 111. In other words, the further matrix material portion 122 is attached to the exposed surface of the fillers 111, while the matrix material portion 112 is attached to the exposed surface of the further fillers 121.

[0085] In this design, the exposed filler 111 and the embedded further material portion 122 are configured to avoid separation of the electrically insulating layer structure 110 and the further electrically insulating layer structure 120 in a non-destructive manner.

[0086] For example, at least 75% of the surface of the further main material portion 122 of the further electrically insulating layer structure 120 attached to the main surface 115 of the electrically insulating layer structure 110 is in contact with the exposed surface of the filler 111 .

[0087] It is schematically shown that the main surface 115 comprises a surface with a surface roughness at least partially defined by (rounded) peaks and / or (rounded) valleys, and wherein undercuts 130 are formed in some of the valleys (see also Figure 5B ). Therefore, the further main material portion 122 of the further electrically insulating layer structure 120 embedded in the space between the exposed fillers 111 is partially embedded in the undercut portion 130 .

[0088] The material portion 122 of the further electrically insulating layer structure 120 is embedded in the space between the exposed fillers 111 at a depth in the range of 50 nm to 700 nm along the thickness direction (z) of the stack 101. The main surface 115 of the electrically insulating layer structure 110 comprises a roughness that is high compared to the roughness of the opposite main surface (the lower main surface of the further electrically insulating layer structure 120). In other words, more / larger fillers 111 are provided compared to the further fillers 121. The exposed fillers 111 form a protrusion that merges from the electrically insulating layer structure 110 (with the further electrically insulating layer structure 120) and extends away from the main surface 115 of the electrically insulating layer structure 110, wherein the protrusion extends along a straight line direction perpendicular to the orientation of the main surface 115.

[0089] In this example, the material portion 112 of the electrically insulating layer structure 110 comprises epoxy resin, while the filler 111 comprises an inorganic material. The further electrically insulating layer structure 120 comprises a photosensitive layer. The electrically insulating layer structure 110 is a layer of a (layer stack) build-up structure, and the further electrically insulating layer structure 120 is a solder resist layer and / or a surface treatment layer.

[0090] Figure 2 FIG. 1 shows a microscopic image of a joint 150 between an electrically insulating layer structure 110 and a further electrically insulating layer structure 120 of a component carrier according to an exemplary embodiment of the present invention. Figure 4A and Figure 4B ), there is no visible delamination or gap (black line) between the electrically insulating layer structure 110 and the further electrically insulating layer structure 120 .

[0091] FIG. 3A to FIG. 3C A method of manufacturing a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0092] Figure 3A: An electrically insulating layer structure 110 is provided, which includes a matrix material portion 112 with an embedded filler 111, in this example, the electrically insulating layer structure 110 is an Ajinomoto laminated film with SiO2 filler particles. At the upper main surface 115, the filler 111 is exposed and protrudes beyond the outer surface of the matrix material portion 112. In particular, after decontamination, the protrusion of the exposed filler is more obvious. In this case, the adhesion between the insulating material and the other insulating material will be poor. Afterwards, delamination between the two layers will occur in subsequent processes, especially for products that apply low Dk and Df dielectric materials and have a large amount of fillers for high-performance computing applications.

[0093] Figure 3B The treatment of the main surface 115 of the electrically insulating layer structure 110 comprises a plasma treatment 160 which is performed after the desmear treatment of said main surface 115. Due to the formation of chemical bonding features, the properties of the surface can be changed, thereby improving the adhesion of the two layers.

[0094] Figure 3C : After the plasma treatment 160, a further electrically insulating layer structure 120 is formed (laminated) on top of the main surface 115. Thus, a joint 150 is formed at the main surface 115, wherein the exposed fillers 111 of the electrically insulating layer structure 110 protrude into the further electrically insulating layer structure 120, and wherein the (matrix) material portions 122 of the further electrically insulating layer structure 120 are embedded in the spaces between the exposed fillers 111.

[0095] Figure 5A and Figure 5B A detailed microscopic image of a joint 150 of a component carrier 100 according to an exemplary embodiment of the present invention is shown, wherein: Figure 5B yes Figure 5A Detailed view of a specific area of ​​the electrically insulating layer structure 110 . The structure of the undercut 130 is shown in the detailed view, which is formed by a material portion 122 of the further electrically insulating layer structure 120 which is formed below a part of the filler particles of the electrically insulating layer structure 110 .

[0096] Figure 6 A detailed microscopic image of a joint 150 of a component carrier 100 according to an exemplary embodiment of the invention is shown. As an exemplary example, some distances between filler particles 111 of an electrically insulating layer structure 110 and further filler particles 121 of a further electrically insulating layer structure 120 are shown (from left to right): 354 nm, 472 nm, 389 nm, 129 nm and 366 nm.

[0097] Reference numerals

[0098] 100 Component carriers

[0099] 101 stacked pieces

[0100] 104 Electrically conductive layer structure

[0101] 110 Electrical insulation layer structure

[0102] 111 Filler

[0103] 112 Material part and matrix of electrical insulation layer structure

[0104] 115 Main surface

[0105] 120 Additional electrical insulation layer structure

[0106] 121 Additional fillers

[0107] 122 Additional electrical insulating layer structure material part, matrix

[0108] 130 Undercut

[0109] 150 Joint

[0110] 160 Plasma treatment

[0111] 200 Conventional circuit boards

[0112] 250 Conventional joints

[0113] 251 Conventional stratification.

Claims

1. A component carrier (100), wherein: The component carrier (100) comprises: A stack (101) comprising a plurality of electrically insulating layer structures (110, 120) and at least one electrically conductive layer structure (104), At least one of the electrically insulating layer structures (110) comprises a main material portion (112), wherein the main material portion (112) has a filler (111) embedded in the main material portion (112). wherein a further one of the electrically insulating layer structures (120) is arranged on one of the main surfaces (115) of the at least one electrically insulating layer structure (110), and wherein, on the main surface (115), at least a portion of the filler (111) of the electrically insulating layer structure (110) is exposed, and The further main material portion (122) of the further electrically insulating layer structure (120) is embedded in the space between the exposed fillers (111).

2. The component carrier (100) according to claim 1, wherein: The further electrically insulating layer structure (120) is attached to the electrically insulating layer structure (110) by means of the further main material portion (122) of the further electrically insulating layer structure (120) being embedded in the space between the exposed fillers (111).

3. The component carrier (100) according to claim 1 or 2, wherein: At least 50% of the surface of the additional main material portion (122) of the additional electrically insulating layer structure (120) attached to the main surface (115) of the electrically insulating layer structure (110) is in contact with the exposed surface of the filler (111), in particular, at least 75% of the surface of the additional main material portion (122) of the additional electrically insulating layer structure (120) attached to the main surface (115) of the electrically insulating layer structure (110) is in contact with the exposed surface of the filler (111).

4. The component carrier (100) according to any one of claims 1 to 3, wherein: The total volume of the filler (111) accounts for 40% to 80% of the total volume of the electrical insulation layer structure (110), and in particular, the total volume of the filler (111) accounts for 60% to 80% of the total volume of the electrical insulation layer structure (110).

5. The component carrier (100) according to any one of claims 1 to 4, wherein: The additional electrically insulating layer structure (120) includes the additional main material portion (122), and the additional main material portion (122) of the additional electrically insulating layer structure (120) has an additional filler (121) embedded in the additional main material portion (122) of the additional electrically insulating layer structure (120), in particular, the ratio of the total volume occupied by the additional filler (121) in the additional electrically insulating layer structure (120) is smaller than the ratio of the total volume occupied by the filler (111) in the electrically insulating layer structure (110).

6. The component carrier (100) according to any one of claims 1 to 5, wherein: The major surface (115) comprises a surface having a roughness at least partially defined by peaks and / or valleys.

7. The component carrier according to claim 6, wherein: Undercut portions (130) are formed in some of the valley-shaped portions.

8. The component carrier (100) according to claim 7, wherein: The further main material portion (122) of the further electrically insulating layer structure (120) embedded in the space between the exposed fillers (111) is at least partially embedded in the undercut portion (130).

9. The component carrier (100) according to any one of claims 6 to 8, wherein: The exposed filler (111) and the embedded further main material portion (122) are configured to prevent the electrically insulating layer structure (110) and the further electrically insulating layer structure (120) from being separated in a non-destructive manner.

10. The component carrier (100) according to any one of claims 1 to 9, wherein: The filler (111) comprises a non-fibrous filler, in particular, the filler (111) comprises filler particles, more particularly, the filler (111) comprises a non-fibrous filler having a spherical and / or oval shape; and / or wherein, At least a portion of the filler (111) includes a diameter in the range of 0.1 μm to 5 μm, and in particular, at least a portion of the filler (111) includes a diameter in the range of 0.5 μm to 5 μm.

11. The component carrier (100) according to claim 10, wherein: The major surface (115) comprises a surface having a roughness at least partially defined by rounded peaks and / or rounded valleys.

12. The component carrier (100) according to any one of claims 1 to 11, wherein: The further main material portion (122) of the further electrically insulating layer structure (120) is embedded in the space between the exposed fillers (111) at a depth in the range of 50 nm to 700 nm along the thickness direction (z) of the stack.

13. The component carrier (100) according to any one of claims 1 to 12, wherein: The main surface (115) of the electrically insulating layer structure (110) comprises a roughness that is higher than the roughness of the opposing main surface.

14. The component carrier (100) according to any one of claims 1 to 13, wherein: The exposed filler (111) forms a protrusion that fuses from the electrically insulating layer structure (110) and extends away from the main surface (115) of the electrically insulating layer structure (110).

15. The component carrier (100) according to claim 14, wherein: The protrusion extends along a linear direction, in particular, the protrusion extends along a direction perpendicular to the orientation of the main surface (115).

16. The component carrier (100) according to any one of claims 1 to 15, wherein: The material portion (112) of the electrically insulating layer structure (110) comprises an organic material, and in particular, the material portion (112) of the electrically insulating layer structure (110) comprises epoxy resin.

17. The component carrier (100) according to any one of claims 1 to 16, wherein: The filler (111) includes an inorganic material, or the filler (111) is composed of an inorganic material.

18. The component carrier (100) according to any one of claims 1 to 17, wherein: The further electrically insulating layer structure (120) comprises an organic material, in particular, the further electrically insulating layer structure (120) comprises an epoxy resin.

19. The component carrier (100) according to any one of claims 1 to 18, wherein: The further electrically insulating layer structure (120) comprises a photosensitive layer, or the further electrically insulating layer structure (120) consists of a photosensitive layer.

20. The component carrier (100) according to any one of claims 1 to 19, wherein: The electrically insulating layer structure (110) is a layer of a laminated structure, and / or wherein: The further electrically insulating layer structure (120) is a solder resist layer and / or a surface treatment layer.

21. The component carrier (100) according to any one of claims 1 to 20, further comprising: a bonding penetration, the bonding penetration being located between the electrically insulating layer structure (110) and the further electrically insulating layer structure (120), In particular, at least one of the structures of the joint penetration portion is at least 50 nm, in particular, at least one of the structures of the joint penetration portion is at least 300 nm, more particularly, at least one of the structures of the joint penetration portion is at least 600 nm.

22. A method for manufacturing a component carrier (100), the component carrier (100) comprising a stack (101), the stack (101) comprising a plurality of electrically insulating layer structures (110, 120) and at least one electrically conductive layer structure (104), the method comprising: Providing at least one of the electrically insulating layer structures (110), wherein at least one of the electrically insulating layer structures (110) comprises a main material portion (112), wherein the main material portion (112) of the electrically insulating layer structure (110) has a filler (111) embedded in the main material portion (112) of the electrically insulating layer structure (110); Providing a further electrically insulating layer structure (120), wherein one of the main surfaces (115) of the electrically insulating layer structure (110) is treated such that the filler (111) is at least partially exposed; and The further electrically insulating layer structure (120) is arranged on the main surface (115) of the electrically insulating layer structure (110) such that further main material portions (122) of the further electrically insulating layer structure (120) are embedded in the spaces between the exposed fillers (111).

23. The method according to claim 22, wherein: The treatment of the main surface (115) of the electrically insulating layer structure (110) comprises a desmearing treatment.

24. The method according to any one of claims 22 to 23, wherein: The treatment of the main surface (115) of the electrically insulating layer structure (110) comprises plasma treatment, and in particular, after the decontamination treatment of the main surface (115), the treatment of the main surface (115) of the electrically insulating layer structure (110) comprises plasma treatment.

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