Circuit board and method of manufacturing circuit board

Abstract

The invention provides a circuit board and a method of manufacturing the circuit board. The circuit board includes: a first insulating layer having a first surface and a second surface opposite to each other; the first wire layer is embedded in the first insulating layer; and a bump including a base portion disposed transverse to the first line layer to be embedded within the first insulating layer and a protrusion portion integrally extending from the base portion and protruding above the first surface, and the width of the protruding part at the upper end thereof is smaller than the width of the protruding part at the height of the first surface.

Description

Technical Field

[0001] The present disclosure relates to a circuit board and a method of manufacturing the circuit board. Background Art

[0002] Currently, as the number of I / O pins increases, ball grid array (BGA) boards for high-end application processors (APs) need to have a smaller ball pitch. In order to achieve a fine ball pitch, the method of bonding a chip and a board may be changed from a method using solder bumps to a method using copper bumps.

[0003] If copper bumps are used, the bonding method between the board and the chip can be simply implemented even when there is a fine bump-to-bump interval, and no alignment technology between the circuit and the copper bumps is required. Because the change from the method using solder bumps to the method using copper bumps can effectively respond to smaller ball pitches, a finer and more accurate process of copper bumps is required. Summary of the invention

[0004] One aspect of the present disclosure is to provide a circuit board and a method of manufacturing the circuit board that can accurately implement fine pitch metal bumps.

[0005] However, the problems to be solved by the embodiments of the present disclosure are not limited to the above-mentioned problems, and various extensions can be made within the scope of the technical ideas included in the present disclosure.

[0006] According to an embodiment, the circuit board includes: a first insulating layer having a first surface and a second surface opposite to each other; a first wire layer buried in the first insulating layer; and a bump including a base and a protrusion, the base being arranged transversely to the first wire layer to be buried in the first insulating layer, the protrusion extending integrally from the base and protruding above the first surface, and the width of the protrusion at its upper end is smaller than the width at the height of the first surface.

[0007] The width of the protrusion at the height of the first surface may be the largest, and the width of the protrusion at the upper end may be the smallest.

[0008] The width of the protrusion may decrease in a direction away from the first surface.

[0009] The base and the first line layer may have portions disposed at the same height as each other in a height measured in a direction perpendicular to the first surface.

[0010] The base and the protrusion may have the same width at a height of the first surface.

[0011] The circuit board may further include a first solder resist layer disposed on the first surface and configured to cover the first line layer.

[0012] The bump may be disposed to penetrate the first solder resist layer.

[0013] The bump may protrude from the first solder resist layer.

[0014] The protrusion may be disposed to contact the first solder resist layer.

[0015] The first solder resist layer may be provided to surround a portion of a side surface of the protrusion.

[0016] The bump may include copper (Cu).

[0017] The circuit board may further include a build-up structure disposed on the second surface of the first insulating layer and including a plurality of build-up insulating layers and a plurality of build-up line layers.

[0018] The circuit board may further include a second solder resist layer disposed on the buildup insulating layer disposed at the outermost side of the plurality of buildup insulating layers.

[0019] According to an embodiment, a method for manufacturing a circuit board includes: forming a conductive layer including a second metal on a seed layer including a first metal; forming a bump layer on the seed layer exposed by etching the conductive layer; forming an insulating layer and a line layer above the conductive layer; removing the seed layer to form a bump on the bump layer; removing the conductive layer to make the bump protrude from the insulating layer; and forming a solder resist layer on a surface of the insulating layer from which the bump protrudes.

[0020] The first metal may include copper (Cu), and the second metal may include nickel (Ni).

[0021] The step of forming the bump layer may include: forming a plating resist on the conductive layer and patterning the plating resist to expose the conductive layer; removing the exposed portion of the conductive layer to expose the seed layer; and forming the bump layer by plating the first metal on the exposed seed layer.

[0022] The bump may be formed to have a maximum width at a height of the one surface of the insulating layer and a minimum width at an uppermost end of the bump in a direction of protruding from the insulating layer.

[0023] The method may further include the step of forming a buildup structure on another surface of the insulating layer. The buildup structure may include a plurality of buildup insulating layers and a plurality of buildup line layers.

[0024] The conductive layer and the seed layer may be formed on an insulating plate, and the insulating plate may be removed after the buildup structure is formed.

[0025] Based on the method of manufacturing a circuit board according to the embodiment, a fine pitch metal bump may be accurately implemented by preventing misalignment between the metal bump (pillar) and the line.

[0026] Therefore, based on the circuit board according to the embodiment, the board and the chip can be simply bonded by providing metal bumps with a fine pitch. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a cross-sectional view showing a circuit board according to an embodiment.

[0028] Figures 2 to 14 It shows the manufacturing Figure 1 A process cross-sectional view of the circuit board method shown in FIG. DETAILED DESCRIPTION

[0029] The present disclosure will be described more fully below with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. The drawings and description are to be considered schematic and non-restrictive in nature. Throughout the specification, similar reference numerals represent similar elements. In the accompanying drawings, the size of each element is arbitrarily shown for ease of description, and the present disclosure is not necessarily limited to those shown in the accompanying drawings.

[0030] In addition, the drawings are only used to facilitate understanding of the embodiments disclosed in this specification, and the technical ideas disclosed in this specification are not limited by the drawings, and all changes included in the spirit and technical scope of the present disclosure should be understood to include equivalent solutions or alternative solutions.

[0031] Terms including ordinal numbers such as first, second, etc. may be used to describe various constituent elements, but the constituent elements are not limited by the terms. These terms are used only for the purpose of distinguishing one constituent element from another constituent element.

[0032] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "over" another element, it can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, throughout the specification, the words "on" or "over" a target element will be understood as being disposed above or below the target element, and will not necessarily be understood as being disposed on the "upper side" based on a direction opposite to the direction of gravity.

[0033] In the present disclosure, terms such as "include" or "have" are intended to indicate the presence of the features, quantities, steps, operations, components, or combinations thereof described in the specification, and should be understood as not excluding the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, or combinations thereof. In addition, unless explicitly described to the contrary, the word "include" and variations such as "comprises" or "have" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0034] Furthermore, throughout the specification, the phrase "on a plane" means observing a target portion from above, and the phrase "on a cross section" means observing a cross section formed by vertically cutting a target portion from the side.

[0035] In addition, throughout the specification, “connected” means not only that two or more constituent elements are directly connected but also that two or more constituent elements are indirectly connected via another constituent element, or that two or more constituent elements are physically or electrically connected, and “connected” may include a case where substantially integral components are connected to each other although they are represented by different names according to position or function.

[0036] Figure 1 is a cross-sectional view showing a circuit board according to an embodiment.

[0037] Reference Figure 1 The circuit board 100 according to the present embodiment includes a first insulating layer 111 and a first line layer 113 buried in the first insulating layer 111. The first line layer 113 and the first insulating layer 111 may constitute an embedded trace substrate (ETS) structure. The circuit board 100 may be a printed circuit board that can be used for a semiconductor package.

[0038] The first insulating layer 111 may have a first surface 111a and a second surface 111b opposite to each other. The bump 115 may protrude above the first surface 111a of the first insulating layer 111. The bump 115 includes a base 115b buried in the first insulating layer 111 and a protrusion 115c integrally extending from the base 115b to protrude above the first surface 111a. The base 115b may be disposed transversely to the first line layer 113 to be buried in the first insulating layer 111. That is, as Figure 1As shown in , the base 115b may be adjacent to the first line layer 113 in the horizontal direction and buried in the first insulating layer 111. Therefore, in the height measured in the direction perpendicular to the first surface 111a, the base 115b may have a portion disposed at the same height as the height of the first line layer 113. The protrusion 115c may have a maximum width at the height of the first surface 111a, and may have a minimum width at the uppermost end of the protrusion 115c. For example, the protrusion 115c may gradually become narrower along the direction protruding from the first surface 111a. Here, the widths of the protrusion 115c at different heights may be compared with each other based on the width measured in the direction parallel to the first surface 111a (e.g., the above-mentioned horizontal direction) in the cross section of the protrusion 115c. The bump 115 may be formed into a column shape by the base 115b and the protrusion 115c connected as one, and may include copper (Cu).

[0039] The first line layer 113 may not protrude above the first insulating layer 111, and may constitute a circuit line for signal transmission, power supply, grounding, etc. within the first insulating layer 111. The bump 115 may be exposed above the first insulating layer 111 through the protrusion 115c to be connected to a terminal of an electronic component (not shown) such as an IC chip.

[0040] The first insulating layer 111 may include a resin insulating layer. The first insulating layer 111 may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material (e.g., prepreg) prepared by impregnating a reinforcing material such as glass fiber or an inorganic filler in a resin. In addition, the first insulating layer 111 may further include a photocurable resin, but the present disclosure is not limited thereto.

[0041] The width, diameter or cross-sectional area of ​​the protrusion 115c of the bump 115 may be gradually reduced along the direction protruding from the first surface 111a. The direction protruding from the first surface 111a may be the same direction as the thickness direction of the first insulating layer 111. That is, the protrusion 115c may have a trapezoidal cross-section having a narrow top and a wide bottom based on the first surface 111a. Therefore, the width, diameter or cross-sectional area of ​​the bump 115 may be gradually reduced along the thickness direction of the first insulating layer 111.

[0042] The protrusion 115c may have the same width as that of the base 115b buried in the first insulating layer 111 at the height of the first surface 111a. The width of the protrusion 115c and the width of the base 115b may be measured in a direction parallel to the first surface 111a of the first insulating layer 111. Therefore, the protrusion 115c may have a width gradually reduced from the base 115b at the height of the first surface 111a, and may protrude above the first surface 111a.

[0043] The first solder resist layer 131 may be disposed on the first surface 111a of the first insulating layer 111. The first solder resist layer 131 may be configured to cover the first wire layer 113. The bump 115 may be disposed to penetrate the first solder resist layer 131. The bump 115 may be disposed to protrude from the first solder resist layer 131. In this case, the protrusion 115c may be disposed to contact the first solder resist layer 131. In addition, a portion of a side surface of the protrusion 115c may be surrounded by the first solder resist layer 131.

[0044] The stacking structure 120 may be disposed on the second surface 111b of the first insulating layer 111. The stacking structure 120 may include a stacking insulating layer and a stacking line layer. The stacking insulating layer may include a plurality of insulating layers 121, and the stacking line layer may include a plurality of line layers 123 buried in each of the plurality of insulating layers 121 and / or a plurality of line layers 125 disposed on each of the plurality of insulating layers.

[0045] The outermost wire layer 125 may be disposed on the outermost insulating layer 121 of the stacking structure 120, which is disposed at a side of the first insulating layer 111 opposite to the first surface 111a of the first insulating layer 111. The outermost insulating layer 121 may be covered with a second solder resist layer 132, and at least a portion of the outermost wire layer 125 may be exposed through an opening of the second solder resist layer 132. For example, the second solder resist layer 132 may be disposed on the stacking insulating layer 121 disposed at the outermost side of the stacking insulating layer of the stacking structure 120. The exposed outermost wire layer 125 may be used as a pad connected to another external component.

[0046] Figures 2 to 14 It shows the manufacturing Figure 1 The process cross-sectional view of the circuit board method shown in FIG. Figure 1 as well as Figures 2 to 14 A method of manufacturing a circuit board is described.

[0047] Reference Figure 2 and Figure 3 , a carrier plate 80 may be prepared in which a seed layer 84 including a first metal is provided on at least one surface of an insulating plate 81, and a conductive layer 92 including a second metal may be formed on the seed layer 84. The carrier plate 80 may be a copper clad laminate (CCL) including the insulating plate 81 and the seed layer 84. The first metal and the second metal may be metals having different etching conditions, the first metal may include copper (Cu), and the second metal may include nickel (Ni).

[0048] Reference Figure 4 and Figure 5, a first plating resist 71 is formed (eg, coated) on the conductive layer 92, and the first plating resist 71 is patterned to partially expose the conductive layer 92. The exposed portion of the conductive layer 92 may be removed by etching. The first plating resist 71 may be formed by forming only Fig.14 The portion of the bump 115 is exposed and developed to remove the resist pattern.

[0049] The seed layer 84 may be partially exposed by etching the conductive layer 92 to form the opening 92a. In this case, the etching degree of the conductive layer 92 may become weaker as the seed layer 84 is approached in the direction from the upper surface toward the lower surface of the conductive layer 92. Therefore, as the seed layer 84 is approached in the direction from the upper surface toward the lower surface of the conductive layer 92, the width, diameter, or cross-sectional area of ​​the opening 92a of the conductive layer 92 may gradually decrease.

[0050] Reference Figure 6 and Figure 7 , a bump layer 115A is formed by plating a first metal on an exposed portion of the seed layer 84, and the first plating resist 71 is removed. The bump layer 115A may be made of the same metal material as that of the seed layer 84 to be integrally connected to the seed layer 84, and may be stacked along the opening portion of the conductive layer 92 and the first plating resist 71. In a height measured in a direction perpendicular to one surface of the insulating plate 81 on which the seed layer 84 is formed, the bump layer 115A may be formed to be higher than the conductive layer 92, and may be formed to be lower than the first plating resist 71. Therefore, if the first plating resist 71 is removed, the bump layer 115A may be provided to protrude above the conductive layer 92.

[0051] Reference Figure 8 , a second plating resist 72 is formed (e.g., coated) on the conductive layer 92, and the second plating resist is patterned to partially expose the conductive layer 92. The second plating resist 72 may be formed to cover the bump layer 115A, and the exposed portion of the conductive layer 92 may have a planar position different from that of the bump layer 115A.

[0052] Reference Fig. 9 and Fig.10, a first metal is plated on the exposed portion of the conductive layer 92 to form a first wire layer 113, and the second plating resist 72 is removed. The first wire layer 113 may have a planar position different from that of the bump layer 115A, and may be partially formed at the same height as that of the bump layer 115A. However, although not shown in the drawings, because the first wire layer 113 and the bump layer 115A are formed by two independent processes, the height of the first wire layer 113 may be different from (e.g., less than or greater than) the height of the bump layer 115A with reference to the upper surface of the conductive layer 92. In addition, because the conductive layer 92 includes the second metal, the conductive layer 92 can be distinguished from the first wire layer 113 including the first metal by forming a boundary with the first wire layer 113. If the second plating resist 72 is removed, the first wire layer 113 and the bump layer 115A may be arranged to protrude above the conductive layer 92.

[0053] Reference Fig.11 , a buildup structure 120 including a buildup insulating layer and a buildup wire layer is formed over the bump layer 115A and the first wire layer 113. Although not shown, a buildup via layer may be formed in the buildup insulating layer to connect the buildup wire layer to the first wire layer 113. Fig.11 As shown in the diagram, the stacking structure 120 is stacked in the direction from bottom to top, so according to Fig.11 As shown in the diagram of FIG. 1 , the stacked via layer may have a tapered shape with a size decreasing from top to bottom. Each of the stacked insulating layer and the stacked line layer may be formed to have a plurality of layers. In this case, the outermost line layer 125 may be provided to protrude above the outermost insulating layer 121.

[0054] Reference Fig.12 and Fig.13 , the seed layer 84 of the carrier plate 80 is separated from the insulating plate 81, and the seed layer 84 is etched to remove the seed layer 84. The seed layer 84 may be removed by soft etching. If the seed layer 84 is removed, the bump layers 115A are separated from each other to form a plurality of bumps 115, and the conductive layer 92 may be maintained as it is.

[0055] Reference Fig.14 and Figure 1, the conductive layer 92 is removed by etching, and a first solder resist layer 131 and a second solder resist layer 132 are respectively formed on the first insulating layer 111 and the outermost insulating layer 121. Because the conductive layer 92 includes the second metal, even if the conductive layer 92 is etched, the bump 115 and the first line layer 113, which each include the first metal and have different etching conditions, can be maintained. Among the portions of the bump 115, the portion buried in the first insulating layer 111 may become the base 115b, and the portion buried in the conductive layer 92 may become the protrusion 115c. The protrusion 115c may be formed to have a maximum width at a surface height of the first insulating layer 111 (i.e., a height of the first surface 111a of the first insulating layer 111) and a minimum width at the uppermost end of the protrusion 115c along the protruding direction, so as to be aligned with the opening 92a of the conductive layer 92 (e.g., Figure 5 and Figure 6 The shape of the ) is matched.

[0056] A first solder resist layer 131 may be formed on the first insulating layer 111 and the bump 115 may penetrate the first solder resist layer 131. A second solder resist layer 132 may be formed on the outermost insulating layer 121 and a portion of the outermost wire layer 125 may be exposed.

[0057] Although the present disclosure has been described in conjunction with the embodiments, it will be understood that the present disclosure is not limited to the disclosed embodiments. Instead, the present disclosure is intended to cover various modifications and equivalents included within the spirit and scope of the appended claims.

Claims

1. A circuit board, comprising: A first insulating layer having a first surface and a second surface opposite to each other; A first line layer, buried in the first insulating layer; as well as A bump includes a base and a protrusion, wherein the base is arranged transversely to the first line layer to be buried in the first insulating layer, the protrusion extends integrally from the base and protrudes above the first surface, and the width of the protrusion at its upper end is smaller than the width of the protrusion at the height of the first surface.

2. The circuit board according to claim 1, wherein: The width of the protrusion is largest at the height of the first surface, and the width of the protrusion is smallest at the upper end.

3. The circuit board according to claim 1, wherein: The width of the protrusion decreases in a direction away from the first surface.

4. The circuit board according to claim 1, wherein: The base has a portion disposed at the same height as that of the first line layer in a height measured in a direction perpendicular to the first surface.

5. The circuit board according to claim 1, wherein: The base and the protrusion have the same width at a height of the first surface. 6 . The circuit board according to claim 1 , further comprising a first solder resist layer disposed on the first surface and configured to cover the first line layer.

7. The circuit board according to claim 6, wherein: The bump is disposed to penetrate the first solder resist layer.

8. The circuit board according to claim 7, wherein: The bump protrudes from the first solder resist layer.

9. The circuit board according to claim 6, wherein: The protrusion is provided to contact the first solder resist layer.

10. The circuit board according to claim 6, wherein: The first solder resist layer is provided to surround a portion of a side surface of the protruding portion.

11. The circuit board according to claim 1, wherein: The bumps include copper. 12 . The circuit board according to claim 1 , further comprising a build-up structure, the build-up structure being disposed on the second surface of the first insulating layer and comprising a plurality of build-up insulating layers and a plurality of build-up line layers. 13 . The circuit board according to claim 12 , further comprising a second solder resist layer disposed on the buildup insulating layer disposed at the outermost side of the plurality of buildup insulating layers.

14. A method for manufacturing a circuit board, comprising: forming a conductive layer including a second metal on the seed layer including the first metal; forming a bump layer on the seed layer exposed by etching the conductive layer; forming an insulating layer and a line layer above the conductive layer; removing the seed layer so that the bump layer forms bumps; removing the conductive layer so that the bump protrudes from the insulating layer; as well as A solder resist layer is formed on one surface of the insulating layer from which the bump protrudes.

15. The method according to claim 14, wherein: The first metal includes copper and the second metal includes nickel.

16. The method according to claim 14, wherein: The step of forming the bump layer includes: forming a plating resist on the conductive layer and patterning the plating resist to expose the conductive layer; removing the exposed portion of the conductive layer to expose the seed layer; and The bump layer is formed by plating the first metal on the exposed seed layer.

17. The method according to claim 14, wherein: The bump is formed to have a maximum width at a height of the one surface of the insulating layer and a minimum width at an uppermost end of the bump in a direction protruding from the insulating layer.

18. The method according to claim 14, further comprising the step of forming a buildup structure on another surface of the insulating layer, in, The build-up structure includes a plurality of build-up insulating layers and a plurality of build-up line layers.

19. The method according to claim 18, wherein: The conductive layer and the seed layer are formed on an insulating plate, and the insulating plate is removed after the buildup structure is formed.

20. The method according to any one of claims 14 to 19, wherein: The bump protrudes from the solder resist layer.

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