A variable capacitor and its manufacturing method
By forming electrode structures and depletion regions in the grooves of the semiconductor substrate, the problems of large area occupation and high adjustment difficulty of planar variable capacitor devices are solved, achieving precise control of capacitance value and cost reduction, and improving product performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN XINXIN SEMICON MFG CO LTD
- Filing Date
- 2024-12-06
- Publication Date
- 2026-05-26
AI Technical Summary
Existing planar variable capacitors occupy a large active area, which affects miniaturization. The accuracy of capacitance adjustment is difficult to control, resulting in high cost, high adjustment difficulty, and impact on product performance.
A first electrode structure is formed in a first groove of a semiconductor substrate, corresponding to the sidewall of the groove, and a depletion region is formed when a voltage is applied to the gate structure. The portion outside the active region is used as a second electrode structure to form a variable capacitor.
This effectively reduces the area occupied by the capacitor structure, lowers costs, increases the difficulty and accuracy of capacitor value adjustment, and improves product performance.
Smart Images
Figure CN119730257B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a variable capacitor and its manufacturing method. Background Technology
[0002] In semiconductor technology, capacitors are widely used devices. Among them, existing variable capacitors are usually planar structures, that is, the structure of existing variable capacitor devices is usually polysilicon gate-oxide-PW (P-type well) substrate / NW (N-type well) substrate.
[0003] The researchers of this application discovered that existing planar variable capacitors require a large active area (AA), which affects the miniaturization of the device. Furthermore, variable capacitors are usually adjusted by changing the relative effective area between the electrode plates or the distance between the electrode plates. The accuracy of the adjustment is not easy to control, which leads to high cost of variable capacitors and high difficulty in adjusting the capacitance value, thus affecting the performance of subsequent products. Summary of the Invention
[0004] The main technical problem solved by this invention is to provide a variable capacitor and its manufacturing method, wherein a first electrode structure is formed in a first groove of a semiconductor substrate, and at least a portion of the first electrode structure is opposite to a first sidewall of the first groove. When a gate voltage is applied to the gate structure, a depletion region is formed in the active region, and at least a portion of the active region outside the depletion region is used as a second electrode structure. This can effectively reduce the area occupied by the capacitor structure, reduce costs, and increase the difficulty and accuracy of capacitor value adjustment, thereby improving the performance of subsequent products.
[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a variable capacitor device, comprising: a semiconductor substrate, wherein the semiconductor substrate has an active region, and a first groove is formed on one side of the active region, and an insulating structure is disposed in the first groove; a first electrode structure, at least a portion of the first electrode structure covers the insulating structure in the first groove, and at least a portion of the first electrode structure is opposite to a first sidewall of the first groove, the first sidewall being adjacent to the well region; a gate structure, at least a portion of the gate structure is disposed on the active region, wherein when a gate voltage is applied to the gate structure, a depletion region is formed in the active region, and at least a portion of the active region outside the depletion region serves as a second electrode structure, constituting a variable capacitor with the first electrode structure.
[0006] In one embodiment of this application, the semiconductor substrate includes: a semiconductor substrate having an active region therein, and a first groove formed in the semiconductor substrate on one side of the active region, wherein a first doped region and a second doped region are formed in the active region, the first doped region being formed within the semiconductor substrate, the second doped region being close to the surface of the semiconductor substrate, the first doped region being in contact with the second doped region, and the bottom of the first groove extending to at least a portion of the first doped region; and an insulating structure filling the first groove and covering the semiconductor substrate.
[0007] In one embodiment of this application, the insulating structure includes: a first oxide layer, the first oxide layer at least partially covering a first sidewall of the first groove; a dielectric layer covering the first oxide layer and filling the first groove; and covering the semiconductor substrate, wherein a second groove is formed in the dielectric layer in the first groove, and at least partially covering a second sidewall of the second groove of the first electrode structure.
[0008] In one embodiment of this application, the first sidewall of the first groove is in contact with at least the second doped region; wherein, the second sidewall of the second groove is parallel to the first sidewall, so that at least a portion of the first electrode structure is disposed parallel to the first oxide layer, and at least a portion of the first electrode structure is disposed parallel to the second doped region.
[0009] In one embodiment of this application, it further includes: a second oxide layer, the second oxide layer filling the second groove, wherein the second oxide layer is isolated from the dielectric layer by the first electrode layer.
[0010] In one embodiment of this application, the gate structure includes: a third oxide layer, at least partially covering the insulating structure on the second doped region, and at least partially covering the insulating structure and the first electrode structure in the first groove; a gate layer, the gate layer covering the third oxide layer, and at least partially located on the second doped region; and isolation sidewalls covering the sidewalls on both sides of the gate layer.
[0011] In one embodiment of this application, it further includes: an interlayer dielectric layer covering the first electrode structure and the gate structure, and a connecting post is formed in the interlayer dielectric layer, the connecting post including: a first connecting post and a second connecting post; wherein, the first connecting post is correspondingly connected to the first electrode structure, and the second connecting post is correspondingly connected to the gate structure.
[0012] In one embodiment of this application, a doped lead-out region is further formed in the active region, wherein the doped lead-out region is in contact with a second doped region in the active region; the connecting post further includes a third connecting post, wherein the third connecting post is correspondingly connected to the doped lead-out region, so that the second electrode structure is connected to the outside through the doped lead-out region and the third connecting post.
[0013] To solve the above-mentioned technical problems, another technical solution adopted in this application is: providing a method for manufacturing a variable capacitor, comprising: providing a semiconductor substrate, wherein the semiconductor substrate has an active region, and a first groove is formed in the semiconductor substrate on one side of the active region, and an insulating structure is disposed in the first groove; forming a first electrode structure, wherein at least a portion of the first electrode structure covers the insulating structure in the first groove, and at least a portion of the first electrode structure is opposite to a first sidewall of the first groove; forming a gate structure, wherein at least a portion of the gate structure is disposed on the active region, wherein when a gate voltage is applied to the gate structure, a depletion region is formed in the active region, and at least a portion of the active region outside the depletion region serves as a second electrode structure, which together with the first electrode structure constitutes a variable capacitor.
[0014] In one embodiment of this application, providing a semiconductor substrate includes: providing a semiconductor substrate and forming an active region in the semiconductor substrate, wherein a first doped region and a second doped region are formed in the active region, the first doped region being formed within the semiconductor substrate, the second doped region being close to the surface of the semiconductor substrate, and the first doped region being in contact with the second doped region; forming a first groove located on one side of the active region, wherein the bottom of the first groove extends at least to at least a portion of the depth of the first doped region; and forming an insulating structure that fills the first groove and covers the semiconductor substrate.
[0015] In one embodiment of this application, forming an insulating structure includes: forming a first oxide layer, wherein at least a portion of the first oxide layer covers a first sidewall of the first groove; forming a dielectric layer, covering the first oxide layer and filling the first groove, and covering the semiconductor substrate, wherein a second groove is formed in the dielectric layer in the first groove, and at least a portion of the first electrode structure covers a second sidewall of the second groove.
[0016] In one embodiment of this application, the first sidewall of the first groove is in contact with at least the second doped region; wherein, the second sidewall of the second groove is parallel to the first sidewall, so that at least a portion of the first electrode structure is disposed parallel to the first oxide layer, and at least a portion of the first electrode structure is disposed parallel to the second doped region.
[0017] In one embodiment of this application, the method further includes: forming a second oxide layer, the second oxide layer filling the second groove, wherein the second oxide layer is isolated from the dielectric layer by the first electrode structure.
[0018] In one embodiment of this application, forming a gate structure includes: forming a third oxide layer, at least partially covering the second doped region and at least partially covering the insulating structure and the first electrode structure in the first groove; forming a gate layer, the gate layer covering the third oxide layer and at least partially located on the second doped region; and forming an isolation sidewall covering the sidewalls on both sides of the gate layer.
[0019] In one embodiment of this application, the method further includes: forming an interlayer dielectric layer covering the first electrode structure and the gate structure, wherein a connecting post is formed in the interlayer dielectric layer, and the connecting post includes: a first connecting post and a second connecting post; wherein the first connecting post is correspondingly connected to the first electrode structure, and the second connecting post is correspondingly connected to the gate structure.
[0020] In one embodiment of this application, before forming the interlayer dielectric layer, the method further includes: forming a doped lead-out region in the active region, wherein the doped lead-out region is in contact with a second doped region in the active region; the connecting post further includes a third connecting post, wherein the third connecting post is correspondingly connected to the doped lead-out region, so that the second electrode structure is connected to the outside through the doped lead-out region and the third connecting post.
[0021] Unlike current technologies, the variable capacitor device provided in this application includes a semiconductor substrate, a first electrode structure, and a gate structure. The semiconductor substrate has an active region, and a first groove is formed on one side of the active region. An insulating structure is disposed in the first groove. At least a portion of the first electrode structure covers the insulating structure in the first groove, and at least a portion of the first electrode structure is opposite to a first sidewall of the first groove. At least a portion of the gate structure is disposed on the active region. When a gate voltage is applied to the gate structure, a depletion region is formed in the active region. At least a portion of the active region outside the depletion region serves as a second electrode structure, forming a variable capacitor with the first electrode structure. In other words, by forming a first electrode structure covering the sidewall of the first groove in the semiconductor substrate, the area occupied by the capacitor structure is reduced, effectively lowering costs. Furthermore, by using at least a portion of the active region outside the depletion region formed by the applied gate voltage as the second electrode structure, the width of the depletion region can be controlled according to the gate voltage, thereby allowing for accurate adjustment of the capacitor value, reducing adjustment difficulty, and ultimately improving the performance of subsequent products. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0023] Figure 1 This is a schematic diagram of the structure of the first embodiment of the variable capacitor device in this application;
[0024] Figure 2 This is a schematic diagram of the structure of the second embodiment of the variable capacitor device in this application;
[0025] Figure 3 This is a schematic flowchart of an embodiment of the manufacturing method of the variable capacitor device in this application;
[0026] Figure 4 This is a schematic diagram of a structure in an embodiment of forming the first doped region and the second doped region in this application;
[0027] Figure 5 This is a schematic diagram of the structure of an embodiment in which the first groove is formed in this application;
[0028] Figure 6 This is a schematic diagram of an embodiment of the insulating structure formed in this application;
[0029] Figure 7 This is a schematic diagram of an embodiment of the first electrode structure in this application;
[0030] Figure 8 This is a schematic diagram of an embodiment of the gate structure formed in this application;
[0031] Figure 9 This is a schematic diagram of a structure of an embodiment of forming an interlayer dielectric layer and connecting pillars in this application.
[0032] In the attached figures, there are semiconductor substrate 100, semiconductor substrate 110, active region 111, first doped region 1111, second doped region 1112, depletion region A, first trench 101, first sidewall 1011, insulating structure 120, first oxide layer 121, dielectric layer 122, second trench 102, second oxide layer 130, first electrode structure 200, gate structure 300, third oxide layer 310, gate layer 320, isolation sidewall 330, interlayer dielectric layer 400, first connecting post 401, second connecting post 402, third connecting post 403, and doped lead-out region B. Detailed Implementation
[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0034] Current capacitor devices, especially variable capacitor devices, are typically planar in structure. That is, the structure of current variable capacitor devices is usually polysilicon gate-oxide-PW substrate / NW substrate. Because it is a planar structure, it occupies a large area of active area (AA), which makes the cost of variable capacitor devices high. Moreover, the capacitance value is usually adjusted by changing the relative effective area between the electrode plates or the distance between the electrode plates. Adjusting the capacitance value is difficult and affects the performance of subsequent products.
[0035] Therefore, this application provides a variable capacitor device that, by forming a first electrode structure in a first groove of a semiconductor substrate, with at least a portion of the first electrode structure facing the first sidewall of the first groove, and using a substrate portion in the active region other than the depletion region as the second electrode structure, can effectively reduce the area occupied by the capacitor structure, reduce costs, and improve the difficulty and accuracy of capacitor value adjustment.
[0036] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the variable capacitor device in this application.
[0037] The variable capacitor device of this application includes: a semiconductor substrate 100, a first electrode structure 200, and a gate structure 300; the semiconductor substrate 100 has an active region 111, and a first groove 101 is formed in the semiconductor substrate 100 on one side of the active region 111, and an insulating structure 120 is disposed in the first groove 101. At least a portion of the first electrode structure 200 covers the insulating structure 120 in the first groove 101, and at least a portion of the first electrode structure 200 is opposite to a first sidewall 1011 in the first groove 101. At least a portion of the gate structure 300 is disposed on the active region 111, wherein, when a gate voltage is applied to the gate structure 300, a depletion region A is formed in the active region 111, and at least a portion of the active region 111 outside the depletion region A serves as a second electrode structure, and the second electrode structure and the first electrode structure 200 constitute a variable capacitor.
[0038] The first electrode structure 200 can be a metal layer of uniform thickness.
[0039] In some embodiments, the magnitude of the gate voltage can alter the horizontal thickness of the depletion region, thereby affecting the capacitance value of the variable capacitor. The capacitance value of the variable capacitor can be adjusted according to the magnitude of the gate voltage in a negatively correlated manner; that is, the larger the gate voltage, the greater the horizontal thickness of the depletion region, the greater the distance between the first electrode structure and the second electrode structure, and thus the smaller the capacitance value of the variable capacitor; conversely, the smaller the gate voltage, the smaller the horizontal thickness of the depletion region, the smaller the distance between the first electrode structure and the second electrode structure, and thus the larger the capacitance value of the variable capacitor.
[0040] In this embodiment, by forming a first electrode structure in a first groove of a semiconductor substrate, with at least a portion of the first electrode structure facing the first sidewall of the first groove, and applying a gate voltage to the gate structure, a depletion region is formed in the active region. At least a portion of the active region outside the depletion region serves as the second electrode structure. The width of the depletion region can be controlled according to the gate voltage, thereby effectively reducing the area occupied by the capacitor structure, reducing costs, and increasing the difficulty and accuracy of capacitor value adjustment, thereby improving the performance of subsequent products.
[0041] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of the second embodiment of the variable capacitor device in this application.
[0042] like Figure 2 As shown, the semiconductor substrate 100 includes a semiconductor substrate 110 and an insulating structure 120. The semiconductor substrate 110 has an active region 111, and a first groove 101 is formed in the semiconductor substrate 110 on one side of the active region 111. The active region 111 may have a first doped region 1111 and a second doped region 1112. The first doped region 1111 is formed within the semiconductor substrate 110, and the second doped region 1112 is close to the surface of the semiconductor substrate 110, with the first doped region 1111 and the second doped region 1112 in contact. The bottom of the first groove 101 extends to at least a portion of the first doped region 1111. The insulating structure 120 fills the first groove 101 and covers the surface of the semiconductor substrate 100, specifically covering the surface of the semiconductor substrate 110 and the surface of the second doped region 1112.
[0043] The semiconductor substrate 110 can be any suitable substrate known in the art.
[0044] In some embodiments, the first doped region 1111 and the second doped region 1112 in the active region 111 can be doped regions of different types, i.e., with opposite doping types; for example, the first doped region 1111 is an N-type doped region, and the second doped region is a P-type doped region. Furthermore, the first doped region 1111 is located away from the surface of the semiconductor substrate 110, while the second doped region is located close to the surface of the semiconductor substrate 110, such as... Figure 2 As shown, the second doped region 1112 is on the first doped region 1111, and the second doped region 1112 is close to the surface of the semiconductor substrate 110.
[0045] In some embodiments, the first groove 101 can be a trapezoidal groove, a rectangular groove, a square groove, an inverted trapezoidal groove, etc., which can be set according to the actual situation.
[0046] In some embodiments, the first sidewall 1011 of the first groove 101 may be adjacent to the active region 111, while the third sidewall (not shown in the figure) of the first groove 101 may be in contact with the semiconductor substrate or another active region; wherein, a portion of the semiconductor substrate may be present between the first sidewall 1011 and the active region 111, so that the first sidewall 1011 and the active region 111 do not contact each other, but have a certain distance; in another embodiment, the first sidewall 1011 may also be in direct contact with the active region 111, that is, the first sidewall 1011 of the first groove 101 is in contact with the active region 111, while the third sidewall of the first groove 101 is in contact with the semiconductor substrate or another active region. Figure 2 Taking the contact between the first sidewall 1011 and the active region 111 as an example.
[0047] It is understandable that the first sidewall 1011 is an attachment. Figure 2 If the first groove 101 is on the right side wall, then the third side wall is the side wall where the first groove 101 is on the left side wall.
[0048] Furthermore, the depth of the first groove 101 can be the same as the depth of the doped region, that is, the distance from the bottom of the first groove 101 to the bottom of the semiconductor substrate is equal to the distance from the bottom surface of the first doped region 1111 to the bottom of the semiconductor substrate. Alternatively, it can be slightly less than the depth of the doped region, that is, the distance from the bottom of the first groove 101 to the bottom of the semiconductor substrate is slightly less than the distance from the bottom surface of the first doped region 1111 to the bottom of the semiconductor substrate. Or it can be slightly greater than the depth of the doped region, that is, the distance from the bottom of the first groove 101 to the bottom of the semiconductor substrate is slightly greater than the distance from the bottom surface of the first doped region 1111 to the bottom of the semiconductor substrate.
[0049] Continue reading Figure 2The insulating structure 120 may include a first oxide layer 121 and a dielectric layer 122. At least a portion of the first oxide layer 121 covers the first sidewall 1011 of the first groove 101. The dielectric layer 122 covers the first oxide layer 121 and fills the first groove 101.
[0050] The first oxide layer 121 can be made of an oxide material, and the dielectric layer 122 can be made of a dielectric material.
[0051] In some embodiments, the first oxide layer 121 may cover the entire inner sidewall of the first groove 101, that is, cover the first sidewall 1011, the third sidewall and the first bottom wall of the first groove 101, and then form a dielectric layer 122 on the first oxide layer 121, such that the dielectric layer 122 can cover the first oxide layer 121.
[0052] The first sidewall 1011 of the first groove 101 is in contact with the second doped region 1112, thereby allowing the first oxide layer 121 to contact the second doped region 1112.
[0053] Furthermore, the dielectric layer 122 can also cover the surface of the semiconductor substrate 110, that is, the dielectric layer 122 covers the surface of the semiconductor substrate 110 outside the first groove 101; the first electrode structure 200 covers the dielectric layer 122 on the side of the first groove 101 away from the second doped region 1112, and the first electrode structure 200 is in contact with the dielectric layer 122.
[0054] In some embodiments, a second groove 102 is further formed in the dielectric layer 122 of the first groove 101, then at least a portion of the first electrode structure 200 covers the second sidewall 1021 of the second groove 102. Furthermore, the second sidewall 1021 of the second groove 102 is parallel to the first sidewall 1011 of the first groove 101, so that at least a portion of the first electrode structure 200 is arranged parallel to the first oxide layer 121, and at least a portion of the first electrode structure 200 is arranged parallel to the second doped region 1112.
[0055] Furthermore, the second groove 102 may include a second sidewall 1021, a fourth sidewall (not shown in the figure), and a second bottom wall (not shown in the figure). The second sidewall 1021 of the second groove 102 is parallel to the first sidewall 1011 of the first groove 101, the fourth sidewall (not shown in the figure) of the second groove 102 is parallel to the third sidewall (not shown in the figure) of the first groove 101, and the second bottom wall of the second groove 102 is parallel to the first bottom wall (not shown in the figure) of the first groove 101. Additionally, the distance between the second bottom wall of the second groove 102 and the first bottom wall of the first groove 101 can be set according to actual conditions; that is, the depth of the first groove 101 is greater than the depth of the second groove 102, and the specific depth difference can be set according to actual conditions.
[0056] Continue reading Figure 2 It also includes a second oxide layer 130, which fills the second groove 102 so that the second oxide layer 130 is isolated from the dielectric layer 122 by the first electrode structure 200, and the surface of the second oxide layer 130 can be flush with the first electrode structure 200 on the dielectric layer 122.
[0057] The material of the second oxide layer 130 can be an oxide material.
[0058] Continue reading Figure 2 The gate structure 300 may include a third oxide layer 310, a gate layer 320, and an isolation sidewall 330. At least a portion of the third oxide layer 310 covers the insulating structure 120 on the second doped region 1112, and at least a portion of the third oxide layer 310 covers the insulating structure 120 and the first electrode structure 200 in the first recess 101; the gate layer 320 covers the third oxide layer 310, and at least a portion of the gate layer 320 is located on the second doped region 1112; the isolation sidewall 330 covers the sidewalls on both sides of the gate layer 320, and further, the isolation sidewall 330 may also cover the sidewalls on both sides of the third oxide layer 310.
[0059] The third oxide layer 310 is made of an oxide material; the gate layer 320 is made of a gate material, such as polysilicon; and the isolation sidewall 330 is made of an isolation material.
[0060] Specifically, a portion of the third oxide layer 310 covers a portion of the dielectric layer 122, the first electrode structure 200, and the second oxide layer 130 within the first groove 101; another portion of the third oxide layer 310 covers at least a portion of the second doped region 1112, specifically, another portion of the third oxide layer 310 covers the dielectric layer 122 on the second doped region 1112.
[0061] Continue reading Figure 2 It may also include an interlayer dielectric layer 400 covering the first electrode structure 200 and the gate structure 300. Connecting pillars are formed in the interlayer dielectric layer 400, including a first connecting pillar 401 and a second connecting pillar 402. The first connecting pillar 401 is connected to the first electrode structure 200, and the second connecting pillar 402 is connected to the gate structure 300.
[0062] In some embodiments, a doped lead-out region B is also formed in the active region 111, and the doped lead-out region B is in contact with the second doped region 1112. The corresponding connecting post also includes a third connecting post 403, which is connected to the doped lead-out region B. When a gate voltage is applied to the gate structure 300, a depletion region A is formed in the active region 111, and at least a portion of the active region 111 outside the depletion region A serves as the second electrode structure. That is, the depletion region A is formed in the second doped region 1112, and at least a portion of the second doped region 1112 outside the depletion region A serves as the second electrode structure. The second doped region 1112 is in contact with the doped lead-out region B, so that the second electrode structure is connected to the outside through the doped lead-out region B and the third connecting post 403.
[0063] Specifically, the first connecting post 401 connects to the first electrode structure 200 and connects the first electrode structure 200 to an external power supply (Vin) for applying a bias voltage. The second connecting post 402 connects to the gate structure 300 and connects the gate structure 300 to a power supply (DC) for applying a gate voltage, forming a depletion region A in the second doped region 1112. At least a portion of the second doped region outside the depletion region serves as the second electrode structure. The second doped region 1112 is in contact with the doped lead-out region B. Therefore, the third connecting post 403 connects the doped lead-out region B to the second electrode structure so that the second electrode structure is grounded (GND) through the third connecting post 403.
[0064] The working principle is as follows: Applying different forward gate voltages to the gate structure can change the initial thickness of the dielectric layer between the first and second electrode structures, that is, change the first thickness A1 of the depletion region A in the vertical direction, and also change the second thickness A2 of the depletion region A in the horizontal direction. Further, applying a forward voltage to the first electrode structure 200 can change the second thickness A2 of the depletion region A in the horizontal direction from the first sidewall 1011. That is, when a gate voltage is applied, the depletion region A is formed, and the first thickness A1 of the depletion region A in the vertical direction and the second thickness A2 of the depletion region A in the horizontal direction from the first sidewall 1011 of the first groove appear; increasing the gate voltage can increase the first thickness A1, and may even increase the second thickness A2; further applying a forward voltage to the first electrode structure 200 can increase the second thickness A2. Therefore, by controlling the voltage applied to the first electrode structure and the gate voltage applied to the gate structure, variable control of the capacitance value of the variable capacitor can be achieved, where the capacitance is the series capacitance corresponding to the initial thickness of the dielectric layer and the first thickness of the depletion region A in the horizontal direction.
[0065] In this embodiment, by forming a first electrode structure in a first groove of a semiconductor substrate, and at least a portion of the first electrode structure being opposite to the first sidewall of the first groove, a depletion region is formed in the active region when a gate voltage is applied to the gate structure, and at least a portion of the active region other than the depletion region formed in the active region is used as the second electrode structure, the area occupied by the capacitor structure can be effectively reduced, the cost can be reduced, and the difficulty and accuracy of capacitor value adjustment can be increased, thereby improving the performance of subsequent products.
[0066] This application also provides a method for manufacturing a variable capacitor.
[0067] See Figure 3 , Figure 3 This is a schematic flowchart of an embodiment of the manufacturing method of the variable capacitor device in this application.
[0068] like Figure 3 As shown, a method for manufacturing a variable capacitor may include the following steps.
[0069] S10. A semiconductor substrate is provided, wherein the semiconductor substrate has an active region, and a first groove is formed in the semiconductor substrate on one side of the active region, and an insulating structure is disposed in the first groove.
[0070] The semiconductor substrate includes a semiconductor substrate.
[0071] Specifically, an active region 111 is formed in the semiconductor substrate 110, wherein a first doped region 1111 and a second doped region 1112 are formed in the active region 111; then a first groove 101 is formed in the semiconductor substrate 110, and an insulating structure 120 is formed in the first groove 101.
[0072] S20. A first electrode structure is formed, at least a portion of which covers the insulating structure in the first groove, and at least a portion of the first electrode structure is opposite to the first sidewall of the first groove.
[0073] Specifically, a first electrode structure 200 is formed in the first groove 101 to cover the insulating structure 120 in the first groove 101, and at least a portion of the first electrode structure 200 in the first groove 101 is opposite to the first sidewall 1011 of the first groove 101. It can be understood that at least a portion of the opposite first electrode structure 200 is arranged parallel to the first sidewall 1011 of the first groove 101, and an insulating structure 120 is also provided between the first electrode structure 200 and the first sidewall 1011 of the first groove 101.
[0074] S30. A gate structure is formed, at least a portion of which is disposed on the active region. When a gate voltage is applied to the gate structure, a depletion region is formed in the active region. At least a portion of the active region outside the depletion region serves as a second electrode structure, which together with the first electrode structure constitutes a variable capacitor.
[0075] Wherein, at least a portion of the second doped region 1112 serves as the second electrode structure, that is, when a gate voltage is applied to the gate structure 300, at least a portion of the second doped region 1112 in the active region 111 forms a depletion region A, and at least a portion of the second doped region 1112 outside the depletion region A serves as the second electrode structure.
[0076] Specifically, a gate structure 300 is formed on the first groove 101 and the second doped region 1112, such that at least a portion of the gate structure 300 is located on the second doped region 1112 of the active region 111. When a gate voltage is applied to the gate structure 300, at least a portion of the second doped region 1112 between the first doped region 1111 and the gate structure 300 forms a depletion region A. The at least portion of the second doped region 1112 outside the depletion region A is used as a second electrode structure, and electrons flow from the first doped region 1111 towards the gate structure 300.
[0077] In this embodiment, by forming a first electrode structure in a first groove of a semiconductor substrate, and at least a portion of the first electrode structure is opposite to the first sidewall of the first groove, when a gate voltage is applied to the gate structure, a depletion region is formed in the second doped region, and at least a portion of the second doped region outside the depletion region is used as the second electrode structure. This can effectively reduce the area occupied by the capacitor structure, reduce costs, and increase the difficulty and accuracy of capacitor value adjustment, thereby improving the performance of subsequent products.
[0078] The manufacturing method of the variable capacitor is described below with reference to the accompanying drawings.
[0079] First, a semiconductor substrate is provided, and an active region is formed in the semiconductor substrate, wherein a first doped region and a second doped region are formed in the active region.
[0080] See Figure 4 , Figure 4 This is a schematic diagram of a structure in an embodiment of forming the first doped region and the second doped region in this application.
[0081] like Figure 4As shown, a first doped region 1111 and a second doped region 1112 are formed in the active region 111 of the semiconductor substrate 110, and the first doped region 1111 and the second doped region 1112 constitute a part of the active region 111. The first doped region 1111 is formed in the semiconductor substrate 110, and the second doped region 1112 is close to the surface of the semiconductor substrate 110, and the first doped region 1111 and the second doped region 1112 are in contact.
[0082] Then, a first groove 101 is formed in the semiconductor substrate 110.
[0083] See Figure 5 , Figure 5 This is a schematic diagram of an embodiment of forming the first groove in this application.
[0084] like Figure 5 As shown, in Figure 4 Based on this, a first groove 101 is formed in the semiconductor substrate 110. The bottom of the first groove 101 may be flush with the bottom of the first doped region 1111, or slightly higher than the bottom of the first doped region 1111, or slightly lower than the bottom of the first doped region 1111.
[0085] In some embodiments, the first sidewall 1011 of the first groove 101 is adjacent to the active region 111, that is, a portion of the semiconductor substrate 110 may exist between the first sidewall 1011 and the active region 111. In another embodiment, the first sidewall 1011 of the first groove 101 may contact the active region 111, that is, there is no semiconductor substrate 110 between the first sidewall 1011 and the active region 111.
[0086] Furthermore, an insulating structure 120 is formed in the first groove 101.
[0087] See Figure 6 , Figure 6 This is a schematic diagram of an embodiment of forming an insulating structure in this application.
[0088] like Figure 6 As shown, in Figure 5 Based on this, a first oxide layer 121 is formed in the first groove. At least a portion of the first oxide layer 121 covers the first sidewall 1011 of the first groove 101, thereby forming a dielectric layer 122. The dielectric layer 122 covers the first oxide layer 121 and fills the first groove 101, with the first oxide layer 121 and the dielectric layer 122 serving as an insulating structure 120.
[0089] In some embodiments, the dielectric layer 122 may also cover the surface of the active region 111. Further, the dielectric layer 122 may also cover the entire surface of the semiconductor substrate 110.
[0090] In some embodiments, a second groove 102 may also be formed in the dielectric layer of the first groove 101. The second sidewall of the second groove 102 corresponds to and is parallel to the first sidewall 1011 of the first groove 101. The fourth sidewall of the second groove 102 corresponds to and is parallel to the third sidewall of the first groove 101. The second bottom wall of the second groove 102 corresponds to and is parallel to the first bottom wall of the first groove 101.
[0091] Furthermore, a first electrode structure 200 is formed.
[0092] See Figure 7 , Figure 7 This is a schematic diagram of an embodiment of forming the first electrode structure in this application.
[0093] like Figure 7 As shown, in Figure 6 Based on this, a first electrode structure 200 is formed in the second groove 102 and on the dielectric layer 122 on the side of the second groove 102 away from the active region 111, such that at least a portion of the first electrode structure 200 covers the insulating structure 120 in the first groove 101, and at least a portion of the first electrode structure 200 is opposite to the first sidewall 1011 of the first groove 101.
[0094] In some embodiments, a second oxide layer 130 may be formed to cover the first electrode structure 200 in the second groove 102 and fill the second groove 102, and the second oxide layer 130 may be flush with the first electrode structure 200 on the semiconductor substrate; in other embodiments, the second oxide layer 130 may be flush with the dielectric layer 122 on the semiconductor substrate 110.
[0095] In some embodiments, when forming the first electrode structure 200, the first electrode structure 200 may also cover the semiconductor substrate 110 of the active region 111. Then, before forming the gate structure 300, the first electrode structure 200 of the active region 111 is removed, while the first electrode structure 200 in the second groove 102 and on the semiconductor substrate 110 on the side of the second groove 102 away from the active region 111 is retained.
[0096] Furthermore, a gate structure 300 is formed.
[0097] See Figure 8 , Figure 8 This is a schematic diagram of an embodiment of the gate structure formed in this application.
[0098] like Figure 8 As shown, in Figure 7Based on this, a third oxide layer 310 is formed, covering the entire semiconductor substrate. Then, a gate material is formed on the third oxide layer 310. Then, a portion of the gate material and the third oxide layer 310 on the first groove 101 and a portion on the active region 111 are removed, leaving the remaining gate material as the gate layer 320. Isolation sidewalls 330 are formed on the sidewalls on both sides of the gate layer 320. This results in at least a portion of the third oxide layer 310 covering the insulating structure 120 on the second doped region 1112, and at least a portion of the third oxide layer 310 covering the insulating structure 120, the first electrode structure 200, and the second oxide layer 130 in the first groove 101.
[0099] In some embodiments, ion implantation can also be performed in the second doped region 1112 to form a doped extraction region B, which is in contact with the second doped region 1112. The doped extraction region B can be a lightly doped region, such as a P-type lightly doped region.
[0100] Furthermore, an interlayer dielectric layer and connecting pillars are formed.
[0101] See Figure 9 , Figure 9 This is a schematic diagram of a structure of an embodiment of forming an interlayer dielectric layer and connecting pillars in this application.
[0102] like Figure 9 As shown, in Figure 8 Based on this, an interlayer dielectric layer 400 is formed, which covers the first electrode structure 200 and the gate structure 300. Connecting posts are formed in the interlayer dielectric layer 400, which may include a first connecting post 401 and a second connecting post 402. The first connecting post 401 is connected to the first electrode structure 200 so that the first electrode structure 200 is connected to a power source (Vin) through the first connecting post 401. The second connecting post 402 is connected to the gate structure 300 so that the gate structure 300 is connected to a power source (DC) through the second connecting post 402.
[0103] In some embodiments, the connecting post may further include a third connecting post 403, which corresponds to the connection of the doped lead-out region B. When a gate voltage is applied to the gate structure 300, a depletion region A is formed in the active region 111, and at least a portion of the active region 111 outside the depletion region A serves as the second electrode structure. That is, a depletion region A is formed in the second doped region 1112, and at least a portion of the second doped region 1112 outside the depletion region A serves as the second electrode structure. The second doped region 1112 contacts the doped lead-out region B so that the second electrode structure is connected to the outside through the doped lead-out region B via the third connecting post 403. Specifically, the third connecting post 403 may be grounded (GND).
[0104] In this embodiment, a first electrode structure is formed in a first groove of the semiconductor substrate, and at least a portion of the first electrode structure is opposite to the first sidewall of the first groove. When a gate voltage is applied to the gate structure, a depletion region is formed in the active region. At least a portion of the active region other than the depletion region formed in the active region is used as the second electrode structure. This can effectively reduce the area occupied by the capacitor structure, reduce costs, and increase the difficulty and accuracy of capacitor value adjustment, thereby improving the performance of subsequent products.
[0105] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A variable capacitor, characterized in that, include: A semiconductor substrate, wherein the semiconductor substrate has an active region, and a first groove is formed on one side of the active region, and an insulating structure is disposed in the first groove; a first doped region and a second doped region are formed in the active region, the first doped region is formed in the semiconductor substrate of the semiconductor substrate, the second doped region is close to the surface of the semiconductor substrate, the first doped region is in contact with the second doped region, and the bottom of the first groove extends to at least a portion of the first doped region; A first electrode structure, wherein at least a portion of the first electrode structure covers the insulating structure in the first groove, and at least a portion of the first electrode structure is opposite to a first sidewall of the first groove; A gate structure, at least a portion of which is disposed on the active region and at least a portion of which is located on the first electrode structure, wherein the gate structure includes a third oxide layer, a gate layer, and isolation sidewalls, at least a portion of which covers a second doped region in the active region and at least a portion of which covers the insulating structure and the first electrode structure in the first groove, the gate layer covers the third oxide layer and at least a portion of which is located on the second doped region, and the isolation sidewalls cover the sidewalls on both sides of the gate layer; when a gate voltage is applied to the gate structure, a depletion region is formed in the active region, and at least a portion of the active region outside the depletion region serves as a second electrode structure, forming a variable capacitor with the first electrode structure.
2. The variable capacitor device according to claim 1, characterized in that, The semiconductor substrate includes: A semiconductor substrate, wherein the semiconductor substrate has an active region, and a first groove is formed in the semiconductor substrate on one side of the active region; An insulating structure fills the first groove and covers the semiconductor substrate.
3. The variable capacitor device according to claim 2, characterized in that, The insulating structure includes: A first oxide layer, wherein the first oxide layer at least partially covers the first sidewall of the first groove; A dielectric layer covers the first oxide layer and fills the first groove, and covers the semiconductor substrate, wherein a second groove is formed in the dielectric layer in the first groove, and at least a portion of the first electrode structure covers the second sidewall of the second groove.
4. The variable capacitor according to claim 3, characterized in that, The first sidewall of the first groove is in contact with at least the second doped region; Wherein, the second sidewall of the second groove is parallel to the first sidewall, so that at least a portion of the first electrode structure is arranged parallel to the first oxide layer, and at least a portion of the first electrode structure is arranged parallel to the second doped region.
5. The variable capacitor according to claim 3, characterized in that, Also includes: A second oxide layer fills the second groove, wherein the second oxide layer is isolated from the dielectric layer by the first electrode structure.
6. The variable capacitor device according to claim 1, characterized in that, Also includes: An interlayer dielectric layer covers the first electrode structure and the gate structure, and a connecting pillar is formed in the interlayer dielectric layer, the connecting pillar including: a first connecting pillar and a second connecting pillar; The first connecting post is connected to the first electrode structure, and the second connecting post is connected to the gate structure.
7. The variable capacitor according to claim 6, characterized in that, The active region also includes a doped extraction region, wherein the doped extraction region is in contact with a second doped region in the active region. The connecting post further includes a third connecting post, wherein the third connecting post is correspondingly connected to the doped lead-out region, so that the second electrode structure is connected to the outside through the doped lead-out region via the third connecting post.
8. A method for manufacturing a variable capacitor, characterized in that, include: A semiconductor substrate is provided, wherein the semiconductor substrate has an active region, and a first groove is formed in the semiconductor substrate on one side of the active region, the first groove being provided with an insulating structure; a first doped region and a second doped region are formed in the active region, the first doped region being formed within a semiconductor substrate of the semiconductor substrate, the second doped region being close to the surface of the semiconductor substrate, and the first doped region being in contact with the second doped region, the bottom of the first groove extending at least to at least a portion of the depth of the first doped region; A first electrode structure is formed, wherein at least a portion of the first electrode structure covers the insulating structure in the first groove, and at least a portion of the first electrode structure is opposite to the first sidewall of the first groove; A gate structure is formed, at least a portion of which is disposed on the active region and at least a portion of which is located on the first electrode structure. The gate structure includes a third oxide layer, a gate layer, and isolation sidewalls. At least a portion of the third oxide layer covers a second doped region in the active region and at least a portion of the third oxide layer covers the insulating structure and the first electrode structure in the first groove. The gate layer covers the third oxide layer and at least a portion of the gate layer is located on the second doped region. The isolation sidewalls cover the sidewalls on both sides of the gate layer. When a gate voltage is applied to the gate structure, a depletion region is formed in the active region. At least a portion of the active region outside the depletion region serves as a second electrode structure, forming a variable capacitor with the first electrode structure.
9. The manufacturing method according to claim 8, characterized in that, The provision of the semiconductor substrate includes: A semiconductor substrate is provided, and an active region is formed in the semiconductor substrate; A first groove is formed, and the first groove is located on one side of the active region; An insulating structure is formed, which fills the first groove and covers the semiconductor substrate.
10. The manufacturing method according to claim 9, characterized in that, The formation of the insulating structure includes: A first oxide layer is formed, wherein the first oxide layer at least partially covers the first sidewall of the first groove; A dielectric layer is formed to cover the first oxide layer and fill the first groove, and to cover the semiconductor substrate, wherein a second groove is formed in the dielectric layer in the first groove, and at least a portion of the first electrode structure covers the second sidewall of the second groove.
11. The manufacturing method according to claim 10, characterized in that, The first sidewall of the first groove is in contact with at least the second doped region; Wherein, the second sidewall of the second groove is parallel to the first sidewall, so that at least a portion of the first electrode structure is arranged parallel to the first oxide layer, and at least a portion of the first electrode structure is arranged parallel to the second doped region.
12. The manufacturing method according to claim 10, characterized in that, Also includes: A second oxide layer is formed, which fills the second groove, wherein the second oxide layer is isolated from the dielectric layer by the first electrode structure.
13. The manufacturing method according to claim 8, characterized in that, Also includes: An interlayer dielectric layer is formed to cover the first electrode structure and the gate structure, and a connecting pillar is formed in the interlayer dielectric layer, the connecting pillar including: a first connecting pillar and a second connecting pillar; The first connecting post is connected to the first electrode structure, and the second connecting post is connected to the gate structure.
14. The manufacturing method according to claim 13, characterized in that, Before forming the interlayer dielectric layer, it also includes: A doped extraction region is formed in the active region, wherein the doped extraction region is in contact with a second doped region in the active region; The connecting post further includes a third connecting post, wherein the third connecting post is correspondingly connected to the doped lead-out region, so that the second electrode structure is connected to the outside through the doped lead-out region via the third connecting post.