Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present application discloses a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductor, and can improve the capacitance density of a capacitor in the semiconductor structure, reduce the occupied area of the capacitor, and reduce the size of the semiconductor structure. A device stack in the semiconductor structure comprises a capacitor and a transistor. The transistor comprises an epitaxial layer, a dielectric layer and a conductive layer. The epitaxial layer is configured as a first electrode plate layer of the capacitor; the epitaxial layer is located between adjacent first isolation structures and second isolation structures and / or between two adjacent second isolation structures. The dielectric layer is configured as an intermediate dielectric layer between two electrode plate layers of the capacitor; the dielectric layer covers the epitaxial layer and covers the second isolation structures; a part of the dielectric layer covering the second isolation structures away from a side surface of the semiconductor substrate is characterized as a groove. The conductive layer is configured as a second electrode plate layer of the capacitor; the conductive layer covers the dielectric layer and is filled in the groove.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the technological advancements in the semiconductor industry, the density of semiconductor devices per unit area is increasing, and the size of semiconductor devices is continuously shrinking. Improving the performance of each semiconductor element (such as transistors and capacitors) within a semiconductor structure (e.g., integrated circuits) has always been a crucial research direction. For example, research focuses on the capacitance density and occupied area of ​​MOS capacitors. Consequently, the complexity and cost of fabrication processes for MOS capacitors based on transistor structures are also key areas of focus in the research process. Summary of the Invention

[0003] In view of this, the semiconductor structure and its fabrication method provided in this application can improve the capacitance density of the capacitor in the semiconductor structure, reduce the occupied area of ​​the capacitor, reduce the size of the semiconductor structure, and also reduce the complexity and cost of the semiconductor structure fabrication process.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] On one hand, embodiments of this application provide a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a device stack. The semiconductor substrate includes a first isolation structure and at least one second isolation structure disposed within the area enclosed by the first isolation structure; the first isolation structure and the second isolation structure are respectively located at opposite ends along a direction perpendicular to the plane of the semiconductor substrate, with one end exposed from the same side surface of the semiconductor substrate and the other end located within the semiconductor substrate.

[0006] A device stack is disposed on one side of the semiconductor substrate, including a capacitor and a transistor. The transistor includes an epitaxial layer, a dielectric layer, and a conductive layer.

[0007] An epitaxial layer is disposed on one side surface of the semiconductor substrate and is configured as the first electrode layer of the capacitor; the epitaxial layer is located between adjacent first isolation structures and second isolation structures, and / or between two adjacent second isolation structures.

[0008] A dielectric layer is disposed on the side of the epitaxial layer away from the semiconductor substrate and is configured as an intermediate dielectric layer between the two electrode layers of the capacitor; the dielectric layer covers the epitaxial layer and covers the second isolation structure; wherein, the surface of the portion of the dielectric layer covering the second isolation structure away from the semiconductor substrate is characterized as a groove.

[0009] A conductive layer is disposed on the side of the dielectric layer away from the semiconductor substrate and is configured as the second electrode layer of the capacitor; the conductive layer covers the dielectric layer and fills the groove.

[0010] In some examples, the first isolation structure surrounds a plurality of spaced-apart second isolation structures. The second isolation structures are not connected to the first isolation structure; and / or, along a stacking direction perpendicular to the semiconductor substrate and the device stack, one end of one of the opposite ends of the second isolation structure is connected to the first isolation structure; the epitaxial layer has a continuous structure. The conductive layer fills all of the grooves characterized on the surface of the dielectric layer.

[0011] In some examples, the first isolation structure surrounds a plurality of spaced-apart second isolation structures. Along a stacking direction perpendicular to the semiconductor substrate and the device stack, opposite ends of the second isolation structure are connected to the first isolation structure; the epitaxial layer comprises a plurality of spaced epitaxial patterns.

[0012] The dielectric layer covers a plurality of the epitaxial patterns and the second isolation structure between two adjacent epitaxial patterns; the conductive layer fills all the grooves characterized on the surface of the dielectric layer.

[0013] In some examples, the epitaxial layer includes a spaced first electrode region and a second electrode region; the first electrode region is coupled to a first transition structure; and the second electrode region is coupled to a second transition structure.

[0014] The conductive layer includes a first conductive portion and a second conductive portion connected together. The first conductive portion covers the region of the epitaxial layer except for the area coupled to the first and second transition structures. The second conductive portion is disposed on the side of the first isolation structure away from the semiconductor substrate.

[0015] In some examples, the epitaxial layer includes a plurality of spaced epitaxial patterns; the first electrode region includes first sub-electrode regions located in different epitaxial patterns, and the second electrode region includes second sub-electrode regions located in different epitaxial patterns. One first sub-electrode region is coupled to one first transition structure, and the first sub-electrode regions of the plurality of epitaxial patterns are respectively coupled to each other through a plurality of first transition structures. One second sub-electrode region is coupled to one second transition structure, and the second sub-electrode regions of the plurality of epitaxial patterns are respectively coupled to each other through a plurality of second transition structures.

[0016] In some examples, the dimension of the first isolation structure along the direction perpendicular to the plane of the semiconductor substrate is greater than the dimension of the second isolation structure along the direction perpendicular to the plane of the semiconductor substrate;

[0017] A first isolation structure encloses a device region; the semiconductor structure includes a plurality of the device regions, with two adjacent device regions sharing a portion of the first isolation structure.

[0018] In some examples, the semiconductor substrate includes a silicon-on-insulator layer.

[0019] In the aforementioned semiconductor structure, an epitaxial layer is disposed on one side of the semiconductor substrate. This epitaxial layer can serve as the active layer of a transistor structure. In other words, from a semiconductor fabrication perspective, the epitaxial layer is fabricated after the semiconductor substrate is formed, rather than using a portion of the semiconductor substrate material as the epitaxial layer structure during substrate fabrication. This simplifies the fabrication process and reduces costs. Based on this semiconductor substrate, transistors and capacitors are then disposed. The epitaxial layer (the active layer of the transistor) serves as the first electrode layer of the capacitor, and the conductive layer (the gate layer of the transistor) serves as the second electrode layer. Thus, without increasing the thickness of the dielectric layer (i.e., without affecting the gate's control over the channel region), the epitaxial layer, formed based on multiple spaced second isolation structures, can characterize multiple grooves on the surface of the dielectric layer. The conductive layer can continuously extend along the side edges of the epitaxial layer, covering the grooved areas. This also provides a portion of the conductive layer on the sidewalls of the epitaxial layer, increasing the relative area between the epitaxial layer and the conductive layer, thereby increasing the capacitor's capacitance. Furthermore, while maintaining the same capacitance, it reduces the area occupied by a single capacitor, decreases the size of the semiconductor structure, and increases the capacitance density of the semiconductor structure.

[0020] On the other hand, this application also provides a method for fabricating a semiconductor structure. The fabrication method includes forming a semiconductor substrate; the semiconductor substrate includes a first isolation structure and at least one second isolation structure disposed within a region enclosed by the first isolation structure; one end of each of the first isolation structure and the second isolation structure along a direction perpendicular to the plane of the semiconductor substrate is exposed from the same side surface of the semiconductor substrate, and the other end is located within the semiconductor substrate.

[0021] An epitaxial layer is formed on one side surface of the semiconductor substrate; the epitaxial layer is configured as a first electrode layer of a capacitor; the epitaxial layer is located between adjacent first isolation structures and second isolation structures, and / or between two adjacent second isolation structures.

[0022] A dielectric layer is formed on the side of the epitaxial layer away from the semiconductor substrate; the dielectric layer is configured as an intermediate dielectric layer between the two electrode layers of the capacitor; the dielectric layer covers the epitaxial layer and covers the second isolation structure; wherein the surface of the portion of the dielectric layer covering the second isolation structure away from the semiconductor substrate is characterized as a groove.

[0023] A conductive layer is formed on the side of the dielectric layer away from the semiconductor substrate, and the conductive layer is configured as the second electrode layer of the capacitor; the conductive layer covers the dielectric layer and fills the groove.

[0024] In some examples, forming the semiconductor substrate includes: forming a first trench and at least one second trench located within the region enclosed by the first trench on an initial semiconductor substrate; the depth of the first trench is greater than the depth of the second trench; the first trench surrounds the second trench. Wherein, at least one end of the second trench along a direction perpendicular to the plane of the semiconductor substrate is connected to the first trench; or, the second trench is spaced apart from the first trench. A dielectric material is deposited within the first trench and the second trench to form the first isolation structure and the second isolation structure, thereby obtaining the semiconductor substrate.

[0025] In some examples, forming the semiconductor substrate includes: forming an epitaxial layer comprising a plurality of spaced epitaxial patterns; or forming an epitaxial layer with a continuous structure; the epitaxial layer comprising spaced first electrode regions and second electrode regions. A first transition structure coupled to the first electrode region and a second transition structure coupled to the second electrode region are formed. The conductive layer covers the region of the epitaxial layer other than those coupled to the first and second transition structures.

[0026] The above-described semiconductor structure fabrication method produces the semiconductor structure as provided in any of the above examples. The technical effects achieved by the above-described semiconductor structure fabrication method are the same as those achieved by the semiconductor structure provided in any of the above examples, and will not be repeated here. Furthermore, in the process of fabricating transistors and capacitors using the semiconductor structure fabrication method provided in any of the above examples, the use of an epitaxial layer growth process on a semiconductor substrate, compared to the method of increasing trench depth in related technologies, reduces the process difficulty and cost of fabricating the active layer of the transistor. Moreover, it can be integrated into the current semiconductor structure fabrication process, exhibiting high compatibility.

[0027] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0028] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0029] Figure 2 A top view of a capacitor with a semiconductor structure provided in an embodiment of this application. Figure 1 ;

[0030] Figure 3 A top view of a capacitor with a semiconductor structure provided in an embodiment of this application. Figure 2 ;

[0031] Figure 4 A top view of a capacitor with a semiconductor structure provided in an embodiment of this application. Figure 3 ;

[0032] Figure 5 A top view of a capacitor with a semiconductor structure provided in an embodiment of this application. Figure 4 ;

[0033] Figure 6 for Figure 2 A cross-sectional schematic diagram of a semiconductor structure along the BB direction is provided;

[0034] Figure 7 for Figure 2 A cross-sectional view of a semiconductor structure along the AA direction is provided;

[0035] Figure 8 A flowchart illustrating a method for fabricating a semiconductor structure provided in this application embodiment. Figure 1 ;

[0036] Figure 9 (a) in Figure 9 (g) is a schematic cross-sectional view of a semiconductor structure fabrication method provided in an embodiment of this application;

[0037] Figure 10 A flowchart illustrating a method for fabricating a semiconductor structure provided in this application embodiment. Figure 2 . Detailed Implementation

[0038] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0039] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0040] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0044] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0045] With the technological development of the semiconductor industry, the density of semiconductor devices per unit area is getting higher and higher, and the size of semiconductor devices is constantly shrinking. In integrated circuit (IC) devices, which are formed by multiple semiconductor elements (such as transistors and capacitors), improving the performance of each semiconductor element has always been an important research direction in the industry.

[0046] For example, capacitors can include metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, and metal-oxide-semiconductor (MOS) capacitors. Among these, MOS capacitors are widely used due to their compatibility in fabrication processes, simple structural design, and small footprint.

[0047] Improving the capacitance density and reducing the footprint of MOS capacitors is a key research direction. Consequently, the complexity and cost of fabrication processes for MOS capacitors based on transistor structures are also important aspects of the research.

[0048] Based on this, embodiments of this application provide a semiconductor structure and its fabrication method, which can increase the capacitance density of MOS capacitors in the semiconductor structure, reduce the occupied area of ​​MOS capacitors, reduce the size of the semiconductor structure, and also reduce the complexity and cost of the semiconductor structure fabrication process.

[0049] In some embodiments, such as Figures 1 to 7As shown, this application provides a semiconductor structure 100. For example, the semiconductor structure 100 can be a chip, a die, or a wafer. It should be noted that chip and die can refer to the same structure (the names can be interchanged), or a die can be an unpackaged chip. Different levels of chip structures can be set according to requirements; for example, chip, die, and wafer are three different levels of chip structures. The embodiments provided in this application do not limit this; any semiconductor structure with transistors can be implemented using the technology provided in this application. Subsequent examples will use "semiconductor structure" for illustrative purposes.

[0050] In some examples, such as Figure 1 As shown, the semiconductor structure 100 includes a semiconductor substrate 110 and a device stack 120. The device stack 120 is disposed on one side of the semiconductor substrate 110.

[0051] For example, the semiconductor substrate 110 may be a multilayer composite structure of dielectric and conductive materials containing circuit structures. For instance, the semiconductor substrate 110 may include a silicon on insulator (SOI) layer.

[0052] For example, device stack 120 may include multiple transistors. The transistors may include field-effect transistors (FETs). FETs include other transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and silicon-on-insulator field-effect transistors (SOI FETs), and this application does not impose specific limitations on them; they can be configured according to requirements. For example, if the semiconductor substrate 110 is made of SOI material, the device stack 120 formed on the semiconductor substrate 110 may include SOI FET transistors. The active layer, gate dielectric layer, and gate layer of the field-effect transistor may form a MOS capacitor.

[0053] like Figure 1 As shown, the device stack 120 can be divided into multiple device regions N. Multiple transistors T can be disposed within a single device region N, or only one transistor T can be disposed within it. A single transistor portion can form a MOS capacitor. The number of transistors T within a single device region N can be adjusted while ensuring the gate of each transistor T has sufficient control over the channel region.

[0054] It should be noted that the "device region" defined in this application is not limited to a specific physical structure, but rather includes the area containing electronic components. It can be divided according to actual circumstances, and this application does not impose specific limitations. Furthermore, the area size of the device region N can also be adjusted according to the dimensions of the actual semiconductor structure 100; different device regions N can have different areas, and the number of transistors T within different device regions N can also be different. For example, as shown... Figure 1 A transistor and a MOS capacitor composed of partial layers of this transistor can be disposed within a device region N. The MOS capacitor C obtained in this application based on the layer structure of transistor T mainly focuses on setting the structural features of the active layer (i.e., the epitaxial layer mentioned in later examples, serving as one electrode layer of the capacitor) and the gate layer (i.e., the conductive layer mentioned in later examples, serving as the other electrode layer of the capacitor) of transistor T without affecting the transistor performance. This exemplifies the influence of the relative area size of the two electrode layers of the capacitor on the capacitance density and occupied area. The following example illustrates the layer structure of a semiconductor structure 100 within a device region N.

[0055] In some examples, such as Figure 1 As shown, the semiconductor substrate 110 includes a first isolation structure 111 and at least one second isolation structure 112 disposed within the area enclosed by the first isolation structure 111. Each first isolation structure 111 encloses a device region N. The semiconductor structure 100 includes multiple device regions N, with adjacent device regions N sharing a portion of the first isolation structure 111.

[0056] For example, such as Figures 2-5 As shown, the second isolation structure 112 is not connected to the first isolation structure 111; and / or, along a direction perpendicular to the stacking of the semiconductor substrate 110 and the device stack 120 (X or Y), at least one end of the opposite ends of the second isolation structure 112 is connected to the first isolation structure 111. The structure and effects of the epitaxial layer 121, dielectric layer 122, and conductive layer 123 will be illustrated in subsequent examples in conjunction with the structures of the first isolation structure 111 and the second isolation structure 112.

[0057] For example, such as Figure 6 As shown, both the first isolation structure 111 and the second isolation structure 112 extend along a direction perpendicular to the plane of the semiconductor substrate 110. Furthermore, at opposite ends of the first isolation structure 111 and the second isolation structure 112 along the direction perpendicular to the plane of the semiconductor substrate 110, one end of each structure is exposed from the same side surface of the semiconductor substrate 110, and the other end of each structure is located within the semiconductor substrate 110.

[0058] Continue reading Figure 6The first isolation structure 111 can be a shallow trench isolation (STI) structure, which is used to separate different transistor device regions N (see [reference]). Figure 1 For example, multiple transistors that achieve the same functional effect can be grouped within the same device region N. STI can reduce interference between transistors T in different device regions N when they are performing different functions.

[0059] Furthermore, the second isolation structure 112 may be located within the area enclosed by the first isolation structure 111, and as follows: Figure 6 As shown, along the direction Z perpendicular to the plane where the semiconductor substrate 110 is located, the size of the second isolation structure 112 is smaller than the size of the first isolation structure 111. The second isolation structure 112 is used to separate the active layers (i.e., the epitaxial layer 121 mentioned in the following example) of different transistors within the area enclosed by the first isolation structure 111.

[0060] For example, the materials used for the first isolation structure 111 and the second isolation structure 112 may include oxide insulating materials.

[0061] In some examples, such as Figures 1 to 8 As shown, the aforementioned device stack 120 is disposed on one side of the semiconductor substrate 110, including a MOS capacitor C and a transistor T.

[0062] like Figure 6 As shown, transistor T includes an epitaxial layer 121, a dielectric layer 122, and a conductive layer 123. The epitaxial layer 121 is disposed on one side surface of the semiconductor substrate 110, configured as the active layer of transistor T, and serves as the first electrode layer of capacitor C.

[0063] The dielectric layer 122 is disposed on the side of the epitaxial layer 121 away from the semiconductor substrate 110, and is configured as the gate dielectric layer of the transistor T, and as the intermediate dielectric layer between the two plate layers of the capacitor C.

[0064] The conductive layer 123 is disposed on the side of the dielectric layer 122 away from the semiconductor substrate 110, and is configured as the gate of the transistor and as the second plate layer of the capacitor C.

[0065] Continue reading Figure 6 The epitaxial layer 121 is located between adjacent first isolation structures 111 and second isolation structures 112, and / or between two adjacent second isolation structures 112.

[0066] The epitaxial layer 121 can be located between adjacent first isolation structures 111 and second isolation structures 112. For example, a second isolation structure 112 is provided within the area enclosed by the first isolation structure 111 (i.e., within a device region N). In this way, two epitaxial layers 121 can be provided within the area enclosed by the first isolation structure 111, with each epitaxial layer 121 located between adjacent first isolation structures 111 and second isolation structures 112.

[0067] Alternatively, the epitaxial layer 121 can be located between two adjacent second isolation structures 112. For example, at least two second isolation structures 112 are provided within the area enclosed by the first isolation structure 111 (i.e., within a device region N). In this way, the epitaxial layer 121 can be provided only in the region between two adjacent second isolation structures 112 within the region enclosed by the first isolation structure 111. The region between adjacent first isolation structures 111 and second isolation structures 112 may not have an epitaxial layer 121.

[0068] Or, as Figure 6 As shown, a portion of the epitaxial layer 121 may be located between adjacent first isolation structures 111 and second isolation structures 112, and the remaining portion may be located between two adjacent second isolation structures 112. For example, at least two second isolation structures 112 are provided within the area enclosed by the first isolation structure 111 (i.e., within a device region N). Thus, the epitaxial layer 121 may be provided in the region between two adjacent second isolation structures 112 and in the region between adjacent first isolation structures 111 and second isolation structures 112 within the region enclosed by the first isolation structure 111.

[0069] Based on the number of the second isolation structures 112 and their connection with the first isolation structure 111, the surface area of ​​the epitaxial layer 121 can be increased, the area of ​​the subsequently fabricated conductive layer 123 can be increased, and the relative area of ​​the two plates of the MOS capacitor C formed by the epitaxial layer 121 and the conductive layer 123 can be increased.

[0070] Continue reading Figure 6 The dielectric layer 122 covers the epitaxial layer 121 and also covers the second isolation structure 112. The portion of the dielectric layer 122 covering the second isolation structure 112 has a groove 1221 on the side of its surface away from the semiconductor substrate 110.

[0071] For example, the material of the dielectric layer 122 includes one or more insulating materials such as silicon oxynitride (SiON), silicon oxide (SiO2), silicon nitride (SiN), or silicon carbide (SiC). The dielectric layer 122 is used to insulate the epitaxial layer 121 from the conductive layer 123. In this way, the dielectric layer 122 covers the epitaxial layer 121 on the semiconductor substrate 110, which can prevent the epitaxial layer 121 from being directly electrically connected to the subsequently formed conductive layer 123 when it is conductive. Moreover, the dielectric layer 122 extends from the surface of the epitaxial layer 121 to the surface of the second isolation structure 112 and covers the second isolation structure 112, which can prevent conductive particles in the conductive layer 123 from diffusing into the second isolation structure 112 after the subsequently formed conductive layer 123 comes into contact with the second isolation structure 112, thereby improving the reliability of the conductive layer 123 subsequently formed on the dielectric layer 122.

[0072] Continue reading Figure 6 The conductive layer 123 covers the dielectric layer 122 and fills the groove 1221.

[0073] For example, conductive layer 123 can be the gate of transistor T. Conductive layer 123 covers dielectric layer 122, which serves as the gate dielectric layer between the active layer and the gate layer in the transistor structure; that is, conductive layer 123 is not in contact with epitaxial layer 121. By setting conductive layer 123 to extend along the edge of epitaxial layer 121, the relative area between conductive layer 123 and epitaxial layer 121 can be increased. This not only improves the control capability of conductive layer 123 over the channel region of epitaxial layer 121, but also increases the capacitance density of the two plates of epitaxial layer 121 and conductive layer 123 as MOS capacitor C.

[0074] For example, the material used in the conductive layer 123 may include one or more of the following: a metallic element or compound, a semiconductor material, or a conductive polymer. For instance, the material used in the conductive layer 123 may include one or more of the following conductive elements or compounds: gold, silver, copper, aluminum, tin, etc.

[0075] It is understood that the shape and size of the groove 1221 (i.e., the shape and size of the corresponding second isolation structure 112) can be set according to the actual situation, as long as the material of the dielectric layer 122 and the material of the conductive layer 123 can be filled in the groove 1221.

[0076] In the aforementioned semiconductor structure 100, an epitaxial layer 121 is disposed on one side of the semiconductor substrate 110. The epitaxial layer 121 can serve as an active layer of a transistor structure. That is, from the perspective of semiconductor structure fabrication, the epitaxial layer 121 is fabricated after the semiconductor substrate 110 is formed, rather than using a portion of the semiconductor substrate 110 as the structure of the epitaxial layer 121 during the fabrication of the semiconductor substrate 110. This results in a simpler fabrication process and lower cost for the epitaxial layer 121. A transistor T and a MOS capacitor C are then disposed on this semiconductor substrate 110. The epitaxial layer 121 (the active layer of the transistor T) serves as the first electrode layer of the MOS capacitor C, and the conductive layer 123 (the gate layer of the transistor T) serves as the second electrode layer of the MOS capacitor C.

[0077] In this way, without increasing the thickness of the dielectric layer 122, i.e., without affecting the gate control capability of the transistor T over the channel region, the epitaxial layer 121 formed based on the multiple spaced second isolation structures 112 can characterize multiple grooves on the surface of the dielectric layer 122. The conductive layer 123 can extend continuously along the side edge of the epitaxial layer 121, covering the area where the dielectric layer 122 has grooves. Thus, a portion of the conductive layer 123 is also provided on the sidewall of the epitaxial layer 121, increasing the relative area between the epitaxial layer 121 and the conductive layer 123, and increasing the capacitance of the MOS capacitor C. Furthermore, without changing the capacitance, the area occupied by one MOS capacitor C can be reduced, the size of the semiconductor structure 100 can be reduced, and the capacitance density of the semiconductor structure 100 can be increased. Moreover, based on the relative positional relationship and structure of each layer in the semiconductor structure 100, it can be integrated into the current semiconductor structure fabrication process, exhibiting high compatibility.

[0078] In some examples, such as Figure 2 and Figure 3 As shown, the second isolation structure 112 is not connected to the first isolation structure 111. The epitaxial layer 121 has a continuous structure. The conductive layer 123 fills all the grooves 1221 characterized on the surface of the dielectric layer 122.

[0079] For example, such as Figure 2 As shown, a first isolation structure 111 surrounds a plurality of spaced second isolation structures 112. One second isolation structure 112 extends along a first direction X, and along the first direction X, neither of the opposite ends of the second isolation structure 112 is connected to the first isolation structure 111; the plurality of second isolation structures 112 are arranged in a row along a second direction Y; the second direction Y intersects the first direction X.

[0080] For example, such as Figure 3As shown, a first isolation structure 111 surrounds a plurality of spaced second isolation structures 112. The plurality of second isolation structures 112 are arranged in multiple rows along a first direction X and in multiple columns along a second direction Y; the second direction Y intersects the first direction X. The second isolation structures 112 are not connected to the first isolation structures 111.

[0081] Based on the connection between the second isolation structure 112 and the first isolation structure 111, the epitaxial layer 121 is formed in a continuous structure. In this way, the first transition structure 1241 and the second transition structure 1242 can be set one and one respectively in the subsequent setting, which reduces the number of transition structures, reduces the process cost and improves the flexibility of manufacturing transition structures.

[0082] Furthermore, the conductive layer 123 fills all the grooves 1221 characterized on the surface of the dielectric layer 122. The multiple grooves 1221 corresponding to the positions of the second isolation structure 112 can increase the relative area between the conductive layer 123 and the epitaxial layer 121, thereby increasing the capacitance density.

[0083] In other examples, such as Figure 4 As shown, along the stacking direction (X or Y) perpendicular to the semiconductor substrate 110 and the device stack 120, one end of the opposite ends of the second isolation structure 112 is connected to the first isolation structure.

[0084] The epitaxial layer 121 has a continuous structure. The conductive layer 123 fills all the grooves 1221 characterized on the surface of the dielectric layer 122.

[0085] For example, such as Figure 4 As shown, a first isolation structure 111 surrounds a plurality of spaced second isolation structures 112. One second isolation structure 112 extends along a second direction Y, and one end of each opposite end of the second isolation structure 112 is connected to the first isolation structure 111 along the second direction Y. The plurality of second isolation structures 112 are arranged in multiple rows along a first direction X; the second direction Y intersects with the first direction X.

[0086] For example, the shape of the cross-sectional pattern of the epitaxial layer 121 along the direction perpendicular to the plane of the semiconductor substrate 110 can be E-shaped (see [reference]). Figure 4 () or similar to an "S" shape.

[0087] Based on the connection between the second isolation structure 112 and the first isolation structure 111, the epitaxial layer 121 is formed in a continuous structure. In this way, the first transition structure 1241 and the second transition structure 1242 can be set one and one respectively in the subsequent setting, which reduces the number of transition structures, reduces the process cost and improves the flexibility of manufacturing transition structures.

[0088] Furthermore, the conductive layer 123 fills all the grooves 1221 characterized on the surface of the dielectric layer 122. The multiple grooves 1221 corresponding to the positions of the second isolation structure 112 can increase the relative area between the conductive layer 123 and the epitaxial layer 121, thereby increasing the capacitance density.

[0089] In some other examples, such as Figure 5 As shown, the semiconductor substrate 110 and the device stack 120 are stacked in the X or Y direction, and both ends of the second isolation structure 112 are connected to the first isolation structure 111.

[0090] The epitaxial layer 121 includes a plurality of spaced epitaxial patterns 1210.

[0091] The dielectric layer 122 covers a plurality of epitaxial patterns 1210 and a second isolation structure 112 between two adjacent epitaxial patterns 1210.

[0092] The conductive layer 123 fills all the grooves 1221 characterized on the surface of the dielectric layer 122.

[0093] For example, such as Figure 5 As shown, a first isolation structure 111 surrounds a plurality of spaced second isolation structures 112. The plurality of second isolation structures 112 are spaced along a second direction Y. One second isolation structure 112 extends along a first direction X, and along the first direction X, both opposite ends of the second isolation structure 112 are connected to the first isolation structure 111; the second direction Y intersects the first direction X.

[0094] For example, the first isolation structure 111 is square-ring-shaped, and the second isolation structure 112 is strip-shaped, connected to the two opposite sides of the first isolation structure 111, together forming a fence-like structure. Based on the connection relationship between the second isolation structure 112 and the first isolation structure 111, an epitaxial layer 121 is formed, including multiple spaced epitaxial patterns 1210. The conductive layer 123 fills all the grooves 1221 characterized on the surface of the dielectric layer 122. The multiple grooves 1221 corresponding to the positions of the second isolation structure 112 can increase the relative area between the conductive layer 123 and the epitaxial layer 121, thereby increasing the capacitance density. Moreover, a first transition structure 1241 and a second transition structure 1242 can be subsequently coupled to an epitaxial pattern 1210, which is beneficial to improving the electrical performance of the MOS capacitor C.

[0095] Besides the above-described example of setting the size and shape of the cross-sectional pattern of the second isolation structure 112 along the direction perpendicular to the plane of the semiconductor substrate 110, and its connection method with the first isolation structure 111, to adjust the shape and size of the epitaxial layer 121 formed between the first isolation structure 111 and the second isolation structure 112, and between two adjacent second isolation structures 112, there are other means to increase the top and side surface areas of the epitaxial layer 121 and increase the relative area between the epitaxial layer 121 and the conductive layer 123. This application does not impose specific limitations here, and can be set according to actual needs.

[0096] In some examples, combined Figure 2 The semiconductor structure shown can be determined along the AA cross-sectional view as follows: Figure 7 The structure shown is an example. Figure 7 As shown, the epitaxial layer 121 includes a first electrode region 1211 and a second electrode region 1212 spaced apart. The first electrode region 1211 is coupled to a first transition structure 1241; the second electrode region 1212 is coupled to a second transition structure 1242.

[0097] For example, such as Figure 7 As shown, the first transition structure 1241 is disposed on the side of the first electrode region 1211 of the epitaxial layer 121 away from the semiconductor substrate 110, and is coupled to the first electrode region 1211.

[0098] The second transition structure 1242 is disposed on the side of the second electrode region 1212 of the epitaxial layer 121 away from the semiconductor substrate 110, and is coupled to the second electrode region 1212.

[0099] Thus, the first electrode region 1211 of the epitaxial layer 121 can serve as the source of a transistor when the first transition structure 1241 is conductive. The second electrode region 1212 of the epitaxial layer 121 can serve as the drain of a transistor when the second transition structure 1242 is conductive. The conductive layer 123 serves as the gate of the transistor. In this way, an epitaxial layer 121, a dielectric layer 122, and a portion of the conductive layer 123 opposite to the channel region of the epitaxial layer 121 (located between the first electrode region 1211 and the second electrode region 1212, not shown in the figure) can form a transistor. The opposing regions of the epitaxial layer 121 and the conductive layer 123 can form a MOS capacitor, with the epitaxial layer 121 serving as one electrode layer of the MOS capacitor and the conductive layer 123 serving as the other electrode layer.

[0100] For example, the materials used in the first transition structure 1241 and the second transition structure 1242 may include one or more conductive elements or compounds such as gold, silver, copper, aluminum, and tin.

[0101] In some examples, such as Figure 5As shown, the conductive layer 123 includes a first conductive portion 1231 and a second conductive portion 1232 connected together.

[0102] The first conductive portion 1231 covers the area of ​​the epitaxial layer 121 except for the region coupled to the first transition structure 1241 and the second transition structure 1242.

[0103] The second conductive part 1232 is disposed on the side of the first isolation structure 111 away from the semiconductor substrate 110.

[0104] For example, in the layer structure of a transistor, the first conductive portion 1231 extends along the Y direction of the arrangement of a plurality of epitaxial patterns 1210 and covers the plurality of epitaxial patterns 1210 except for the first electrode region 1211 and the second electrode region 1212 (see...). Figure 2 and Figure 7 Areas outside of ).

[0105] For example, the area of ​​the first transition structure 1241 in contact with the epitaxial layer 121 is smaller than the area of ​​the first electrode region 1211, and / or the area of ​​the second transition structure 1242 in contact with the epitaxial layer 121 is smaller than the area of ​​the second electrode region 1212. Depositing a dielectric layer 122 on the epitaxial layer 121 can cover the entire epitaxial layer 121, exposing the portion of the first electrode region 1211 that needs to be coupled to the first transition structure 1241, and the portion of the second electrode region 1212 that needs to be coupled to the second transition structure 1242, through vias. In this way, the formed first conductive portion 1231 can cover the area of ​​the epitaxial layer 121 except for the area coupled to the first transition structure 1241 and the second transition structure 1242, further increasing the relative area of ​​the epitaxial layer 121 and the conductive layer 123, and increasing the capacitance density.

[0106] The second conductive portion 1232 is disposed on the side of the first isolation structure 111 away from the semiconductor substrate 110. The second conductive portion 1232 can be used to realize electrical connection between multiple first conductive portions 1231 and external electronic components. This application does not impose specific limitations on the shape and extension direction of the second conductive portion 1232, nor does it impose limitations on the dimensional relationship between the second conductive portion 1232 and the first conductive portion 1231, as long as the second conductive portion 1232 does not overlap with the epitaxial layer 121.

[0107] Continue reading Figure 5 The epitaxial layer 121 includes a plurality of spaced epitaxial patterns 1210. The first electrode region 1211 includes a first sub-electrode region 1211a located in different epitaxial patterns 1210, and the second electrode region 1212 includes a second sub-electrode region 1212a located in different epitaxial patterns 1210.

[0108] A first sub-electrode region 1211a is coupled to a first transition structure 1241, and the first sub-electrode regions 1211a of multiple epitaxial patterns 1210 are coupled to each other through multiple first transition structures 1241.

[0109] A second sub-electrode region 1212a is coupled to a second transition structure 1242, and the second sub-electrode regions 1212a of multiple epitaxial patterns 1210 are coupled to each other through multiple second transition structures 1242.

[0110] In addition, such as Figures 2-5 As shown, the device stack 120 also includes a transition structure 1230 coupled to the conductive layer 123, used to couple the conductive layer 123 to word lines (not shown) in the semiconductor structure 100, and to transmit electrical signals to the conductive layer 123 through the word lines, thereby enabling the conductive layer 123 to control the transistor. This application does not impose specific limitations on the size, shape, and number of the transition structure 1230.

[0111] It should be noted that the examples provided in this application do not impose specific limitations on the specific layer structure and internal conductive signal lines of the semiconductor structure 100, which can be set according to actual needs. The following example illustrates the fabrication process of the semiconductor structure 100 without affecting the control capability of the conductive layer 123 over the epitaxial layer 121 (i.e., transistor performance) and without increasing the thickness of the dielectric layer 122, based on the structure of the MOS capacitor C composed of the epitaxial layer 121 and the conductive layer 123.

[0112] like Figures 8-10 As shown, this application provides a method for fabricating a semiconductor structure 100, S100 to S400. The process of this fabrication method is more compatible with the steps of semiconductor structure fabrication methods in related technologies.

[0113] S100: As Figure 8 ,and Figure 9 (a) and Figure 9 As shown in (b), a semiconductor substrate 110 is formed. The semiconductor substrate 110 includes a first isolation structure 111 and at least one second isolation structure 112 disposed within the region enclosed by the first isolation structure 111. Figure 6 As shown, at opposite ends of the first isolation structure 111 and the second isolation structure 112 along the plane Z perpendicular to the semiconductor substrate 110, one end of each structure is exposed from the same side surface of the semiconductor substrate 110, and the other end is located inside the semiconductor substrate 110.

[0114] S200: such as Figure 8 and Figure 9As shown in (c), an epitaxial layer 121 is formed on one side surface of the semiconductor substrate 110. The epitaxial layer 121 is configured as the first electrode layer of a MOS capacitor C. The epitaxial layer 121 is located between adjacent first isolation structures 111 and second isolation structures 112, and / or between two adjacent second isolation structures 112.

[0115] For example, the semiconductor substrate 110 is made of silicon or SOI material. A semiconductor material can be grown and ion-doped in the region between the first isolation structure 111 and the second isolation structure 112, and / or in the region between two adjacent second isolation structures 112, to obtain an epitaxial layer 121. The epitaxial layer 121 can serve as the active layer of a transistor.

[0116] It is understood that by setting a first isolation structure 111 and a second isolation structure 112 on the semiconductor substrate 110, and the materials of the first isolation structure 111 and the second isolation structure 112 include dielectric materials, based on the material properties of the first isolation structure 111 and the second isolation structure 112 and their relative positional relationship, semiconductor materials can be grown on the top surface of the semiconductor substrate 110, and in the region where the top surfaces of the first isolation structure 111 and the second isolation structure 112 are not exposed. The resulting epitaxial layer 121 has a high quality and will not be formed on the top surface of the first isolation structure 111 or the second isolation structure 112. Moreover, the fabrication process of the epitaxial layer 121 is simple.

[0117] S300: such as Figure 8 and Figure 9 As shown in (d), a dielectric layer 122 is formed on the side of the epitaxial layer 121 away from the semiconductor substrate 110; the dielectric layer 122 is configured as an intermediate dielectric layer between the two electrode layers of the MOS capacitor C. The dielectric layer 122 covers the epitaxial layer 121 and covers the second isolation structure 112. The surface of the portion of the dielectric layer 122 covering the second isolation structure 112 away from the semiconductor substrate 110 is characterized as a groove 1221.

[0118] For example, a dielectric material is deposited on the side of the epitaxial layer 121 away from the semiconductor substrate 110 using a deposition process.

[0119] S400: such as Figure 8 and Figure 9 As shown in (e), a conductive layer 123 is formed on the side of the dielectric layer 122 away from the semiconductor substrate 110. The conductive layer 123 is configured as the second electrode layer of the MOS capacitor C. The conductive layer 123 covers the dielectric layer 122 and fills the groove 1221.

[0120] For example, a conductive material can be deposited on the side of the dielectric layer 122 away from the semiconductor substrate 110 using a deposition process and filled within the groove 1221, allowing the conductive layer 123 to extend along the side of the dielectric layer 122 or the epitaxial layer 121 (e.g., Figure 6 As shown in the figure, the three sides surround the epitaxial layer 121, which increases the relative area between the conductive layer 123 and the epitaxial layer 121, thereby increasing the capacitance density of the MOS capacitor formed by the conductive layer 123 and the epitaxial layer 121.

[0121] For example, the conductive layer 123 may be made of one or more of the following materials: elemental metals, semiconductor materials, or conductive polymers. For instance, the conductive layer 123 may be made of one or more conductive elements or compounds such as gold, silver, copper, aluminum, and tin.

[0122] In the aforementioned process for fabricating the semiconductor structure 100, an epitaxial layer 121 is fabricated after the semiconductor substrate 110 is formed. The semiconductor substrate 110 has a first isolation structure 111 and a second isolation structure 112. By growing the epitaxial layer 121 on the semiconductor substrate 110, a transistor channel structure (i.e., the active layer of the transistor, including the source and drain) and structural features of the relative regions of the epitaxial layer 121 and the conductive layer 123 (i.e., the gate of the transistor) are obtained, improving the gate's control over the channel region and enhancing the performance of the semiconductor structure 100. Compared to related technologies that increase trench depth, the process of growing the epitaxial layer 121 on the semiconductor substrate 110 reduces the difficulty of fabricating the active layer of the transistor, improves the transistor's structural yield, reduces process costs, and allows for integration into current semiconductor structure fabrication processes, exhibiting high compatibility.

[0123] In some examples, such as Figure 9 (a) and Figure 9 (b) in the middle, and Figure 10 As shown, step S100 above: forming a semiconductor substrate 110 includes S110.

[0124] S110: A first trench 1101 and at least one second trench 1102 located within the region enclosed by the first trench 1101 are formed on the initial semiconductor substrate 110'. The depth of the first trench 1101 is greater than the depth of the second trench 1102; the first trench 1101 surrounds the second trench 1102. Wherein, at least one end of the second trench 1102 along a direction perpendicular to the stacking direction of the semiconductor substrate 110 and the device stack 120 is connected to the first trench 1101; or, the second trench 1102 is spaced apart from the first trench 1101.

[0125] For example, a dry etching or wet etching process can be used to etch the initial semiconductor substrate 110' to form a first trench 1101. Then, within the area enclosed by the first trench 1101, etching is performed again to form a second trench 1102.

[0126] S120: Deposit dielectric material in the first trench 1101 and the second trench 1102 to form the first isolation structure 111 and the second isolation structure 112, thereby obtaining the semiconductor substrate 110.

[0127] The relative positional relationship between the first isolation structure 111 formed based on the first trench 1101 and the second isolation structure 112 formed based on the second trench 1102 can be referred to as follows: Figures 2-5 The structure shown.

[0128] For example, a low-dielectric-constant dielectric material can be filled in the first trench 1101 and the second trench 1102 using chemical vapor deposition (CVD) or spin-on processes. The dielectric material may include one or more insulating materials such as silicon oxynitride (SiON), silicon oxide (SiO2), silicon nitride (SiN), or silicon carbide (SiC).

[0129] For example, by using a spin coating process, dielectric material can be filled into the first trench 1101 and the second trench 1102 in a single process, which helps to improve process efficiency. The first isolation structure 111 and the second isolation structure 112 formed in this way have one side surface flush with one side surface of the semiconductor substrate 110.

[0130] For example, by using CVD to fill the dielectric material in the first trench 1101 and the second trench 1102, the amount of dielectric material filling in different trenches can be controlled. For instance, after depositing dielectric material in the first trench 1101, one side surface of the first isolation structure 111 is flush with one side surface of the semiconductor substrate 110. After depositing dielectric material in the second trench, one side surface of the second isolation structure 112 is lower than one side surface of the semiconductor substrate 110. In this way, the side area of ​​the subsequently formed epitaxial layer 121 is increased, which is beneficial to increasing the area of ​​the conductive layer 123 surrounding the epitaxial layer 121 on three sides, increasing the channel control capability of the conductive layer 123 for the transistor, and increasing the relative area between the epitaxial layer 121 and the conductive layer 123, thereby increasing the capacitance density.

[0131] In some examples, such as Figure 9 (c)~ Figure 9 (g) in, and Figure 10 As shown, a semiconductor structure 100 is formed, including S210 and S510.

[0132] S210: Forming an epitaxial layer 121 comprising multiple spaced epitaxial patterns; or, forming an epitaxial layer 121 with a continuous structure. The epitaxial layer 121 includes spaced first electrode regions 1211 and second electrode regions 1212 (see...). Figure 7 ).

[0133] For example, such as Figures 2-5 As shown, based on the number and arrangement of the second trenches 1102, an epitaxial layer 121 is grown in the region between the second isolation structure 112 and the first isolation structure 111. The shape and size of the epitaxial layer 121 can be referenced as follows: Figures 2-5 The structures shown are continuous grid-like, "E"-shaped, or multiple independent strip structures.

[0134] S510: A first transition structure 1241 coupled to the first electrode region 1211 and a second transition structure 1242 coupled to the second electrode region 1212 are formed. A conductive material is deposited on one side of the dielectric layer 122 to form a conductive layer 123. The conductive layer 123 covers the area of ​​the epitaxial layer 121 except for the area coupled to the first transition structure 1241 and the second transition structure 1242.

[0135] For example, such as Figure 9 (f) and Figure 9 As shown in (g), an insulating layer 125 is formed on the side of the conductive layer 123 away from the semiconductor substrate 110. The insulating layer 125 covers a plurality of epitaxial layers 121 (including a dielectric layer 122 and the top surface of the semiconductor substrate 110). A plurality of vias are formed in the insulating layer 125, and conductive material can be filled in the vias. Some vias may expose a first electrode region 1211 of the epitaxial layer 121 or a portion of the first electrode region 1211 used for coupling with the first transition structure 1241, for forming the first transition structure 1241. Some vias may expose a second electrode region 1212 of the epitaxial layer 121 or a portion of the first electrode region 1211 used for coupling with the first transition structure 1241, for forming a second transition structure 1242. Additionally, some vias may expose a portion of the conductive layer 123 located on the first isolation structure 111, for forming a transition structure 1230 electrically connected to the conductive layer 123. In this way, the first conductive portion 1231 formed can cover the area of ​​the epitaxial layer 121 except for the area coupled to the first transition structure 1241 and the second transition structure 1242, further increasing the relative area of ​​the epitaxial layer 121 and the conductive layer 123, and increasing the capacitance density of the MOS capacitor C.

[0136] The first transition structure 1241 and the second transition structure 1242 are also used to couple with different conductive signal lines (not shown) in the semiconductor structure 100. For example, in the case where a transistor is formed by stacking an epitaxial layer 121, a dielectric layer 122, and a conductive layer 123, under the control of the electrical signal transmitted through the conductive layer 123 (coupled with the transition structure 1230), the electrical signal transmitted through the conductive signal line coupled to the first transition structure 1241 can be transmitted to the conductive signal line coupled to the second transition structure 1242, thereby realizing the function of the transistor.

[0137] It should be noted that the embodiments of the semiconductor structure provided in this application and the embodiments of the semiconductor structure fabrication method belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict. However, it should be further noted that the combination of technical features of the semiconductor structure provided in the embodiments of this application can already solve the technical problem to be solved by this application; therefore, the semiconductor structure fabrication method provided in the embodiments of this application is not limited to the semiconductor structure provided in the embodiments of this application, and any semiconductor structure prepared by the fabrication method that can form the semiconductor structure provided in the embodiments of this application is within the scope of protection of this application.

[0138] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized by, Comprising: a semiconductor substrate comprising a first isolation structure and at least one second isolation structure disposed within a region enclosed by the first isolation structure; the first isolation structure and the second isolation structure are respectively exposed from a same side surface of the semiconductor substrate at one end and located within the semiconductor substrate at the other end, along opposite ends in a direction perpendicular to a plane in which the semiconductor substrate lies; a device stack disposed on one side of the semiconductor substrate, comprising a capacitor and a transistor; the transistor comprises: an epitaxial layer disposed on a side surface of the semiconductor substrate, configured as a first plate layer of the capacitor; the epitaxial layer is located between adjacent first isolation structures and second isolation structures, and / or between two adjacent second isolation structures; a dielectric layer disposed on a side of the epitaxial layer away from the semiconductor substrate, configured as an intermediate dielectric layer between two plate layers of the capacitor; the dielectric layer covers the epitaxial layer and covers the second isolation structure; wherein the part of the dielectric layer covering the second isolation structure away from the side surface of the semiconductor substrate is characterized as a groove; a conductive layer disposed on a side of the dielectric layer away from the semiconductor substrate, configured as a second plate layer of the capacitor; the conductive layer covers the dielectric layer and fills the groove.

2. The semiconductor structure of claim 1, wherein, The first isolation structure surrounds a plurality of spaced second isolation structures; The second isolation structure is not connected with the first isolation structure; and / or, along a stacking direction perpendicular to the semiconductor substrate and the device stack, one end of the opposite ends of the second isolation structure is connected with the first isolation structure; The epitaxial layer is in a continuous structure; The conductive layer fills all the grooves characterized by the surface of the dielectric layer.

3. The semiconductor structure of claim 1, wherein, The first isolation structure surrounds a plurality of spaced second isolation structures; Along a stacking direction perpendicular to the semiconductor substrate and the device stack, both opposite ends of the second isolation structure are connected with the first isolation structure; the epitaxial layer comprises a plurality of spaced epitaxial patterns; The dielectric layer covers a plurality of epitaxial patterns and the second isolation structure between adjacent epitaxial patterns; the conductive layer fills all the grooves characterized by the surface of the dielectric layer.

4. The semiconductor structure according to claim 2 or 3, characterized in that The epitaxial layer comprises a plurality of spaced first electrode regions and second electrode regions; the first electrode regions are coupled with first transfer structures; the second electrode regions are coupled with second transfer structures; The conductive layer comprises connected first conductive parts and second conductive parts; The first conductive parts cover regions of the epitaxial layer other than the regions coupled with the first transfer structures and the second transfer structures; The second conductive parts are disposed on a side of the first isolation structure away from the semiconductor substrate.

5. The semiconductor structure of claim 4, wherein, The epitaxial layer comprises a plurality of spaced epitaxial patterns; the first electrode regions comprise first sub-electrode regions respectively located in different epitaxial patterns, and the second electrode regions comprise second sub-electrode regions respectively located in different epitaxial patterns; One of the first sub-electrode regions is coupled with one of the first transfer structures, and the first sub-electrode regions of the plurality of the epitaxial patterns are coupled with each other through the first transfer structures; One of the second sub-electrode regions is coupled with one of the second transfer structures, and the second sub-electrode regions of the plurality of the epitaxial patterns are coupled with each other through the second transfer structures.

6. The semiconductor structure of claim 1, wherein, The first isolation structure has a dimension along a direction perpendicular to a plane in which the semiconductor substrate is located, which is greater than a dimension of the second isolation structure along the direction perpendicular to the plane in which the semiconductor substrate is located. One of the first isolation structures encloses a device region, and the semiconductor structure includes a plurality of the device regions, and adjacent two of the device regions share part of the first isolation structures.

7. The semiconductor structure of claim 1, wherein, The semiconductor substrate includes a silicon-on-insulator layer.

8. A method of fabricating a semiconductor structure, characterized by, The method comprises: forming a semiconductor substrate; the semiconductor substrate includes a first isolation structure and at least one second isolation structure arranged in a region enclosed by the first isolation structure; the first isolation structure and the second isolation structure have one end exposed from a same side surface of the semiconductor substrate and the other end located in the semiconductor substrate along opposite ends of a direction perpendicular to a plane in which the semiconductor substrate is located; forming an epitaxial layer on a side surface of the semiconductor substrate; the epitaxial layer is configured as a first electrode layer of a capacitor; the epitaxial layer is located between adjacent first isolation structures and second isolation structures, and / or between two adjacent second isolation structures; forming a dielectric layer on a side of the epitaxial layer away from the semiconductor substrate; the dielectric layer is configured as an intermediate dielectric layer between two electrode layers of the capacitor; the dielectric layer covers the epitaxial layer and covers the second isolation structure; a part of the dielectric layer covering the second isolation structure away from the side surface of the semiconductor substrate is characterized as a groove; forming a conductive layer on a side of the dielectric layer away from the semiconductor substrate, the conductive layer is configured as a second electrode layer of the capacitor; the conductive layer covers the dielectric layer and fills in the groove.

9. The preparation method according to claim 8, characterized in that, The method of forming a semiconductor substrate comprises: forming a first trench and at least one second trench in a region enclosed by the first trench on an initial semiconductor substrate; the depth of the first trench is greater than the depth of the second trench; the first trench surrounds the second trench; wherein at least one of the opposite ends of the second trench along a direction perpendicular to a plane in which the semiconductor substrate is located is connected with the first trench; or, the second trench is arranged apart from the first trench; depositing a dielectric material in the first trench and the second trench to form the first isolation structure and the second isolation structure, to obtain the semiconductor substrate.

10. The method of claim 9, wherein, The method of forming a semiconductor substrate comprises: forming an epitaxial layer including a plurality of spaced epitaxial patterns; or, forming an epitaxial layer in a continuous structure; the epitaxial layer includes spaced first electrode regions and second electrode regions; forming first transfer structures coupled with the first electrode regions and second transfer structures coupled with the second electrode regions; The conductive layer covers the region of the epitaxial layer except for the region coupled to the first and second transfer structures. The conductive layer covers the region of the epitaxial layer except for the region coupled to the first and second transfer structures.

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