Preparation method of semiconductor element with annular semiconductor fin

Abstract

The invention discloses a preparation method of a semiconductor element. The preparation method comprises the following steps: forming an annular structure on a semiconductor substrate; using the annular structure as a mask to etch the semiconductor substrate to form an annular semiconductor fin; epitaxially growing a first bottom source / drain structure in the annular semiconductor fin and a second bottom source / drain structure surrounding the annular semiconductor fin; forming a first silicide layer on the first bottom source / drain structure, and forming a second silicide layer on the second bottom source / drain structure; forming a first gate structure on the first silicide layer, and forming a second gate structure on the second silicide layer; epitaxially growing a top source / drain structure on the annular semiconductor fin; and forming a contact structure on the top source / drain structure. The step of forming the contact structure on the top source / drain structure includes: forming a lower contact of the contact structure on the top source / drain structure; forming a middle contact of the contact structure on the lower contact; and forming an upper contact on the middle contact. A width of the upper contact is greater than a width of the middle contact.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2023116702179, filed on December 5, 2023, with the invention name of "Semiconductor element with annular semiconductor fins and preparation method thereof". Application No. 2023116702179 claims priority and benefits of U.S. formal application No. 18 / 372,241 filed on September 25, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a method for preparing a semiconductor element, and in particular to a method for preparing a semiconductor element with an annular semiconductor fin. Background Art

[0003] Semiconductor components are essential to many modern applications. With the development of electronic technology, semiconductor components are getting smaller and smaller, while their functions are getting more and more powerful, and the number of integrated circuits is increasing. Due to the miniaturization of semiconductor components, various types and sizes of semiconductor components providing different functions are integrated and packaged into one module. In addition, many preparation operations are performed to integrate various types of semiconductor components.

[0004] However, the preparation and assembly of semiconductor components involve many complex steps and operations. The assembly of semiconductor components is becoming more and more complex. The increase in the complexity of semiconductor component preparation and assembly may lead to defects. Therefore, it is necessary to continuously improve the preparation process of semiconductor components to solve these problems.

[0005] The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0006] In one embodiment of the present disclosure, a semiconductor element is provided. The semiconductor element includes a substrate, an annular semiconductor fin, a first bottom source / drain structure, a second bottom source / drain structure, a first silicide layer, a second silicide layer, a first gate structure, a second gate structure, a top source / drain structure and a contact structure. The annular semiconductor fin is disposed on the substrate. The first bottom source / drain structure is disposed in the semiconductor fin. The second bottom source / drain structure surrounds the annular semiconductor fin. The first silicide layer and the second silicide layer are disposed on the first bottom source / drain structure and the second bottom source / drain structure, respectively. The first gate structure and the second gate structure are disposed on the first silicide layer and the second silicide layer, respectively. The contact structure includes a lower contact, a middle contact on the lower contact and an upper contact on the middle contact. A width of the upper contact is greater than a width of the middle contact.

[0007] In another embodiment of the present disclosure, a method for preparing a semiconductor element is provided. The preparation method includes forming an annular structure on a semiconductor substrate; using the annular structure as a mask to etch the semiconductor substrate to form an annular semiconductor fin; epitaxially growing a first bottom source / drain structure and a second bottom source / drain structure surrounding the annular semiconductor fin; forming a first silicide layer on the first bottom source / drain structure, and forming a second silicide layer on the second bottom source / drain structure; forming a first gate structure on the first silicide layer, and forming a second gate structure on the second silicide layer; epitaxially growing a top source / drain structure on the annular semiconductor fin; and forming a contact structure on the top source / drain structure. The step of forming the contact structure on the top source / drain structure includes: forming a lower contact of the contact structure on the top source / drain structure; forming a middle contact of the contact structure on the lower contact; and forming an upper contact on the middle contact. A width of the upper contact is greater than a width of the middle contact.

[0008] The present disclosure provides an embodiment of a method for preparing a semiconductor element. The preparation method includes using an annular structure as a mask to etch a semiconductor substrate to form an annular semiconductor fin, and using the annular semiconductor fin as a vertical channel to form a transistor (e.g., a vertical field effect transistor (FET)). Therefore, the accumulation density of the semiconductor element can be significantly improved. In addition, the preparation method also includes forming a first gate structure in the annular semiconductor fin, and forming a second gate structure around the annular semiconductor fin. Therefore, the current control in the annular semiconductor fin can be improved, thereby improving the performance of the element.

[0009] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purposes as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the disclosure of the present application can be obtained by referring to the detailed description in conjunction with the drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0011] Figure 1 is a flow chart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0012] Figure 2 1 is a top view illustrating an intermediate stage of forming a cylindrical structure and a ring-shaped structure on a semiconductor substrate during a process of forming a semiconductor element according to some embodiments of the present disclosure.

[0013] Figure 3 is a cross-sectional view illustrating the process of forming a semiconductor element in some embodiments of the present disclosure, along Figure 2 The section line II' in FIG. 1 is an intermediate stage in which a cylindrical structure and a ring structure are formed on the semiconductor substrate.

[0014] Figure 4 is a top view illustrating an intermediate stage of removing a cylindrical structure during a formation process of a semiconductor device according to some embodiments of the present disclosure.

[0015] Figure 5 is a cross-sectional view illustrating the process of forming a semiconductor element in some embodiments of the present disclosure, along Figure 4 The section line I-I' in FIG. 1 removes the intermediate stage of the cylindrical structure.

[0016] Figure 6 is a cross-sectional view illustrating an intermediate stage of etching a semiconductor substrate to form a ring-shaped semiconductor fin during a process of forming a semiconductor device according to some embodiments of the present disclosure.

[0017] Figure 7 is a cross-sectional view illustrating an intermediate stage of forming a processing region during the formation of a semiconductor device according to some embodiments of the present disclosure.

[0018] Figure 82 is a top view illustrating an intermediate stage of forming inner spacers and outer spacers during a process of forming a semiconductor device according to some embodiments of the present disclosure.

[0019] Fig. 9 is a cross-sectional view illustrating the process of forming a semiconductor element in some embodiments of the present disclosure, along Figure 8 The section line II' in FIG. 5 forms an intermediate stage between the inner interstitial and the outer interstitial.

[0020] Fig.10 is a cross-sectional view illustrating an intermediate stage of etching a semiconductor substrate to form a groove around a ring-shaped semiconductor fin during a process of forming a semiconductor device according to some embodiments of the present disclosure.

[0021] Fig.11 is a cross-sectional view illustrating an intermediate stage of forming an isolation structure in a groove during a formation process of a semiconductor device according to some embodiments of the present disclosure.

[0022] Fig.12 is a cross-sectional view illustrating an intermediate stage of etching a semiconductor substrate to form a groove in a ring-shaped semiconductor fin during a formation process of a semiconductor device according to some embodiments of the present disclosure.

[0023] Fig.13 is a top view illustrating an intermediate stage of forming first and second bottom source / drain structures during a process of forming a semiconductor device according to some embodiments of the present disclosure.

[0024] Fig.14 is a cross-sectional view illustrating the process of forming a semiconductor element in some embodiments of the present disclosure, along Fig.13 The section line II' in FIG. 1 forms an intermediate stage between the first and second bottom source / drain structures.

[0025] Fig.15 is a top view illustrating an intermediate stage of forming first and second silicide layers during a process of forming a semiconductor device according to some embodiments of the present disclosure.

[0026] Fig.16 is a cross-sectional view illustrating the process of forming a semiconductor element in some embodiments of the present disclosure, along Fig.15 The section line II' in FIG. 5 forms an intermediate stage between the first and second silicide layers.

[0027] Fig.17 is a cross-sectional view illustrating an intermediate stage of forming an interlayer dielectric (ILD) layer to surround a second silicide layer during a process of forming a semiconductor device according to some embodiments of the present disclosure.

[0028] Fig.18is a cross-sectional view illustrating an intermediate stage of forming a bottom spacer sublayer to cover the first and second silicide layers during the formation of a semiconductor device according to some embodiments of the present disclosure.

[0029] Fig.19 is a top view illustrating an intermediate stage of forming first and second gate structures during a process of forming a semiconductor device according to some embodiments of the present disclosure.

[0030] Fig. 20 is a cross-sectional view illustrating the process of forming a semiconductor element in some embodiments of the present disclosure, along Fig.19 The section line II' in FIG. 1 forms an intermediate stage of the first and second gate structures.

[0031] Fig.21 is a cross-sectional view illustrating an intermediate stage of forming a top gap sub-layer and an ILD layer during the formation of a semiconductor device according to some embodiments of the present disclosure.

[0032] Fig. 22 is a cross-sectional view illustrating an intermediate stage of removing a ring structure and a portion of a top gap sub-layer during formation of a semiconductor device according to some embodiments of the present disclosure.

[0033] Fig.23 is a cross-sectional view illustrating an intermediate stage of forming a top source / drain structure during a formation process of a semiconductor device according to some embodiments of the present disclosure.

[0034] Fig.24 is a cross-sectional view illustrating an intermediate stage of forming a contact structure on a top source / drain structure during a formation process of a semiconductor device according to other embodiments of the present disclosure.

[0035] Fig.25 is a cross-sectional view illustrating an intermediate stage of forming a contact structure on a top source / drain structure during a formation process of a semiconductor device according to other embodiments of the present disclosure.

[0036] Fig.26 is a cross-sectional view illustrating an intermediate stage of forming a contact structure on a top source / drain structure during a formation process of a semiconductor device according to other embodiments of the present disclosure.

[0037] Fig. 27 is a cross-sectional view illustrating an intermediate stage of forming a contact structure on a top source / drain structure during a formation process of a semiconductor device according to other embodiments of the present disclosure.

[0038] Fig.28 is a cross-sectional view illustrating an intermediate stage of forming a contact structure on a top source / drain structure during a formation process of a semiconductor device according to other embodiments of the present disclosure.

[0039] Fig.29is a cross-sectional view illustrating an intermediate stage of forming a contact structure on a top source / drain structure during a formation process of a semiconductor device according to other embodiments of the present disclosure.

[0040] Fig.30 is a cross-sectional view illustrating an intermediate stage of forming a pad during the formation of a semiconductor device according to various embodiments of the present disclosure.

[0041] The reference numerals are described as follows:

[0042] 10: Preparation method

[0043] 100: Semiconductor components

[0044] 101: Semiconductor substrate

[0045] 103a: Cylindrical structure

[0046] 103b: Cylindrical structure

[0047] 105a: Ring structure

[0048] 105b: Ring structure

[0049] 110a: Opening

[0050] 110b: Opening

[0051] 120a: Open

[0052] 120b: Open

[0053] 123a: Ring-shaped semiconductor fin

[0054] 123b: Ring-shaped semiconductor fin

[0055] 125: Processing area

[0056] 127a1: Intra-interstitial

[0057] 127a2: Exointerstitial

[0058] 127b1: Intra-interstitial

[0059] 127b2: External interstitial

[0060] 130: Groove

[0061] 133: Isolation Structure

[0062] 140a: Groove

[0063] 140b: Grooved

[0064] 143a1: First bottom source / drain structure

[0065] 143a2: Second bottom source / drain structure

[0066] 143b1: First bottom source / drain structure

[0067] 143b2: Second bottom source / drain structure

[0068] 145a1: first silicide layer

[0069] 145a2: Second silicide layer

[0070] 145b1: first silicide layer

[0071] 145b2: Second silicide layer

[0072] 147: Interlayer dielectric (ILD) layer

[0073] 149: Bottom gap sublayer

[0074] 151a1: Gate dielectric layer

[0075] 151a2: Gate dielectric layer

[0076] 151b1: Gate dielectric layer

[0077] 151b2: Gate dielectric layer

[0078] 153a1: Gate electrode layer

[0079] 153a2: Gate electrode layer

[0080] 153b1: Gate electrode layer

[0081] 153b2: Gate electrode layer

[0082] 155a1: First gate structure

[0083] 155a2: Second gate structure

[0084] 155b1: First gate structure

[0085] 155b2: Second gate structure

[0086] 157: Top gap sublayer

[0087] 159: ILD layer

[0088] 160a: Ring opening

[0089] 160b: Ring opening

[0090] 163a: Top source / drain structure

[0091] 163b: Top source / drain structure

[0092] 200: Semiconductor components

[0093] 202: Gap sublayer

[0094] 204a: Lower contact

[0095] 204b: Medium contact

[0096] 204c: Upper contact

[0097] 206: Dielectric layer

[0098] 208: Dielectric layer

[0099] 210: Mask layer

[0100] 212: Conductive covering layer

[0101] 300: Semiconductor components

[0102] 302: Padding

[0103] H1: Thickness

[0104] H2: Thickness

[0105] I-I': Hatch line

[0106] O1: Opening

[0107] O3: Opening

[0108] O4: Opening

[0109] O5: Speak

[0110] O6: Opening

[0111] S1: medial wall

[0112] S2: Outer wall

[0113] S3: medial wall

[0114] S4: Lateral wall

[0115] S5: Sidewall

[0116] S7: Sidewall

[0117] S11: Steps

[0118] S13: Steps

[0119] S15: Steps

[0120] S17: Steps

[0121] S19: Steps

[0122] S21: Steps

[0123] S23: Steps

[0124] S25: Steps

[0125] S27: Steps

[0126] T1: Top surface

[0127] T2: Top surface

[0128] T5: Top surface

[0129] W1: Width

[0130] W2: Width

[0131] W3: Width

[0132] W4: Width

[0133] W5: Width

[0134] W6: Width DETAILED DESCRIPTION

[0135] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided claims. In order to simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are just examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or above a second feature may include an embodiment in which the first and second features are directly in contact with each other, and may also include an embodiment in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various embodiments. This repetition is for simplicity and clarity, and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0136] In addition, spatially relative terms, such as "lower", "below", "below", "upper", "above", etc., may be used herein to describe the relationship of one element or feature to another element or feature shown in the figure for ease of description. Spatially relative terms are intended to include different orientations of the element in use or operation, as well as the orientation depicted in the figure. The element may have other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0137] Figure 1 is a flow chart illustrating a method 10 for preparing a semiconductor element 100 according to some embodiments of the present disclosure, wherein the method 10 comprises steps S11, S13, S15, S17, S19, S21, S23, S25 and S27. First, a brief introduction is given Figure 1 Steps S11 to S27 in the embodiment are described in detail in conjunction with the following figure.

[0138] like Figure 1 As shown, the preparation method 10 starts from step S11, forming an annular structure on a semiconductor substrate, and in step S13, using the annular structure as a mask to etch the semiconductor substrate, thereby forming an annular semiconductor fin. In some embodiments, the annular semiconductor fin exposes the top surface of the semiconductor substrate. Then, in step S15, a processing area is formed in the semiconductor substrate. In some embodiments, in order to form the processing area, dopants are implanted into the top surface of the semiconductor substrate exposed by the annular semiconductor fin.

[0139] In step S17, inner gaps and outer gaps are formed on the sidewalls of the annular semiconductor fins. In some embodiments, the inner gaps are formed on the inner sidewalls of the annular semiconductor fins, and the outer gaps are formed on the outer sidewalls of the annular semiconductor fins. In step S19, a bottom source / drain structure is epitaxially grown inside and around the annular semiconductor fins. In some embodiments, the semiconductor substrate (including the processing area) is further etched to form grooves inside and around the annular semiconductor fins, and a bottom source / drain structure is epitaxially grown in the grooves.

[0140] Still refer to Figure 1 , in step S21, a silicide layer is formed on the bottom source / drain structure. In some embodiments, the bottom source / drain structure around the annular semiconductor fin is covered and surrounded by a silicide layer. In step S23, the inner spacers and the outer spacers are removed. In some embodiments, the inner sidewalls and the outer sidewalls of the annular semiconductor fin are exposed. Next, in step S25, a gate structure is formed that contacts the sidewalls of the annular semiconductor fin. In some embodiments, the inner sidewalls and the outer sidewalls of the annular semiconductor fin are in direct contact with the gate structure.

[0141] In step S27, a top source / drain structure is epitaxially grown on the annular semiconductor fin. In some embodiments, before the top source / drain structure grows, the annular structure on the annular semiconductor fin is removed, and the top surface of the annular semiconductor fin is in direct contact with the top source / drain structure. After the top source / drain structure is grown, the semiconductor element 100 is obtained. In some embodiments, the semiconductor element 100 includes a vertical field effect transistor, each annular semiconductor fin is a vertical channel, and has a source / drain structure at both ends of the channel at the top and bottom of the fin. Specifically, the current flows through the annular semiconductor fin in a vertical direction. For example, from the bottom source / drain structure to the top source / drain structure.

[0142] Figure 2 and Figure 4 1 is a top view illustrating an intermediate stage of forming ring structures 105 a and 105 b on a semiconductor substrate 101 during a process of forming a semiconductor device 100 according to some embodiments of the present disclosure. Figure 3 It is a cross-sectional view, along Figure 2 The section line II' in FIG. 1 illustrates some embodiments of the present disclosure. Figure 5 is a cross-sectional view, along Figure 4 Section line II' in FIG. 1 illustrates some embodiments of the present disclosure.

[0143] like Figure 2 and Figure 3 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. In addition, the semiconductor substrate 101 may also include elementary semiconductor materials, compound semiconductor materials and / or alloy semiconductor materials. The elementary semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium and / or diamond, etc. The compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, for example. The alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, etc.

[0144] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer on the substrate, and a semiconductor layer on the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The manufacturing technology of the semiconductor-on-insulator substrate may adopt a separation by oxygen implantation method (SIMOX), a wafer bonding method, and / or other applicable methods.

[0145] Still refer to Figure 2 and Figure 3 According to some embodiments, cylindrical structures 103a and 103b are formed on the semiconductor substrate 101. In some embodiments, the cylindrical structures 103a and 103b include a dielectric material. In some embodiments, the cylindrical structures 103a and 103b include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), other applicable materials or combinations thereof.

[0146] In addition, the manufacturing technology of the cylindrical structures 103a and 103b includes a deposition process and a patterning process. For example, a material layer (not shown) may be deposited on the semiconductor substrate 101, and the material layer may be patterned to form the cylindrical structures 103a and 103b. The deposition process may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, other applicable processes or a combination thereof.

[0147] In some embodiments, the patterning process includes a photolithography process and a subsequent etching process. The photolithography process may form a photoresist pattern (not shown) on the upper surface of the material layer. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). In some embodiments, the etching process is a dry etching process, a wet etching process, or a combination thereof.

[0148] Furthermore, according to some embodiments, the annular structures 105a and 105b are formed around the cylindrical structures 103a, 103b, such as Figure 2 and Figure 3 Specifically, the sidewall of the cylindrical structure 103a is completely surrounded by and in direct contact with the annular structure 105a, and the sidewall of the cylindrical structure 103b is completely surrounded by and in direct contact with the annular structure 105b. Some materials and processes used to form the annular structures 105a and 105b are similar or identical to the materials and processes used to form the cylindrical structures 103a and 103b, and are not described in detail here. However, it should be noted that the materials of the annular structures 105a and 105b are different from those of the cylindrical structures 103a and 103b.

[0149] Then, according to some embodiments, the cylindrical structures 103a and 103b are removed to form openings 110a and 110b in the annular structures 105a and 105b, such as Figure 4 and Figure 5 As shown. In some embodiments, the opening 110a is completely surrounded by the annular structure 105a, and the opening 110b is completely surrounded by the annular structure 105b. In some embodiments, the removal technology of the cylindrical structures 103a and 103b includes an etching process (such as a dry etching process). As mentioned above, the material of the cylindrical structures 103a, 103b is different from the material of the annular structures 105a, 105b, and the purpose of selecting these materials is to make the cylindrical structures 103a, 103b have high etching selectivity relative to the annular structures 105a, 105b. Therefore, the cylindrical structures 103a and 103b can be removed by the etching process, while the annular structures 105a and 105b can be substantially retained, thereby obtaining the openings 110a and 110b.

[0150] Figure 6 1 is a cross-sectional view illustrating an intermediate stage of etching the semiconductor substrate 101 to form the annular semiconductor fins 123a and 123b during the formation process of the semiconductor device 100 according to some embodiments of the present disclosure. The corresponding steps are shown in FIG. Figure 1 The step S13 in the manufacturing method 10 is shown. The annular semiconductor fins 123a and 123b are also referred to as annular vertical fins or tubular vertical fins.

[0151] Subsequently, the semiconductor substrate 101 is etched by using the annular structures 105a and 105b as masks to form annular semiconductor fins 123a and 123b, as shown in FIG. Figure 6 As shown, according to some embodiments. In some embodiments, openings 120a and 120b under the openings 110a and 110b are formed in the semiconductor substrate 101 and are surrounded by the annular semiconductor fins 123a and 123b. In addition, the top surface T1 of the semiconductor substrate 101 is exposed to the outside through the annular semiconductor fins 123a and 123b. In some embodiments, the semiconductor substrate 101 is etched by a dry etching process or a wet etching process.

[0152] Figure 7 is a cross-sectional view illustrating an intermediate stage of forming a processing region 125 during the formation of a semiconductor device 100 according to some embodiments of the present disclosure. The corresponding steps are shown in FIG. Figure 1 Step S15 in the preparation method 10 shown. Figure 7 As shown, according to some embodiments, the fabrication technique of the processing region 125 includes performing an ion implantation process on the semiconductor substrate 101 .

[0153] In some embodiments, dopants are implanted into the top surface T1 of the semiconductor substrate 101 exposed by the annular semiconductor fins 123a and 123b. In some embodiments, P-type dopants, such as boron (B), gallium (Ga) or indium (In), or N-type dopants, such as phosphorus (P) or arsenic (As), may be implanted according to the design requirements of the semiconductor device 100 to form the processing region 125. It should be noted that in the process of forming the processing region 125, the annular semiconductor fins 123a and 123b are covered by the annular structures 105a and 105b.

[0154] Figure 8 1 is a top view illustrating an intermediate stage of forming inner spacers 127a1, 127b1 and outer spacers 127a2, 127b2 during the formation process of the semiconductor element 100 according to some embodiments of the present disclosure. Fig. 9 is a cross-sectional view, along Figure 8 The cross-hatching lines in the figure illustrate some embodiments of the present disclosure. The corresponding steps are shown in Figure 1 Step S17 in the preparation method 10 is shown.

[0155] More specifically, the inner spacer 127a1 is formed on and in direct contact with the inner sidewall S1 of the annular semiconductor fin 123a, and the outer spacer 127a2 is formed on and in direct contact with the outer sidewall S2 of the annular semiconductor fin 123a. Similarly, the inner spacer 127b1 is formed on and in direct contact with the inner sidewall S3 of the annular semiconductor fin 123b, and the outer spacer 127b2 is formed on and in direct contact with the outer sidewall S4 of the annular semiconductor fin 123b. In other words, the inner spacers 127a1 and 127b1 are formed in the openings 120a and 120b, respectively. In some embodiments, the processing area 125 is partially covered by the inner spacers 127a1, 127b1 and the outer spacers 127a2, 127b2.

[0156] In some embodiments, the inner spacers 127a1, 127b1 and the outer spacers 127a2, 127b2 include dielectric materials. In some embodiments, the inner spacers 127a1, 127b1 and the outer spacers 127a2, 127b2 include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), other applicable materials or combinations thereof. In some embodiments, the material of the inner spacers 127a1, 127b1 and the material of the outer spacers 127a2, 127b2 are different from the material of the annular structures 105a and 105b. In some embodiments, the material of the inner spacers 127a1, 127b1 is the same as the material of the outer spacers 127a2, 127b2. In addition, the inner spacers 127a1, 127b1 and the outer spacers 127a2, 127b2 are fabricated by selectively growing or depositing dielectric materials on the sidewalls of the annular semiconductor fins 123a, 123b. In some embodiments, the inner spacers 127a1, 127b1 and the outer spacers 127a2, 127b2 are fabricated by epitaxial (epi) processes.

[0157] Fig.10 , Fig.11 , Fig.12 and Fig.14 is a cross-sectional view illustrating an intermediate stage of epitaxially growing bottom source / drain structures 143a1, 143a2, 143b1, 143b2 during the formation of the semiconductor element 100 according to some embodiments of the present disclosure, Fig.14 is along Fig.13 The section line II' in the top view illustrates a cross-sectional view of some embodiments of the present disclosure. The corresponding steps are shown in Figure 1 Step S19 in the preparation method 10 shown.

[0158] like Fig.10As shown, according to some embodiments, the semiconductor substrate 101 is etched to form a groove 130 surrounding the annular semiconductor fins 123a and 123b. In some embodiments, the processing area 125 in the semiconductor substrate 101 is partially etched. In some embodiments, the manufacturing technology of the groove 130 includes a dry etching process, such as a directional reactive ion etching (RIE) process. In some embodiments, due to the loading effect, the portion of the semiconductor substrate 101 (including the processing area 125) surrounded by the annular semiconductor fins 123a and 123b will not be recessed by the etching process.

[0159] Next, according to some embodiments, an isolation structure 133 is formed in the groove 130, such as Fig.11 In some embodiments, the isolation structure 133 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other applicable dielectric materials. In some embodiments, an insulating material (not shown) is deposited in the recess 130, and an etch-back process is performed on the insulating material to form the isolation structure 133. In some embodiments, the top surface of the isolation structure 133 is lower than the top surface of the processing region 125.

[0160] After the isolation structure 133 is formed, according to some embodiments, the semiconductor substrate 101 is etched to form recesses 140a and 140b in the annular semiconductor fins 123a and 123b. Fig.12 In some embodiments, the portion of the semiconductor substrate 101 (including the processing area 125) within the annular semiconductor fins 123a and 123b is etched by using the annular structures 105a, 105b, the inner spacers 127a1, 127b1, and the outer spacers 127a2, 127b2 as masks, and the portion of the semiconductor substrate 101 covered by the isolation structure 133 is protected by the isolation structure 133. In some embodiments, the etching process includes a dry etching process, such as an RIE process.

[0161] In some embodiments, the semiconductor substrate 101 is partially recessed within the annular semiconductor fins 123a and 123b to be coplanar with the isolation structure 133. However, other recess dimensions are also applicable. In some embodiments, the sidewalls of the processing region 125 are exposed through the recesses 130, 140a and 140b.

[0162] After the grooves 130, 140a and 140b are formed in the semiconductor substrate 101 and under the annular semiconductor fins 123a and 123b, the first bottom source / drain structures 143a1 and 143b1 are epitaxially grown in the grooves 140a and 140b, respectively (see FIG. Fig.12 ), the second bottom source / drain structures 143a2, 143b2 are epitaxially grown in the groove 130, such as Fig.13 and Fig.14 As shown, according to some embodiments. In some embodiments, the first bottom source / drain structure 143a1 is located in the annular semiconductor fin 123a, and the second source / drain structure 143a2 is located around the annular semiconductor fin 123a. Similarly, the first bottom source / drain structure 143b1 is located in the annular semiconductor fin 123b, and the second source / drain structure 143b2 is located around the annular semiconductor fin 123b.

[0163] In some embodiments, the inner spacer 127a1 and the outer spacer 127a2 are located between the first bottom source / drain structure 143a1 and the second bottom source / drain structure 143a2, and the inner spacer 127b1 and the outer spacer 127b2 are located between the first bottom source / drain structure 143b1 and the second bottom source / drain structure 143b2. In some embodiments, the first bottom source / drain structures 143a1, 143b1 and the second bottom source / drain structures 143a2, 143b2 are in direct contact with the processing region 125, and the second bottom source / drain structures 143a2, 143b2 cover a portion of the isolation structure 133.

[0164] In some embodiments, strained material is grown on the recessed portion of the semiconductor substrate 101 by an epitaxial process to form the first bottom source / drain structure 143a1, 143b1 and the second bottom source / drain structure 143a2, 143b2. In some embodiments, the first bottom source / drain structure 143a1, 143b1 and the second bottom source / drain structure 143a2, 143b2 include Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP or similar materials. The epitaxial process may include a rapid thermal chemical vapor deposition (RTCVD) process, an ultra-high vacuum chemical vapor deposition (UHVCVD) process, a molecular beam epitaxy (MBE) process, a metal organic vapor deposition (MOCVD) process or other applicable processes.

[0165] Fig.15 1 is a top view illustrating an intermediate stage of forming the first silicide layer 145a1, 145b1 and the second silicide layer 145a2, 145b2 during the formation process of the semiconductor element 100 according to some embodiments of the present disclosure. Fig.16 is a cross-sectional view, along Fig.15 The section line II' in FIG. 1 illustrates some embodiments of the present disclosure. The corresponding steps are shown in FIG. Figure 1Step S21 in the manufacturing method 10 is shown. A first silicide layer 145a1 is formed to cover the first bottom source / drain structure 143a1, and a second silicide layer 145a2 is formed to cover and surround the second bottom source / drain structure 143a2. Similarly, a first silicide layer 145b1 is formed to cover the first bottom source / drain structure 143b1, and a second silicide layer 145b2 is formed to cover and surround the second bottom source / drain structure 143b2.

[0166] In some embodiments, the first silicide layer 145a1 is in direct contact with the top surface of the first bottom source / drain structure 143a1, and the second silicide layer 145a2 is in direct contact with the top surface and sidewalls of the second bottom source / drain structure 143a2, for example. Fig.16 The top surface T2 and the sidewall S5 of the second bottom source / drain structure 143a2 are shown. The first silicide layer 145b1, the first bottom source / drain structure 143b1, the second silicide layer 145b2 and the second bottom source / drain structure 143b2 have similar features to those of the first silicide layer 145a1, the first bottom source / drain structure 143a1, the second silicide layer 145a2 and the second bottom source / drain structure 143a2 described above, and the details thereof are not repeated here.

[0167] Furthermore, in some embodiments, the first silicide layers 145a1 and 145b1 are in direct contact with the inner spacers 127a1 and 127b1, respectively, and the second silicide layers 145a2 and 145b2 are in direct contact with the outer spacers 127a2 and 127b2, respectively. It should be noted that the first silicide layers 145a1 and 145b1 and the second silicide layers 145a2 and 145b2 are used to reduce the contact resistance between the bottom source / drain structure and the contact to be subsequently formed on the bottom source / drain structure.

[0168] In some embodiments, the first silicide layer 145a1, 145b1 and the second silicide layer 145a2, 145b2 include metal silicide materials, such as cobalt silicide, titanium silicide, tantalum silicide, nickel silicide, copper silicide, tungsten silicide, molybdenum silicide or other applicable materials. In addition, the manufacturing technology of the first silicide layer 145a1, 145b1 and the second silicide layer 145a2, 145b2 may include a silicide process. In some embodiments, the silicide process includes a metal material deposition process and an annealing process performed in sequence. In some embodiments, the deposition process of the silicide process includes a PVD process, an ALD process or other applicable processes. In some embodiments, the annealing process of the silicide process is performed at a temperature range of about 400°C to about 700°C. After the annealing process is completed, the unreacted metal material is removed.

[0169] Fig.171 is a cross-sectional view illustrating an intermediate stage of forming an interlayer dielectric (ILD) layer 147 to surround the second silicide layers 145a2 and 145b2 during the formation of the semiconductor device 100 according to some embodiments of the present disclosure. Fig.17 As shown, according to some embodiments, an ILD layer 147 is formed to fill the remaining space of the groove 130 .

[0170] In some embodiments, the ILD layer 147 may include multiple layers including a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k (dielectric constant) dielectric materials, and / or other applicable dielectric materials. The fabrication techniques of the ILD layer 147 may include a CVD process, a PVD process, an ALD process, a spin coating process, or other applicable processes. In some embodiments, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed on the ILD layer 147 until the top surfaces of the second silicide layers 145a2 and 145b2 are exposed.

[0171] Fig.18 1 is a cross-sectional view illustrating an intermediate stage of removing the inner spacers 127a1, 127b1 and the outer spacers 127a2, 127b2 and forming a bottom spacer layer 149 to cover the first silicide layer 145a1, 145b1 and the second silicide layer 145a2, 145b2 during the formation process of the semiconductor device 100 according to some embodiments of the present disclosure. The corresponding steps are shown in FIG. Figure 1 Step S23 in the manufacturing method 10 is shown. In some embodiments, after the inner spacers 127a1, 127b1 and the outer spacers 127a2, 127b2 are removed, annular gaps (not shown) are formed in and around the annular semiconductor fins 123a and 123b.

[0172] In some embodiments, the inner spacers 127a1, 127b1 and the outer spacers 127a2, 127b2 are removed by a selective etching process (such as an RIE process). After removing the inner spacers 127a1, 127b1 and the outer spacers 127a2, 127b2, the sidewalls (i.e., Fig. 9 Then, a bottom gap sublayer 149 is deposited on the first silicide layer 145a1, 145b1 and the second silicide layer 145a2, 145b2, and a portion of the bottom gap sublayer 149 extends into the annular gap between the first silicide layer 145a1, 145b1, the second silicide layer 145a2, 145b2 and the annular semiconductor fins 123a, 123b, as shown in FIG. Fig.18 As shown, according to some embodiments.

[0173] In some embodiments, the bottom gap sub-layer 149 includes a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), other applicable materials or combinations thereof. In addition, the bottom gap sub-layer 149 fabrication technique includes a directional deposition process, such as a high density plasma (HDP) deposition process, a gas cluster ion beam (GCIB) deposition process, or other applicable deposition processes. The directional deposition process preferably deposits the material of the bottom gap sub-layer 149 on the exposed horizontal surface rather than on the lateral sidewalls. In some embodiments, the bottom gap sub-layer 149 material formed on the top surface of the ring structures 105a and 105b will be removed in a subsequent planarization process (such as a CMP process).

[0174] Fig.19 1 is a top view illustrating an intermediate stage of forming the first gate structure 155a1, 155b1 and the second gate structure 155a2, 155b2 during the formation process of the semiconductor device 100. Fig. 20 is a cross-sectional view, along Fig.19 The section line II' in FIG. 1 illustrates some embodiments of the present disclosure. The corresponding steps are shown in FIG. Figure 1 The step S25 in the preparation method 10 is shown. The first gate structure 155a1 includes a gate dielectric layer 151a1 and a gate electrode layer 153a1, and the second gate structure 155a2 includes a gate dielectric layer 151a2 and a gate electrode layer 153a2. Similarly, the first gate structure 155b1 includes a gate dielectric layer 151b1 and a gate electrode layer 153b1, and the second gate structure 155b2 includes a gate dielectric layer 151b2 and a gate electrode layer 153b2.

[0175] In some embodiments, the gate electrode layers 153a1, 153a2, 153b1, and 153b2 are formed on the gate dielectric layers 151a1, 151a2, 151b1, and 151b2, and the sidewalls of the gate electrode layers 153a1, 153a2, 153b1, and 153b2 are covered by the gate dielectric layers 151a1, 151a2, 151b1, and 151b2. In addition, a work function layer (not shown) may be formed between each of the gate dielectric layers 151a1, 151a2, 151b1, and 151b2 and each of the gate electrode layers 153a1, 153a2, 153b1, and 153b2.

[0176] Each gate dielectric layer 151a1, 151a2, 151b1, and 151b2 may be a single layer or multiple layers. In some embodiments, the gate dielectric layers 151a1, 151a2, 151b1, and 151b2 include silicon oxide, silicon nitride, silicon oxynitride (SiON), a dielectric material having a high dielectric constant (high-k), or a combination thereof. In some embodiments, the gate dielectric layers 151a1, 151a2, 151b1, and 151b2 are deposited by an ALD process, a plasma enhanced chemical vapor deposition (PECVD) process, or a spin coating process.

[0177] In addition, according to some embodiments, the gate electrode layers 153a1, 153a2, 153b1, and 153b2 include a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. The manufacturing technology of the gate electrode layers 153a1, 153a2, 153b1, and 153b2 may include a deposition process, such as a CVD process, a PVD process, an ALD process, a high-density plasma CVD (HDPCVD) process, a MOCVD process, or a PECVD process.

[0178] The work function layer (not shown) may include a metal material, and according to the design requirements of the semiconductor device 100, the metal material may include an N-type work function metal or a P-type work function metal. The N-type work function metal may include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or a combination thereof. The P-type work function metal may include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or a combination thereof.

[0179] After the material of the gate dielectric layers 151a1, 151a2, 151b1 and 151b2 and the gate electrode layers 153a1, 153a2, 153b1 and 153b2 are deposited, excess material of the gate dielectric layers 151a1, 151a2, 151b1 and 151b2 and the gate electrode layers 153a1, 153a2, 153b1 and 153b2 are removed by a single etching process or multiple etching processes (such as a dry etching process) to form a first gate structure 155a1 and 155b1 within the annular semiconductor fins 123a and 123b, and a second gate structure 155a2 and 155b2 around the annular semiconductor fins 123a and 123b. Therefore, the inner sidewall S1 of the annular semiconductor fin 123a is in direct contact with the gate dielectric layer 151a1 of the first gate structure 155a1, and the outer sidewall S2 of the annular semiconductor fin 123a is in direct contact with the gate dielectric layer 151a2 of the second gate structure 155a2.

[0180] In some embodiments, the inner sidewall S1 and the outer sidewall S2 of the annular semiconductor fin 123a are partially exposed by the first gate structure 155a1 and the second gate structure 155a2. The annular semiconductor fin 123b, the first gate structure 155b1 and the second gate structure 155b2 have similar features to the annular semiconductor fin 123a, the first gate structure 155a1 and the second gate structure 155a2, and the details thereof are not repeated here. In some embodiments, a portion of the bottom gap sublayer 149 is exposed by the second gate structures 155a2 and 155b2.

[0181] Fig.21 is a cross-sectional view illustrating a process of forming a semiconductor element 100 according to some embodiments of the present disclosure. Fig. 20 After forming the first gate structure 155a1, 155b1 and the second gate structure 155a2, 155b2, according to some embodiments, as shown in FIG. Fig.21 As shown, a top gap sub-layer 157 is conformally deposited to surround it, and an ILD layer 159 is deposited on the top gap sub-layer 157 to be in direct contact with the top gap sub-layer 157. Some materials and processes used to form the top gap sub-layer 157 are similar or identical to those used to form the bottom gap sub-layer 149, and are not described in detail herein.

[0182] In addition, some materials and processes used to form the ILD layer 159 are similar or the same as the materials and processes used to form the ILD layer 147, and are not described in detail herein. However, it should be noted that the material of the top gap sub-layer 157 is different from the material of the ILD layer 159. Thereafter, a planarization process, such as a CMP process, is performed on the ILD layer 159 until the top surfaces of the ring structures 105a and 105b are exposed. In some embodiments, a portion of the top gap sub-layer 157 is in direct contact with a portion of the bottom gap sub-layer 149.

[0183] Fig. 22 1 is a cross-sectional view illustrating an intermediate stage of removing the ring structures 105a, 105b and a portion of the top gap sub-layer 157 during the formation of the semiconductor element 100 according to some embodiments of the present disclosure. In some embodiments, the vertical portions of the ring structures 105a, 105b and the top gap sub-layer 157 that are in direct contact with the sidewalls of the ring structures 105a, 105b and the ring-shaped semiconductor fins 123a, 123b are removed. For example, a selective etching process (such as a wet etching process) can be used to remove the above portions of the ring structures 105a, 105b and the top gap sub-layer 157.

[0184] Thus, annular openings 160a and 160b are obtained that expose the annular semiconductor fins 123a and 123b. Specifically, the top surface and a portion of the sidewall of the annular semiconductor fin 123a are exposed by the annular opening 160a, and the top surface and a portion of the sidewall of the annular semiconductor fin 123b are exposed by the annular opening 160b. For example, the top surface T5 and the top surface portion of the sidewall S7 of the annular semiconductor fin 123a are exposed to the outside through the annular opening 160a. In some embodiments, the remaining portion of the top gap sublayer 157 is also exposed through the annular openings 160a and 160b.

[0185] Fig.23 is a cross-sectional view illustrating an intermediate stage of forming top source / drain structures 163a and 163b on the annular semiconductor fins 123a and 123b during the formation of the semiconductor device 100 according to some embodiments of the present disclosure. The corresponding steps are shown in FIG. Figure 1 This is step S27 of the manufacturing method 10. In some embodiments, top source / drain structures 163a and 163b are epitaxially grown in the annular openings 160a and 160b, respectively.

[0186] Some materials and processes used to form the top source / drain structures 163a and 163b are similar or identical to the materials and processes used to form the first bottom source / drain structures 143a1, 143b1 and the second bottom source / drain structures 143a2, 143b2, and the details are not repeated here. In some embodiments, the top source / drain structures 163a and 163b are in-situ doped with P-type dopants, such as boron (B), or N-type dopants, such as phosphorus (P) during the epitaxial growth process. In some other embodiments, the top source / drain structures 163a and 163b are not doped during the epitaxial growth process. In contrast, after the top source / drain structures 163a and 163b are grown, the top source / drain structures 163a and 163b are doped in a subsequent process (such as an ion implantation process).

[0187] In particular, due to the slow growth rate of the top source / drain structures 163a and 163b on the (111) oriented surface during their epitaxial growth, faceted top source / drain structures 163a and 163b are obtained according to some embodiments, such as Fig.23 As shown. In some embodiments, the top source / drain structures 163a and 163b are in direct contact with the top surface and a portion of the sidewalls of the annular semiconductor fins 123a and 123b. In addition, the top source / drain structures 163a and 163b can be in direct contact with a portion of the top gap sublayer 157. After the top source / drain structures 163a and 163b are grown, the semiconductor element 100 is obtained.

[0188] The present disclosure provides an embodiment of a method for preparing a semiconductor element 100. The method includes etching a semiconductor substrate 101 using annular structures 105a and 105b as masks to form annular semiconductor fins 123a and 123b, and using the annular semiconductor fins 123a and 123b as vertical channels to form a semiconductor element 100 (including a vertical field effect transistor). Therefore, the packing density of the semiconductor element 100 can be significantly improved.

[0189] In addition, the preparation method also includes forming first gate structures 155a1 and 155b1 in the annular semiconductor fins 123a and 123b, and forming second gate structures 155a2 and 155b2 around the annular semiconductor fins 123a and 123b. The first gate structures 155a1 and 155b1 can be used for current control in the vertical channel, and the second gate structures 155a2 and 155b2 can be configured to apply a voltage bias to adjust the threshold voltage of the transistor. Since the first gate structures 155a1, 155b1 and the second gate structures 155a2, 155b2 can be operated independently, the current control in the annular semiconductor fins 123a and 123b can be improved, thereby improving the performance of the device.

[0190] In addition, by forming the second silicide layers 145a2 and 145b2 around the second bottom source / drain structures 143a2 and 143b2, the contact area between the second silicide layers 145a2 and 145b2 and the second bottom source / drain structures 143a2 and 143b2 is increased. Therefore, the contact resistance of the second bottom source / drain structures 143a2 and 143b2 can be reduced, thereby significantly improving the overall performance of the element.

[0191] In other embodiments, the semiconductor device 100 further includes source / drain contact structures located on the top source / drain structures 163a and 163b, such as Fig.29 The semiconductor device 200 is shown in FIG.

[0192] Please refer to Figure 24 to Figure 29 . Figures 24 to 28 2 is a cross-sectional view illustrating an intermediate stage of forming a source / drain contact structure on a top source / drain structure during the formation of a semiconductor device 200 according to another embodiment of the present disclosure. It should be noted that Figures 2 to 23 The intermediate stages shown in the formation of semiconductor device 100 are also applicable to the formation of semiconductor device 200. Therefore, they will not be repeated here. Figures 2 to 23 The process shown.

[0193] exist Fig.24In the embodiment, a gap sublayer 202 is formed on the ILD layer 159, the top source / drain structure 163a, and the top source / drain structure 163b. In some embodiments, the top surface of the gap sublayer 202 is higher than the top of the top source / drain structures 163a and 163b. After the gap sublayer 202 is formed, the gap sublayer 202 is etched to form an opening, thereby exposing the top source / drain structures 163a and 163b. Next, a contact material is deposited into the opening. A planarization process such as chemical mechanical polishing can then be performed to remove excess contact material and provide a substantially flat surface for subsequent process steps, while forming Fig.24 The lower contact 204a is shown.

[0194] In some embodiments, each lower contact 204 a has a width W1 that is smaller than the width of the widest portion of the top source / drain structures 163 a and 163 b .

[0195] exist Fig.25 In the embodiment, a dielectric layer 206 and a dielectric layer 208 are sequentially formed on the gap sublayer 202 and the lower contact 204a. In some embodiments, the thickness of the dielectric layer 206 is between about 3 nanometers and about 10 nanometers or about 5 nanometers. In some embodiments, the thickness of the dielectric layer 208 is between about 10 nanometers and about 30 nanometers.

[0196] The fabrication technique of the dielectric layer 206 includes any suitable deposition process, such as atomic layer deposition or chemical vapor deposition. In some embodiments, the dielectric layer 206 includes silicon nitride, silicon boron nitride carbon, silicon carbon nitride, or silicon oxy-carbon nitride. In some embodiments, the dielectric layer 206 includes, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric material, silicon nitride, silicon nitride oxide, silicon boron nitride carbon, silicon carbon nitride, or silicon oxy-carbon nitride.

[0197] The dielectric layer 208 may be formed by any suitable deposition process, such as atomic layer deposition or chemical vapor deposition. In some embodiments, the dielectric layer 208 includes a material having an etch selectivity to the dielectric layer 206. In some embodiments, the dielectric layer 208 includes an oxide (eg, silicon oxide).

[0198] Next, a mask layer 210 is formed on the dielectric layer 208. In some embodiments, the mask layer 210 is a photoresist layer. In some embodiments, the mask layer 210 includes a hard mask layer on the dielectric layer 208 and a photoresist layer on the hard mask layer. Fig.25As shown, the mask layer 210 has a pattern of openings O1. Each opening O1 is aligned with a corresponding lower contact 204a. In some embodiments, a width W2 of the opening O1 is smaller than a width W1 of the lower contact 204a.

[0199] exist Fig.26 In the process, a first etching process is performed to remove a portion of the dielectric layer 208 and a portion of the dielectric layer 206, thereby forming an opening O4. At the current stage, the opening O4 can be set along the dielectric layer 206 and the dielectric layer 208. The lower contact 204a is exposed through the opening O4. In addition, the opening O1 is expanded to the opening O3 during the first etching process. Therefore, the width W3 of the opening O3 is greater than the width W2 of the opening O1. The width W4 of the opening O4 is less than the width W1 of the lower contact 204a. The width W4 is less than the width W3. In some embodiments, the width W3 is less than the width W1. After the openings O3 and O4 are formed, the mask layer 210 is removed.

[0200] exist Fig. 27 In the embodiment of the present invention, a second etching process is performed to remove a portion of the dielectric layer 208, thereby expanding the opening O4 to form an opening O5. In some embodiments, the dielectric layer 206 is not etched by the second etching process, so the remaining opening O4 on the dielectric layer 206 becomes an opening O6. The width W5 of the opening O5 is greater than the width W6 of the opening O6. It should be noted that since the dielectric layer 206 is not etched during the second etching process, the width W6 is equal to the width W4. In some embodiments, the width W5 of the opening O5 is greater than the width W1 of the lower contact 204a. In various embodiments, the width W5 of the opening O5 is substantially equal to the width W1 of the lower contact 204a.

[0201] exist Fig.28 In the process, a conductive material such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, transition metal aluminide or a combination thereof is deposited into the opening O5 and the opening O6 through a deposition process. After the deposition process is completed, a planarization process, such as chemical mechanical polishing, can be performed until the top surface of the dielectric layer 208 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps, while forming a middle contact 204b in the opening O6 and an upper contact 204c in the opening O5.

[0202] exist Fig.29 In the embodiment, a third etching process is performed to recess the dielectric layer 208. The dielectric layer 208 (eg, Fig.28 As shown in FIG. 1 , the etched portion 20 becomes thinner after the third etching process, and its thickness H2 is less than the thickness H1.

[0203] In some embodiments, the upper contact 204c is not etched by the third etching process, so after the third etching process, the upper contact 204c protrudes from the dielectric layer 208. After performing the third etching process, a conductive capping layer 212 is formed on the upper contact 204c and the dielectric layer 208. In some embodiments, the conductive capping layer 212 includes copper germanium, etc. In some embodiments, the manufacturing technology of the conductive capping layer 212 includes sputtering, electron beam thermal evaporation, gas-solid reaction or epitaxial growth. In this embodiment, it is preferred to use the conductive capping layer 212 formed by epitaxial growth to provide a lower resistivity.

[0204] More specifically, the conductive covering layer 212 has a circular profile. The conductive covering layer 212 directly contacts and covers the entire protruding portion of the upper contact 204c. Fig.29 As shown, the protruding portion of the upper contact 204c is surrounded by the conductive cover layer 212. The conductive cover layer 212 is also in contact with the dielectric layer 208.

[0205] In various embodiments, the semiconductor device 100 further includes a pad disposed between the gate structures, such as Fig.30 The semiconductor device 300 shown in FIG. In some embodiments, the liner is configured to enhance the isolation between the gate structures.

[0206] Please refer to Fig.30 . Fig.30 is a cross-sectional view illustrating an intermediate stage of forming a liner during the formation of a semiconductor element 300 according to various embodiments of the present disclosure. It should be noted that Figures 2 to 23 The intermediate stages shown in forming semiconductor component 100 are also applicable to forming semiconductor component 300. Figures 2 to 23 The process shown will not be repeated here.

[0207] In various embodiments, before forming the ILD layer 159, a liner layer is conformally deposited on the top gap sub-layer 157. More specifically, the top gap sub-layer 157 between the annular semiconductor fins 123a and 123b is partially covered by the liner layer. Therefore, a portion of the liner layer is deposited between the annular semiconductor fins 123a and 123b.

[0208] In some embodiments, the liner layer includes, for example, titanium, titanium nitride, titanium-tungsten alloy, tantalum, tantalum nitride, or combinations thereof.

[0209] After the liner layer is deposited, an etching process, such as an anisotropic dry etching process, is performed to form the liner 302. In other words, the liner 302 is the remaining portion of the liner layer after the etching process.

[0210] like Fig.30As shown, the top gap sublayer 157 forms a groove between the annular semiconductor fins 123a and 123b, and forms a groove outside the annular semiconductor fins 123a and 123b. The pad 302 covers the side surface of the top gap sublayer 157 in the above-mentioned groove. Each pad 302 has a vertical surface, a curved surface and a bottom surface. The vertical surface and the bottom surface are connected to the top gap sublayer 157, and the curved surface connects the vertical surface and the bottom surface. Each pad 302 has the widest width along the bottom surface, and the width shrinks from the bottom surface to the intersection of the vertical surface and the curved surface. The intersection of the vertical surface and the curved surface coincides with a corner of the groove.

[0211] After forming the liner 302, the ILD layer 159 is formed, and the subsequent processes of the semiconductor device 300 are similar to those of the semiconductor device 300. Figure 22 to Figure 23 The process shown is essentially the same.

[0212] In other embodiments, the semiconductor device 200 further includes a pad 302 .

[0213] In one embodiment of the present disclosure, a semiconductor element includes an annular semiconductor fin disposed on a semiconductor substrate, a first bottom source / drain structure in the annular semiconductor fin, a second bottom source / drain structure surrounding the annular semiconductor fin, a first silicide layer, a second silicide layer, a first gate structure, a second gate structure, a top source / drain structure, and a contact structure on the top source / drain structure. The first silicide layer and the second silicide layer are disposed on the first bottom source / drain structure and the second bottom source / drain structure, respectively. The first gate structure and the second gate structure are disposed on the first silicide layer and the second silicide layer, respectively. The contact structure includes a lower contact, a middle contact on the lower contact, and an upper contact on the middle contact. A width of the upper contact is greater than a width of the middle contact.

[0214] In another embodiment of the present disclosure, a method for preparing a semiconductor element is provided. The preparation method includes forming an annular structure on a semiconductor substrate; using the annular structure as a mask to etch the semiconductor substrate to form an annular semiconductor fin; epitaxially growing a first bottom source / drain structure and a second bottom source / drain structure surrounding the annular semiconductor fin in the annular semiconductor fin; forming a first silicide layer on the first bottom source / drain structure, and forming a second silicide layer on the second bottom source / drain structure; forming a first gate structure on the first silicide layer, and forming a second gate structure on the second silicide layer; epitaxially growing a top source / drain structure on the annular semiconductor fin; and forming a contact structure on the top source / drain structure. The step of forming the contact structure on the top source / drain structure includes: forming a lower contact of the contact structure on the top source / drain structure; forming a middle contact of the contact structure on the lower contact; and forming an upper contact on the middle contact. A width of the upper contact is greater than a width of the middle contact.

[0215] The embodiments of the present disclosure have some advantageous features. By forming an annular semiconductor fin on a semiconductor substrate using an annular structure and using the annular semiconductor fin as a vertical channel to form a transistor, the packing density of semiconductor components can be significantly improved. In addition, the gate structure formed in the annular semiconductor fin and the gate structure formed around the annular semiconductor fin can be operated independently, and a silicide layer is formed around the bottom source / drain structure. Therefore, the performance of the entire component can be significantly improved.

[0216] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure defined by the claims. For example, many of the above processes can be implemented in different ways, and other processes, or combinations thereof, can be used to replace many of the above processes.

[0217] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A method for preparing a semiconductor element, comprising: forming a ring structure on a semiconductor substrate; Using the annular structure as a mask to etch the semiconductor substrate to form an annular semiconductor fin; Epitaxially growing a first bottom source / drain structure in the annular semiconductor fin and a second bottom source / drain structure surrounding the annular semiconductor fin; forming a first silicide layer on the first bottom source / drain structure, and forming a second silicide layer on the second bottom source / drain structure; forming a first gate structure on the first silicide layer, and forming a second gate structure on the second silicide layer; epitaxially growing a top source / drain structure on the annular semiconductor fin; as well as A contact structure is formed on the top source / drain structure, comprising: forming a lower contact of the contact structure on the top source / drain structure; forming a middle contact of the contact structure on the lower contact; and forming an upper contact on the middle contact, A width of the upper contact is greater than a width of the middle contact. 2 . The method of claim 1 , wherein a width of the lower contact is greater than the width of the middle contact.

3. The preparation method according to claim 1, further comprising: A first ion implantation region and a second ion implantation region are formed, wherein the first ion implantation region is disposed between the first bottom source / drain structure and the annular semiconductor fin, and the second ion implantation region is disposed between the second bottom source / drain structure and the annular semiconductor fin.

4. The preparation method according to claim 3, further comprising: forming a bottom gap sublayer covering the first silicide layer and the second silicide layer and contacting the annular semiconductor fin, wherein the bottom gap sublayer has a first protruding portion and a second protruding portion, The first protruding portion is disposed in the annular semiconductor fin and between the first silicide layer and the annular semiconductor fin, and the second protruding portion surrounds the annular semiconductor fin and is disposed between the second silicide layer and the annular semiconductor fin. The first protruding portion is disposed on the first ion implantation region, and the second protruding portion is disposed on the second ion implantation region.

5. The preparation method according to claim 4, further comprising: forming a top gap sublayer on the bottom gap sublayer, the first gate structure and the second gate structure, The top gap sublayer includes a first portion and a second portion, wherein the first portion of the top gap sublayer is disposed on the first gate structure and within the annular semiconductor fin, and the second portion of the top gap sublayer is disposed on the second gate structure, wherein the second portion of the top gap sublayer comprises a first section configured to contact the top gap sublayer; a second section configured to contact a sidewall of the second gate electrode; and a third section configured to contact a top surface of the second gate electrode, The annular semiconductor fin protrudes from the top gap sublayer, and the top source / drain structure contacts the top gap sublayer.

6. The preparation method according to claim 5, further comprising: forming a liner in contact with the first section and the second section of the second portion of the top gap sublayer, The pad has a vertical surface, a bottom surface, and a curved surface, wherein the vertical surface is connected to the second section of the second part of the top gap sublayer, the bottom surface is connected to the first section of the second part of the top gap sublayer, and the curved surface connects the vertical surface and the bottom surface, A width of the pad shrinks from the bottom surface to an intersection of the vertical surface and the arc surface.

7. The preparation method according to claim 5, further comprising: forming a first interlayer dielectric (ILD) layer surrounding the second silicide layer; and forming a second interlayer dielectric layer on the top gap sublayer, wherein the second interlayer dielectric layer is in contact with the top source / drain structure, The first interlayer dielectric layer and the second interlayer dielectric layer are separated by the bottom gap sublayer and the top gap sublayer.

8. The preparation method according to claim 7, further comprising: forming a gap sub-layer on the second interlayer dielectric layer; and forming a first opening in the gap sub-layer, wherein the top source / drain structure is exposed through the first opening, The lower contact of the contact structure is formed in the first opening.

9. The preparation method according to claim 8, further comprising: After forming the lower contact of the contact structure, forming a first dielectric layer on the spacer sub-layer; forming a second dielectric layer on the first dielectric layer; forming a second opening in the first dielectric layer, forming a third opening in the second dielectric layer, wherein the lower contact is exposed through the second opening, and the second opening is aligned with the third opening; and The third opening in the second dielectric layer is enlarged to become a fourth opening. 10 . The method of claim 9 , wherein the middle contact is formed in the second opening, and the upper contact is formed in the fourth opening.

11. The preparation method according to claim 10, further comprising: After forming the upper contact, thinning the second dielectric layer so that the upper contact protrudes out of the second dielectric layer; and A conductive cover layer is formed on the upper contact. 12 . The manufacturing method as claimed in claim 9 , wherein a width of the second opening is smaller than a width of the fourth opening.

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