High-voltage VDMOS structure with high conduction current and preparation method thereof
By using the structure of composite substrate and epitaxial growth drift region in VDMOS devices, the P-type and N-type drift regions are formed, which solves the problem of increased area and surge in on-resistance when the on-current is increased, and a combination of high on-current and good performance is achieved.
Patent Information
- Application Number
- CN202411911389.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-03-28
AI Technical Summary
When existing VDMOS devices increase the on-current, more devices need to be connected in parallel to increase the chip area, and the on-resistance increases with the increase of the withstand voltage value, making it difficult to effectively increase the on-current.
Using the structure of a composite substrate and an epitaxial growth drift region, the P-type and N-type drift regions are formed by forming an oxidation groove on the left and right sides of the device and setting up an inverted L-shaped metal electrode to form a P-type and N-type drift region, thereby increasing the breakdown voltage and conduction current.
It significantly improves the on-current of VDMOS devices, improves device performance, reduces the increase in chip area, and reduces the on-resistance.
Smart Images
Figure CN119730328A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a high-voltage VDMOS structure with high on-current and a preparation method thereof, which are applied to technical fields such as communication electronics, switching power supplies, and motor drives. Background Art
[0002] The VDMOS structure, with its gate and source on the surface and its drain at the bottom, facilitates parallel connection. Its withstand voltage and on-resistance are proportional to the thickness of the drift region. A thicker drift region increases the withstand voltage and the on-resistance. Therefore, to achieve a higher on-current, more VDMOS devices must be connected in parallel, increasing the chip area. Techniques for increasing on-current are a topic of research for those skilled in the art. Summary of the Invention
[0003] The object of the present invention is to provide a high voltage VDMOS structure with high on-current. The PN-VDMOS structure can significantly increase the on-current.
[0004] To achieve this purpose, the present invention adopts the following technical solution: a high-voltage VDMOS structure with high on-current, comprising: a composite substrate, the composite substrate being composed of a left substrate and a right substrate, a P-type drift region being epitaxially grown on the left substrate, and an N-type drift region being epitaxially grown on the right substrate, the structure also comprising oxidation grooves arranged on the left and right sides of the device and inverted L-shaped metal electrodes arranged in the oxidation grooves, a drain P+ region being arranged in the upper left corner of the P-type drift region, a P-body region and a trench gate being arranged in the upper right corner of the N-type drift region, the trench gate being located on the right side of the P-body region, and a source P+ region and a source N+ region being arranged in the P-body region.
[0005] As a specific implementation manner, the left substrate is composed of an N+ substrate and a P+ substrate stacked in sequence, and the right substrate is an N+ substrate.
[0006] As a specific implementation manner, the thickness of the P+ substrate in the left substrate is 2.5-3 μm, the thickness of the N+ substrate in the left substrate is 2.5-3 μm, and the thickness of the right substrate is 2.0-2.5 μm.
[0007] As a specific embodiment, the P+ substrate in the left substrate is a silicon substrate doped with boron at a doping concentration of 3.3-3.5×10 16 cm -3 The N+ substrate on the left is doped with arsenic, with a doping concentration of 4.2~4.5×10 16 cm -3 The right substrate is doped with arsenic, with a doping concentration of 4.2~4.5×10 16 cm -3 .
[0008] As a specific embodiment, the thickness of the P-type drift region is 35-39 μm, and the P-type drift region is doped with boron at a doping concentration of 6.2-6.5×10 14 cm -3 The thickness of the N-type drift region is 39~43μm, and the N-type drift region is doped with phosphorus at a doping concentration of 6.8~7×10 14 cm -3 .
[0009] As a specific implementation, the bottoms of the oxidation grooves on the left and right sides of the device are flush with the bottom of the composite substrate, and the tops extend into the P-type drift region and the N-type drift region respectively.
[0010] Another object of the present invention is to provide a method for preparing the above-mentioned high-voltage VDMOS structure with high on-current, comprising the following steps: (1) Growing a P-type drift region and an N-type drift region on a composite substrate; (2) Using a mask and dry etching, two grooves of the same depth are formed on the left and right sides of the composite substrate, and oxidation grooves are formed by high-temperature oxidation; (3) Dry etching and metal deposition are performed in the oxidation tank to obtain an inverted L-shaped metal electrode; (4) A drain P+ region is formed on the upper left corner of the P-type drift region by ion implantation and thermal diffusion, and a P-body region, a source N+ region, and a source P+ region are formed on the upper right corner of the N-type drift region; (5) A gate oxide trench is formed on the right side of the P-body region by high-temperature oxidation, and polysilicon is grown in the gate oxide trench to form a trench gate; (6) Use dry etching and metal deposition to form source electrodes and gate electrodes on the surfaces of the P-type drift region and the N-type drift region.
[0011] Compared with the prior art, the technical solution of the present invention has the following advantages: the high-voltage VDMOS structure with high on-current of the present invention adopts a composite substrate and then performs epitaxial growth of the drift region. The resulting structure effectively improves the breakdown voltage and the on-current, and the device performance is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1a-Figure 1f Schematic diagram of device cross-sections at various steps in the preparation process of the high-voltage VDMOS structure with high on-current according to the present invention.
[0013] Among them: 1. Left substrate; 2. Right substrate; 3. P-type drift region; 4. N-type drift region; 5. Oxide groove; 6. Inverted L-shaped metal electrode; 7. Drain P+ region; 8. P-body region; 9. Source P+ region; 10. Source N+ region; 11. Trench gate. DETAILED DESCRIPTION
[0014] The technical solution of the present invention will be further described below with reference to the accompanying drawings and through specific embodiments.
[0015] The present invention provides a high voltage VDMOS structure with high on-current. Figure 1f As shown, it includes: a composite substrate, which is composed of a left substrate 1 and a right substrate 2, a P-type drift region 3 is epitaxially grown on the left substrate 1, and an N-type drift region 4 is epitaxially grown on the right substrate 2. The structure also includes an oxidation groove 5 arranged on the left and right sides of the device and an inverted L-shaped metal electrode 6 arranged in the oxidation groove 5, a drain P+ region 7 is arranged in the upper left corner of the P-type drift region 3, a P-body region 8 and a trench gate 11 are arranged in the upper right corner of the N-type drift region 4, the trench gate 11 is located on the right side of the P-body region 8, and a source P+ region 9 and a source N+ region 10 are arranged in the P-body region 8.
[0016] Here, the left substrate 1 is composed of an N+ substrate and a P+ substrate stacked in sequence, and the right substrate 2 is an N+ substrate.
[0017] The thickness of the P+ substrate in the left substrate 1 is 2.5~3μm, the thickness of the N+ substrate in the left substrate 1 is 2.5~3μm, and the thickness of the right substrate 2 is 2.0~2.5μm. The P+ substrate in the left substrate 1 is a silicon substrate doped with boron with a doping concentration of 3.3~3.5×10 16 cm -3 The N+ substrate in the left substrate 1 is doped with arsenic, with a doping concentration of 6.5~7×10 16 cm -3 The right substrate 2 is doped with arsenic, with a doping concentration of 6.2~6.8×10 16 cm -3 .
[0018] In addition, the thickness of the P-type drift region 3 is 35-39 μm, and the P-type drift region 3 is doped with boron with a doping concentration of 6.2-6.5×10 14 cm -3 The thickness of the N-type drift region 4 is 39~43μm, and the N-type drift region 4 is doped with phosphorus at a doping concentration of 6.8~7×10 14 cm -3 .
[0019] In addition, the bottoms of the oxidation grooves on the left and right sides of the device are flush with the bottom of the composite substrate, and the tops extend into the P-type drift region 3 and the N-type drift region 4 respectively.
[0020] The method for preparing the high-voltage VDMOS structure with high on-current comprises the following steps: (1) If Figure 1a , growing a P-type drift region 3 and an N-type drift region 4 on the composite substrate; (2) If Figure 1b , using a mask and dry etching to form two grooves of the same depth on the left and right sides of the composite substrate, and forming an oxidation groove 5 by high temperature oxidation; (3) If Figure 1c , using dry etching and metal deposition in the oxidation tank 5 to obtain an inverted L-shaped metal electrode 6; (4) If Figure 1d , by ion implantation and thermal diffusion, a drain P+ region 7 is formed on the upper left corner of the P-type drift region 3, a P-body region 8, a source N+ region 10 and a source P+ region 9 are formed on the upper right corner of the N-type drift region 4; (5) If Figure 1e , forming a gate oxide groove on the right side of the P-body region 8 by high temperature oxidation, and growing polysilicon in the gate oxide groove to form a trench gate 11; (6) If Figure 1f , dry etching and metal deposition are performed to form a source electrode and a gate electrode on the surface of the P-type drift region 3 and the N-type drift region 4.
[0021] The high-voltage VDMOS structure fabricated using the above-described fabrication method has two majority carriers. When the PN-VDMOS device is turned on, the NMOS drift region and the PMOS drift region are turned on sequentially, and the electron current and hole current in the two drift regions do not interfere with each other. When the PN-VDMOS device is turned off, the PN junction formed by the P-type drift region 3 and the N-type drift region 4 can effectively improve the electric field distribution inside the VDMOS, thereby increasing the breakdown voltage.
[0022] Furthermore, when a PN-VDMOS device is on, its current is the parallel value of the PMOS current (L) and the NMOS current (L). Furthermore, the PMOS drift region concentration is higher than that of the NMOS drift region, resulting in a lower on-resistance and a higher current when the PMOS is on. Therefore, the current of a PN-VDMOS device is significantly higher than that of a conventional VDMOS.
[0023] The above contents are only preferred embodiments of the present invention. For ordinary technicians in this field, according to the concept of the present invention, there may be changes in the specific implementation methods and application scopes. The contents of this specification should not be understood as limiting the present invention.
Claims
1. A high voltage VDMOS structure with high on-current, characterized in that: include: A composite substrate, the composite substrate is composed of a left substrate and a right substrate, a P-type drift region is epitaxially grown on the left substrate, and an N-type drift region is epitaxially grown on the right substrate, the structure also includes oxidation grooves arranged on the left and right sides of the device and inverted L-shaped metal electrodes arranged in the oxidation grooves, a drain P+ region is arranged at the upper left corner of the P-type drift region, a P-body region and a groove gate are arranged at the upper right corner of the N-type drift region, the groove gate is located on the right side of the P-body region, and a source P+ region and a source N+ region are arranged in the P-body region.
2. A high voltage VDMOS structure with high on-current according to claim 1, characterized in that: The left substrate is composed of an N+ substrate and a P+ substrate stacked in sequence, and the right substrate is an N+ substrate.
3. A high voltage VDMOS structure with high on-current according to claim 2, characterized in that: The thickness of the P+ substrate in the left substrate is 2.5~3μm, the thickness of the N+ substrate in the left substrate is 2.5~3μm, and the thickness of the right substrate is 2.0~2.5μm.
4. A high voltage VDMOS structure with high on-current according to claim 2, characterized in that: The P+ substrate on the left is a silicon substrate doped with boron at a concentration of 3.3~3.5×10 16 cm -3 ; The N+ substrate on the left is doped with arsenic, with a doping concentration of 4.2~4.5×10 16 cm -3 The right substrate is doped with arsenic, with a doping concentration of 4.2~4.5×10 16 cm -3 .
5. The high voltage VDMOS structure with high on-current according to claim 1, characterized in that: The thickness of the P-type drift region is 35-39 μm, and the P-type drift region is doped with boron with a doping concentration of 6.2-6.5×10 14 cm -3 The thickness of the N-type drift region is 39-43 μm, and the N-type drift region is doped with phosphorus at a doping concentration of 6.8-7×10 14 cm -3 .
6. A high voltage VDMOS structure with high on-current according to claim 1, characterized in that: The bottoms of the oxidation grooves on the left and right sides of the device are flush with the bottom of the composite substrate, and the tops extend into the P-type drift region and the N-type drift region respectively.
7. A method for preparing a high voltage VDMOS structure with high on-current according to any one of claims 1 to 6, characterized in that: The following steps are involved: (1) Growing a P-type drift region and an N-type drift region on the composite substrate; (2) using a mask and dry etching to form two grooves of the same depth on the left and right sides of the composite substrate, and forming an oxidation groove by high-temperature oxidation; (3) Using dry etching and metal deposition in the oxidation tank to obtain an inverted L-shaped metal electrode; (4) A drain P+ region is formed at the upper left corner of the P-type drift region by ion implantation and heat diffusion, and a P-body region, a source N+ region and a source P+ region are formed at the upper right corner of the N-type drift region; (5) A gate oxide groove is formed on the right side of the P-body region by high-temperature oxidation, and polysilicon is grown in the gate oxide groove to form a trench gate; (6) Use dry etching and metal deposition to form source electrodes and gate electrodes on the surfaces of the P-type drift region and the N-type drift region.