Electronic device and manufacturing method thereof

Abstract

An electronic device includes a substrate, a buffer layer, an oxide semiconductor layer, a first insulating layer, and a gate electrode. The buffer layer is disposed on the substrate. The oxide semiconductor layer is disposed on the buffer layer and has a first portion and a second portion adjacent to the first portion. The first insulating layer is disposed on the oxide semiconductor layer. The gate electrode is disposed on the substrate and overlaps the first portion of the oxide semiconductor layer. And, in a mass spectrum measured by TOF-SIMS, an intensity of SiN-at an interface between the first portion and the first insulating layer is greater than an intensity of SiN-at an interface between the first portion and the buffer layer. The invention also provides a manufacturing method of the electronic device.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to an electronic device having a thin film transistor structure and a manufacturing method thereof. Background Art

[0002] Electronic devices such as tablets, laptops, smartphones, monitors and TVs have become an indispensable necessity in modern society. With the booming development of such portable electronic products, consumers have high expectations for the quality, functionality or price of these products.

[0003] Electronic devices usually include electronic components with driving functions, such as thin film transistor structures, among which metal oxide thin film transistors have been widely used due to their high electron mobility and low off-state current.

[0004] However, since the metal oxide thin film transistor undergoes multiple heating and annealing processes during the manufacturing process, these processes may easily cause the positive-bias-temperature stressing (PBTS) performance of the thin film transistor to be poor, thereby affecting the reliability of the electronic device.

[0005] Therefore, further improving the performance of driving components of electronic devices is still one of the research topics that the industry is committed to. Summary of the invention

[0006] According to some embodiments of the present disclosure, an electronic device is provided, comprising a substrate, a buffer layer, an oxide semiconductor layer, a first insulating layer and a gate electrode. The buffer layer is disposed on the substrate. The oxide semiconductor layer is disposed on the buffer layer and has a first portion and a second portion adjacent to the first portion. The first insulating layer is disposed on the oxide semiconductor layer. The gate electrode is disposed on the substrate and overlaps with the first portion of the oxide semiconductor layer. Furthermore, in a mass spectrum measured by TOF-SIMS, the intensity of SiN- at the interface between the first portion and the first insulating layer is greater than the intensity of SiN- at the interface between the first portion and the buffer layer.

[0007] The present disclosure also provides a method for manufacturing an electronic device, comprising the following steps: providing a substrate; forming a buffer layer on the substrate; forming an oxide semiconductor layer on the buffer layer, wherein the oxide semiconductor layer has a first portion and a second portion adjacent to the first portion; performing N2 plasma treatment on the surface of the oxide semiconductor layer; forming a first insulating layer on the oxide semiconductor layer; and forming a gate electrode on the substrate, wherein the gate electrode overlaps with the first portion of the oxide semiconductor layer.

[0008] In order to make the features and advantages of the present disclosure more obvious and understandable, some embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic diagram showing a cross-sectional structure of an electronic device according to some embodiments of the present disclosure;

[0010] Figure 2 A diagram showing the results of analyzing an electronic device using a Time-of-Flight Secondary Ion Mass Spectrometry (TOF-SIMS) according to some embodiments of the present disclosure;

[0011] Figure 3 A diagram showing the results of analyzing an electronic device by TOF-SIMS according to some embodiments of the present disclosure;

[0012] Figure 4 A diagram showing the results of analyzing an electronic device by TOF-SIMS according to some embodiments of the present disclosure;

[0013] Figure 5 A diagram showing the results of analyzing an electronic device by TOF-SIMS according to some embodiments of the present disclosure;

[0014] Figure 6 A schematic diagram of a cross-sectional structure of an electronic device according to some embodiments of the present disclosure is shown.

[0015]

Explanation of symbols

[0016] 10: Electronic devices

[0017] 20: Electronic devices

[0018] 102:Substrate

[0019] 104: Buffer layer

[0020] 104a: Sublayer

[0021] 104b: Sublayer

[0022] 106: Insulation layer

[0023] 106b:lower part

[0024] 106t: upper part

[0025] 108: Insulation layer

[0026] 108p-1: Part 3

[0027] 108p-2: Part 4

[0028] 110: Insulation layer

[0029] 202:Metal layer

[0030] 204: Gate electrode

[0031] 206:Metal layer

[0032] 300: oxide semiconductor layer

[0033] 300a: Part I

[0034] 300b: Part 2

[0035] A-A': Tangent

[0036] B-B': Tangent

[0037] Pa: upper part

[0038] Pb: lower part

[0039] Pc: Middle

[0040] S1: Interface

[0041] S2: Interface

[0042] S3: Interface

[0043] V1: Through hole DETAILED DESCRIPTION

[0044] The following is a detailed description of the electronic device and its manufacturing method according to the embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only used as examples and are not limitations of the present disclosure. In addition, similar and / or corresponding numbers may be used in different embodiments to indicate similar and / or corresponding components to clearly describe the present disclosure. However, the use of these similar and / or corresponding numbers is only for the purpose of simply and clearly describing some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and / or structures discussed.

[0045] It should be understood that relative terms, such as "lower" or "bottom" or "upper" or "top", may be used in the embodiments to describe the relative relationship of one component to another component in the drawings. It is understood that if the device in the drawings is turned upside down, the component described on the "lower" side will become the component on the "upper" side. The embodiments of the present disclosure may be used in conjunction with the attached drawings. Figure 1It is also understood that the drawings of the present disclosure are also considered as part of the disclosure. It should be understood that the drawings of the present disclosure are not drawn to scale, and in fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0046] Furthermore, when a first material layer is mentioned as being located on or above a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0047] In addition, it should be understood that the ordinal numbers used in the specification and claims, such as "first", "second", etc., to modify components, do not imply or represent any previous ordinal numbers of the component (or components), nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The same words may not be used in the claims and the specification. For example, the first component in the specification may be the second component in the claims.

[0048] In some embodiments of the present disclosure, terms such as "connection", "interconnection", etc., related to bonding and connection, unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein another structure is disposed between the two structures. Such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "coupled" include any direct and indirect electrical connection means.

[0049] In the text, the terms "about", "substantially", and "approximately" usually mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The term "range between a first value and a second value" means that the range includes the first value, the second value, and other values ​​therebetween. Furthermore, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0050] Furthermore, according to the embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable methods may be used to measure the thickness, length, width, or distance and angle of each component. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional image of a structure and measure the thickness, length, width, or distance and angle of each component.

[0051] When describing that “in a mass spectrum measured by TOF-SIMS, the intensity of a certain negative ion at a specific position is greater than the intensity of a certain negative ion at another specific position”, it includes a case where the certain negative ion is not substantially included at the other specific position.

[0052] It should be understood that the following embodiments may replace, reorganize, or combine features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment may be used in any combination as long as they do not violate the spirit of the invention or conflict with each other.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0054] According to an embodiment of the present disclosure, an electronic device is provided, including an oxide semiconductor layer processed by a specific process, thereby improving the stability of the positive bias temperature stress (PBTS) performance of the thin film transistor, thereby enhancing the reliability of the electronic device.

[0055] According to an embodiment of the present disclosure, the electronic device may include a display device, a splicing device, a touch electronic device, a sensing device, a curved electronic device or a non-rectangular electronic device, but is not limited thereto. The electronic device may, for example, include a liquid crystal, a light emitting diode, fluorescence, phosphorescence, other suitable display media, or a combination of the foregoing, but is not limited thereto. The display device may be a non-self-luminous display device or a self-luminous display device. The electronic device may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode (LED) or a photodiode. The light-emitting diode may, for example, include an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto. The splicing device may, for example, be a display splicing device, but is not limited thereto. It should be noted that the electronic device may be any combination of the foregoing, but is not limited thereto. In addition, the electronic device may be a bendable or flexible electronic device. In addition, the appearance of the electronic device may be a rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have a peripheral system such as a drive system, a control system, a light source system, a shelf system, etc. to support a display device or a splicing device. For the convenience of description, the following description will be based on the state of the electronic device as a display device, but the present disclosure is not limited to this.

[0056] Please refer to Figure 1 , Figure 1 A schematic cross-sectional view of an electronic device 10 is shown in some embodiments of the present disclosure. It should be understood that for the sake of clarity, some components of the electronic device 10 may be omitted in the drawings, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 10 described below.

[0057] As mentioned above, the electronic device 10 may be a display device. Figure 1 As shown, the electronic device 10 may include a substrate 102 , a buffer layer 104 , an oxide semiconductor layer 300 , an insulating layer 106 , and a gate electrode 204 .

[0058] According to some embodiments, the substrate 102 may be used as a substrate for carrying an active driving circuit and / or a passive driving circuit. Figure 1As shown, the electronic device 10 may include a thin film transistor formed by a metal layer 202 (which may also serve as a gate electrode), an oxide semiconductor layer 300, an insulating layer 106, and a gate electrode 204. According to some embodiments, the thin film transistor may include a driving transistor, a switching transistor, a reset transistor, a transistor amplifier, or other suitable thin film transistors. In addition, it should be understood that although the thin film transistors shown in the drawings are dual gate or double gate thin film transistors, according to different embodiments, the thin film transistors may also be top gate thin film transistors or bottom gate thin film transistors. Furthermore, according to some embodiments, the electronic device 10 may further include data lines, scan lines, touch signal lines, shared voltage lines, power lines, or other lines disposed on the substrate 102 as needed, but is not limited thereto.

[0059] The substrate 102 may include a rigid substrate or a flexible substrate. According to some embodiments, the material of the substrate 102 may include glass, quartz, sapphire, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), other suitable materials or a combination thereof, but not limited thereto. Furthermore, according to some embodiments, the substrate 102 may include a metal-glass fiber composite sheet or a metal-ceramic composite sheet, but not limited thereto. In addition, the substrate 102 may be a light-transmitting substrate, a semi-transmitting substrate or an opaque substrate.

[0060] According to some embodiments, the electronic device 10 may further include a metal layer 202, which may be disposed on the substrate 102. Furthermore, the metal layer 202 may overlap with the oxide semiconductor layer 300. The metal layer 202 may serve as a lower gate electrode of a thin film transistor, but is not limited thereto. The metal layer 202 may have a single-layer or multi-layer structure. For example, Figure 1 As shown, according to some embodiments, the metal layer 202 may have a double-layer structure, but is not limited thereto.

[0061] According to some embodiments, the material of the metal layer 202 may include a conductive material, such as copper (Cu), titanium (Ti), silver (Ag), gold (Au), tin (Sn), aluminum (Al), molybdenum (Mo), tungsten (W), chromium (Cr), nickel (Ni), platinum (Pt), palladium (Pd), alloys of the aforementioned metals, other suitable conductive materials, or combinations thereof, but not limited thereto. According to some embodiments, the metal layer 202 may be a double-layer structure (Ti / Cu) formed by a lower layer of titanium and an upper layer of copper, but not limited thereto.

[0062] The buffer layer 104 may be disposed on the substrate 102. The buffer layer 104 may be disposed between the metal layer 202 and the oxide semiconductor layer 300. According to some embodiments, the buffer layer 104 may also be conformally disposed on the metal layer 202. The buffer layer 104 may mitigate the strain difference between the insulating layer 108 and the substrate 102. Furthermore, the buffer layer 104 may have a single layer or a multi-layer structure. For example, Figure 1 As shown, according to some embodiments, the buffer layer 104 may have a double-layer structure formed of a sub-layer 104 a and a sub-layer 104 b .

[0063] According to some embodiments, the material of the buffer layer 104 may include silicon nitride, silicon oxide, silicon oxynitride, other suitable buffer materials or combinations thereof, but is not limited thereto. According to some embodiments, the sublayer 104a of the buffer layer 104 includes silicon nitride, and the sublayer 104b of the buffer layer 104 includes silicon oxide.

[0064] The oxide semiconductor layer 300 may be disposed on the buffer layer 104, and the oxide semiconductor layer 300 may have a first portion 300a and a second portion 300b adjacent to the first portion 300a. Specifically, the oxide semiconductor layer 300 may have two second portions 300b disposed on both sides of the first portion 300a, respectively, the first portion 300a overlaps with the gate electrode 204 in the normal direction of the substrate 102 (e.g., the Z direction in the drawings), and the second portion 300b does not overlap with the gate electrode 204 in the normal direction of the substrate 102. The first portion 300a may serve as a channel region, and the second portion 300b may serve as a doping region, and the doping region may have appropriate dopants so that the second portion 300b has conductive properties (e.g., n-type or p-type). According to some embodiments, the second portion 300b may serve as a source contact, and may be further electrically connected to a source electrode (not shown).

[0065] According to some embodiments, the oxide semiconductor layer 300 may include indium (In) and gallium (Ga). Further, according to some embodiments, the material of the oxide semiconductor layer 300 may include indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), other suitable materials or a combination thereof, but is not limited thereto.

[0066] The insulating layer 106 may be disposed on the oxide semiconductor layer 300. According to some embodiments, the insulating layer 106 may serve as a gate insulating layer of a thin film transistor. According to some embodiments, in the normal direction of the substrate 102 (e.g., the Z direction in the drawings), the insulating layer 106 may overlap with the first portion 300a of the oxide semiconductor layer 300, and partially overlap with the second portion 300b of the oxide semiconductor layer 300. Furthermore, the insulating layer 106 may have an upper portion 106t and a lower portion 106b, and the upper portion 106t is disposed above the lower portion 106b. According to some embodiments, the upper portion 106t and the lower portion 106b may be distinguished by half the thickness of the insulating layer 106.

[0067] According to some embodiments, the material of the insulating layer 106 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials or combinations thereof, but is not limited thereto.

[0068] Furthermore, the gate electrode 204 may be disposed on the insulating layer 106 and overlap the first portion 300a of the oxide semiconductor layer 300. The gate electrode 204 may have a single-layer or multi-layer structure. Figure 1 As shown, according to some embodiments, the gate electrode 204 may have a double-layer structure, but is not limited thereto.

[0069] According to some embodiments, the material of the gate electrode 204 may include a conductive material, such as copper (Cu), titanium (Ti), silver (Ag), gold (Au), tin (Sn), aluminum (Al), molybdenum (Mo), tungsten (W), chromium (Cr), nickel (Ni), platinum (Pt), palladium (Pd), alloys of the aforementioned metals, other suitable conductive materials, or combinations thereof, but not limited thereto. According to some embodiments, the gate electrode 204 may be a double-layer structure (Ti / Cu) formed with a lower layer of titanium and an upper layer of copper, but not limited thereto.

[0070] According to some embodiments, the electronic device 10 may further include an insulating layer 108, and the insulating layer 108 may be disposed on the gate electrode 204. In detail, the insulating layer 108 may be conformably disposed on the buffer layer 104, the oxide semiconductor layer 300, the insulating layer 106, and the gate electrode 204. Furthermore, the insulating layer 108 may have a third portion 108p-1 overlapping with the gate electrode 204 in the normal direction of the substrate 102 (e.g., the Z direction in the figure). The insulating layer 108 may have a fourth portion 108p-2 overlapping with the second portion 300b of the oxide semiconductor layer 300 in the normal direction of the substrate 102, and the fourth portion 108p-2 has an upper portion Pa, a lower portion Pb, and a middle portion Pc disposed between the upper portion Pa and the lower portion Pb. According to some embodiments, the thickness of the fourth portion 108p-2 of the insulating layer 108 may be divided into three equal parts, which are defined as an upper portion Pa, a middle portion Pc, and a lower portion Pb from top to bottom.

[0071] According to some embodiments, the material of the insulating layer 108 may include silicon oxynitride (SiON), other suitable materials, or combinations thereof, but is not limited thereto.

[0072] According to some embodiments, the electronic device 10 may further include a metal layer 206, and the metal layer 206 may be disposed on the insulating layer 108. According to some embodiments, the metal layer 206 may overlap with the gate electrode 204 in the normal direction of the substrate 102 (e.g., the Z direction in the drawings). The metal layer 206 may have a single-layer or multi-layer structure. Figure 1 As shown, according to some embodiments, the metal layer 206 may have a three-layer structure, but is not limited thereto. According to some embodiments, the metal layer 206 may serve as a drain contact and may be further electrically connected to a drain electrode (not shown).

[0073] According to some embodiments, the material of the metal layer 206 may include a metal conductive material, a transparent conductive material, other suitable materials, or a combination thereof, but is not limited thereto. The metal conductive material may include, for example, copper (Cu), titanium (Ti), silver (Ag), gold (Au), tin (Sn), aluminum (Al), molybdenum (Mo), tungsten (W), chromium (Cr), nickel (Ni), platinum (Pt), palladium (Pd), alloys of the aforementioned metals, other suitable conductive materials, or a combination thereof, but is not limited thereto. The transparent conductive material may include, for example, a transparent conductive oxide (TCO), such as indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials, or a combination thereof, but not limited thereto. According to some embodiments, the metal layer 206 may be a three-layer structure (Ti / Cu / ITO) formed of titanium, copper and indium tin oxide, but not limited thereto.

[0074] Furthermore, according to some embodiments, the electronic device 10 may further include an insulating layer 110, and the insulating layer 110 may be disposed on the metal layer 206. Specifically, the insulating layer 110 may be disposed on the insulating layer 108 and the metal layer 206 in a conforming manner.

[0075] According to some embodiments, the material of the insulating layer 110 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination thereof, but is not limited thereto.

[0076] Next, please refer to Figure 2 , Figure 2The figure shows the result of analyzing the electronic device 10 by using a Time-of-Flight Secondary Ion Mass Spectrometry (TOF-SIMS) according to some embodiments of the present disclosure. In detail, TOF-SIMS can bombard the surface of the sample to be tested with incident ions with energy, blasting out atoms in the target area to generate secondary ions. The secondary ions have different flight speeds due to the difference in mass. TOF-SIMS can distinguish ions with different charge-to-mass ratios to perform component analysis, and TOF-SIMS can obtain the concentration information of the depth profile of different elements in the sample.

[0077] Figure 2 Displays the corresponding Figure 1 The TOF-SIMS analysis results of the electronic device 10 obtained by the tangent line A-A', the vertical dotted lines in the figure indicate the positions of different layers in the electronic device 10, for example, along the tangent line A-A', the depth from shallow to deep is the insulating layer 110, the metal layer 206, the insulating layer 108, the gate electrode 204, the insulating layer 106, the oxide semiconductor layer 300 (first part 300a), the sublayer 104b of the buffer layer 104, the sublayer 104a of the buffer layer 104 and the metal layer 202. The horizontal axis in the figure is the depth of the structure to be analyzed, and the vertical axis is the signal intensity of the received ions, which is measured in counts. However, the relative size of the signal intensity of the same secondary ion at different depths can also be equivalently understood as the relative size of the ion concentration of the same secondary ion at different depths. Furthermore, the measurement is performed in the negative ion mode of TOF-SIMS, so the ions are all negatively charged. It should be understood that for the sake of clarity, not all measured ion types are shown in the figure.

[0078] like Figure 2 As shown, in the mass spectrum measured by TOF-SIMS, the intensity of SiN- at the interface S1 between the first portion 300a of the oxide semiconductor layer 300 and the insulating layer 106 is greater than the intensity of SiN- at the interface S2 between the first portion 300a and the buffer layer 104 (e.g., the sublayer 104b). In other words, the SiN- concentration at the interface S1 between the first portion 300a (e.g., the channel region) of the oxide semiconductor layer 300 and the insulating layer 106 is greater than the SiN- concentration at the interface S2 between the first portion 300a and the buffer layer 104. The aforementioned interface S1 and interface S2 are defined by the position of half the peak value of the InO- signal.

[0079] It is worth noting that the interface S1 has a relatively large SiN-strength, indicating that SiN bonding is generated at the interface S1 between the first portion 300a (e.g., the channel region) of the oxide semiconductor layer 300 and the insulating layer 106. The SiN bonding can repair defects on the surface of the oxide semiconductor layer 300, such as passivating dangling bonds, thereby improving the stability of the positive bias temperature stress (PBTS) performance of the thin film transistor, thereby enhancing the reliability of the electronic device 10.

[0080] Next, please refer to Figure 1 and Figure 3 , Figure 3 The figure shows the result of analyzing the electronic device 10 by TOF-SIMS according to some other embodiments of the present disclosure. Figure 3 It also shows the corresponding Figure 1 TOF-SIMS analysis results of the electronic device 10 obtained from the tangent line AA′.

[0081] The insulating layer 106 may have an upper portion 106t and a lower portion 106b, and in the mass spectrum measured by TOF-SIMS, the intensity of SiN- in the lower portion 106b is greater than the intensity of SiN- in the upper portion 106t. In other words, the SiN- concentration in the lower portion 106b of the insulating layer 106 is greater than the SiN- concentration in the upper portion 106t. As mentioned above, the upper portion 106t and the lower portion 106b can be distinguished by half the thickness of the insulating layer 106.

[0082] Furthermore, it should be understood that, according to some embodiments, "the strength of SiN- in the lower portion 106b is greater than the strength of SiN- in the upper portion 106t" means that the strength of SiN- at any point in the lower portion 106b of the insulating layer 106 is greater than the strength of SiN- at any point in the upper portion 106t. According to other embodiments, "the strength of SiN- in the lower portion 106b is greater than the strength of SiN- in the upper portion 106t" means that the strength of SiN- at a position of half the thickness of the lower portion 106b of the insulating layer 106 is greater than the strength of SiN- at a position of half the thickness of the upper portion 106t. According to yet other embodiments, "the strength of SiN- in the lower portion 106b is greater than the strength of SiN- in the upper portion 106t" means that the maximum strength of SiN- in the lower portion 106b of the insulating layer 106 is greater than the maximum strength of SiN- in the upper portion 106t.

[0083] It is noteworthy that the lower portion 106b of the insulating layer 106 has a relatively large SiN-strength, that is, the insulating layer 106 has a relatively large SiN-strength at a portion closer to the oxide semiconductor layer 300, so that the oxygen vacancies at the interface between the insulating layer 106 and the oxide semiconductor layer 300 are relatively reduced, thereby improving the stability of the positive bias temperature stress (PBTS) performance of the thin film transistor, thereby enhancing the reliability of the electronic device 10.

[0084] Next, please refer to Figure 1 and Figure 4 , Figure 4 The figure shows the result of analyzing the electronic device 10 by TOF-SIMS according to some other embodiments of the present disclosure. Figure 4 It also shows the corresponding Figure 1 TOF-SIMS analysis results of the electronic device 10 obtained from the tangent line AA′.

[0085] The insulating layer 108 has a third portion 108p-1 overlapping the gate electrode 204. In the mass spectrum measured by TOF-SIMS, the intensity of SiN- at the interface S3 between the third portion 108p-1 and the gate electrode 204 is greater than the intensity of SiN- at the interface S1 between the first portion 300a of the oxide semiconductor layer 300 and the insulating layer 106. In other words, the concentration of SiN- at the interface S3 between the third portion 108p-1 of the insulating layer 108 and the gate electrode 204 is greater than the concentration of SiN- at the interface S1 between the first portion 300a (e.g., the channel region) of the oxide semiconductor layer 300 and the insulating layer 106. The aforementioned interface S1 is defined by the position of half the peak of the InO-signal, and the interface S3 is defined by the position of half the peak of the Si-signal.

[0086] It is worth noting that the interface S3 has a greater SiN-intensity than the interface S1, which means that the SiN-concentration of the insulating layer 108 in the channel region is greater than the SiN-concentration of the interface between the insulating layer 106 and the oxide semiconductor layer 300 (the oxygen content is relatively low). Therefore, the peeling between the insulating layer 108 and the gate electrode 204 can be reduced, or the oxidation of the gate electrode 204 leading to increased wiring impedance can be prevented, thereby improving the reliability of the electronic device 10.

[0087] Next, please refer to Figure 1 and Figure 5 , Figure 5 The figure shows the result of analyzing the electronic device 10 by TOF-SIMS according to some other embodiments of the present disclosure. Figure 5 Displays the corresponding Figure 1The TOF-SIMS analysis results of the electronic device 10 obtained along the cut line BB' are shown in the figure. The vertical dotted lines in the figure indicate the positions of different layers in the electronic device 10. For example, along the cut line BB', the depth from shallow to deep is the insulating layer 110, the insulating layer 108, the oxide semiconductor layer 300 (the second part 300b), the sublayer 104b of the buffer layer 104, the sublayer 104a of the buffer layer 104, and the metal layer 202.

[0088] The insulating layer 108 has a fourth portion 108p-2 overlapping with the second portion 300b of the oxide semiconductor layer 300, and the fourth portion 108p-2 has an upper portion Pa, a lower portion Pb, and a middle portion Pc disposed between the upper portion Pa and the lower portion Pb, and in the mass spectrum measured by TOF-SIMS, the intensity of SiN- in the lower portion Pb is greater than the intensity of SiN- in the middle portion Pc. In other words, the SiN- concentration in the lower portion Pb of the fourth portion 108p-2 of the insulating layer 108 is greater than the SiN- concentration in the middle portion Pc. Furthermore, according to some embodiments, the intensity (concentration) of SiN- in the lower portion Pb is also greater than the intensity (concentration) of SiN- in the upper portion Pa. Based on the foregoing, the thickness of the fourth portion 108p-2 can be divided into three equal parts, which are defined as the upper portion Pa, the middle portion Pc, and the lower portion Pb from top to bottom. Furthermore, the interface of the upper portion Pa of the insulating layer 108 is defined by the position where the O-signal starts, and the interface of the lower portion Pb of the insulating layer 108 is defined by the position of half of the peak value of the InO-signal.

[0089] Furthermore, it should be understood that, according to some embodiments, "the strength of SiN- in the lower Pb is greater than the strength of SiN- in the middle Pc" means that the strength of SiN- at any point in the lower Pb of the insulating layer 108 is greater than the strength of SiN- at any point in the middle Pc. According to other embodiments, "the strength of SiN- in the lower Pb is greater than the strength of SiN- in the middle Pc" means that the strength of SiN- at a position of half the thickness of the lower Pb of the insulating layer 108 is greater than the strength of SiN- at a position of half the thickness of the middle Pc. According to yet other embodiments, "the strength of SiN- in the lower Pb is greater than the strength of SiN- in the middle Pc" means that the maximum strength of SiN- in the lower Pb of the insulating layer 108 is greater than the maximum strength of SiN- in the middle Pc.

[0090] It is noteworthy that after the oxide semiconductor layer 300 has undergone several heating and annealing processes, the free carriers in the second portion 300b (e.g., the doped region) of the oxide semiconductor layer 300 not covered by the insulating layer 106 will decrease, resulting in reduced conductivity. However, due to the aforementioned configuration (the lower Pb of the fourth portion 108p-2 of the insulating layer 108 has a relatively large SiN-strength), the fourth portion 108p-2 of the insulating layer 108 has a relatively large SiN-strength at a portion closer to the oxide semiconductor layer 300, thereby increasing the free carriers at the interface between the fourth portion 108p-2 of the insulating layer 108 and the second portion 300b (e.g., the doped region) of the oxide semiconductor layer 300, thereby improving the conductivity of the second portion 300b of the oxide semiconductor layer 300 or repairing defects on the surface of the oxide semiconductor layer 300.

[0091] Next, please refer to Figure 6 , Figure 6 A schematic diagram of the cross-sectional structure of the electronic device 20 is shown according to some other embodiments of the present disclosure. It should be understood that for the sake of clarity, some components of the electronic device 20 may be omitted in the drawings, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 20 described below. It should be understood that the components or components that are the same or similar to those in the previous text will be represented by the same or similar reference numerals, and their materials and functions are the same or similar to those described in the previous text, so this part will not be repeated in the following text.

[0092] In addition, the manufacturing method of the electronic device will be described below by taking the electronic device 20 as an example. Although the structure of the electronic device 20 is not exactly the same as that of the electronic device 10, similar or similar manufacturing methods are also applicable to the electronic device 10, and those skilled in the art can make corresponding adjustments according to different structures. It should be understood that according to some embodiments, additional operating steps may be provided before, during and / or after the manufacturing method of the electronic device 20. According to some embodiments, some of the operating steps may be replaced or omitted, and the order of some of the operating steps is interchangeable.

[0093] First, a substrate 102 is provided, and a buffer layer 104 is formed on the substrate 102. As mentioned above, the buffer layer 104 may have a single-layer or multi-layer structure. Figure 6As shown, according to some embodiments, the buffer layer 104 may have a double-layer structure, and the sub-layer 104a may be first formed on the substrate 102, and then the sub-layer 104b may be formed on the sub-layer 104a. According to some embodiments, the buffer layer 104 may be formed on the substrate 102 by a spin coating process, a chemical vapor deposition (CVD) process, other suitable methods or a combination thereof. The CVD process may include, for example, a low pressure chemical vapor deposition (LPCVD) process, a low temperature chemical vapor deposition (LTCVD) process, a rapid thermal chemical vapor deposition (RTCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, etc., but is not limited thereto.

[0094] Next, an oxide semiconductor layer 300 may be formed on the buffer layer 104, and the oxide semiconductor layer 300 has a first portion 300a and a second portion 300b adjacent to the first portion 300a. The first portion 300a may be used as a channel region, and the second portion 300b may be used as a doped region with a conductive property (e.g., n-type or p-type). According to some embodiments, the oxide semiconductor layer 300 may be formed by a chemical vapor deposition process, a physical vapor deposition (PVD) process, other suitable processes, or a combination thereof, and the second portion 300b may be doped with a suitable dopant by an ion implantation process.

[0095] Next, the surface 300s of the oxide semiconductor layer 300 may be treated with N2 plasma. It is worth noting that after the oxide semiconductor layer 300 is formed, further treating the surface 300s of the oxide semiconductor layer 300 with N2 plasma may passivate the dangling bonds on the surface 300s (e.g., forming SiN bonds), thereby repairing the defects on the surface 300s, improving the stability of the positive bias temperature stress (PBTS) performance of the thin film transistor, and thus improving the reliability of the electronic device 20.

[0096] Next, an insulating layer 106 may be formed on the oxide semiconductor layer 300. The insulating layer 106 may overlap with the first portion 300a of the oxide semiconductor layer 300, and partially overlap with the second portion 300b of the oxide semiconductor layer 300. According to some embodiments, the insulating layer 106 may be formed by a chemical vapor deposition process, a physical vapor deposition process, other suitable processes, or a combination thereof, and the insulating layer 106 may be patterned by one or more photolithography processes and / or etching processes. According to some embodiments, the photolithography process may include photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying, etc., but is not limited thereto. The etching process may include a dry etching process or a wet etching process, but is not limited thereto.

[0097] In detail, according to some embodiments, the step of forming the insulating layer 106 on the oxide semiconductor layer 300 includes introducing N2O(g), SiH4(g) and N2(g) in the deposition process to form a first layer (e.g., the lower portion 106b), and introducing N2O(g) and SiH4(g) in the deposition process to form a second layer (e.g., the upper portion 106t) on the first layer.

[0098] The oxide semiconductor layer 300 and the insulating layer 106 are substantially completed through the aforementioned steps. In particular, in the mass spectrum measured by TOF-SIMS, the concentration of SiN- at the interface S1 between the first portion 300a of the oxide semiconductor layer 300 and the insulating layer 106 is greater than the concentration of SiN- at the interface S2 between the first portion 300a and the buffer layer 104. Furthermore, in the mass spectrum measured by TOF-SIMS, the concentration of SiN- in the lower portion 106b is greater than the concentration of SiN- in the upper portion 106t.

[0099] Next, a gate electrode 204 may be formed on the insulating layer 106, and the gate electrode 204 overlaps the first portion 300a of the oxide semiconductor layer 300. As described above, the gate electrode 204 may have a single-layer or multi-layer structure. According to some embodiments, the gate electrode 204 may be formed by a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable methods, or a combination thereof. Furthermore, the gate electrode 204 may be patterned by one or more photolithography processes and / or etching processes.

[0100] Furthermore, if Figure 6As shown, according to some embodiments, an insulating layer 108 may be further formed on the gate electrode 204. Further, the insulating layer 108 may be conformably formed on the buffer layer 104, the oxide semiconductor layer 300, the insulating layer 106, and the gate electrode 204. According to some embodiments, the insulating layer 108 may be formed by a chemical vapor deposition process, a physical vapor deposition process, other suitable processes, or a combination thereof, and the insulating layer 108 may be patterned by one or more photolithography processes and / or etching processes.

[0101] In detail, according to some embodiments, N2O(g), SiH4(g), and N2(g) may be introduced into the deposition process to form the insulating layer 108 on the gate electrode 204. Furthermore, a portion of the insulating layer 108 may be removed by a patterning process to form a through hole V1 exposing the second portion 300b of the oxide semiconductor layer 300.

[0102] As described above, the insulating layer 108 may have a third portion 108p-1 (not shown) overlapping the gate electrode 204. In the mass spectrum measured by TOF-SIMS, the concentration of SiN- at the interface S3 between the third portion 108p-1 and the gate electrode 204 is greater than the concentration of SiN- at the interface S1 between the first portion 300a of the oxide semiconductor layer 300 and the insulating layer 106 (e.g. Figure 4 ). Furthermore, the insulating layer 108 may have a fourth portion 108p-2 (not shown) overlapping the second portion 300b of the oxide semiconductor layer 300, and the fourth portion 108p-2 has an upper portion Pa, a lower portion Pb, and a middle portion Pc disposed between the upper portion Pa and the lower portion Pb, and in the mass spectrum measured by TOF-SIMS, the concentration of SiN- in the lower portion Pb is greater than the concentration of SiN- in the middle portion Pc (as shown in FIG. Figure 5 shown).

[0103] According to some embodiments, a metal layer 206 may be further formed on the insulating layer 108, the metal layer 206 may be filled in the through hole V1 of the insulating layer 108, and electrically connected to the second portion 300b of the oxide semiconductor layer 300. The metal layer 206 may have a single-layer or multi-layer structure. According to some embodiments, the metal layer 206 may be formed by a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable methods, or a combination of the foregoing. In addition, the metal layer 206 may be patterned by one or more photolithography processes and / or etching processes.

[0104] like Figure 6As shown, compared with the electronic device 10, the electronic device 20 may not have the metal layer 202, and the thin film transistor in the electronic device 20 has a top gate thin film transistor structure. Furthermore, the first portion 300a and the second portion 300b of the oxide semiconductor layer 300 may serve as source / drain contacts and may be electrically connected to the source electrode / drain electrode (not shown) through the metal layer 206.

[0105] In summary, according to the embodiments of the present disclosure, the provided electronic device includes an oxide semiconductor layer processed by a specific process, thereby improving the stability of the positive bias temperature stress (PBTS) performance of the thin film transistor, thereby enhancing the reliability or overall performance of the electronic device.

[0106] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. The features between the embodiments of the present disclosure can be mixed and matched as needed as long as they do not violate the spirit of the invention or conflict with each other. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. The scope of protection of the present disclosure shall be subject to the scope of the appended claims. Any embodiment or claim of the present disclosure does not need to achieve all the purposes, advantages and features disclosed in this disclosure.

Claims

1. An electronic device, characterized in that: include: a substrate; a buffer layer disposed on the substrate; an oxide semiconductor layer disposed on the buffer layer and having a first portion and a second portion adjacent to the first portion; a first insulating layer disposed on the oxide semiconductor layer; and a gate electrode disposed on the substrate and overlapping the first portion of the oxide semiconductor layer; In the mass spectrum measured by TOF-SIMS, the intensity of SiN− at the interface between the first portion and the first insulating layer is greater than the intensity of SiN− at the interface between the first portion and the buffer layer.

2. The electronic device according to claim 1, wherein: The first insulating layer has an upper portion and a lower portion, and in a mass spectrum measured by TOF-SIMS, the intensity of SiN- in the lower portion is greater than the intensity of SiN- in the upper portion.

3. The electronic device according to claim 1, wherein: The invention further comprises a second insulating layer disposed on the gate electrode, the second insulating layer having a third portion overlapping the gate electrode, wherein in a mass spectrum measured by TOF-SIMS, the intensity of SiN- at the interface between the third portion and the gate electrode is greater than the intensity of SiN- at the interface between the first portion and the first insulating layer.

4. The electronic device as claimed in claim 3, characterized in that: The second insulating layer has a fourth portion overlapping the second portion of the oxide semiconductor layer, the fourth portion has an upper portion, a lower portion, and a middle portion arranged between the upper portion and the lower portion, and in the mass spectrum measured by TOF-SIMS, the intensity of SiN- in the lower portion is greater than the intensity of SiN- in the middle portion.

5. The electronic device according to claim 1, wherein: The invention further comprises a second insulating layer disposed on the gate electrode, wherein the second insulating layer comprises silicon oxynitride.

6. The electronic device as claimed in claim 1, wherein: The invention further comprises a metal layer overlapping with the oxide semiconductor layer, wherein the buffer layer is disposed between the metal layer and the oxide semiconductor layer.

7. The electronic device as claimed in claim 1, characterized in that: The oxide semiconductor layer includes indium and gallium.

8. The electronic device as claimed in claim 1, wherein: It is a display device.

9. A method for manufacturing an electronic device, characterized in that: include: providing a substrate; forming a buffer layer on the substrate; forming an oxide semiconductor layer on the buffer layer, wherein the oxide semiconductor layer has a first portion and a second portion adjacent to the first portion; performing N2 plasma treatment on a surface of the oxide semiconductor layer; forming a first insulating layer on the oxide semiconductor layer; as well as A gate electrode is formed on the substrate, wherein the gate electrode overlaps the first portion of the oxide semiconductor layer.

10. The method for manufacturing an electronic device according to claim 9, wherein: In a mass spectrum measured by TOF-SIMS, a SiN concentration at an interface between the first portion and the first insulating layer is greater than a SiN concentration at an interface between the first portion and the buffer layer.

11. The method for manufacturing an electronic device according to claim 9, wherein: The step of forming the first insulating layer on the oxide semiconductor layer comprises: Introducing N2O(g), SiH4(g) and N2(g) in a deposition process to form a first layer; and N2O(g) and SiH4(g) are introduced into the deposition process to form a second layer on the first layer.

12. The method for manufacturing an electronic device according to claim 11, wherein: The first insulating layer has an upper portion and a lower portion, and in a mass spectrum measured by TOF-SIMS, the concentration of SiN- in the lower portion is greater than the concentration of SiN- in the upper portion.

13. The method for manufacturing an electronic device according to claim 9, wherein: The method further includes introducing N2O(g), SiH4(g) and N2(g) in another deposition process to form a second insulating layer on the gate electrode.

14. The method for manufacturing an electronic device according to claim 13, wherein: The second insulating layer has a third portion overlapping the gate electrode, and in a mass spectrum measured by TOF-SIMS, a SiN- concentration at an interface between the third portion and the gate electrode is greater than a SiN- concentration at an interface between the first portion and the first insulating layer.

15. The method for manufacturing an electronic device according to claim 13, wherein: The second insulating layer has a fourth portion overlapping the second portion of the oxide semiconductor layer, the fourth portion has an upper portion, a lower portion, and a middle portion arranged between the upper portion and the lower portion, and in the mass spectrum measured by TOF-SIMS, the concentration of SiN- in the lower portion is greater than the concentration of SiN- in the middle portion.

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