Silicon carbide transverse JFET device and manufacturing method thereof

Abstract

The embodiment of the invention provides a silicon carbide transverse JFET device and a manufacturing method thereof, and the silicon carbide transverse JFET device comprises a p-type silicon carbide substrate; an n-type silicon carbide epitaxial layer formed on the silicon carbide substrate; the doping concentration of the silicon carbide substrate is greater than that of the silicon carbide epitaxial layer; the silicon carbide source region, the silicon carbide gate region and the silicon carbide drain region are formed in the silicon carbide epitaxial layer. According to the silicon carbide transverse JFET device and the manufacturing method thereof provided by the embodiment of the invention, the process steps of two epitaxial layers, a drift region, an injection region and the like in the traditional scheme are omitted, the production efficiency is greatly improved, the process difficulty is reduced, and the production cost is also reduced.

Description

Technical Field

[0001] The present application relates to semiconductor technology, and in particular to a silicon carbide lateral JFET device and a method for manufacturing the same. Background Art

[0002] Silicon carbide SiC lateral junction field effect transistor (Junction Field-Effect Transistor, referred to as: JFET) device is a semiconductor device that is very suitable for use as a radio frequency amplifier (Radio Frequency Power Amplifier, referred to as: RF PA). The bandgap width of SiC is several times larger than that of Si, which means that when designing devices with the same operating voltage, the size of silicon carbide devices is expected to be reduced to a fraction of that of silicon devices, and their on-resistance is also expected to be reduced several times. Secondly, unlike metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-EffectTransistor, referred to as: MOS) devices, the current conduction of JFET devices is inside the device and will not be affected by the high defect density of the SiC-oxide interface, so that a higher saturation current density can be achieved, and then a higher saturation output power can be achieved. In addition, SiC material has a high thermal conductivity and has a natural advantage in solving the heat dissipation problem under high power output conditions.

[0003] Traditional JFET devices all use n-type highly doped substrates, and make p+ epitaxial layers on the n-type substrates, and then make p- epitaxial layers, and then form drift regions, drain injection regions, drains, first source contact regions, second source contact regions, sources, channel regions, gates, oxide layers, metal compound layers, contact holes, metal layers and other functional regions in the p- epitaxial layers by means of photolithography and implantation. After the active region of the device is formed, the source of the device needs to be grounded by forming a grounding back hole, resulting in more manufacturing steps for JFET devices, more complex processes, lower production efficiency and higher costs. Summary of the invention

[0004] In order to solve one of the above technical defects, a silicon carbide lateral JFET device and a manufacturing method thereof are provided in an embodiment of the present application.

[0005] According to a first aspect of an embodiment of the present application, a silicon carbide lateral JFET device is provided, comprising:

[0006] A silicon carbide substrate, wherein the silicon carbide substrate is a p-type substrate;

[0007] A silicon carbide epitaxial layer is formed on a silicon carbide substrate, wherein the silicon carbide epitaxial layer is an n-type epitaxial layer; the doping concentration of the silicon carbide substrate is greater than the doping concentration of the silicon carbide epitaxial layer;

[0008] A silicon carbide source region, a silicon carbide gate region and a silicon carbide drain region are formed in the silicon carbide epitaxial layer.

[0009] According to a second aspect of an embodiment of the present application, a method for manufacturing a silicon carbide lateral JFET device is provided, comprising:

[0010] A silicon carbide epitaxial layer is formed on a silicon carbide substrate; the silicon carbide substrate is a p-type substrate, and the silicon carbide epitaxial layer is an n-type epitaxial layer; and a doping concentration of the silicon carbide substrate is greater than a doping concentration of the silicon carbide epitaxial layer;

[0011] A silicon carbide source region, a silicon carbide gate region and a silicon carbide drain region are respectively formed in the silicon carbide epitaxial layer.

[0012] The technical solution provided in the embodiment of the present application adopts a p-type silicon carbide substrate and an n-type silicon carbide epitaxial layer on the silicon carbide substrate, and the doping concentration of the p-type silicon carbide substrate is greater than the doping concentration of the n-type silicon carbide epitaxial layer. A silicon carbide source region, a silicon carbide gate region and a silicon carbide drain region can be directly formed in the n-type silicon carbide epitaxial layer, eliminating the two epitaxial layers and the process steps of the drift region, the injection region, and the two source contact regions in the traditional solution, greatly improving the production efficiency, reducing the process difficulty, and reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0014] Figure 1 A schematic diagram of the structure of a silicon carbide lateral JFET device provided in an embodiment of the present application;

[0015] Figure 2 A flow chart of a method for manufacturing a silicon carbide lateral JFET device provided in an embodiment of the present application;

[0016] Figure 3 A schematic diagram of a structure for forming an epitaxial layer on a substrate in a method for manufacturing a silicon carbide lateral JFET device provided in an embodiment of the present application;

[0017] Figure 4 A schematic diagram of the structure of forming various functional regions in an epitaxial layer in a method for manufacturing a silicon carbide lateral JFET device provided in an embodiment of the present application;

[0018] Figure 5 A schematic diagram of a structure for forming an insulating layer and a field plate on an epitaxial layer in a method for manufacturing a silicon carbide lateral JFET device provided in an embodiment of the present application;

[0019] Figure 6 A simulation diagram of a silicon carbide lateral JFET device provided in an embodiment of the present application;

[0020] Figure 7 This is an Id-Vg curve diagram of the silicon carbide lateral JFET device provided in an embodiment of the present application.

[0021] Reference numerals:

[0022] 1-Silicon carbide substrate; 2-Silicon carbide epitaxial layer; 3-Insulating layer; 41-Source region metal compound layer; 42-Gate region metal compound layer; 43-Drain region metal compound layer; 51-Source region contact through hole; 52-Gate region contact through hole; 53-Drain region contact through hole; 6-Field plate; 71-Source contact region; 72-Source contact region; 8-Silicon carbide gate region; 91-Drain step injection region; 92-Drain contact region; 10-Metal electrode layer. DETAILED DESCRIPTION

[0023] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0024] This embodiment provides a silicon carbide lateral JFET device, which has a relatively simple structure and requires fewer process steps, thus greatly reducing process difficulty, improving production efficiency, and significantly reducing production costs.

[0025] like Figure 1 As shown, the silicon carbide lateral JFET device provided in this embodiment includes: a silicon carbide substrate 1 and a silicon carbide epitaxial layer 2, wherein the silicon carbide epitaxial layer 2 is formed on the upper surface of the silicon carbide substrate 1. The silicon carbide substrate 1 is a p-type substrate, the silicon carbide epitaxial layer is an n-type substrate, and the doping concentration of the silicon carbide substrate 1 is greater than the doping concentration of the silicon carbide epitaxial layer 2.

[0026] A silicon carbide source region, a silicon carbide gate region and a silicon carbide drain region can be formed directly in the silicon carbide epitaxial layer 2, and a source region metal compound layer 41, a gate region metal compound layer 42 and a drain region metal compound layer 43 are respectively formed on the upper surfaces of the silicon carbide source region, the silicon carbide gate region and the silicon carbide drain region.

[0027] An insulating layer 3 may also be formed on the upper surfaces of the silicon carbide epitaxial layer 2 and the source metal compound layer 41, the gate metal compound layer 42 and the drain metal compound layer 43, and a source contact through hole 51, a gate contact through hole 52 and a drain contact through hole 53 which are electrically contacted with the source metal compound layer 41, the gate metal compound layer 42 and the drain metal compound layer 43 are formed in the insulating layer 3, and a field plate 6 is also provided in the insulating layer 3.

[0028] The technical solution provided in this embodiment adopts a p-type silicon carbide substrate, an n-type silicon carbide epitaxial layer on the silicon carbide substrate, and the doping concentration of the p-type silicon carbide substrate is greater than the doping concentration of the n-type silicon carbide epitaxial layer. A silicon carbide source region, a silicon carbide gate region, and a silicon carbide drain region can be directly formed in the n-type silicon carbide epitaxial layer, eliminating the two epitaxial layers and the process steps of the drift region, the injection region, and the two source contact regions in the traditional solution, thereby greatly improving the production efficiency, reducing the process difficulty, and reducing the production cost.

[0029] The silicon carbide substrate 1 may be a p-type polycrystalline silicon carbide substrate. Polycrystalline silicon carbide has the advantage of high activation concentration of p-type doping, and this material and single-crystalline silicon carbide can naturally form good contact. In addition, the growth of polycrystalline silicon carbide substrates has low equipment requirements, thereby reducing production costs.

[0030] The silicon carbide substrate 1 is highly doped, with a doping concentration of 1e19-1e20. The silicon carbide epitaxial layer 2 is low doped, with a doping concentration of 1e14-1e17.

[0031] For a lateral JFET device, a silicon carbide source region, a silicon carbide gate region and a silicon carbide drain region are spaced apart in a silicon carbide epitaxial layer, and the silicon carbide gate region is located between the silicon carbide source region and the silicon carbide drain region.

[0032] One implementation method is: the silicon carbide source region includes a source grounding region 71 formed in the silicon carbide epitaxial layer 2. The source grounding region 71 is in electrical contact with the silicon carbide substrate 1 and is used for grounding. Compared with the conventional solution, in this embodiment, the source grounding region 71 is provided in the silicon carbide epitaxial layer 2 to be in electrical contact with the silicon carbide substrate 1 and grounded, and there is no need to open a back hole on the device for grounding, thus eliminating the step of opening a back hole, which improves production efficiency on the one hand and reduces process difficulty on the other hand, thereby reducing production costs.

[0033] Another embodiment is that the silicon carbide source region further includes: a source contact region 72 formed in the silicon carbide epitaxial layer 2. Specifically, the source contact region 71 is located at the edge of the device, the source contact region 72 is located between the source contact region 71 and the silicon carbide gate region 8, and the source contact region 72 is located at the upper part of the silicon carbide epitaxial layer 2.

[0034] The source contact region 72 is electrically connected to the source grounding region 71, and the source metal compound layer 41 is formed on the upper surface of the source grounding region 71 and the source contact region 72, and is in electrical contact with the source grounding region 71 and the source contact region 72. The implantation depth of the source grounding region 71 can be equal to or greater than the thickness of the silicon carbide epitaxial layer 2, so that the source grounding region 71 is in electrical contact with the silicon carbide substrate 1. The source contact region 72 forms a good ohmic contact with the silicon carbide substrate 1 through the source grounding region 71, and is grounded, so there is no need to open a back hole on the device for grounding, and the step of opening the back hole is omitted.

[0035] Further, the silicon carbide drain region includes: a drain step injection region 91 and a drain contact region 92, both of which are arranged in the silicon carbide epitaxial layer 2 and located on the upper part of the silicon carbide epitaxial layer 2. The drain contact region 92 is formed in the drain step injection region 91 and located on the upper part of the drain step injection region 91. The drain region metal compound layer 43 is formed on the upper surface of the drain step injection region 91 and the drain contact region 92 and is in electrical contact with the drain step injection region 91 and the drain contact region 92.

[0036] An insulating layer 3 is formed on the upper surface of the silicon carbide epitaxial layer 2, the source metal compound layer 41, the gate metal compound layer 42 and the drain metal compound layer 43. The insulating layer 3 is specifically an oxide layer. In the process of growing the insulating layer 3 layer by layer, a source contact through hole 51, a gate contact through hole 52 and a drain contact through hole 53 are punched in the insulating layer 3 to form electrical contacts with the source metal compound layer 41, the gate metal compound layer 42 and the drain metal compound layer 43. In addition, in the process of growing the insulating layer 3, a field plate 6 is also formed in the insulating layer 3.

[0037] Afterwards, a metal electrode layer 10 is formed on the upper portion of the insulating layer 3 , corresponding to and electrically contacting the source region contact through hole 51 .

[0038] Based on the above technical solution, this embodiment also provides a method for manufacturing a silicon carbide lateral JFET device. Figure 2 As shown, the method includes:

[0039] Step 101, forming a silicon carbide epitaxial layer on a silicon carbide substrate; the silicon carbide substrate is a p-type substrate, and the silicon carbide epitaxial layer is an n-type epitaxial layer; the doping concentration of the silicon carbide substrate is greater than the doping concentration of the silicon carbide epitaxial layer.

[0040] like Figure 3 As shown, a lightly doped n-type silicon carbide epitaxial layer 2 is grown on the upper surface of a heavily doped p-type silicon carbide substrate 1 .

[0041] Step 102: forming a silicon carbide source region, a silicon carbide gate region and a silicon carbide drain region in the silicon carbide epitaxial layer respectively.

[0042] like Figure 4As shown, a silicon carbide source region, a silicon carbide gate region and a silicon carbide drain region are formed in the silicon carbide epitaxial layer 2 by an implantation process.

[0043] Specifically, a source contact region 71 is formed on the left side of the silicon carbide epitaxial layer 2, and a source contact region 72 is formed on the upper right side of the source contact region 71. A silicon carbide gate region 8 is formed on the right side of the source contact region 72, and the silicon carbide gate region 8 is spaced apart from the source contact region 72. A drain step implantation region 91 is formed on the right side of the silicon carbide epitaxial layer 2, and then a drain contact region 92 is formed in the drain step implantation region 91.

[0044] The source grounding region 71 is in electrical contact with the silicon carbide substrate 1 and is used for grounding, which can solve the problem of greater difficulty and more steps in traditional back hole grounding.

[0045] The above technical scheme forms a silicon carbide epitaxial layer on a silicon carbide substrate; the silicon carbide substrate is a p-type substrate, and the silicon carbide epitaxial layer is an n-type epitaxial layer; the doping concentration of the silicon carbide substrate is greater than the doping concentration of the silicon carbide epitaxial layer; a silicon carbide source region, a silicon carbide gate region, and a silicon carbide drain region are respectively formed in the silicon carbide epitaxial layer, thereby eliminating the two epitaxial layers and the process steps of the drift region, the injection region, and the two source contact regions in the traditional scheme, thereby greatly improving the production efficiency, reducing the process difficulty, and reducing the production cost.

[0046] On the basis of the above technical solution, the following steps may also be included: forming a source region metal compound layer, a gate region metal compound layer and a drain region metal compound layer on the upper surfaces of the silicon carbide source region, the silicon carbide gate region and the silicon carbide drain region respectively.

[0047] like Figure 5 As shown, a source region metal compound layer 42 is formed on the upper surface of the source contact region 71 and a portion of the source contact region 72 by etching and deposition processes. A gate region metal compound layer 42 is formed on the upper surface of the silicon carbide gate region 8. A drain region metal compound layer 43 is formed on the upper surface of a portion of the drain step implantation region 91 and the drain contact region 92.

[0048] Then, an insulating layer is formed over the silicon carbide epitaxial layer and the source region metal compound layer, the gate region metal compound layer and the drain region metal compound layer.

[0049] like Figure 5 As shown, after step 103, an oxide is grown on the upper surfaces of the silicon carbide epitaxial layer 2, the source metal compound layer 41, the gate metal compound layer 42 and the drain metal compound layer 43 to form an insulating layer 3. A field plate 6 is formed in the process of growing the oxide, and the field plate 6 is also formed by etching and deposition processes.

[0050] Next, a field plate and a source contact through hole, a gate contact through hole and a drain contact through hole which are respectively in electrical contact with the source metal compound layer, the gate metal compound layer and the drain metal compound layer are formed in the insulating layer.

[0051] In the process of forming the insulating layer 3, holes are etched downwards at positions corresponding to the source metal compound layer 41, the gate metal compound layer 42 and the drain metal compound layer 43 in the insulating layer 3 for multiple times, so that the source metal compound layer 41, the gate metal compound layer 42 and the drain metal compound layer 43 are exposed. Then, metal is filled into the holes by a deposition process to form a source contact through hole 51, a gate contact through hole 52 and a drain contact through hole 53, wherein the metal in the source contact through hole 51 is in electrical contact with the source metal compound layer 41, the metal in the gate contact through hole 52 is in electrical contact with the gate metal compound layer 42, and the metal in the drain contact through hole 53 is in electrical contact with the drain metal compound layer 43.

[0052] Afterwards, a metal electrode layer 10 is formed on the upper portion of the insulating layer 3 to electrically contact the source region contact via 51 , the gate region contact via 52 , and the drain region contact via 53 , respectively, so as to lead out source, gate, and drain electrical signals.

[0053] The silicon carbide substrate 1 may be a p-type polycrystalline silicon carbide substrate. Polycrystalline silicon carbide has the advantage of high activation concentration of p-type doping, and this material and single-crystalline silicon carbide can naturally form good contact. In addition, the growth of polycrystalline silicon carbide substrates has low equipment requirements, thereby reducing production costs.

[0054] The silicon carbide substrate 1 is highly doped, with a doping concentration of 1e19-1e20. The silicon carbide epitaxial layer 2 is low doped, with a doping concentration of 1e14-1e17.

[0055] In the above scheme, a silicon carbide source region is formed in the silicon carbide epitaxial layer, specifically comprising: first forming a source grounding region 71 in the silicon carbide epitaxial layer 2, the source grounding region 71 being located at the edge of the device. Then forming a source contact region 72 in the silicon carbide epitaxial layer 2, the source contact region 72 being located at the upper part of the silicon carbide epitaxial layer 2 and between the source grounding region 71 and the silicon carbide gate region 8, the source contact region 72 being electrically connected to the source grounding region 71. The source grounding region 71 is in electrical contact with the silicon carbide substrate 1 for grounding.

[0056] By grounding the source contact region 72 through the source grounding region 71, there is no need to open a back hole for grounding on the device, thus eliminating the step of opening a back hole, which improves production efficiency on the one hand and reduces process difficulty on the other hand, thereby reducing production costs.

[0057] Furthermore, a silicon carbide drain region is formed in the silicon carbide epitaxial layer, specifically comprising: firstly forming a drain step implantation region 91 in the silicon carbide epitaxial layer 2 , and then forming a drain contact region 92 in the drain step implantation region 91 .

[0058] The patent document with publication number CN116759464B is a typical traditional solution, which uses a highly doped n-type substrate, and makes a p+ epitaxial layer on the n-type substrate, and then makes a p- epitaxial layer, and then forms a drift region, a drain injection region, a drain, a first source contact region, a second source contact region, a source, a channel region, a gate, an oxide layer, a metal compound layer, a contact through hole, a metal layer and other functional regions in the p- epitaxial layer by means of photolithography and implantation, etc., using a process of two epitaxy and more than seven implantations.

[0059] The solution provided in this embodiment only requires one epitaxial growth and four implantation processes (to form source, gate, and drain, respectively), which greatly reduces the process steps, improves production efficiency, reduces production costs, and can significantly improve the yield rate.

[0060] After the active area of ​​the device is formed, the above patent document also needs to ground the source of the device by forming a grounding back hole, which leads to more manufacturing steps and more complicated processes of the JFET device, resulting in lower production efficiency and higher cost.

[0061] The solution provided in this embodiment can achieve source grounding by electrically contacting and grounding the source grounding area to the silicon carbide substrate, eliminating the step of forming a grounding control in the traditional solution, simplifying the manufacturing process, thereby improving production efficiency and reducing production costs.

[0062] like Figure 6 and Figure 7 As shown, the above technical solution can generate simulation results with normal device structure through simulation software, indicating that the above solution can be used to manufacture actual devices using conventional process production lines. In addition, it can be seen from the Id-Vg curve that when the gate voltage of the device is lower than a certain value (about -4.5V), the device is turned off; when the gate voltage is higher than a certain value (about -4.5V), the drain current increases with the increase of the gate voltage, and the overall device can be turned on and off, with good gate control capability.

[0063] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0064] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0065] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0066] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0067] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A silicon carbide lateral JFET device, characterized in that: include: A silicon carbide substrate, wherein the silicon carbide substrate is a p-type substrate; A silicon carbide epitaxial layer is formed on a silicon carbide substrate, wherein the silicon carbide epitaxial layer is an n-type epitaxial layer; the doping concentration of the silicon carbide substrate is greater than the doping concentration of the silicon carbide epitaxial layer; A silicon carbide source region, a silicon carbide gate region and a silicon carbide drain region are formed in the silicon carbide epitaxial layer.

2. The silicon carbide lateral JFET device according to claim 1, characterized in that: The silicon carbide substrate is a p-type polycrystalline silicon carbide substrate.

3. The silicon carbide lateral JFET device according to claim 1, characterized in that: The doping concentration of the silicon carbide substrate is 1e19-1e20, and / or the doping concentration of the silicon carbide epitaxial layer is 1e14-1e17.

4. The silicon carbide lateral JFET device according to any one of claims 1 to 3, characterized in that: The silicon carbide source region, the silicon carbide gate region and the silicon carbide drain region are arranged in the silicon carbide epitaxial layer at intervals, and the silicon carbide gate region is located between the silicon carbide source region and the silicon carbide drain region.

5. The silicon carbide lateral JFET device according to claim 1, characterized in that: The silicon carbide source region includes: a source contact region formed in the silicon carbide epitaxial layer; the source contact region is in electrical contact with the silicon carbide substrate and is used for grounding.

6. The silicon carbide lateral JFET device according to claim 5, characterized in that: The silicon carbide source region also includes: The source contact region is formed in the silicon carbide epitaxial layer and is located at the upper part of the silicon carbide epitaxial layer; the source contact region is located between the source contact region and the silicon carbide gate region, and the source contact region is electrically connected to the source contact region; the source contact region is electrically connected to the silicon carbide substrate and is grounded.

7. The silicon carbide lateral JFET device according to claim 4, characterized in that: The SiC drain region includes: A drain step implantation region is formed in the silicon carbide epitaxial layer and is located at an upper portion of the silicon carbide epitaxial layer; The drain contact region is formed in the drain step implantation region and is located at the upper portion of the drain step implantation region.

8. A method for manufacturing a silicon carbide lateral JFET device, characterized in that: include: A silicon carbide epitaxial layer is formed on a silicon carbide substrate; the silicon carbide substrate is a p-type substrate, and the silicon carbide epitaxial layer is an n-type epitaxial layer; and a doping concentration of the silicon carbide substrate is greater than a doping concentration of the silicon carbide epitaxial layer; A silicon carbide source region, a silicon carbide gate region and a silicon carbide drain region are respectively formed in the silicon carbide epitaxial layer.

9. The manufacturing method according to claim 8, characterized in that: The silicon carbide substrate is a p-type polycrystalline silicon carbide substrate; The doping concentration of the silicon carbide substrate is 1e19-1e20, and / or the doping concentration of the silicon carbide epitaxial layer is 1e14-1e17.

10. The manufacturing method according to claim 8, characterized in that: A silicon carbide source region is formed in the silicon carbide epitaxial layer, comprising: forming a source contact region in the silicon carbide epitaxial layer, the source contact region being in electrical contact with the substrate; A source contact region is formed in the silicon carbide epitaxial layer. The source contact region is located at the upper part of the silicon carbide epitaxial layer and between the source contact region and the silicon carbide gate region. The source contact region is electrically connected to the source contact region.

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