Integrated circuit device and method of forming same

Abstract

An integrated circuit device is provided. An integrated circuit device includes a substrate and a cell having a plurality of transistors. The transistor includes an upper transistor having an upper channel region. Further, the transistor includes a lower transistor between the substrate and the upper transistor. The lower transistor includes a lower channel region. The integrated circuit device includes a power line extending longitudinally in a first horizontal direction below a substrate and defining cell boundaries of cells extending longitudinally in the first horizontal direction. The integrated circuit device includes a cell boundary signal metal pattern extending longitudinally in a first horizontal direction on the cell and over the cell boundary and connected to at least two transistors of the plurality of transistors. Related methods of forming integrated circuit devices are also provided.

Description

Technical Field

[0001] The present disclosure relates generally to the field of integrated circuit devices, and more particularly, to an integrated circuit device including a standard cell having a lower interconnect metal layer at a cell boundary and a method of forming the same. Background Art

[0002] As the demand for high performance and / or high speed of integrated circuit devices increases, the degree of integration in integrated circuit devices also increases. Therefore, various structures of integrated circuit devices and methods of forming the same have been proposed to increase the integration density of integrated circuit devices. Summary of the invention

[0003] According to some embodiments, an integrated circuit device may include a substrate and a cell having a plurality of transistors. The plurality of transistors may include an upper transistor having an upper channel region. In addition, the plurality of transistors may also include a lower transistor between the substrate and the upper transistor. The lower transistor may include a lower channel region. The integrated circuit device may include a power line extending longitudinally in a first horizontal direction below the substrate and defining a cell boundary of the cell extending longitudinally in the first horizontal direction. The integrated circuit device may include a cell boundary signal metal pattern extending longitudinally in the first horizontal direction on the cell and above the cell boundary and connected to at least two transistors of the plurality of transistors.

[0004] According to some embodiments, an integrated circuit device may include a cell having a plurality of transistors arranged on a first side of a substrate. The plurality of transistors may include an upper transistor having an upper source / drain region. In addition, the plurality of transistors may include a lower transistor between the substrate and the upper transistor. The lower transistor may include a lower source / drain region. The integrated circuit device may include a back-end-of-line (BEOL) structure having a plurality of metal layers on a first side of the substrate. The upper transistor and the lower transistor may be between a bottommost metal layer of the plurality of metal layers and the substrate. The integrated circuit device may include a first power line and a second power line extending longitudinally in parallel in a first horizontal direction on a second side of the substrate. The first power line and the second power line may define a first cell boundary and a second cell boundary of the cell, respectively. The bottommost metal layer may have a cell boundary signal metal pattern extending longitudinally in a first horizontal direction above the first cell boundary and connected to at least two transistors of the plurality of transistors.

[0005] According to some embodiments, a method of forming an integrated circuit device may include forming a cell on a substrate. The cell may include a plurality of transistors on the substrate, the plurality of transistors including a lower transistor and an upper transistor. The lower transistor may include a lower channel region and the upper transistor may include an upper channel region. The cell may have a cell boundary extending in a first horizontal direction. The method may include forming a cell boundary metal pattern in a first metal layer above the substrate. The cell boundary metal pattern may extend in a first horizontal direction and may overlap with the cell boundary in a vertical direction. The cell boundary metal pattern may interconnect at least two transistors of the plurality of transistors. The cell boundary metal pattern may be connected to at least one of the lower transistor and the upper transistor. In addition, the method may include forming a power line extending longitudinally in the first horizontal direction. The cell boundary metal pattern may overlap with the power line and the cell boundary in a vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram schematically illustrating a portion of an integrated circuit according to some embodiments of the present disclosure.

[0007] Figure 2 and Figure 3 is a schematic layout of a portion of an integrated circuit device having a front side power distribution network (FSPDN).

[0008] Figure 4 is a schematic layout of an integrated circuit device with a backside power distribution network (BSPDN).

[0009] Figure 5 is a schematic layout of a first standard cell and a second standard cell that is a flipped version of the first standard cell.

[0010] Figure 6 and Figure 7 is a layout of standard cells with different horizontal sizes.

[0011] Fig. 8A is a top view of a standard cell according to some embodiments, and Figure 8B and Figure 8C They are Fig. 8A sectional views of a standard cell taken along line BB and line CC.

[0012] Fig. 9 and Fig.10 According to some embodiments, Fig. 8A A cross-sectional view of a standard cell taken along line BB in FIG.

[0013] Fig.11 is a layout view of a standard cell having sizes in a first horizontal direction and a second horizontal direction.

[0014] Fig.12 and Fig.13 are schematic layouts each showing a first standard cell and a second standard cell that is a flipped version of the first standard cell.

[0015] Fig.14 is a flow chart of a method of forming a device according to some embodiments.

[0016] Fig.15 is a flow chart of a method of manufacturing an integrated circuit according to some embodiments. DETAILED DESCRIPTION

[0017] Figure 1 1 is a diagram schematically illustrating a portion of an integrated circuit 100 according to some embodiments of the present disclosure. More specifically, Figure 1 1 is a top view showing the layout of the integrated circuit 100. The integrated circuit 100 includes a plurality of standard cells C11, C12, C13, C14, C15, C16, C17, C18, C19 on a plane containing an X-axis and a Y-axis. In this article, the X-axis direction may be referred to as the first horizontal axis, the first horizontal direction, or the first direction, the Y-axis direction may be referred to as the second horizontal axis, the second horizontal direction, or the second direction, and the Z-axis direction may be referred to as the vertical axis, the vertical direction, or the third direction. The plane including the X-axis and the Y-axis may be referred to as a horizontal plane. A component disposed relative to another component in the +Z-axis direction may be referred to as being on or above another component, and a component disposed relative to another component in the -Z-axis direction may be referred to as being below or below another component. Unless otherwise specified in the specification, the height of a component may indicate the length of the component in the Y-axis direction, and the thickness of a component may indicate the length of the component in the Z-axis direction. In addition, the area of ​​a component may refer to the size occupied by a component in a horizontal plane and a plane parallel to the horizontal plane. In the drawings of the specification, for convenience of explanation, some layers may be omitted, and for example, only some connections between a metal layer pattern and other patterns above and / or below the metal layer pattern are shown.

[0018] like Figure 1As shown in the image of , the integrated circuit 100 may include power lines PL11 to PL14 extending in the X-axis direction. The power lines PL11 to PL14 may provide a power supply voltage for providing power to the first cell C11 to the ninth cell C19, and the power lines PL11 to PL14 may be arranged on corresponding power rails of the integrated circuit 100. In some embodiments, different power supply voltages may be applied to adjacent power lines PL11 to PL14. For example, a positive power supply voltage may be applied to the odd power lines PL11 and PL13, and a ground voltage (or a negative power supply voltage) may be applied to the even power lines PL12 and PL14. In some embodiments, a ground voltage may be applied to the odd-numbered power lines PL11 and PL13, and a positive power supply voltage may be applied to the even-numbered power lines PL12 and PL14. The power lines PL11 to PL14 may be formed in one or more conductive layers.

[0019] Each of the plurality of standard cells C11 to C19 may be a unit of a layout included in an integrated circuit, may be designed to perform a predefined function, and may be referred to as a cell. The integrated circuit 100 may include a plurality of various standard cells, and the standard cells may be aligned along a plurality of rows.

[0020] A plurality of standard cells can be reused in integrated circuit design. Standard cells can be pre-designed according to manufacturing technology and stored in a standard cell library, and an integrated circuit can be designed by arranging and interconnecting the standard cells stored in the standard cell library according to design rules.

[0021] For example, the standard cell may include various basic circuits, such as inverters, AND gates, NAND gates, OR gates, XOR gates, and NOR gates, which are frequently used in digital circuit designs of electronic devices, such as central processing units (CPUs), graphics processing units (GPUs), and system-on-chip (SOC) designs. Alternatively, for example, the standard cell may include other circuits frequently used in circuit blocks, such as flip-flops and latches.

[0022] Standard cell library (or cell library) D12 (see Fig.15 ) can include information about standard cells, for example, Figure 1 The function information, feature information and layout information of the first cell C11 to the ninth cell C19 shown in FIG.

[0023] Figure 2 and Figure 3 is a schematic layout view of a portion of an integrated circuit device having a front side power distribution network (FSPDN).

[0024] In some embodiments and with reference to Figure 2, a layout 200 of a portion of an integrated circuit may include a first active region 204 and a second active region 206 that may be on an upper portion of a substrate 202. The first active region 204 and the second active region 206 may be a PMOSFET region and an NMOSFET region, respectively, but the present disclosure is not limited thereto. The first active region 204 and the second active region 206 may extend in an X-axis direction. In some embodiments, the first active region 204 and the second active region 206 may include vertical protrusions of the substrate 202. A device isolation layer (not shown) may be between the first active region 204 and the second active region 206. The device isolation layer may include a silicon oxide layer.

[0025] A transistor (e.g., a field effect transistor FET) may be formed in the first active region 204 and the second active region 206. More specifically, a gate line and the first active region 204 and the second active region 206 may form a transistor. The gate lines (e.g., the first gate line 208a, the second gate line 208b, etc.) may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. In some embodiments, the gate line may include a work function metal layer and a gap filling metal layer. For example, the work function metal layer may include at least one metal among Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd, and the gap filling metal layer may include a W layer or an Al layer. In some embodiments, the gate line may include a stacked structure of TiAlC / TiN / W, a stacked structure of TiN / TaN / TiAlC / TiN / W, or a stacked structure of TiN / TaN / TiN / TiAlC / TiN / W.

[0026] In some embodiments and with reference to Figure 3 In the layout 300 of FIG. 1 , stacked FETs may be included in a standard cell to form a logic circuit therein. The stacked FETs are described in more detail below. A stacking region or stacking area 310 on a substrate 302 may include one or more stacked transistor structures, and a transistor may be formed by a gate line and the stacking region 310. When compared to the planar area of ​​a standard cell including a non-stacked FET, the stacked FET may reduce the planar area of ​​the standard cell by about half, thereby facilitating a higher degree of integration in an integrated circuit device.

[0027] exist Figure 2 The layout of 200 and Figure 3In both of the layouts 300, a first metal layer 212 may be provided over the substrates 202 and 302. In some embodiments, a plurality of metal layers may be provided over the substrates 202 and 302, and the first metal layer 212 may be the lowest metal layer of the plurality of metal layers or the metal layer closest to the substrates 202 and 302. The first metal layer 212 may include a plurality of metal tracks 214a, 214b, 216a, 216b, and 216c, and it should be understood that the present disclosure is not limited to five metal tracks in the first metal layer 212. The plurality of metal tracks may extend parallel to each other in the X-axis direction and may be spaced apart from each other in the Y-axis direction. The plurality of metal tracks may include a first power track 214a and a second power track 214b and a plurality of lower interconnect tracks ( Figure 2 and Figure 3 2. The first metal layer 212 may further include first to third lower interconnection tracks 216a to 216c. Figure 2 and Figure 3 First and second power metal patterns 218a and 218b may be formed on respective first and second power rails 214a and 214b, and lower interconnection metal patterns (e.g., lower interconnection metal patterns 220a, 220b, and 220c) may be formed on each of the plurality of lower interconnection rails 216a-216c.

[0028] In other words, in layouts 200 and 300, a plurality of lower interconnection tracks may be defined between the first power track 214a and the second power track 214b. The first power track 214a and the second power track 214b may extend in the X-axis direction and may be spaced apart from each other in the Y-axis direction. In some embodiments, the plurality of lower interconnection tracks may be arranged to have a different spacing therebetween than between the lower interconnection tracks (e.g., the first lower interconnection track 216a) and the adjacent power tracks in the first power track 214a and the second power track 214b.

[0029] Figure 2 and Figure 3 The cell boundaries CB in the layout 200 and the layout 300 may be defined by the first power rail 214a and the second power rail 214b. For example, each cell boundary CB may correspond to the center portion of one of the first power rail 214a or the second power rail 214b in the Y-axis direction. Each cell boundary CB may be an imaginary line extending in the X-axis direction and intersecting the center portion of one of the first power line PL11 or the second power line PL12 in the Y-axis direction. Each cell boundary CB may also be in an imaginary plane defined by the X-axis direction and the Z-axis direction. Each cell boundary CB may indicate a boundary (e.g., an outermost range) of the layout 200 or 300 in the Y-axis direction.

[0030] Figure 4 is a schematic layout 400 of an integrated circuit device with a backside power distribution network (BSPDN). The BSPDN may provide increased integration and may address power requirements within an integrated circuit. Figure 4 The layout 400 does not show the substrate, but shows the first power rail 422a and the second power rail 422b that can contact the lower surface (in the Z-axis direction) of the substrate. Each of the first power rail 422a and the second power rail 422b can be electrically connected to a power source and provide a predetermined voltage (e.g., a drain voltage VDD or a source voltage VSS) to the components within the layout 400. Stacked or non-stacked transistors can be provided on the upper surface of the substrate and connected to Figure 4 The BSPDN may increase the power delivery efficiency in the layout 400 , reduce the area used for power delivery in the layout 400 , and / or improve the voltage drop (ie, IR drop) in the layout 400 .

[0031] It can be seen that providing a BSPDN for a standard cell can "free up" or make available the first power rail 214a and the second power rail 214b in the FSPDN. These available areas for the first metal rail and the second metal rail can instead be used for block routing metal rails 414a and 414b, which can be used in Figure 4 The layout 400 of FIG. 400 provides additional and / or more compact block routing. Block routing may refer to the process of establishing connections or paths between different standard cells or functional components within an integrated circuit. Block routing metal patterns 424 a and 424 b and vertical vias may be created along block routing metal tracks 414 a and 414 b to route signals between various standard cells and their components, such as logic gates, memory cells, and / or other application specific modules.

[0032] Block routing metal tracks 414a and 414b may be contrasted with lower interconnect tracks 216a-216c, which may also use horizontal metal patterns and vertical vias to route signals in first metal layer 212 within a standard cell (e.g., in Figure 4 The lower interconnect tracks 216a-216c are used to localize the interconnection to each standard cell, so they may be referred to herein as local interconnect tracks 216a-216c.

[0033] To maintain signal integrity and avoid crosstalk and parasitic capacitance, careful routing of both lower interconnect metal patterns 220a-220c and block routing metal patterns 424a and 424b is employed during the integrated circuit design process. Limited chip real estate, especially limited chip real estate at the metal layer of the substrate relatively close to the standard cells, can present challenges during routing.

[0034] In some cases, to provide improved routing efficiency in an integrated circuit, a standard cell may be flipped along a horizontal axis. Figure 5 5 is an enlarged schematic layout 500 of a first standard cell 526a and a second standard cell 526b that is a flipped version of the first standard cell 526a. The first standard cell 526a may have transistors, gates, and other components arranged in manner A, and the second standard cell 526b may have transistors, gates, and other components arranged in manner Ɐ. In other words, the layout of the first standard cell 526a may be horizontally mirrored or inverted to produce a layout of the second standard cell 526b. The first standard cell 526a and the second standard cell 526b may share a first power rail 422a and a common block routing metal track 414a, and may have corresponding power rails 422b / 422c and corresponding block routing metal tracks 414b / 414c. The flipping of the standard cell may be done during the design phase of manufacturing or fabricating an integrated circuit. The flipping of the standard cell may be performed to optimize the overall chip layout, improve routing efficiency, and / or meet specific design constraints. In some cases, the flipped standard cell (eg, the second standard cell 526 b ) may not be vertically aligned with the non-flipped standard cell (eg, the first standard cell 526 a ).

[0035] As the demand for high performance and / or high speed of integrated circuit devices increases, the level of integration in integrated circuit devices also increases. One way to increase the level of integration in an integrated circuit may be to utilize standard cells having smaller sizes. However, there may be practical limitations on reducing the size of a standard cell in a first dimension (e.g., the height of the standard cell), which may result in an increase in the size of the standard cell in a second dimension (e.g., the length or width of the standard cell). For example, Figure 6 and Figure 7 600, 700 are example layouts of portions of a standard cell that implement an AND-OR-NOT (AOI) function. Not all features or components of a standard cell are shown; for example, Figure 6 The layout of 600 and Figure 7 The buried power rail or backside power rail in layout 700 is not Figure 6 and Figure 7 Shown in.

[0036] refer to Figure 6 and Figure 7 , the gate lines 208d in layout 600 and layout 700 may each be spaced apart from each other by a first contact poly pitch CPP distance in the X-axis direction, as measured from a center or midline portion of each gate line 208d. Source / drain regions (not shown) may be formed between the gate lines 208d extending in the Y-axis direction, and contacts may be formed on the source / drain regions. The source / drain regions may include stacked source / drain regions of different conductivity types. For example, the stacked structure may include a first transistor structure and a second transistor structure, the first transistor structure being on a substrate and including a first source / drain region having a first conductivity type, the second transistor structure being stacked on the first transistor structure in a vertical (Z-axis) direction, the second transistor structure including a second source / drain region having a second conductivity type opposite to the first conductivity type.

[0037] The first metal layer (eg, M1 metal layer) 612 / 712 may be provided above the source / drain region (in the Z-axis direction). Figure 6 As seen in the layout 600 of FIG. 600 , the first metal layer 612 may include a first block routing metal track 614a and a second block routing metal track 614b and a first to fourth lower interconnection track (or local interconnection track) 616a, 616b, 616c and 616d. A lower via (not shown) may also be included in the first metal layer 612. The first block routing metal track 614a and the second block routing metal track 614b may extend in length in the X-axis direction along the cell boundary in the Y-axis direction of the layout 600. One or more metal patterns may be formed on each of the first block routing metal track 614a and the second block routing metal track 614b and the first to fourth lower interconnection track 616a to 616d. The pattern formed in the first metal layer 612 may extend in the X-axis direction.

[0038] Each of the block routing metal tracks and the lower interconnection tracks of the first metal layer 612 can be spaced apart by a distance T in the Y-axis direction, which is measured from the center or midline of each block routing metal track 614a and 614b (or in other words, each cell boundary CB in the Y-axis direction) and the center or midline of each lower interconnection track 616a to 616d. Therefore, the height in the Y-axis direction of the layout 600 can be said to be 5*T or 5T. As described above, the gate lines 208d in the layout 600 can each be spaced apart from each other by a first contact poly pitch CPP distance in the X-axis direction, and the length or width in the X-axis direction of the layout 600 can be said to be 4*CPP or 4CPP.

[0039] As from Figure 6 The layout of 600 and Figure 7As can be seen from the comparison between the layout 700 and the layout 700, if an attempt is made to reduce the height of the standard cell providing the AOI function from 5T to 4T (e.g., by having only the first to third lower interconnection tracks (or local interconnection tracks) 716a, 716b, and 716c between the first block routing metal track 714a and the second block routing metal track 714b or between the cell boundaries CB in the Y-axis direction), the limited ability to provide the lower interconnection metal pattern may result in Figure 7 The layout of 700 and Figure 6 The layout 600 has an increased width or length in the X-axis direction. In other words, Figure 7 The length or width of the layout 700 in the X-axis direction may be 5*CPP. Since the total horizontal or planar area of ​​each standard layout may be the product of the length in the X-axis direction and the height in the Y-axis direction, in some cases, Figure 7 The layout 700 may actually have a Figure 6 of the layout 600 larger area (for example, if CPP>T).

[0040] According to the inventive concept of the present disclosure, an integrated circuit and a standard cell are provided, wherein metal tracks at the cell boundary can be used for lower interconnection (e.g., interconnection within a standard cell) or for block routing (e.g., interconnection between standard cells). Such an arrangement can allow the standard cell to have a reduced planar area, reduce its effective size, and increase the density of the integrated circuit.

[0041] Fig. 8A , Figure 8B and Figure 8C is a diagram illustrating a standard cell 800 included in an integrated circuit according to some embodiments of the inventive concept. Fig. 8A is a top view of the standard cell 800, and Figure 8B and Figure 8C Along Fig. 8A For simplicity, FIG. 8A to FIG. 8C Not all components of the standard cell 800 are shown in the figure.

[0042] refer to FIG. 8A to FIG. 8C , the standard cell may include a substrate 828. The lower surface of the substrate 828 may extend in the X-axis direction and the Y-axis direction. The X-axis direction and the Y-axis direction may be parallel to the lower surface of the substrate 828.

[0043] In some embodiments, the substrate 828 may include or may be (multiple) insulating materials, such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or low-k materials. Low-k materials may include, for example, fluorine-doped silicon oxide, organic silicate glass, carbon-doped oxide, porous silicon dioxide, porous organic silicate glass, spin-on organic polymer dielectrics, and / or spin-on silicon-based polymer dielectrics. In some other embodiments, the substrate 828 may include or may be (multiple) semiconductor materials, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. For example, the substrate 828 may be (multiple) insulating layers, a bulk substrate (e.g., a bulk silicon wafer), and / or a semiconductor on insulator (SOI) substrate. The thickness of the substrate 828 in the Z-axis direction may be in the range of 50 nm to 100 nm, but the present disclosure is not limited thereto.

[0044] The substrate 828 may include portions separated from each other by trench isolation layers 830. The trench isolation layers 830 may include insulating material(s) (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or low-k materials). The lower channel region 832 and the upper channel region 834 may be on portions of the substrate 828 between the trench isolation layers 830.

[0045] In some embodiments, each of the lower channel region 832 and the upper channel region 834 may include a plurality of channel regions stacked in the Z-axis direction, and the channel regions may be spaced apart from each other in the Z-axis direction. Figure 8C It is shown that each of the lower channel region 832 and the upper channel region 834 includes two channel regions stacked in the Z-axis direction, but the present disclosure is not limited thereto. In some embodiments, each of the lower channel region 832 and the upper channel region 834 may include more or less than two channel regions stacked in the Z-axis direction.

[0046] The standard cell 800 may include one or more gate electrodes 808. Although not shown, the standard cell 800 may also include one or more gate insulators. Each gate electrode 808 and the corresponding gate insulator together may constitute a gate structure. The lower channel region 832 and the upper channel region 834 may extend through the gate electrode 808 in the X-axis direction, and a gate insulator may be provided between the gate electrode 808 and each of the lower channel region 832 and the upper channel region 834 to provide insulation therebetween. The gate insulator may contact the gate electrode 808 and / or each of the lower channel region 832 and the upper channel region 834. The gate insulator may separate the gate electrode 808 from the lower channel region 832 and the upper channel region 834. As shown in FIG. Figure 8CAs best shown in , the gate electrode 808 can extend longitudinally in the Y-axis direction and intersect the lower channel region 832 and the upper channel region 834.

[0047] The standard cell 800 may further include a pair of lower source / drain regions 836 and a pair of upper source / drain regions 838, of which only one is shown. FIG. 8A to FIG. 8C Although not shown in the figure, the gate electrode 808 may be provided between a pair of lower source / drain regions 836 in the X-axis direction, and between a pair of upper source / drain regions 838 in the X-axis direction. The pair of lower source / drain regions 836 may contact opposite side surfaces of the lower channel region 832 in the X-axis direction, respectively. Similarly, the pair of upper source / drain regions 838 may contact opposite side surfaces of the upper channel region 834 in the X-axis direction, respectively.

[0048] Each of the lower channel region 832 and the upper channel region 834 may include semiconductor material(s) (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some embodiments, each of the lower channel region 832 and the upper channel region 834 may be a nanosheet that may have a thickness in the range of 1 nanometer (nm) to 100 nm in the Z-axis direction, or may be a nanowire that may have a circular cross-section with a diameter in the range of 1 nm to 100 nm.

[0049] Each of the pair of lower source / drain regions 836 and the pair of upper source / drain regions 838 may include a semiconductor layer (e.g., a silicon (Si) layer and / or a silicon germanium (SiGe) layer), and may further include a dopant in the semiconductor layer. In some embodiments, each of the pair of lower source / drain regions 836 and the pair of upper source / drain regions 838 may include a metal layer including, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co), and / or ruthenium (Ru).

[0050] The gate insulator may include a single layer or multiple layers (eg, an interface layer and / or a high-k material layer). For example, the interface layer may include a silicon oxide layer, and the high-k material layer may include Al 2 O 3 , HfO 2 、ZrO 2 、HfZrO 4 、TiO 2 Sc 2 O 3 , Y 2 O 3 ,La 2 O 3 、Lu 2O 3 , Nb 2 O 5 and / or 2 O 5 .

[0051] The gate electrode 808 may include a single layer or multiple layers. In some embodiments, the gate electrode 808 may include a metal layer including, for example, W, Al, Cu, Mo, Co, and / or Ru.

[0052] In some embodiments, work function layer(s) 840 may be provided between the gate electrode 808 and the gate insulator. In some embodiments, work function layer(s) 840 may separate the gate electrode 808 from the gate insulator. Work function layer(s) 840 may include, for example, a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer.

[0053] The lower transistor may include a lower channel region 832, a pair of lower source / drain regions 836, and a portion of the gate electrode 808. The upper transistor may include an upper channel region 834, a pair of upper source / drain regions 838, and a portion of the gate electrode 808. In some embodiments, the lower transistor may be an N-type metal oxide semiconductor FET (NMOSFET) and the upper transistor may be a P-type MOSFET (PMOSFET), or vice versa, depending on the specifications of the standard cell 800. Together, the lower transistor and the upper transistor may constitute a stacked FET.

[0054] In some embodiments, the gate electrode 808 may be a common gate layer, such as Figure 8C As shown in . The upper portion of gate electrode 808 may be the gate electrode of the upper transistor including the upper channel region 834, and the lower portion of gate electrode 808 may be the gate electrode of the lower transistor including the lower channel region 832. Since gate electrode 808 is shared by the lower transistor as well as the upper transistor, the input of standard cell 800 may be commonly applied through gate electrode 808. Although Figure 8C The gate electrode 808 is shown to be shared by the lower transistor and the upper transistor, but the present disclosure is not limited thereto. In some embodiments, the lower portion of the gate electrode 808 can be separated and spaced apart from the upper portion of the gate electrode 808. For example, (multiple) insulating layers can be between the lower portion and the upper portion of the gate electrode 808, and the lower portion of the gate electrode 808 can be separated from the upper portion of the gate electrode 808. In this case, the lower portion of the gate electrode 808 can be the first gate electrode of the lower transistor, and the upper portion of the gate electrode 808 can be the second gate electrode of the upper transistor.

[0055] In some embodiments, each of the lower transistor and the upper transistor may be a three-dimensional (3D) FET, such as a multi-bridge channel FET (MBCFET). In some embodiments, one or more of the lower transistor and the upper transistor may have a structure different from that shown. For example, one or more of the lower transistor and the upper transistor may be a gate all around FET (GAAFET) or a fin FET (FinFET) including a single channel region.

[0056] An interlayer insulating layer 842 may be provided on the substrate 828, and a lower transistor and an upper transistor may be provided in the interlayer insulating layer 842. In particular, a lower channel region 832, an upper channel region 834, a pair of lower source / drain regions 836, a pair of upper source / drain regions 838, and a gate electrode 808 may be provided in the interlayer insulating layer 842.

[0057] Although the interlayer insulating layer 842 is shown as a single layer, in some embodiments, the interlayer insulating layer 842 may include multiple layers. The lower surface of the interlayer insulating layer 842 may contact the upper surface of the trench isolation layer 830. The interlayer insulating layer 842 may include (multiple) insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or low-k material).

[0058] The standard cell 800 may include a back-end-of-line (BEOL) structure formed by a BEOL portion of device fabrication. The BEOL structure may include a BEOL insulating layer 844. The BEOL insulating layer may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or a low-k material.

[0059] Furthermore, the BEOL structure may include multiple metal layers, and Fig. 8A A first metal layer 812 and a second metal layer 846 among the plurality of metal layers are shown. The first metal layer 812 may be the lowest metal layer among the plurality of metal layers relative to the substrate 828, or the metal layer of the BEOL structure closest to the substrate 828. The second metal layer 846 may be a metal layer among the plurality of metal layers that is further away from the substrate 828 than the first metal layer 812. Figure 8B and Figure 8C The second metal layer 846 is omitted.

[0060] The standard cell 800 may include a plurality of tracks for each of the plurality of metal layers including the first metal layer 812, and may include a pattern extending in a certain direction along the plurality of tracks. For example, the standard cell 800 may include lower interconnection tracks (or local interconnection tracks) 816a, 816b, and 816c, which may be similar to Figures 2 to 41 to 3 lower interconnecting rails 216a to 216c shown in FIG.

[0061] The standard cell 800 may include one or more lower interconnect metal patterns 848 on each lower interconnect track (or local interconnect track) for transmitting signals (e.g., data signals). For example, each lower interconnect track may include one or more lower interconnect metal patterns 848 arranged on the lower interconnect track and extending in the X direction, and spaced apart from other lower interconnect metal patterns 848 disposed on the same track in the X direction and spaced apart from other lower interconnect metal patterns 848 disposed on other tracks in the Y direction. Each lower interconnect metal pattern 848 may be a signal metal pattern and is referred to as a signal metal pattern 848. As discussed above, the lower interconnect metal pattern 848 extending along a plurality of lower interconnect tracks may be a lower interconnect metal pattern that interconnects two or more components or regions located within the standard cell 800.

[0062] In addition, the standard cell 800 may include one or more cell boundary metal tracks (e.g., a first cell boundary metal track 850a, a second cell boundary metal track 850b), which may include metal patterns for local interconnection within the standard cell 800 and / or metal patterns for block routing to standard cells (not shown) outside the standard cell 800.

[0063] One or more metal patterns may be on each cell boundary metal track and used to transmit signals (e.g., data signals), and may therefore be referred to as cell boundary metal patterns or cell boundary signal metal patterns. For example, either or both of the cell boundary metal patterns 852a and 852b may be metal patterns within the first metal layer 812 and disposed at the cell boundary CB of the standard cell 800. In some embodiments, one or both of the cell boundary metal tracks disposed at the cell boundary CB of the standard cell 800 may be block routing metal patterns that interconnect the standard cell 800 with different standard cells of the integrated circuit.

[0064] A plurality of metal tracks (including the cell boundary metal track and the lower interconnection track) may extend parallel to each other in the X-axis direction and may be spaced apart from each other in the Y-axis direction.

[0065] The metal patterns 848 and 852a, 852b formed in each of the plurality of metal layers may include metal, conductive metal nitride, metal silicide, or a combination thereof. In the drawings herein, for ease of illustration, only some layers may be shown, and vias may not be shown even if they are located under the patterns of the metal layers.

[0066] The standard cell 800 may further include a backside power distribution network structure (BSPDN) 856. The BSPDN 856 may contact the lower surface of the substrate 828. The BSPDN 856 may include a backside insulator 858, and the first power line 822a and the second power line 822b may be provided in the backside insulator. The BSPDN 856 may include a power delivery network including the first power line 822a and the second power line 822b. The first power line 822a and the second power line 822b may each be electrically connected to a drain voltage having a predetermined voltage (e.g., a drain voltage V DD or source voltage V SS ) which can be used to provide power to, for example, a pair of lower source / drain regions 836 and a pair of upper source / drain regions 838. In some embodiments, more than one of the first power line 822a and the second power line 822b can be provided in the standard cell 800. For example, the standard cell 800 can include two of the first power lines 822a and one of the second power lines 822b. In other words, the number of first power lines 822a may not be equal to the number of second power lines 822b. The first power line 822a and the second power line 822b can be electrically connected to a pair of lower source / drain regions 836 or a pair of upper source / drain regions 838 via (multiple) conductive paths and / or (multiple) contact structures (such as contact structures 860), and in some embodiments, the contact structures 860 can extend through or penetrate the substrate 828.

[0067] The BSPDN 856 may include one or more conductive layers (e.g., metal layers) stacked in the Z-axis direction, which provide power delivery. The conductive layers may be respectively included in insulating layers such as the backside insulator 858, and conductive via plugs (e.g., metal via plugs) may electrically connect the conductive layers to each other in the Z-axis direction. For example, the backside insulator of the BSPDN 856 may include a plurality of layers stacked on the lower surface of the substrate 828. The conductive layer may include one or more conductive lines (e.g., metal lines). In some embodiments, an intermediate structure may be provided between the substrate 828 and the BSPDN 856, and the substrate 828 may be separated from the BSPDN 856. The BSPDN 856 may increase the power delivery efficiency in the standard cell 800, reduce the area used for power delivery in the standard cell 800, and / or improve the voltage drop (i.e., IR drop) in the standard cell 800.

[0068] Fig. 9is a cross-sectional view of a layout 900 according to some embodiments of the present disclosure, showing that an upper transistor (more specifically, one of a pair of upper source / drain regions 938 thereof) can be connected to a cell boundary metal pattern 952a in a cell boundary metal track 950a that overlaps a cell boundary CB (in the Z-axis direction) extending in the X-axis direction on the Y-axis side of the layout 900. At the same time, a lower transistor (more specifically, one of a pair of lower source / drain regions 936 thereof) can be connected to a lower interconnect metal pattern 948c in a lower interconnect track 916c that does not overlap one of the cell boundaries CB of the layout 900. It can also be seen that the cell boundary metal pattern 952a can overlap one of the first power lines 922a in the Z-axis direction.

[0069] The upper source / drain region 938 may be connected to the cell boundary metal pattern 952a through a first via 964a and a first source / drain contact 966a. The lower source / drain region 936 may be connected to the lower interconnect metal pattern 948c through a second via 964b, a third via 964c, and a second source / drain contact 966b. In some embodiments, the second via 964b and the third via 964c may be formed as a single via. Fig. 9 The description of some repeated parts is omitted.

[0070] Fig.10 is a cross-sectional view of a layout 1000 according to some embodiments of the present disclosure, showing that a lower transistor (more specifically, one of a pair of lower source / drain regions 1036 thereof) can be connected to a cell boundary metal pattern 1052b in a cell boundary metal track 1050b that overlaps a cell boundary CB (in the Z-axis direction) extending in the X-axis direction on the Y-axis side of the layout 1000. At the same time, an upper transistor (more specifically, one of a pair of upper source / drain regions 1038 thereof) can be connected to a lower interconnect metal pattern 1048a in a lower interconnect track 1016a that does not overlap one of the cell boundaries CB of the layout 1000. It can also be seen that a cell boundary metal pattern 1052a in the cell boundary metal track 1050a can overlap one of the first power lines 1022a in the Z-axis direction.

[0071] The upper source / drain region 1038 may be connected to the lower interconnect metal pattern 1048a through a first via 1064a and a first source / drain contact 1066a. The lower source / drain region 1036 may be connected to the cell boundary metal pattern 1052b through a second via 1064b, a third via 1064c, and a second source / drain contact 1066b. In some embodiments, the second via 1064b and the third via 1064c may be formed as a single via. Fig.10 The description of some repeated parts is omitted.

[0072] Fig.11 It realizes the AND or NOT (AOI) function and can be used with Figure 6 The layout of 600 and Figure 7 Layout 700 is compared to an example layout 1100 of a portion of a standard cell. Not all features or components of the standard cell of layout 1100 are shown; for example, Fig.11 The buried power rail or backside power rail present in the layout 1100 is not Fig.11 Shown in.

[0073] refer to Fig.11 , the gates 1108 in the layout 1100 may each be spaced apart from each other by a first contact poly pitch CPP distance in the X-axis direction, as measured from the center or midline portion of each gate 1108. In the first metal layer 1112, the three lower interconnection tracks 1116a, 1116b, and 1116c of the first metal layer 1112 may be spaced apart by a distance T in the Y-axis direction, as measured from the center or midline of each of the lower interconnection tracks 1116a, 1116b, and 1116c. In addition, a cell boundary metal track 1150a extending in the X-axis direction over the first cell boundary CB in the Y-axis direction may be used for the lower interconnection, and a lower interconnection metal pattern may be formed therein. A cell boundary metal track 1150a extending in the X-axis direction over the second cell boundary CB in the Y-axis direction may be used for block routing. Therefore, the layout 1100 may have four metal tracks for the lower interconnection, including the lower interconnection tracks 1116a to 1116c and the cell boundary metal track 1150a.

[0074] The height of the layout 1100 in the Y-axis direction can be referred to as 4*T or 4T. As discussed above, the gates 1108 in the layout 1100 can each be spaced apart from each other by a first contact poly pitch CPP distance in the X-axis direction, and the length or width of the layout 1100 in the X-axis direction can be referred to as 4*CPP or 4CPP. Figure 6 The layout of 600 and Figure 7 Compared to layout 700 , layout 1100 may have a reduced plan area.

[0075] It will be appreciated that when a standard cell is flipped and placed, the cell boundary metal tracks (e.g. FIG. 8A to FIG. 8C One or both of the cell boundary metal tracks 850a, 850b) may conflict. For example, Fig.12 A layout 1200 of a first standard cell 1226a and a second standard cell 1226b that is a flipped version of the first standard cell 1226a is shown. The first standard cell 1226a may have one or more metal patterns in its cell boundary metal track 1250a, and flipping and placing the second standard cell 1226b so as to share a common power rail may result in the second standard cell 1226b having one or more metal patterns in its cell boundary metal track 1250a. Figure 5 Attempting to place the first standard cell 1226a and the second standard cell 1226b as in the layout 500 of FIG. 5 may result in a conflict because the metal patterns in the cell boundary metal track 1250a and the cell boundary metal track 1250b may incorrectly interfere with or overlap each other. Fig.13 and the layout 1300 therein, providing two or more first power lines 1322a (or two or more second power lines 1322b) may result in a standard cell 1326a having power lines 1322a having the same potential at its first cell boundary CB and second cell boundary CB, the first cell boundary CB and the second cell boundary CB being opposite to each other across the standard cell 1326a. Thus, flipping the first standard cell 1326a twice, or conversely not flipping the first standard cell 1326a at all, to produce the second standard cell 1326b will however allow the first standard cell 1326a and the second standard cell 1326b to be placed such that the first standard cell 1326a and the second standard cell 1326b share a common power rail, as Fig.13 As can be seen in Figures 11 to 13 The description of some repeated parts is omitted.

[0076] Fig.14 is a flow chart of a method of forming an integrated circuit device according to some embodiments.

[0077] refer to Fig.14 and FIG. 8A to FIG. 8C , can be on a substrate (e.g., FIG. 8A to FIG. 8C A cell is formed on a substrate 828 of a substrate 828 (block 1410). Forming the cell may include forming a lower channel region 832, which may be formed on the substrate 828. The lower channel region 832 may be alternately stacked with a portion of a sacrificial layer (not shown) in a third direction Z. An upper channel region 834 may be formed on the lower channel region. The lower channel region 832 may be between the substrate 828 and the upper channel region 834. The upper channel region 834 may be alternately stacked with a portion of a sacrificial layer in the third direction Z.

[0078] The sacrificial layer may include a material having an etching selectivity relative to the lower channel region 832 and the upper channel region 834. The sacrificial layer may include, for example, semiconductor material(s) (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some embodiments, the sacrificial layer may include a SiGe layer.

[0079] The sacrificial layer may be removed and replaced with the gate electrode 808 and the gate insulator. For example, the sacrificial layer may be selectively removed by an etching process (eg, a dry etching process and / or a wet etching process) without removing the lower channel region 832 and the upper channel region 834.

[0080] In some embodiments, work function layer(s) 840 can be provided between the gate electrode 808 and the gate insulator. In some embodiments, work function layer(s) 840 can extend between the gate electrode 808 and the gate insulator and can separate the gate electrode 808 from the gate insulator.

[0081] Forming the unit may include forming a pair of lower source / drain regions 836. The pair of lower source / drain regions 836 may be formed, for example, by performing an epitaxial growth process using the lower channel region 832 as a seed layer. Specifically, the pair of lower source / drain regions 836 may be grown from opposite side surfaces of the lower channel region 832 in the first direction X, respectively, by an epitaxial growth process. The first lower source / drain region 836 may be grown from a first side surface of the lower channel region 832, and the second lower source / drain region 836 may be grown from a second side surface of the lower channel region 832 opposite to the first side surface in the first direction X.

[0082] Forming the unit may include forming a pair of upper source / drain regions 838. The pair of upper source / drain regions 838 may be formed by performing an epitaxial growth process using the upper channel region 834 as a seed layer. Specifically, the pair of upper source / drain regions 838 may be grown from opposite side surfaces of the upper channel region 834 in the first direction X, respectively, by an epitaxial growth process. The first upper source / drain region 838 may be grown from a first side surface of the upper channel region 834, and the second upper source / drain region 838 may be grown from a second side surface of the upper channel region 834 opposite to the first side surface in the first direction X.

[0083] refer to Fig.14 , FIG. 8A to FIG. 8C , Fig. 9 and Fig.10, a BEOL structure may be formed over the cell and may include a plurality of metal layers and metal patterns arranged along tracks therein. The metal patterns may include lower interconnect metal patterns. A cell boundary signal metal pattern may be formed over the cell on its cell boundary CB (block 1420). The cell boundary signal metal pattern may be formed in the cell boundary metal track. Reference Fig. 8A , the BEOL structure may include a first metal layer 812 and a second metal layer 846 among the plurality of metal layers, and a cell boundary signal metal pattern may be formed on a cell boundary metal track in the first (lowest) metal layer 812. In addition, forming the BEOL structure and the plurality of metal layers and metal patterns may include forming contacts and vias (e.g., contacts 966a / 966b and / or vias 964a / 964b) to connect the cell boundary metal pattern with one or more of the upper source / drain region 838 and the lower source / drain region 838. For example, Fig. 9 An upper source / drain region 938 connected to a cell boundary metal pattern 952a is shown, and Fig.10 The lower source / drain region 1036 connected to the cell boundary metal pattern 1052 b is shown, but it is understood that the present disclosure is not limited thereto.

[0084] refer to Fig.14 , FIG. 8A to FIG. 8C , Fig. 9 and Fig.10 , a BSPDN 856 including the first power line 822a and the second power line 822b may be formed, and the BSPDN 856 may be formed on a side of the substrate 828 opposite to the cell (block 1430). Central portions of at least some of the first power line 822a and the second power line 822b in the second direction Y may define or extend along the cell boundary CB.

[0085] Fig.15 is a flow chart of a method 1500 of manufacturing an IC according to some embodiments. In detail, Fig.15 The flowchart of FIG. 1 shows an example of a method of manufacturing an IC including a standard cell. Fig.15 As shown in , the method of manufacturing an IC may include operations S10, S30, S50, S70, and S90. As shown in the figure, the cell library (or standard cell library) D12 may include information about the standard cell, for example, information about the function, feature, layout, etc. of the standard cell. In some embodiments, the cell library D12 may define a standard cell that uses at least one boundary metal track as a lower interconnect track or uses a boundary wiring layer as a lower interconnect wiring layer.

[0086] Design rule D14 may include requirements for IC layout. For example, design rule D14 may include requirements for spacing between patterns in a layer, minimum width of a pattern, routing direction of a wiring layer, etc. In some embodiments, design rule D14 may define the minimum spacing in tracks of a wiring layer.

[0087] Logic synthesis (by which a netlist D13 is generated from the RTL data D11) may be performed in operation S10. For example, a semiconductor design tool (e.g., a logic synthesis tool) may perform logic synthesis on the RTL data D11 written in a very high speed IC (VHSIC) hardware description language (HDL) (VHDL) and HDL such as Verilog with reference to the cell library D12, and generate a netlist D13. The netlist D13 may correspond to an input for placement and routing, which will be described below.

[0088] In operation S30, a cell may be placed. For example, a semiconductor design tool (e.g., a P&R tool) may refer to a cell library D12 to place a standard cell used in a netlist D13. In some embodiments, the semiconductor design tool may select a standard cell from the cell library D12 and place the selected standard cell. In operation S50, the pins of the standard cell may be routed. For example, the semiconductor design tool may generate an interconnection that electrically connects the output pins and input pins of the placed standard cell, and generate layout data D15 defining the placed standard cell and the interconnection. The interconnection may include a pattern of a path layer and / or a wiring layer. In some embodiments, the interconnection may include a pattern that connects heterogeneous devices to each other. For example, the layout data D15 may have a format such as GDSII and include geometric information of the cell and the interconnection. The semiconductor design tool may refer to the design rule D14 when routing the pins of the cell. The layout data D15 may correspond to the output of the placement and routing. Operation S50 may be separate, or operations S30 and S50 may be collectively referred to as a method for designing an IC.

[0089] A mask may be manufactured in operation S70. For example, optical proximity correction (OPC) for correcting distortion (such as refraction) caused by characteristics of light in photolithography may be performed on the layout data D15. Based on the data that has undergone OPC, a pattern on a mask may be defined to form a pattern arranged in a plurality of layers, and at least one mask (or photomask) for forming a pattern of each layer may be manufactured. In some embodiments, the layout of the IC may be limitedly modified in operation S70. Limitedly modifying the IC in operation S70 may be a post-processing for optimizing the structure of the IC, and is referred to as design polishing.

[0090] The IC may be manufactured in operation S90. For example, the IC may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S70. For example, FEOL may include planarizing and cleaning the wafer, forming trenches, forming wells, forming gate electrodes, and forming source and drain electrodes. Various devices, such as transistors, capacitors, resistors, etc., may be formed in the substrate via FEOL. BEOL (back-end process) may include silicide of the gate and source and drain regions, adding dielectrics, planarizing, forming holes, adding metal layers, forming paths, and forming passivation layers. Various devices (e.g., transistors, capacitors, resistors, etc.) may be interconnected to each other via BEOL. In some embodiments, MOL may be performed between FEOL and BEOL so that contacts may be formed on various devices. Thereafter, the IC may be packaged in a semiconductor package and used as a component for various applications.

[0091] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of the present disclosure, and therefore the present disclosure should not be construed as being limited to the example embodiments set forth herein. Rather, these exemplary embodiments are provided so that the present disclosure will be thorough and complete, and will convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements.

[0092] Example embodiments are described herein with reference to cross-sectional illustrations, which are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the embodiments herein should not be construed as limited to the specific shapes shown herein, but may include deviations in shape, for example, caused by manufacturing. Although an element is shown as a single layer in the drawings, the element may include multiple layers.

[0093] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0094] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to also include plural forms, unless the context clearly states otherwise. It will be further understood that when used in this specification, the terms "comprising", "comprising ... ", "including" and / or "comprising ... " indicate the presence of the features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or their groups.

[0095] It will be understood that when an element is referred to as being "connected to" or "on" another element, it may be directly connected to or on another element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected to" or "directly on" another element, there are no intervening elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the symbol " / " (for example, when used in the term "source / drain") will be understood to be equivalent to the term "and / or".

[0096] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, the first element can be referred to as the second element without departing from the teaching of this embodiment.

[0097] For ease of description, spatial relative terms such as "below", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between an element or feature and another (multiple) element or feature as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as being "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the term "below" can cover both the above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0098] Many different embodiments have been disclosed herein in conjunction with the above description and accompanying drawings. It will be understood that literally describing and illustrating every combination and subcombination of these embodiments would be overly repetitive and confusing. Therefore, this specification (including the accompanying drawings) should be interpreted as constituting a complete written description of all combinations and subcombinations of the embodiments described herein, as well as the manner and process of making and using them, and should support claims to any such combination or subcombination.

[0099] The subject matter disclosed above is considered to be illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the invention. Therefore, to the maximum extent allowed by law, the scope will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

[0100] This application claims priority to U.S. Provisional Application No. 63 / 585,747, filed in the USPTO on September 27, 2023, and entitled “Integrated Circuit Device and Method of Forming the Same,” the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: substrate; a cell comprising a plurality of transistors, the plurality of transistors comprising an upper transistor, the upper transistor comprising an upper channel region, and the plurality of transistors comprising a lower transistor located between the substrate and the upper transistor, the lower transistor comprising a lower channel region; electric field lines extending longitudinally in a first horizontal direction beneath the substrate and defining cell boundaries of the cells extending longitudinally in the first horizontal direction; as well as A cell boundary signal metal pattern is on the cell and extends longitudinally above the cell boundary in the first horizontal direction and is connected to at least two transistors of the plurality of transistors.

2. The integrated circuit device according to claim 1, further comprising: The back-end process structure includes a plurality of metal layers on the unit, wherein the unit boundary signal metal pattern is in a first metal layer closest to the substrate among the plurality of metal layers.

3. The integrated circuit device of claim 1 , wherein the cell boundary signal metal pattern is arranged along a cell boundary metal track extending longitudinally above the cell boundary, the integrated circuit device further comprising a plurality of lower interconnect metal tracks extending parallel to the cell boundary signal metal pattern in the first horizontal direction and spaced apart from each other and the cell boundary in a second horizontal direction intersecting the first horizontal direction.

4. An integrated circuit device according to claim 3, wherein the power line is a first power line and the cell boundary defined thereby is a first cell boundary of the cell, and the integrated circuit device further comprises a second power line extending longitudinally in the first horizontal direction parallel to the first power line, the second power line defining a second cell boundary of the cell extending longitudinally in the first horizontal direction. 5 . The integrated circuit device of claim 4 , wherein the first power line and the second power line are configured to carry power signals having a same power supply voltage.

6. The integrated circuit device according to claim 4 further includes a third power line, which extends horizontally in the first horizontal direction and is between the first power line and the second power line and is spaced apart from the first power line and the second power line in the second horizontal direction, and the third power line is configured to carry a power signal having a different power supply voltage from the first power line.

7. An integrated circuit device according to claim 4, wherein the integrated circuit device includes a plurality of cells, and the cell is a first cell among the plurality of cells, the integrated circuit device also includes a block routing metal pattern extending longitudinally in the first horizontal direction on the first cell and above the second cell boundary, the block routing metal pattern being connected between a transistor of the first cell and another cell of the integrated circuit device. 8 . The integrated circuit device of claim 1 , wherein the upper transistor or the lower transistor is electrically connected to the power line through a via extending through the substrate.

9. An integrated circuit device comprising: a cell comprising a plurality of transistors arranged on a first side of a substrate, the plurality of transistors comprising an upper transistor including an upper source / drain region, the plurality of transistors comprising a lower transistor between the substrate and the upper transistor, the lower transistor comprising a lower source / drain region; a back-end-of-line structure, comprising a plurality of metal layers on the first side of the substrate, the upper transistor and the lower transistor being between a bottommost metal layer of the plurality of metal layers and the substrate; as well as first and second power lines extending longitudinally in parallel in a first horizontal direction on a second side of the substrate, the first and second power lines defining a first cell boundary and a second cell boundary of the cell, respectively, The lowermost metal layer includes a cell boundary signal metal pattern, the cell boundary signal metal pattern extending longitudinally in the first horizontal direction over the first cell boundary and connected to at least two transistors of the plurality of transistors.

10. The integrated circuit device of claim 9, wherein the cell boundary signal metal pattern is arranged along a first cell boundary metal track extending longitudinally over the first cell boundary.

11. The integrated circuit device of claim 10, wherein the cell is a first cell, the integrated circuit device further comprising a block routing metal pattern arranged along a second cell boundary metal track and connected to a second cell of the integrated circuit device, the second cell boundary metal track extending longitudinally over the second cell boundary. 12 . The integrated circuit device of claim 9 , wherein the cell boundary signal metal pattern is electrically connected to the upper source / drain region.

13. The integrated circuit device of claim 9, wherein the cell boundary signal metal pattern is electrically connected to the lower source / drain region. 14 . The integrated circuit device of claim 9 , wherein the first power line and the second power line are configured to provide the same power supply voltage to the cell.

15. The integrated circuit device according to claim 14 further includes a third power line, which extends horizontally in the first horizontal direction and is between the first power line and the second power line and is spaced apart from the first power line and the second power line in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction, and the third power line is configured to carry a power signal having a different power supply voltage from the first power line. 16 . The integrated circuit device according to claim 9 , wherein the lower transistor is an N-type metal oxide semiconductor field effect transistor (NMOSFET), and the upper transistor is a P-type metal oxide semiconductor field effect transistor (PMOSFET).

17. A method of forming an integrated circuit device, the method comprising: forming a cell on a substrate, the cell comprising a plurality of transistors, the plurality of transistors comprising a lower transistor and an upper transistor on the substrate, the lower transistor comprising a lower channel region and the upper transistor comprising an upper channel region, the cell comprising a cell boundary extending in a first horizontal direction; forming a cell boundary metal pattern in a first metal layer over the substrate, the cell boundary metal pattern extending in the first horizontal direction and overlapping the cell boundary in a vertical direction, and the cell boundary metal pattern interconnecting at least two transistors of the plurality of transistors, the cell boundary metal pattern being connected to at least one of the lower transistor and the upper transistor; as well as A power line is formed to extend longitudinally in the first horizontal direction, and the cell boundary metal pattern overlaps the power line and the cell boundary in the vertical direction. 18 . The method of claim 17 , wherein the cell boundary metal pattern is electrically connected to an upper source / drain region of the upper transistor.

19. The method of claim 17, wherein the cell boundary metal pattern is electrically connected to a lower source / drain region of the lower transistor.

20. The method of claim 17, wherein the power line is a first power line and the cell boundary is a first cell boundary of the cell, the method further comprising forming a second power line extending longitudinally in the first horizontal direction parallel to the first power line, the second power line overlapping a second cell boundary of the cell, the second cell boundary extending longitudinally in the first horizontal direction and spaced apart from the first cell boundary in a second horizontal direction intersecting the first horizontal direction.

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