Electrostatic discharge protection structure and forming method thereof
The static discharge protection structure addresses the inadequacy of existing structures by incorporating lightly doped regions to enhance doping concentration near the PN junction, effectively lowering breakdown voltage and improving current flow, thus enhancing protection against static discharge in semiconductor manufacturing.
Patent Information
- Application Number
- CN202311246193.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-25
- Publication Date
- 2025-03-28
AI Technical Summary
Current static discharge protection structures in semiconductor manufacturing are inadequate, particularly as CMOS circuit features shrink, leading to increased vulnerability of chips to static discharge damage.
A static discharge protection structure is developed, featuring lightly doped regions around source and drain areas that overlap with the gate, reducing the size of the lightly doped regions near the gate, thereby increasing the doping concentration near the PN junction, lowering the breakdown voltage, and facilitating easier activation of NPN junctions.
The structure effectively reduces the breakdown voltage and enhances the ease of activation of NPN junctions, improving the protection against static discharge by increasing the current flow into the substrate without altering the substrate resistance.
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Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an electrostatic discharge protection structure and a forming method thereof. Background Art
[0002] Electrostatic discharge (ESD) is one of the most common factors that can damage chips during chip manufacturing and use. As the feature size of CMOS circuits continues to shrink, the gate oxide thickness becomes thinner and the distance between transistors becomes closer, the requirements for ESD protection structures become higher and higher.
[0003] The existing electrostatic discharge protection structure needs to be further improved. Summary of the invention
[0004] The technical problem solved by the present invention is to provide an electrostatic discharge protection structure and a forming method thereof, so as to improve the performance of the formed electrostatic discharge protection structure.
[0005] To solve the above technical problems, the technical solution of the present invention provides an electrostatic discharge protection structure, comprising: a substrate, the substrate comprising a first active area, the first active area comprising a gate area; a gate located on the gate area; a source area located in the first active area on one side of the gate; a first lightly doped area located in the first active area, the first lightly doped area surrounds the side wall and the bottom of the source area, and the portion of the first lightly doped area overlapping with the gate has a first size in the channel length direction; a drain area located in the first active area on the other side of the gate; a second lightly doped area located in the first active area, the second lightly doped area surrounds the side wall and the bottom of the drain area, and the portion of the second lightly doped area overlapping with the gate has a second size in the channel length direction, and the second size is smaller than the first size.
[0006] Optionally, it also includes: a substrate lead-out region located in the substrate.
[0007] Optionally, it further includes: a first conductive layer, the first conductive layer is electrically connected to the substrate lead-out region, the gate and the source region; and a second conductive layer, the second conductive layer is electrically connected to the drain region.
[0008] Optionally, the gate region is a first gate region, the gate is a first gate, and the source region is a first source region; the first active region also includes a second gate region; the electrostatic discharge protection structure also includes: a second gate located on the second gate region, the drain region is located in the first active region between the first gate and the second gate, and the portion of the second lightly doped region overlapping the second gate has a third size in the channel length direction; a second source region located in the first active region on the side of the second gate away from the drain region; a third lightly doped region located in the first active region, the third lightly doped region surrounds the sidewalls and bottom of the second source region, and the portion of the third lightly doped region overlapping the second gate has a fourth size in the channel length direction, and the third size is smaller than the fourth size; the first conductive layer is also electrically connected to the second gate and the second source region.
[0009] Optionally, the substrate further includes a second active region, and an isolation structure located between the first active region and the second active region; the substrate lead-out region is located in the second active region; and the second active region surrounds the first active region.
[0010] Optionally, it includes: the first active region and the second active region have well regions; the source region, the drain region, the first lightly doped region and the second lightly doped region are all located in the well region of the first active region, and have a conductivity type different from that of the well region; the substrate lead-out region is located in the well region of the second active region, and has the same conductivity type as that of the well region; the substrate also has a deep well region, the deep well region is located under the well region, and has a conductivity type different from that of the well region.
[0011] Correspondingly, the technical solution of the present invention also provides a method for forming an electrostatic discharge protection structure, comprising: providing a substrate, the substrate comprising a first active area, the first active area comprising a gate area; forming an initial first lightly doped area and an initial second lightly doped area in the first active area on both sides of the gate area, respectively, the initial first lightly doped area also extends to part of the gate area, and the part in the gate area has a first size in the channel length direction, the initial second lightly doped area also extends to part of the gate area, and the part in the gate area has a second size in the channel length direction, and the second size is smaller than the first size; forming a gate on the gate area; forming a source area and a drain area in the first active area on both sides of the gate, respectively, the source area is located in the initial first lightly doped area, and the initial first lightly doped area surrounding the sidewalls and bottom of the source area is the first lightly doped area, and the drain area is located in the initial second lightly doped area, and the initial second lightly doped area surrounding the sidewalls and bottom of the drain area is the second lightly doped area.
[0012] Optionally, the method for forming the initial first lightly doped region and the initial second lightly doped region includes: forming a first mask layer on a portion of the surface of the substrate, the first mask layer exposing the surface of the first active region; using the first mask layer as a mask, injecting first doping ions into the substrate to form the initial first lightly doped region and the initial second lightly doped region.
[0013] Optionally, the method for forming the source region, the drain region, the first lightly doped region and the second lightly doped region includes: forming a second mask layer on a portion of the surface of the substrate, the second mask layer exposing the surface of the first active region; using the second mask layer and the gate as masks, injecting second doping ions into the substrate to form the source region and the drain region, respectively, and the initial first lightly doped region outside the source region is the first lightly doped region, and the initial second lightly doped region outside the drain region is the second lightly doped region.
[0014] Optionally, after forming the gate, the method further includes: forming a substrate lead-out region in the substrate.
[0015] Optionally, after forming the source region, the drain region and the substrate lead-out region, a first conductive layer and a second conductive layer are formed on the substrate, the first conductive layer being electrically connected to the substrate lead-out region, the gate and the source region, and the second conductive layer being electrically connected to the drain region.
[0016] Optionally, after forming the source region, the drain region and the substrate lead-out region, and before forming the first conductive layer and the second conductive layer, it further includes: forming a metal silicide layer on the surface of the source region, the drain region, the substrate lead-out region and the gate.
[0017] Optionally, the substrate further includes a second active region and an isolation structure located between the first active region and the second active region; and the substrate lead-out region is located in the second active region.
[0018] Optionally, the first active region and the second active region have well regions; the source region, the drain region, the first lightly doped region and the second lightly doped region are all located in the well region of the first active region and have a different conductivity type from that of the well region; the substrate lead-out region is located in the well region of the second active region and has the same conductivity type as that of the well region; the substrate also has a deep well region, which is located under the well region and has a different conductivity type from that of the well region; the second active region surrounds the first active region.
[0019] Optionally, the gate region is a first gate region, the gate is a first gate, the source region is a first source region, and the first active region also includes a second gate region; the method also includes: while forming the initial first lightly doped region and the initial second lightly doped region, forming an initial third lightly doped region in the first active region on a side of the second gate region away from the initial second lightly doped region, the portion of the initial third lightly doped region in the second gate region has a fourth size in the channel length direction, the portion of the initial second lightly doped region in the second gate region has a third size in the channel length direction, and the third size is smaller than the fourth size; while forming the first gate on the first gate region, forming the second gate on the second gate region; while forming the first source region and the drain region, forming the second source region in the first active region on a side of the second gate away from the drain region, so that the initial third lightly doped region surrounding the sidewall and bottom of the second source region is a third lightly doped region.
[0020] Optionally, after forming the first gate and the second gate, the method further includes: forming a substrate lead-out region in the substrate.
[0021] Optionally, the first conductive layer is also electrically connected to the second gate and the second source region.
[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0023] In the electrostatic discharge protection structure provided by the technical solution of the present invention, a first lightly doped region is located in the first active region, the first lightly doped region surrounds the side wall and the bottom of the source region, and the portion of the first lightly doped region overlapping the gate has a first size in the channel length direction, and a second lightly doped region is located in the first active region, the second lightly doped region surrounds the side wall and the bottom of the source region, and the portion of the second lightly doped region overlapping the gate has a second size in the channel length direction, the second size is smaller than the first size, so that the size of the second lightly doped region outside the drain region extending under the gate is reduced, which is equivalent to increasing the doping concentration on one side of the drain region near the PN junction interface between the drain region and the substrate. When a large current is instantly injected into the drain region, the position where the PN junction between the drain region and the substrate undergoes avalanche breakdown moves toward the side wall of the drain region under the gate, thereby reducing the breakdown voltage and increasing the current entering the substrate. When the substrate resistance remains unchanged, the parasitic NPN device of the structure is easier to turn on, thereby reducing the turn-on voltage (Vtrigger).
[0024] In the method for forming an electrostatic discharge protection structure provided by the technical solution of the present invention, the size of the second lightly doped region outside the drain region extending under the gate is reduced, which is equivalent to increasing the doping concentration on one side of the drain region near the PN junction interface between the drain region and the substrate. When a large current is instantly injected into the drain region, the position where the PN junction between the drain region and the substrate undergoes avalanche breakdown moves toward the side wall of the drain region under the gate, thereby reducing the breakdown voltage and increasing the current entering the substrate. When the substrate resistance remains unchanged, the parasitic NPN device of the structure is easier to turn on, thereby reducing the turn-on voltage (Vtrigger).
[0025] Furthermore, the initial first lightly doped region is used to form a first lightly doped region, and the initial second lightly doped region is used to form a second lightly doped region. The initial first lightly doped region and the initial second lightly doped region can be formed based on the same mask without adding a new mask, which is conducive to reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 It is a schematic diagram of the cross-sectional structure of an electrostatic discharge protection structure;
[0027] Figures 2 to 10 is a structural schematic diagram of each step in a method for forming an electrostatic discharge protection structure according to an embodiment of the present invention;
[0028] Figures 11 to 17 It is a structural schematic diagram of each step in a method for forming an electrostatic discharge protection structure according to another embodiment of the present invention. DETAILED DESCRIPTION
[0029] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.
[0030] As described in the background art, the performance of the existing electrostatic discharge protection structure needs to be improved. Now, an existing electrostatic discharge protection structure is described and analyzed.
[0031] Figure 1 It is a schematic diagram of the cross-sectional structure of an electrostatic discharge protection structure.
[0032] Please refer to Figure 1 The electrostatic discharge protection structure includes: a substrate 100; a gate 101 located on the substrate 100; a source region 102 and a drain region 103 located in the substrate 100 on both sides of the gate 101; a lightly doped region 104 located outside the source region 102 and the drain region 103 and surrounding the source region 102 and the drain region 103 respectively; a substrate lead-out region 105 in the substrate 100, and the gate 101, the source region 102 and the substrate lead-out region 105 are electrically connected to each other.
[0033] The above-mentioned electrostatic discharge protection structure is used in the protection circuit of medium voltage devices. For the electrostatic discharge protection structure, taking the NMOS device as an example, its gate 101 is in the closed state, and the PN junction between the source region 102 and the substrate 100 is originally short-circuited and 0-biased. When a large current Iesd is instantly injected into the drain region 103, the PN junction between the drain region 103 and the substrate 100 undergoes avalanche breakdown, and the substrate 100 instantly has a large current and forms a voltage difference with the resistance of the substrate 100, causing the PN junction between the substrate 100 and the source region 102 to be forward biased. The parasitic NPN of the NMOS device is turned on to form a low-resistance path, and the large current will be discharged, and will not flow to the gate 101 to cause gate oxide breakdown, thereby achieving the purpose of protecting the internal circuit.
[0034] However, the trigger voltage (Vtrigger) of the electrostatic discharge protection structure is relatively large, which makes it difficult for the NPN to be turned on and fails to protect the internal circuit in time.
[0035] In order to solve the above problems, the present invention provides an electrostatic discharge protection structure and a method for forming the same, in which the size of the second lightly doped region outside the drain region extending under the gate is reduced, which is equivalent to increasing the doping concentration on one side of the drain region near the PN junction interface between the drain region and the substrate. When a large current is instantly injected into the drain region, the position where the PN junction between the drain region and the substrate undergoes avalanche breakdown moves toward the side wall of the drain region under the gate, thereby reducing the breakdown voltage and increasing the current entering the substrate. When the substrate resistance remains unchanged, the parasitic NPN device of the structure is easier to turn on, thereby reducing the turn-on voltage (Vtrigger).
[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0037] Figures 2 to 10 It is a structural schematic diagram of each step in a method for forming an electrostatic discharge protection structure according to an embodiment of the present invention.
[0038] Please refer to Figure 2 and Figure 3 , Figure 2 This is a top view of the structure. Figure 3 for Figure 2 A cross-sectional structural diagram along the AA1 direction is shown in FIG. 1 , providing a substrate 200 , wherein the substrate 200 includes a first active region I, and the first active region I includes a gate region G.
[0039] In this embodiment, the substrate 200 further includes a second active region II and an isolation structure 201 located between the first active region I and the second active region II.
[0040] The first active region I and the second active region II have a well region 202. In this embodiment, the conductivity type of the well region 202 is P type. In another embodiment, the conductivity type of the well region is N type.
[0041] In this embodiment, the substrate 200 further has a deep well region 203, which is located below the well region 202 and has a different conductivity type from the well region 202. Specifically, the conductivity type of the deep well region 203 is N-type.
[0042] In this embodiment, the method for forming the well region 202 and the deep well region 203 includes: forming a second mask layer (not shown in the figure) on a portion of the surface of the substrate 200; using the second mask layer as a mask, injecting third doping ions into the substrate 200 to form an initial deep well region (not shown in the figure); after forming the initial deep well region, forming a third mask layer (not shown in the figure) on a portion of the surface of the substrate 200; using the third mask layer as a mask, injecting fourth doping ions into the substrate 200, the conductivity type of the fourth doping ions being different from the conductivity type of the third doping ions, forming the well region 202 in the initial deep well region, and forming the deep well region 203 with the initial deep well region under the well region 202.
[0043] Please refer to Figure 4 and Figure 5 , Figure 4 This is a top view of the structure. Figure 5 for Figure 4 In the schematic diagram of the cross-sectional structure along the AA1 direction, an initial first lightly doped region 204 and an initial second lightly doped region 205 are respectively formed in the first active region I on both sides of the gate region G, the initial first lightly doped region 204 also extends into part of the gate region G, and the part in the gate region G has a first size d1 in the channel length direction, the initial second lightly doped region 205 also extends into part of the gate region G, and the part in the gate region G has a second size d2 in the channel length direction, and the second size d2 is smaller than the first size d1.
[0044] The initial first lightly doped region 204 is used to form a first lightly doped region, and the initial second lightly doped region 205 is used to form a second lightly doped region. The initial first lightly doped region 204 and the initial second lightly doped region 205 can be formed based on the same mask without adding a new mask, which is conducive to reducing production costs.
[0045] It should be noted that there is a channel between the source region and the drain region below the gate, and the channel length direction refers to the arrangement direction of the source region and the drain region.
[0046] In this embodiment, the method for forming the initial first lightly doped region 204 and the initial second lightly doped region 205 includes: forming a first mask layer 206 on a portion of the surface of the substrate 200, the first mask layer 206 exposing the surface of the first active region I; using the first mask layer 206 as a mask, injecting first doping ions into the substrate 200 to form the initial first lightly doped region 204 and the initial second lightly doped region 205.
[0047] Please refer to Figure 6 and Figure 7 , Figure 6 This is a top view of the structure. Figure 7 for Figure 6 The cross-sectional structure schematic diagram along the AA1 direction in FIG. 1 shows a gate 207 formed on the gate region G. In FIG.
[0048] In this embodiment, before forming the gate 207, the first mask layer 206 (eg, Figure 5 shown).
[0049] The method for forming the gate 207 includes: forming a gate material layer (not shown in the figure) on the substrate 200; forming a fourth mask layer (not shown in the figure) on the gate material layer on the gate region G; using the fourth mask layer as a mask, etching the gate material layer until the surface of the substrate 200 is exposed; and removing the fourth mask layer.
[0050] Please refer to Figure 8 and Fig. 9 , Figure 8 This is a top view of the structure. Fig. 9 for Figure 8 In the schematic diagram of the cross-sectional structure along the AA1 direction, a source region 208 and a drain region 209 are respectively formed in the first active region I on both sides of the gate 207, the source region 208 is located in the initial first lightly doped region 204, and the initial first lightly doped region 204 surrounding the side wall and the bottom of the source region 208 is the first lightly doped region 210, and the drain region 209 is located in the initial second lightly doped region 205, and the initial second lightly doped region 205 surrounding the side wall and the bottom of the drain region 209 is the second lightly doped region 211.
[0051] Here, since the second size d2 is smaller than the first size d1, the size of the second lightly doped region 211 outside the drain region 209 extending under the gate 207 is reduced, which is equivalent to an increase in the doping concentration on one side of the drain region 209 near the PN junction interface between the drain region 209 and the substrate 200. When a large current is instantly injected into the drain region 209, the position where the PN junction between the drain region 209 and the substrate 200 undergoes avalanche breakdown moves toward the side wall of the drain region 209 under the gate 207, thereby reducing the breakdown voltage and increasing the current entering the substrate 200. When the substrate resistance remains unchanged, the parasitic NPN device of the structure is easier to turn on, thereby reducing the turn-on voltage (Vtrigger).
[0052] In this embodiment, the method for forming the source region 208, the drain region 209, the first lightly doped region 210 and the second lightly doped region 211 includes: forming a second mask layer (not shown in the figure) on a portion of the surface of the substrate 200, the second mask layer exposing the surface of the first active region I; using the second mask layer and the gate 207 as masks, injecting second doping ions into the substrate 200 to form the source region 208 and the drain region 209, respectively, and the initial first lightly doped region 204 outside the source region 208 is the first lightly doped region 210, and the initial second lightly doped region 205 outside the drain region 209 is the second lightly doped region 211.
[0053] Specifically, the source region 208 , the drain region 209 , the first lightly doped region 210 and the second lightly doped region 211 are all located in the well region 202 of the first active region I, and have a conductivity type different from that of the well region 202 .
[0054] In this embodiment, the electrostatic discharge protection structure is an NMOS device, and the conductivity types of the source region 208, the drain region 209, the first lightly doped region 210, and the second lightly doped region 211 are all N-type. In another embodiment, the electrostatic discharge protection structure is a PMOS device, and the conductivity types of the source region, the drain region, the first lightly doped region, and the second lightly doped region may be P-type.
[0055] In this embodiment, after the gate 207 is formed, a substrate lead-out region 212 is further formed in the substrate 200 .
[0056] Specifically, the substrate lead-out region 212 is located in the second active region II.
[0057] More specifically, the substrate lead-out region 212 is located in the well region 202 of the second active region II, and has the same conductivity type as the well region 202. In this embodiment, the conductivity type of the substrate lead-out region 212 is P type.
[0058] In this embodiment, the method for forming the substrate lead-out region 212 includes: forming a fifth mask layer (not shown in the figure) on a portion of the surface of the substrate 200, the fifth mask layer exposing the surface of the second active region II; using the fifth mask layer as a mask, injecting fifth doping ions into the substrate 200.
[0059] Please Fig. 9 Based on reference Fig.10 After forming the source region 208, the drain region 209 and the substrate lead-out region 212, a first conductive layer 213 and a second conductive layer 214 are formed on the substrate 200, the first conductive layer 213 is electrically connected to the substrate lead-out region 212, the gate 207 and the source region 208, and the second conductive layer 214 is electrically connected to the drain region 209.
[0060] After forming the source region 208, the drain region 209 and the substrate lead-out region 212, and before forming the first conductive layer 213 and the second conductive layer 214, a metal silicide layer 215 is further formed on the surface of the source region 208, part of the drain region 209, the substrate lead-out region 212 and the gate 208. The metal silicide layer 215 is used to reduce contact resistance.
[0061] Correspondingly, an embodiment of the present invention further provides an electrostatic discharge protection structure formed by the above method, please continue to refer to Fig.10 , comprising: a substrate 200, the substrate 200 comprising a first active region I, the first active region I comprising a gate region G; a gate 207 located on the gate region G; a source region 208 located in the first active region I on one side of the gate 207; a first lightly doped region 210 located in the first active region I, the first lightly doped region 210 surrounds the sidewall and bottom of the source region 208, and the portion of the first lightly doped region 210 overlapping with the gate 207 has a first size d1 in the channel length direction; a drain region 209 located in the first active region I on the other side of the gate 207; a second lightly doped region 211 located in the first active region I, the second lightly doped region 211 surrounds the sidewall and bottom of the drain region 209, and the portion of the second lightly doped region 211 overlapping with the gate 207 has a second size d2 in the channel length direction, and the second size d2 is smaller than the first size d1.
[0062] Here, since the second size d2 is smaller than the first size d1, the size of the second lightly doped region 211 outside the drain region 209 extending under the gate 207 is reduced, which is equivalent to an increase in the doping concentration on one side of the drain region 209 near the PN junction interface between the drain region 209 and the substrate 200. When a large current is instantly injected into the drain region 209, the position where the PN junction between the drain region 209 and the substrate 200 undergoes avalanche breakdown moves toward the side wall of the drain region 209 under the gate 207, thereby reducing the breakdown voltage and increasing the current entering the substrate 200. When the substrate resistance remains unchanged, the parasitic NPN device of the structure is easier to turn on, thereby reducing the turn-on voltage (Vtrigger).
[0063] In this embodiment, the electrostatic discharge protection structure further includes: a substrate lead-out region 212 located in the substrate 200 .
[0064] In this embodiment, the electrostatic discharge protection structure further includes: a first conductive layer 213 , which is electrically connected to the substrate lead-out region 212 , the gate 207 and the source region 208 ; and a second conductive layer 214 , which is electrically connected to the drain region 209 .
[0065] In this embodiment, the substrate 200 further includes a second active region II and an isolation structure 201 located between the first active region I and the second active region II.
[0066] In this embodiment, the substrate lead-out region 212 is located in the second active region II.
[0067] In this embodiment, the first active region I and the second active region II have a well region 202. Specifically, the substrate lead-out region 212 is located in the well region 202 of the second active region II and has the same conductivity type as the well region 202.
[0068] In this embodiment, the source region 208 , the drain region 209 , the first lightly doped region 210 and the second lightly doped region 211 are all located in the well region 202 of the first active region I, and have a conductivity type different from that of the well region 202 .
[0069] In this embodiment, the electrostatic discharge protection structure is an NMOS device, and the conductivity types of the source region 208, the drain region 209, the first lightly doped region 210, and the second lightly doped region 211 are all N-type. In another embodiment, the electrostatic discharge protection structure is a PMOS device, and the conductivity types of the source region, the drain region, the first lightly doped region, and the second lightly doped region may be P-type.
[0070] The substrate further has a deep well region 203, which is located below the well region 202 and has a different conductivity type from the well region 202. In this embodiment, the conductivity type of the deep well region 203 is N-type.
[0071] In this embodiment, the conductivity type of the substrate lead-out region 212 is P type.
[0072] Figures 11 to 17 It is a structural schematic diagram of each step in a method for forming an electrostatic discharge protection structure according to another embodiment of the present invention.
[0073] Please refer to Fig.11 and Fig.12 , Fig.11 This is a top view of the structure. Fig.12 for Fig.11 A cross-sectional structural diagram along the AA1 direction in FIG. 1 is provided, wherein a substrate 300 is provided, and the substrate 300 includes a first active region i, and the first active region i includes a first gate region g1.
[0074] In this embodiment, the first active region i further includes a second gate region g2.
[0075] In this embodiment, the substrate 300 further includes a second active region ii and an isolation structure 301 located between the first active region i and the second active region ii.
[0076] In this embodiment, the second active region ii surrounds the first active region i.
[0077] In this embodiment, a well region 302 is provided in the first active region i and the second active region ii.
[0078] In this embodiment, the substrate 300 further has a deep well region 303 . The deep well region 303 is located under the well region 302 and has a different conductivity type from that of the well region 302 .
[0079] In this embodiment, the deep well region 303 is of N type.
[0080] Please refer to Fig.13 and Fig.14 , Fig.13 This is a top view of the structure. Fig.14 for Fig.13In the schematic diagram of the cross-sectional structure along the AA1 direction, an initial first lightly doped region 304 and an initial second lightly doped region 305 are respectively formed in the first active region i on both sides of the first gate region g1, the initial first lightly doped region 304 also extends into a portion of the first gate region g1, and the portion in the first gate region g1 has a first size D1 in the channel length direction, the initial second lightly doped region 306 also extends into a portion of the first gate region g1, and the portion in the first gate region g1 has a second size D2 in the channel length direction, and the second size D2 is smaller than the first size D1.
[0081] In this embodiment, while forming the initial first lightly doped region 304 and the initial second lightly doped region 305, an initial third lightly doped region 306 is formed in the first active region i on the side of the second gate region g2 away from the initial second lightly doped region 305, and the portion of the initial third lightly doped region 306 in the second gate region g2 has a fourth size D4 in the channel length direction, and the portion of the initial second lightly doped region 305 in the second gate region g2 has a third size D3 in the channel length direction, and the third size D3 is smaller than the fourth size D4.
[0082] Please refer to Fig.15 and Fig.16 , Fig.15 This is a top view of the structure. Fig.16 for Fig.15 The schematic cross-sectional structure diagram along the AA1 direction in the first gate region g1 (such as Fig.14 A first gate 307 is formed on the surface; a first source region 308 and a drain region 309 are formed in the first active region i on both sides of the first gate 307, and the first source region 308 is located in the initial first lightly doped region 304 (as shown); Fig.14 ), the initial first lightly doped region 304 surrounding the sidewall and bottom of the first source region 308 is the first lightly doped region 310, and the drain region 309 is located in the initial second lightly doped region 305 (as shown in Fig.14 As shown in FIG. 1 , the initial second lightly doped region 305 surrounding the sidewall and bottom of the drain region 309 is the second lightly doped region 311.
[0083] In this embodiment, while the first gate 307 is formed on the first gate region g1, the second gate region g2 (such as Fig.14308 and the drain region 309 are formed; while the first source region 308 and the drain region 309 are formed, a second source region 313 is formed in the first active region i on the side of the second gate 312 away from the drain region 309 to surround the initial third lightly doped region 306 (as shown) on the sidewall and bottom of the second source region 313. Fig.14 ) is the third lightly doped region 314.
[0084] Here, since the second size D2 is smaller than the first size D1, the size of the second lightly doped region 311 outside the drain region 309 extending into the first gate 307 is reduced, which is equivalent to increasing the doping concentration on one side of the drain region 309 near the PN junction interface between the drain region 309 and the substrate 300. When a large current is instantly injected into the drain region 309, the position where the PN junction between the drain region 309 and the substrate 300 undergoes avalanche breakdown moves toward the side wall of the drain region 309 under the first gate 307, thereby reducing the breakdown voltage and increasing the current entering the substrate 300. Under the condition that the substrate resistance remains unchanged, The parasitic NPN device of the structure is made easier to turn on, thereby reducing the turn-on voltage (Vtrigger); for the same reason, since the third dimension D3 is smaller than the fourth dimension D4, when a large current is instantly injected into the drain region 309, the position where the PN junction between the drain region 309 and the substrate 300 undergoes avalanche breakdown moves toward the side wall of the drain region 309 under the second gate 312, thereby reducing the breakdown voltage and increasing the current entering the substrate 300. Under the condition that the substrate resistance remains unchanged, the parasitic NPN device of the structure is made easier to turn on, thereby reducing the turn-on voltage (Vtrigger).
[0085] In this embodiment, after the first gate 307 is formed, a substrate lead-out region 315 is further formed in the substrate 300 .
[0086] In this embodiment, the substrate lead-out region 315 is located in the well region 302 of the second active region ii, and has the same conductivity type as that of the well region 302 .
[0087] In this embodiment, the electrostatic discharge protection structure is an NMOS device, and the conductivity types of the first source region 308, the drain region 309, the second source region 313, the first lightly doped region 310, the second lightly doped region 311 and the third lightly doped region 314 are all N-type. The conductivity type of the well region 302 is P-type, and the conductivity type of the substrate lead-out region 315 is P-type.
[0088] Please Fig.16 Based on reference Fig.17After forming the first source region 308, the drain region 309 and the substrate lead-out region 315, a first conductive layer 316 and a second conductive layer 317 are formed on the substrate 300, the first conductive layer 316 is electrically connected to the substrate lead-out region 315, the first gate 307 and the first source region 308, and the second conductive layer 317 is electrically connected to the drain region 309.
[0089] In this embodiment, the first conductive layer 316 is also electrically connected to the second gate 312 and the second source region 313 .
[0090] Correspondingly, another embodiment of the present invention further provides an electrostatic discharge protection structure formed by the above method, please continue to refer to Fig.17 , comprising: a substrate 300, the substrate 300 comprising a first active region i, the first active region i comprising a first gate region g1; a first gate 307 located on the first gate region g1; a first source region 308 located in the first active region i on one side of the first gate 307; a first lightly doped region 310 located in the first active region i, the first lightly doped region 310 surrounding the sidewall and bottom of the first source region 308, and the portion of the first lightly doped region 310 overlapping with the first gate 307 having a first size D1 in the channel length direction (such as Fig.14 ); a drain region 309 located in the first active region i on the other side of the first gate 307; a second lightly doped region 311 located in the first active region i, the second lightly doped region 311 surrounds the sidewall and bottom of the drain region 309, and the portion of the second lightly doped region 311 overlapping with the first gate 307 has a second size D2 in the channel length direction (as shown); Fig.14 As shown), the second dimension D2 is smaller than the first dimension D1.
[0091] In this embodiment, the first active region i further includes a second gate region g2.
[0092] In this embodiment, the electrostatic discharge protection structure further includes: a second gate 312 located on the second gate region g2, the drain region 309 is located in the first active region i between the first gate 307 and the second gate 312, and the portion where the second lightly doped region 311 overlaps with the second gate 312 has a third size D3 (such as Fig.14a second source region 313 located in the first active region i on the side of the second gate 312 away from the drain region 309; a third lightly doped region 314 located in the first active region i, the third lightly doped region 314 surrounding the sidewall and bottom of the second source region 313, and the portion of the third lightly doped region 314 overlapping with the second gate 312 having a fourth size D4 in the channel length direction (as shown); Fig.14 As shown), the third dimension D3 is smaller than the fourth dimension D4.
[0093] Here, since the second dimension D2 is smaller than the first dimension D1, the dimension of the second lightly doped region 311 outside the drain region 309 extending into the first gate 307 is reduced, which is equivalent to increasing the doping concentration on one side of the drain region 309 near the PN junction interface between the drain region 309 and the substrate 300. When a large current is instantly injected into the drain region 309, the position where the PN junction between the drain region 309 and the substrate 300 undergoes avalanche breakdown moves toward the side wall of the drain region 309 under the first gate 307, thereby reducing the breakdown voltage and increasing the current entering the substrate 300. When the substrate resistance remains unchanged, The parasitic NPN device of this structure is easier to turn on, thereby reducing the turn-on voltage (Vtrigger); for the same reason, since the third dimension D3 is smaller than the fourth dimension D4, when a large current is instantly injected into the drain region 309, the position where the PN junction between the drain region 309 and the substrate 300 undergoes avalanche breakdown moves toward the side wall of the drain region 309 under the second gate 312, thereby reducing the breakdown voltage and increasing the current entering the substrate 300. When the substrate resistance remains unchanged, the other parasitic NPN device of this structure is easier to turn on, thereby reducing the turn-on voltage (Vtrigger).
[0094] In this embodiment, the electrostatic discharge protection structure further includes: a substrate lead-out region 315 located in the substrate 300 .
[0095] In this embodiment, the electrostatic discharge protection structure further includes: a first conductive layer 316 , which is electrically connected to the substrate lead-out region 315 , the first gate 307 and the first source region 308 ; and a second conductive layer 317 , which is electrically connected to the drain region 309 .
[0096] In this embodiment, the first conductive layer 316 is also electrically connected to the second gate 312 and the second source region 313 .
[0097] In this embodiment, the substrate 300 further includes a second active region ii and an isolation structure 301 located between the first active region i and the second active region ii. Specifically, the substrate lead-out region 315 is located in the second active region ii.
[0098] In this embodiment, the second active region ii surrounds the first active region i.
[0099] In this embodiment, the first active region i and the second active region ii have a well region 302. Specifically, the substrate lead-out region 315 is located in the well region 302 of the second active region ii, and has the same conductivity type as the well region 302.
[0100] Specifically, the first source region 308, the drain region 309, the first lightly doped region 310, and the second lightly doped region 311 are all located in the well region 302 of the first active region i, and have a different conductivity type from the well region 302. In this embodiment, the electrostatic discharge protection structure is an NMOS device, and the conductivity types of the first source region 308, the drain region 309, the second source region 313, the first lightly doped region 310, the second lightly doped region 311, and the third lightly doped region 313 are all N-type. In another embodiment, the electrostatic discharge protection structure is a PMOS device, and the conductivity types of the first source region, the drain region, the second source region, the first lightly doped region, the second lightly doped region, and the third lightly doped region may be P-type.
[0101] In this embodiment, the substrate further has a deep well region 303, which is located below the well region 302 and has a different conductivity type from the well region 302. In this embodiment, the conductivity type of the deep well region 303 is N-type.
[0102] In this embodiment, the conductivity type of the substrate lead-out region 315 is P type.
[0103] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. An electrostatic discharge protection structure, characterized in that: include: a substrate, the substrate comprising a first active region, the first active region comprising a gate region; a gate located on the gate region; a source region located in the first active region on one side of the gate; a first lightly doped region located in the first active region, the first lightly doped region surrounding the sidewall and the bottom of the source region, and a portion of the first lightly doped region overlapping the gate having a first size in a channel length direction; a drain region located in the first active region on the other side of the gate; A second lightly doped region is located in the first active region, the second lightly doped region surrounds the sidewall and bottom of the drain region, and a portion of the second lightly doped region overlapping the gate has a second size in the channel length direction, and the second size is smaller than the first size.
2. The electrostatic discharge protection structure according to claim 1, characterized in that: Also includes: A substrate lead-out region is located in the substrate.
3. The electrostatic discharge protection structure according to claim 2, characterized in that: Also includes: a first conductive layer, the first conductive layer being electrically connected to the substrate lead-out region, the gate and the source region; A second conductive layer is electrically connected to the drain region.
4. The electrostatic discharge protection structure according to claim 3, characterized in that: The gate region is a first gate region, the gate is a first gate, and the source region is a first source region; the first active region also includes a second gate region; the electrostatic discharge protection structure also includes: a second gate located on the second gate region, the drain region is located in the first active region between the first gate and the second gate, and the portion of the second lightly doped region overlapping with the second gate has a third size in the channel length direction; a second source region located in the first active region on the side of the second gate away from the drain region; a third lightly doped region located in the first active region, the third lightly doped region surrounds the sidewalls and bottom of the second source region, and the portion of the third lightly doped region overlapping with the second gate has a fourth size in the channel length direction, and the third size is smaller than the fourth size; the first conductive layer is also electrically connected to the second gate and the second source region.
5. The electrostatic discharge protection structure according to claim 2, characterized in that: The substrate further includes a second active region and an isolation structure located between the first active region and the second active region; the substrate lead-out region is located in the second active region; and the second active region surrounds the first active region.
6. The electrostatic discharge protection structure according to claim 5, characterized in that: include: The first active region and the second active region have well regions; the source region, the drain region, the first lightly doped region and the second lightly doped region are all located in the well region of the first active region and have a conductivity type different from that of the well region; the substrate lead-out region is located in the well region of the second active region and has the same conductivity type as that of the well region; the substrate also has a deep well region, which is located under the well region and has a conductivity type different from that of the well region.
7. A method for forming an electrostatic discharge protection structure, characterized in that: include: Providing a substrate, the substrate comprising a first active region, the first active region comprising a gate region; forming an initial first lightly doped region and an initial second lightly doped region in the first active region on both sides of the gate region, respectively, wherein the initial first lightly doped region also extends to a portion of the gate region, and the portion in the gate region has a first size in the channel length direction, and the initial second lightly doped region also extends to a portion of the gate region, and the portion in the gate region has a second size in the channel length direction, and the second size is smaller than the first size; forming a gate on the gate region; A source region and a drain region are respectively formed in the first active region on both sides of the gate, the source region is located in the initial first lightly doped region, and the initial first lightly doped region surrounding the side wall and bottom of the source region is the first lightly doped region, and the drain region is located in the initial second lightly doped region, and the initial second lightly doped region surrounding the side wall and bottom of the drain region is the second lightly doped region.
8. The method for forming an electrostatic discharge protection structure according to claim 7, wherein: The method for forming the initial first lightly doped region and the initial second lightly doped region includes: forming a first mask layer on a portion of the surface of the substrate, the first mask layer exposing the surface of the first active region; using the first mask layer as a mask, injecting first doping ions into the substrate to form the initial first lightly doped region and the initial second lightly doped region.
9. The method for forming an electrostatic discharge protection structure according to claim 8, wherein: The method for forming the source region, the drain region, the first lightly doped region and the second lightly doped region includes: forming a second mask layer on a portion of the surface of the substrate, the second mask layer exposing the surface of the first active region; using the second mask layer and the gate as masks, injecting second doping ions into the substrate to form the source region and the drain region respectively, and the initial first lightly doped region outside the source region is the first lightly doped region, and the initial second lightly doped region outside the drain region is the second lightly doped region.
10. The method for forming an electrostatic discharge protection structure according to claim 7, wherein: After forming the gate, the method further includes: forming a substrate lead-out region in the substrate.
11. The method for forming an electrostatic discharge protection structure according to claim 10, wherein: After forming the source region, the drain region and the substrate lead-out region, a first conductive layer and a second conductive layer are formed on the substrate, the first conductive layer is electrically connected to the substrate lead-out region, the gate and the source region, and the second conductive layer is electrically connected to the drain region.
12. The method for forming an electrostatic discharge protection structure according to claim 11, wherein: After forming the source region, the drain region and the substrate lead-out region, and before forming the first conductive layer and the second conductive layer, the method further includes: forming a metal silicide layer on the surface of the source region, the drain region, the substrate lead-out region and the gate.
13. The method for forming an electrostatic discharge protection structure according to claim 10, wherein: The substrate further includes a second active region and an isolation structure located between the first active region and the second active region; the substrate lead-out region is located in the second active region.
14. The method for forming an electrostatic discharge protection structure according to claim 13, wherein: The first active region and the second active region have well regions; the source region, the drain region, the first lightly doped region and the second lightly doped region are all located in the well region of the first active region and have a conductivity type different from that of the well region; the substrate lead-out region is located in the well region of the second active region and has the same conductivity type as that of the well region; the substrate also has a deep well region, which is located under the well region and has a conductivity type different from that of the well region; the second active region surrounds the first active region.
15. The method for forming an electrostatic discharge protection structure according to claim 11, wherein: The gate region is a first gate region, the gate is a first gate, the source region is a first source region, and the first active region also includes a second gate region; the method also includes: while forming the initial first lightly doped region and the initial second lightly doped region, forming an initial third lightly doped region in the first active region on a side of the second gate region away from the initial second lightly doped region, the portion of the initial third lightly doped region in the second gate region has a fourth size in the channel length direction, the portion of the initial second lightly doped region in the second gate region has a third size in the channel length direction, and the third size is smaller than the fourth size; while forming the first gate on the first gate region, forming the second gate on the second gate region; while forming the first source region and the drain region, forming the second source region in the first active region on a side of the second gate away from the drain region, so that the initial third lightly doped region surrounding the sidewall and bottom of the second source region is the third lightly doped region.
16. The method for forming an electrostatic discharge protection structure according to claim 15, wherein: After forming the first gate and the second gate, the method further includes: forming a substrate lead-out region in the substrate.
17. The method for forming an electrostatic discharge protection structure according to claim 16, wherein: The first conductive layer is also electrically connected to the second gate and the second source region.