Electrostatic discharge (ESD) protection circuit and method of operation thereof

Abstract

The application provides an electrostatic discharge (ESD) protection circuit, comprising a first diode, a second diode and a first electrostatic discharge module, wherein the anode of the first diode is coupled to an input-output port, and the cathode of the first diode is coupled to a voltage source pin; the cathode of the second diode is coupled to the input-output port and the anode of the first diode, and the anode of the second diode is connected to the first electrostatic discharge module; the first end of the first electrostatic discharge module is connected to the anode of the second diode, and the second end of the first electrostatic discharge module is coupled to a ground pin. The circuit can realize positive and negative voltage input and output of the input-output port, meet the electrostatic discharge protection requirement, and prevent latch-up.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit, in particular to an electrostatic discharge (ESD) circuit and a working method thereof. BACKGROUND

[0002] The latest trend of miniaturized integrated circuits (IC) has resulted in smaller devices consuming less power but providing higher speed than before. Miniaturization processes have also increased the sensitivity of devices to electrostatic discharge (ESD) events due to various factors, such as thinner dielectric layer thickness and associated reduced dielectric breakdown voltage. ESD is one of the causes of electronic circuit damage and is one of the considerations in advanced semiconductor technologies.

[0003] In the traditional ESD scheme, the input-output (IO) pin is composed of an N-type MOS tube and a P-type MOS tube, so that the IO has a parasitic diode to ground, the anode of the parasitic diode is connected to ground, and the cathode is connected to the IO. Because there is a parasitic diode between the input-output (IO) port and ground, when the IO port outputs a negative voltage, the parasitic diode will be turned on, and the input / output voltage of the IO will be stuck, and even the risk of double locking of the chip may be triggered.

[0004] In the traditional scheme, when the voltage of the IO port is lower than -0.6V, the parasitic diode is turned on, and the larger the voltage difference, the larger the leakage current, and in extreme conditions, the latch-up effect may be triggered, and even the chip may be burned. Therefore, the traditional IO cannot support negative voltage applications below -0.6V.

[0005] In order to meet the electrostatic discharge protection requirements of the positive and negative voltage IO, a new electrostatic discharge protection circuit needs to be designed. SUMMARY

[0006] Based on the above status, the main purpose of the present application is to provide an electrostatic discharge protection circuit and a working method thereof, which meets the input-output electrostatic discharge protection requirements of positive and negative voltage and can prevent latch-up.

[0007] To achieve the above purpose, the present application provides an electrostatic discharge protection circuit, comprising: a first diode, a second diode, wherein, further comprising a first electrostatic discharge module, wherein,

[0008] An anode of the first diode is coupled to an input-output port, and a cathode thereof is coupled to a voltage source pin; a cathode of the second diode is coupled to the input-output port and the anode of the first diode, and an anode thereof is connected to the first electrostatic discharge module; a first end of the first electrostatic discharge module is connected to the anode of the second diode, and a second end thereof is coupled to a ground pin; when a working voltage of the input-output port is a negative voltage and an absolute value of the working voltage is less than or equal to V1+VD, the first electrostatic discharge module and the second diode are cut off; when the input-output port receives a negative ESD voltage and an absolute value of the negative ESD voltage is greater than V1+VD, a negative charge of the negative ESD voltage is discharged to the ground pin through the second diode and the first electrostatic discharge module; wherein VD is an absolute value of a critical voltage drop of the second diode in conduction, and V1 is an absolute value of a critical voltage drop of the first electrostatic discharge module in conduction.

[0009] Preferably, the circuit further comprises a second electrostatic discharge module, one end of which is coupled to the voltage source pin, and the other end thereof is coupled to the ground pin.

[0010] Preferably, the first electrostatic discharge module comprises a P-type MOS tube.

[0011] Preferably, a drain of the P-type MOS tube is connected to the anode of the second diode, a source of the P-type MOS tube is connected to the ground pin, and a gate of the P-type MOS tube is connected to the ground pin through a resistor R0.

[0012] Preferably, the gate of the P-type MOS tube is connected to the anode of the second diode through a capacitor C0.

[0013] Preferably, the first electrostatic discharge module comprises an N-type MOS tube.

[0014] Preferably, a source of the N-type MOS tube is connected to the anode of the second diode, a drain of the N-type MOS tube is connected to the ground pin, and a gate of the N-type MOS tube is connected to the anode of the second diode through a resistor R0.

[0015] Preferably, the gate of the N-type MOS tube is connected to the ground pin through a capacitor C0.

[0016] Preferably, the second electrostatic discharge module is a power clamp circuit.

[0017] The application further provides a layout of an electrostatic discharge protection circuit, comprising: the first diode, the second diode, the first electrostatic discharge module, a p+ isolation ring, an N-type well and a deep N-type well as claimed in claim 1, wherein the N-type well encloses the first diode, the deep N-type well encloses the second diode and the first electrostatic discharge module, and the p+ isolation ring surrounds the N-type well and the deep N-type well.

[0018] Preferably, the cathodes of the first diode and the second diode surround the anodes, and the N-type well encloses the cathodes of the first diode.

[0019] Preferably, when the first electrostatic discharge module comprises a MOS tube, the drain of the MOS tube is located between two silicide blocking layers, the two silicide blocking layers are outside the gates, the two gates are outside the source, and the substrate of the MOS tube surrounds the source, the gates, the drain and the silicide blocking layers.

[0020] The application further provides a working method of the electrostatic discharge protection circuit, wherein the voltage source pin is connected to a positive power supply VCC, the first electrostatic discharge module is selected so that the value of V1+VD is equal to VCC, and the working method comprises:

[0021] When the voltage of the input / output port is 0V to VCC, the first diode, the second diode and the first electrostatic discharge module are all cut off;

[0022] When the voltage of the input / output port is 0V to -VCC, the first diode is cut off, the second diode and the first electrostatic discharge module are also all cut off, so that the input / output port can normally work in the range of -VCC to VCC.

[0023] Preferably, the working method further comprises:

[0024] When the input / output port receives a positive ESD voltage, the first diode is turned on, and the positive charge of the positive ESD voltage flows into the voltage source pin through the first diode, wherein the positive ESD voltage is higher than the voltage VCC of the voltage source pin.

[0025] Preferably, the working method further comprises:

[0026] When the input / output port receives a negative ESD voltage, the second diode and the first electrostatic discharge module are turned on, and the negative charge of the negative ESD voltage is discharged to the ground pin through the second diode and the first electrostatic discharge module, wherein the absolute value of the negative ESD voltage is greater than V1+VD.

[0027] The application further provides a chip comprising the electrostatic discharge protection circuit.

[0028] The application further provides an LED lamp comprising the chip.

[0029] The electrostatic discharge (ESD) protection circuit provided by the application can connect a voltage source pin, a first diode, a second diode, a first electrostatic discharge module and a ground pin in sequence, and the input and output port is located between the first diode and the second diode. There is no parasitic diode between the input and output port and the ground, the working voltage of the input and output port is negative voltage, and the value is less than or equal to V1+VD. The input and output port can normally output negative voltage. Compared with the prior art in which the input and output port is only grounded through the second diode, the input and output port of the application can normally output a larger range of negative voltage and support more negative voltage application scenarios. In the range of negative voltage, there is no risk of triggering latch-up or burning the chip due to large current injection into the substrate.

[0030] When the first electrostatic discharge module is selected such that the value of V1+VD is equal to VCC, the first diode and the second diode are both cut off, and the first electrostatic discharge module is also cut off when the input and output port works in the voltage range of -VCC to VCC (outputs or inputs the voltage in the range). Therefore, the input and output port can normally work in the voltage range of -VCC to VCC without the risk of triggering latch-up or burning the chip due to large current injection into the substrate, and the ESD current can be discharged in time when the input and output port receives an ESD voltage exceeding the voltage range of -VCC to VCC.

[0031] The working method of the electrostatic discharge (ESD) protection circuit of the application can flexibly realize electrostatic discharge in different electrostatic environments. BRIEF DESCRIPTION OF DRAWINGS

[0032] The preferred embodiments of the electrostatic discharge (ESD) protection circuit and its working method will be described below with reference to the accompanying drawings. In the drawings:

[0033] Figure 1 The figure is a schematic diagram of the electrostatic discharge (ESD) protection circuit according to the preferred embodiment of the application.

[0034] Figure 2 The figure is another schematic diagram of the electrostatic discharge (ESD) protection circuit according to the preferred embodiment of the application.

[0035] Figure 3 The figure is a schematic diagram of the first electrostatic discharge module in Figure 1 and Figure 2 The figure is a schematic diagram of the first electrostatic discharge module in

[0036] Figure 3-1Gate-to-Drain PMOS (GdPMOS) transistor;

[0037] Figure 3-2 Gate Couple PMOS (GCPMOS) transistor;

[0038] Figure 3-3 Grounded-gate NMOS (GGNMOS) transistor;

[0039] Figure 3-4 Gate Couple NMOS (GCNMOS) transistor.

[0040] Figure 4 is Figure 2 a schematic diagram of a second electrostatic discharge module in

[0041] Figure 5 is Figure 1 a specific implementation layout of

[0042] Figure 6 a working method of an electrostatic discharge (ESD) protection circuit.

[0043] Figure 7 another working method of an electrostatic discharge (ESD) protection circuit. DETAILED DESCRIPTION

[0044] The present application is described in the following based on examples, but the present application is not limited to these examples only. In the following detailed description of the present application, some specific details are described in detail in order to avoid obscuring the essence of the present application, and well-known methods, processes, procedures, elements are not described in detail.

[0045] In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0046] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to".

[0047] In the description of the present application, it should be understood that the terms "first", "second", etc. are only for the purpose of description and should not be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise stated, the meaning of "multiple" is two or more.

[0048] Please refer to Figure 1 ,Figure 1 Fig. 1 shows a schematic diagram of an electrostatic discharge (ESD) protection circuit according to an embodiment of the present application, which is included in a chip, which can be an LED chip, and one or more of the LED chips can form an LED lamp.

[0049] In the embodiment, the electrostatic discharge (ESD) protection circuit includes a first diode 110, a second diode 130, and a first electrostatic discharge module 140, wherein an anode of the first diode 110 is coupled to an input-output port 120, and a cathode thereof is coupled to a voltage source pin; a cathode of the second diode 130 is coupled to the input-output port 120 and an anode of the first diode 110, and an anode thereof is connected to the first electrostatic discharge module 140; a first end of the first electrostatic discharge module 140 is connected to an anode of the second diode 130, and a second end thereof is coupled to a ground pin.

[0050] In the embodiment, when a working voltage (e.g., output or output) of the input-output port 120 is a negative voltage, and an absolute value of the working voltage is less than or equal to V1+VD, the first electrostatic discharge module 140 and the second diode 130 are turned off, when the input-output port 120 receives a negative ESD voltage, and an absolute value of the negative ESD voltage is greater than V1+VD, a negative charge of the negative ESD voltage is discharged to the ground pin through the second diode 130 and the first electrostatic discharge module 140.

[0051] In the embodiment, VD is an absolute value of a critical voltage drop at which the second diode 130 is turned on, and V1 is an absolute value of a critical voltage drop at which the first electrostatic discharge module 140 is turned on.

[0052] The electrostatic discharge protection circuit in the embodiment sequentially connects the voltage source pin, the first diode, the second diode, the first electrostatic discharge module, and the ground pin in series, and the input-output port is located between the first diode and the second diode, and there is no parasitic diode between the input-output port and the ground. When the working voltage of the input-output port is a negative voltage and the value is less than or equal to V1+VD, the input-output port can normally output the negative voltage. Compared with the prior art in which the input-output port is only grounded through the second diode, the input-output port according to the present application can normally output a larger range of negative voltages, and can support more negative voltage application scenarios.

[0053] In the embodiment, the absolute value V1 of the voltage threshold at which the first electrostatic discharge module 140 is turned on can be 5V-8V.

[0054] When the above chip is installed into a circuit and works normally: the voltage source pin is connected to a positive voltage source VCC, the ground pin is connected to ground, when the voltage of the input / output port 120 (output or input voltage) is 0V to VCC, the first diode 110 and the second diode 130 will not be turned on, so there will be no leakage to the voltage source pin and the ground pin; when the voltage of the input / output port 120 is 0V to -(V1+VD), the first diode 110 is cut off, the input / output port 120 will not leak to the voltage source pin, and the first ESD module 140 and the second diode 130 are also cut off, so the input / output port 120 will not leak to the ground pin, and will not trigger the latch effect or burn the chip.

[0055] In addition, due to the presence of the first ESD module 140, there is no direct parasitic diode between the second diode and the ground pin.

[0056] Therefore, when the above chip is installed into a circuit and works normally: the voltage source pin is connected to a positive voltage source VCC, the ground pin is connected to ground, when the voltage of the input / output port 120 (output or input voltage) is 0V to VCC, the first diode 110 and the second diode 130 will not be turned on, so there will be no leakage to the voltage source pin and the ground pin; when the voltage of the input / output port 120 is 0V to -(V1+VD), the first diode 110 is cut off, the input / output port 120 will not leak to the voltage source pin, and the first ESD module 140 and the second diode 130 are also cut off, so the input / output port 120 will not leak to the ground pin, and will not trigger the latch effect or burn the chip.

[0057] In the embodiment, VCC can be 1.8V, 5.5V or 5V.

[0058] In other embodiments of the application, VCC can also be 10V, 16V, 20V, 25V or 30V.

[0059] In the embodiment, the positive ESD voltage is generally a very high voltage, such as HBM 2KV.

[0060] It can be understood that no matter it is a positive ESD voltage or a negative ESD voltage, the absolute value of the voltage is much higher than the voltage of the voltage source pin.

[0061] Please refer to Figure 2 , Figure 2 Another schematic diagram of the ESD protection circuit of the preferred embodiment of the application.

[0062] In the embodiment, Figure 1 The ESD protection circuit 10 shares the voltage source pin and the ground pin with other common IO circuits (such as 20 shown in Figure 2 .

[0063] In the embodiment, in addition to including Figure 1The electrostatic discharge (ESD) protection circuit 10 in the present embodiment further comprises a second electrostatic discharge module 30, one end of which is coupled with the voltage source pin and the other end of which is coupled with the ground pin.

[0064] In the present embodiment, the electrostatic discharge (ESD) protection circuit comprises at least two normal IO circuits 20, which share the voltage of the voltage source pin and the voltage of the ground pin.

[0065] Please refer to Figure 3 , Figure 3 for Figure 1 and Figure 2 for a schematic diagram of the first electrostatic discharge module 140.

[0066] In the present embodiment, the first electrostatic discharge module comprises a P-type metal-oxide-semiconductor field-effect transistor (MOS) tube. For example, as a Gate-to-Drain PMOS (Gdpmos) tube in Figure 3-1 , or as a Gate Couple PMOS (Gcpmos) tube in Figure 3-2 .

[0067] Please refer to Figure 3-1 , the drain of the P-type MOS tube is connected with the anode of the second diode 130, the source of the P-type MOS tube is connected with the ground pin, and the gate of the P-type MOS tube is connected with the ground pin through a resistor R0.

[0068] Please refer to Figure 3-2 , further, the gate of the P-type MOS tube is connected with the anode of the second diode 130 through a capacitor C0. In the present embodiment, the P-type MOS tube introduces an RC trigger circuit, which can further reduce the trigger voltage of the P-type MOS tube and improve the opening uniformity.

[0069] In another embodiment of the present application, the first electrostatic discharge module comprises an N-type MOS tube.

[0070] For example, as a Grounded-gate NMOS (Ggnmos) tube in Figure 3-3 , or as a Gate Couple NMOS (Gcnmos) tube in Figure 3-4 .

[0071] Please refer to Figure 3-3The source of the N-type MOS is connected with the anode of the second diode 130, the drain of the N-type MOS is connected with the ground pin, and the gate of the N-type MOS is connected with the anode of the second diode 130 through the resistor R0.

[0072] Please refer to Figure 3-4 The gate of the N-type MOS is connected with the ground pin through the capacitor C0. In the embodiment, the N-type MOS further introduces the RC trigger circuit, which can further reduce the trigger voltage of the N-type MOS and improve the opening uniformity.

[0073] Please refer to Figure 4 , Figure 4 is Figure 2 a schematic diagram of the second static discharge module 30 in

[0074] The static discharge protection circuit 10 in the embodiment shares the voltage source pin and the ground pin with other common IO circuits 20, and through cooperation with the second static discharge module 30, a larger range of static discharge can be achieved, and latch-up can be prevented.

[0075] In the embodiment, the second static discharge module 30 is a power clamp circuit.

[0076] In the embodiment, when the input and output port 120 encounters a positive ESD voltage, the positive charge of the positive ESD voltage can be conducted to the shared voltage source pin through the first diode 110, and when the input and output ports IO2 to IOn encounter a positive ESD voltage, the positive charge of the positive ESD voltage can be conducted to the shared voltage source pin through the MPESD therein. At this time, due to the RC delay of R1 and C1 in the second static discharge module 30, the voltage vtg at the RC end is at a low level, and after passing through the inverter composed of the transistor MP0 (P-type MOS) and the transistor MN0 (N-type MOS), the output end vg voltage is pulled to a high level, thereby triggering the conduction of the transistor MN1 (N-type MOS) at the high potential of the vg end. Thus, the positive charge of the positive ESD voltage is discharged to the ground pin through MN1.

[0077] Therefore, the static discharge (ESD) protection circuit in the embodiment shares the voltage source pin and the ground pin with other circuits, and through cooperation with the second static discharge module, flexible static discharge can be achieved, and latch-up can be prevented.

[0078] Please refer to Figure 5 , Figure 5 is Figure 1 a specific implementation layout of

[0079] In the layout of the ESD protection circuit in the embodiment, it comprises: a first diode (region 100), a second diode (region 101), a first ESD module (region 102), a p+ isolation ring (region 103), an N well (region 104) and a deep N well (region 108), wherein the N well covers the first diode, the deep N well covers the second diode and the first ESD module, and the p+ isolation ring surrounds the N well and the deep N well.

[0080] In the embodiment, region 100 corresponds to the first diode 110 in Figure 1 In the embodiment, the first diode 110 is a p-type diode (p+ / NW).

[0081] In the embodiment, region 101 corresponds to the second diode 130. In the embodiment, the second diode is an n-type diode (n+ / PW).

[0082] In the embodiment, the cathode of the first diode and the second diode surrounds the anode, and the N well (region 104) covers the cathode (region 106) of the first diode.

[0083] In the embodiment, region 102 corresponds to the first ESD module 140. In the embodiment, the first ESD module 140 is implemented by NMOS, as shown in Fig. c or Fig. d in Figure 3

[0084] In the embodiment, both region 101 and region 102 are separated from the P substrate (PSUB) by a deep N well (DNW, region 108), and the potential of the deep N well is VCC or floating.

[0085] In the embodiment, region 103 is a p+ isolation ring surrounding region 100.

[0086] In the embodiment, region 100 where the first diode 110 is located comprises: region 104, region 105 and region 106, wherein region 104 is an N well (NW), region 105 is a p+ active area (i.e. the anode of the first diode 110), and region 106 is an n+ active area (i.e. the cathode of the first diode 110). Region 105 is located in the center, region 106 surrounds region 105, and region 104 covers region 106.

[0087] In the embodiment, region 107 is an n+ isolation ring, and region 108 is a deep N well (DNW), wherein region 107 surrounds region 108, and region 108 covers region 101 and region 102.

[0088] ​In the embodiment, the region 101 where the second diode 120 is located includes a region 109 and a region 110, wherein the region 109 is a p+ active region (i.e. the anode of the first diode 110), and the region 110 is an n+ active region (i.e. the cathode of the second diode 110), and the region 109 surrounds the region 110.

[0089] In the embodiment, the region 102 where the first static discharge module 140 is located includes a region 111, a region 112, a region 113, a region 114 and a region 115. The region 111 is a p+ substrate contact (i.e. the substrate end of the NMOS), the region 112 is an n+ active region (i.e. the source end of the NMOS), the region 114 is an n+ active region (i.e. the drain end of the NMOS), the region 113 is the gate end of the NMOS, and the region 115 is a silicide blocking layer. The region 114 is located in the middle of the region 102, and two regions 115 are respectively located outside the region 114, two regions 113 are respectively located outside the two regions 115, two regions 112 are respectively located outside the two regions 113, and the region 111 surrounds the regions 112, 113, 114 and 115.

[0090] From Figure 5 It can be seen that the static discharge protection circuit in the application is simple to implement.

[0091] In the application, a chip is also provided, which comprises the static discharge protection circuit 10.

[0092] In the application, an LED lamp is also provided, which comprises the chip.

[0093] Please refer to Figure 6 , Figure 6 The working method of the static discharge protection circuit is shown in the application, which is used in Figure 1 .

[0094] In the embodiment, the voltage source pin is connected to the positive power supply VCC, the first static discharge module is selected so that the value of V1+VD is equal to VCC, and the ground pin is connected to the ground.

[0095] The method comprises the following steps:

[0096] In step S300, when the voltage of the input and output port 120 is 0V to VCC, the first diode 110, the second diode 120 and the first static discharge module are all cut off.

[0097] When the input / output port 120 receives a positive ESD voltage, the first diode 110 is turned on, and the positive charge of the positive ESD voltage flows into the voltage source pin through the first diode 110, where the value of the positive ESD voltage is higher than the voltage VCC of the voltage source pin. In other embodiments of the present application, the positive charge of the positive ESD voltage flows into the ground pin through the first diode 110 and the second ESD module 30.

[0098] When the input / output port 120 receives a positive ESD voltage, the first diode 110 is turned on, and the positive charge of the positive ESD voltage flows into the voltage source pin through the first diode 110, where the value of the positive ESD voltage is higher than the voltage VCC of the voltage source pin. In other embodiments of the present application, the positive charge of the positive ESD voltage flows into the ground pin through the first diode 110 and the second ESD module 30.

[0099] When the input / output port 120 receives a positive ESD voltage, the first diode 110 is turned on, and the positive charge of the positive ESD voltage flows into the voltage source pin through the first diode 110, where the value of the positive ESD voltage is higher than the voltage VCC of the voltage source pin. In other embodiments of the present application, the positive charge of the positive ESD voltage flows into the ground pin through the first diode 110 and the second ESD module 30.

[0100] The ESD protection circuit provided by the present embodiment connects the voltage source pin, the first diode, the second diode, the first ESD module and the ground pin in sequence, and the input / output port is located between the first diode and the second diode. There is no parasitic diode between the input / output port and the ground. When the input / output port works at a voltage in the range of -VCC to VCC (input or output), the first diode and the second diode are both turned off, and the first ESD module is also turned off. Therefore, the input / output port can work normally in the voltage range of -VCC to VCC, and there is no risk of large current injection into the substrate triggering latch-up or burning. When the input / output port receives an ESD voltage exceeding the voltage range of -VCC to VCC, the ESD charge can be discharged in time.

[0101] Please refer to Figure 7 , Figure 7 Another working method of the ESD protection circuit is shown in the flowchart of FIG. 4.

[0102] In the present embodiment, when the chip containing the ESD protection circuit 10 is mounted to a circuit, the voltage source pin is grounded, and the ground pin is left floating during ESD testing.

[0103] The method comprises the following steps:

[0104] At step S400, when the input / output port 120 receives a positive ESD voltage, the first diode 110 is turned on, the second diode 130 and the first static discharge module 140 are cut off, and the positive charge of the positive ESD voltage flows into the voltage source pin through the first diode 120.

[0105] At step S402, when the input / output port 120 receives a negative ESD voltage, the second diode 130 and the first static discharge module 140 are turned on, the first diode 110 is cut off, and the negative charge of the negative ESD voltage is discharged to the voltage source pin through the second diode 130 and the second static discharge module 30, wherein the absolute value of the negative ESD voltage is greater than V1+VD.

[0106] Therefore, the working method of the electrostatic discharge (ESD) protection circuit in the present application can flexibly realize electrostatic discharge in different situations.

[0107] It should be noted that the step numbers (letters or numbers) are used in the present application to refer to certain specific method steps, which is only for the purpose of convenience and brevity, and is not intended to limit the order of the method steps by letters or numbers. Those skilled in the art can understand that the order of the related method steps should be determined by the technology itself, and should not be improperly limited by the step numbers. Those skilled in the art can determine various allowed and reasonable step orders according to the technology itself.

[0108] Those skilled in the art can understand that the above-mentioned preferred schemes can be freely combined and superimposed without conflict.

[0109] It should be understood that the above-mentioned embodiments are only exemplary and non-limiting, and those skilled in the art can make various obvious or equivalent modifications or replacements to the above-mentioned details without departing from the basic principles of the present application, which will be included in the scope of the claims of the present application.

Claims

1. An electrostatic discharge protection circuit, comprising: The first diode and the second diode are characterized in that further comprising a first electrostatic discharge module, wherein, an anode of the first diode is coupled to an input-output port, and a cathode of the first diode is coupled to a voltage source pin; a cathode of the second diode is coupled to the input-output port and an anode of the first diode, and an anode of the second diode is connected to the first electrostatic discharge module; a first end of the first electrostatic discharge module is connected to the anode of the second diode, and a second end of the first electrostatic discharge module is coupled to a ground pin; when a working voltage of the input-output port is a negative voltage, and an absolute value of the working voltage is less than or equal to V1+VD, the first electrostatic discharge module and the second diode are turned off, when the input-output port receives a negative ESD voltage, and an absolute value of the negative ESD voltage is greater than V1+VD, a negative charge of the negative ESD voltage is discharged to the ground pin through the second diode and the first electrostatic discharge module; wherein VD is an absolute value of a critical voltage drop of the second diode being turned on, and V1 is an absolute value of a critical voltage drop of the first electrostatic discharge module being turned on; the first electrostatic discharge module comprises a P-type MOS tube, a drain of the P-type MOS tube is connected to the anode of the second diode, a source of the P-type MOS tube is connected to the ground pin, and a gate of the P-type MOS tube is connected to the ground pin through a resistor R0; or the first electrostatic discharge module comprises an N-type MOS tube, a source of the N-type MOS tube is connected to the anode of the second diode, a drain of the N-type MOS tube is connected to the ground pin, and a gate of the N-type MOS tube is connected to the anode of the second diode through a resistor R0.

2. The electrostatic discharge protection circuit of claim 1, wherein, further comprising a second electrostatic discharge module, one end of the second electrostatic discharge module is coupled to the voltage source pin, and the other end of the second electrostatic discharge module is coupled to the ground pin.

3. The electrostatic discharge protection circuit of claim 1, wherein, when the first electrostatic discharge module comprises the P-type MOS tube, the gate of the P-type MOS tube is connected to the anode of the second diode through a capacitor C0.

4. The electrostatic discharge protection circuit of claim 1, wherein, when the first electrostatic discharge module comprises the N-type MOS tube, the gate of the N-type MOS tube is connected to the ground pin through a capacitor C0.

5. The electrostatic discharge protection circuit of claim 2, wherein, the second electrostatic discharge module is a power clamp circuit.

6. A layout including the electrostatic discharge protection circuit as claimed in claim 1, characterized in that, comprising: the first diode, the second diode, the first electrostatic discharge module, a p+ isolation ring, an N-type well, and a deep N-type well, wherein the N-type well encloses the first diode, the deep N-type well encloses the second diode and the first electrostatic discharge module, and the p+ isolation ring surrounds the N-type well and the deep N-type well.

7. The electrostatic discharge protection circuit layout of claim 6, wherein, cathodes of the first diode and the second diode surround anodes, and an N-type well encloses the cathodes of the first diode.

8. The electrostatic discharge protection circuit layout of claim 6, wherein, when the first electrostatic discharge module comprises a P-type or N-type MOS tube, a drain of the MOS tube is located between two silicification blocking layers, gates of the MOS tube are located outside the two silicification blocking layers, a source of the MOS tube is located outside the two gates, and a substrate of the MOS tube surrounds the source, the gates, the drain, and the silicification blocking layers.

9. A method of operating an electrostatic discharge protection circuit as claimed in any one of claims 1 to 5, characterized by, The voltage source pin is connected to a positive power supply VCC, and the first ESD module is selected so that the value of V1+VD is equal to VCC, and the working method comprises: When the voltage of the input / output port is 0V to VCC, the first diode, the second diode and the first ESD module are all cut off; When the voltage of the input / output port is 0V to -VCC, the first diode is cut off, and the second diode and the first ESD module are also all cut off, so that the input / output port can normally work in the range of -VCC to VCC.

10. The working method of claim 9, further comprising: When the input / output port receives a positive ESD voltage, the first diode is turned on, and the positive charge of the positive ESD voltage flows into the voltage source pin through the first diode, wherein the value of the positive ESD voltage is higher than the voltage VCC of the voltage source pin.

11. The working method of claim 10, further comprising: When the input / output port receives a negative ESD voltage, the second diode and the first ESD module are turned on, and the negative charge of the negative ESD voltage is discharged to the ground pin through the second diode and the first ESD module, wherein the absolute value of the negative ESD voltage is greater than V1+VD.

12. A chip, characterized by An ESD protection circuit comprising any one of claims 1-5.

13. An LED lamp, characterized by A chip comprising the ESD protection circuit of claim 12.

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