Display panel and method of manufacturing same

Abstract

The invention relates to a display panel and a method of manufacturing the same. The display panel includes: a base layer; a transistor disposed on the base layer; a common electrode disposed on the transistor; a conductive partition wall disposed on the common electrode and having a partition wall opening defined therein; a partition wall insulating layer disposed on the conductive partition wall; and a light emitting element disposed on the partition wall insulating layer and including a first electrode electrically connected to the transistor, an emission pattern disposed on the first electrode, and a second electrode disposed on the emission pattern and electrically connected to the conductive partition wall.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0129308, filed on September 26, 2023, and all rights arising therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a display panel and a display panel manufacturing method, and more particularly, to a display panel having improved display quality. Background Art

[0004] Display devices such as televisions, monitors, smartphones, tablet computers, etc. that provide images to users include display panels that display images. Various display panels such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, electrophoretic display panels, etc. are being developed.

[0005] The organic light emitting display panel may include an anode, a cathode, and an emission pattern. The emission patterns may be divided from each other for respective emission regions, and the cathode may provide a common voltage for respective emission regions. Summary of the invention

[0006] Embodiments of the present invention provide a display panel having improved display quality and a method for manufacturing the display panel, the display panel including a light emitting element formed without using a metal mask.

[0007] According to an embodiment, a display panel includes: a base layer; a transistor disposed on the base layer; a common electrode disposed on the transistor; a conductive partition wall disposed on the common electrode and having a partition wall opening defined therein; a partition wall insulating layer disposed on the conductive partition wall; and a light emitting element disposed on the partition wall insulating layer and including a first electrode electrically connected to the transistor, an emission pattern disposed on the first electrode, and a second electrode disposed on the emission pattern and electrically connected to the conductive partition wall.

[0008] In an embodiment, the conductive partition wall may include: a first partition wall layer disposed on the common electrode; and a second partition wall layer disposed on the first partition wall layer. The partition wall opening may include: a first region defined by the first partition wall layer; and a second region defined by the second partition wall layer and formed integrally with the first region, and the first region may have a greater length in the first direction than the second region.

[0009] In an implementation, the display panel may further include a pixel defining layer disposed on the partition wall insulating layer and having a light emitting opening exposing at least a portion of the first electrode.

[0010] In an embodiment, the light emitting opening may not overlap with the partition wall opening.

[0011] In an embodiment, the emission pattern may cover a side surface of the second partition wall layer, and the second electrode may cover an upper surface of the emission pattern and at least a portion of a side surface of the emission pattern.

[0012] In an implementation, the display panel may further include an auxiliary electrode covering the second electrode and a lower surface of the second partition wall layer and directly contacting a lower surface of the second partition wall layer.

[0013] In an implementation, the auxiliary electrode may be in contact with a side surface of the first partition wall layer.

[0014] In an implementation, the display panel may further include a dummy auxiliary electrode spaced apart from the auxiliary electrode and in contact with a side surface of the first partition wall layer.

[0015] In an implementation, the display panel may further include a lower inorganic encapsulation pattern covering an upper surface of the auxiliary electrode and spaced apart from the common electrode.

[0016] In an implementation, the display panel may further include a light emitting contact hole that passes through the conductive partition wall and the common electrode and overlaps the first electrode when viewed from above a plane.

[0017] In an implementation, the first electrode may include a circular portion and a protrusion portion extending from one side of the circular portion, and the light emitting contact hole may overlap the protrusion portion of the first electrode when viewed from above a plane.

[0018] In an implementation, the first electrode may include a circular portion, and the light emitting contact hole may overlap with a center of the circular portion when viewed from above a plane.

[0019] In an implementation, the first electrode may be disposed between the second electrode and the common electrode.

[0020] According to an embodiment, a display panel includes: a base layer; a conductive partition wall disposed on the base layer and having a partition wall opening defined therein; a partition wall insulating layer disposed on the conductive partition wall; and a light emitting element including a first electrode disposed on the partition wall insulating layer, an emission pattern covering the first electrode and the partition wall insulating layer, and a second electrode covering the emission pattern and electrically connected to the conductive partition wall. When viewed from above a plane, the partition wall opening and the first electrode are spaced apart from each other.

[0021] In an implementation, the first electrode may overlap a center of the conductive partition wall.

[0022] According to an embodiment, a method for manufacturing a display panel includes: forming a common electrode and a circuit element layer including a transistor on a base layer; forming a preliminary conductive partition wall on the common electrode; forming a preliminary partition wall insulating layer, a first electrode, and a preliminary pixel defining layer covering the first electrode on the preliminary conductive partition wall; forming a light emitting opening overlapping the first electrode by etching the preliminary pixel defining layer; forming a conductive partition wall, a partition wall insulating layer, and a pixel defining layer by etching the preliminary conductive partition wall, the preliminary partition wall insulating layer, and the preliminary pixel defining layer, wherein the conductive partition wall defines a partition wall opening; forming an emission pattern covering the first electrode on the conductive partition wall; and forming a second electrode electrically connected to the conductive partition wall on the emission pattern. When viewed from above a plane, the light emitting opening and the partition wall opening do not overlap each other.

[0023] In an embodiment, the preliminary conductive partition wall may include: a first preliminary partition wall layer disposed on the common electrode; and a second preliminary partition wall layer disposed on the first preliminary partition wall layer. Forming the conductive partition wall, the partition wall insulating layer, and the pixel defining layer may include: primarily etching the preliminary conductive partition wall, the preliminary partition wall insulating layer, and the preliminary pixel defining layer; and forming the first partition wall layer and the second partition wall layer by secondarily etching the first preliminary partition wall layer of the preliminary conductive partition wall.

[0024] In an embodiment, the method may further include forming an auxiliary electrode covering lower surfaces of the second electrode and the second partition wall layer.

[0025] In an implementation, the auxiliary electrode may be in contact with a side surface of the first partition wall layer.

[0026] In an embodiment, the method may further include forming a lower inorganic encapsulation pattern covering an upper surface of the auxiliary electrode, wherein the lower inorganic encapsulation pattern may be spaced apart from the common electrode.

[0027] In an embodiment, the method may further include: forming a light emitting contact hole by etching the preliminary conductive partition wall and the common electrode. The first electrode and the transistor may be electrically connected to each other through the light emitting contact hole.

[0028] In an embodiment, forming the preliminary partition wall insulating layer, the first electrode, and the preliminary pixel defining layer covering the first electrode on the preliminary conductive partition wall may include forming the preliminary partition wall insulating layer covering an inner surface of the light emitting contact hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects and features of the present invention will become apparent by describing in detail the embodiments of the present invention with reference to the attached drawings.

[0030] Figure 1A is a perspective view of a display device according to an embodiment.

[0031] Figure 1B is an exploded perspective view of a display device according to an embodiment.

[0032] Figure 2 is a cross-sectional view of a display module according to an embodiment.

[0033] Figure 3 is a plan view of a display panel according to an embodiment.

[0034] Figure 4 It is shown that according to the embodiment Figure 3 An enlarged plan view of a portion of a display area of ​​a display panel.

[0035] Figure 5 According to the implementation method Figure 4 A cross-sectional view of the display panel taken along line II'.

[0036] Figure 6 According to the implementation method Figure 4 2 is a cross-sectional view of a portion of the display panel taken along line II-II'.

[0037] Figure 7 According to the implementation method Figure 4 A cross-sectional view of the display panel taken along line III-III'.

[0038] Figure 8 According to the implementation method Figure 4 A cross-sectional view of the display panel taken along line II'.

[0039] Fig. 9 According to the implementation method Figure 4 A cross-sectional view of the display panel taken along line II'.

[0040] Fig. 10A is an enlarged plan view showing a portion of a display area of ​​a display panel according to an embodiment.

[0041] Fig. 10B According to the implementation method Fig. 10A A cross-sectional view of the display panel taken along line IV-IV'.

[0042] Fig.11A are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0043] Fig. 11B are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0044] Fig. 11C are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0045] Fig.11D are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0046] Fig.11E are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0047] Fig.11F are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0048] Fig.11G are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0049] Fig.11H are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0050] Fig.11I are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0051] Fig.11J are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0052] Figure 11K are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0053] Fig.11L are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0054] Fig. 12A are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0055] Fig. 12B are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0056] Fig. 12C are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment.

[0057] Fig.12D are cross-sectional views illustrating steps of a method for manufacturing a display panel according to an embodiment. DETAILED DESCRIPTION

[0058] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0059] In this specification, when a component (or region, layer, component, etc.) is referred to as being "on," "connected to" or "coupled to" another component, this means that the component may be directly on, directly connected to or directly coupled to the other component, or a third component may be present therebetween.

[0060] The same reference numerals represent the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for effective description. As used herein, the term "and / or" includes all of one or more combinations defined by the relevant components.

[0061] Terms such as first, second, etc. can be used to describe various components, but these components should not be limited by these terms. These terms can only be used to distinguish one component from other components. For example, without departing from the scope of the present invention, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component. Unless otherwise specified, terms in the singular may include plural forms.

[0062] In addition, terms such as "below", "beneath", "above", and "on" are used to describe the relationship of components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0063] It should be understood that when used herein, terms such as “include,” “comprises,” and “has” indicate the presence of stated features, quantities, steps, operations, components, parts, or a combination thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, or a combination thereof.

[0064] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. Those terms defined in commonly used dictionaries will be interpreted as having the same meaning as the contextual meaning in the relevant field, and should not be interpreted as having an ideal or overly formal meaning unless clearly defined as having such a meaning in this application.

[0065] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0066] Figure 1A is a perspective view of a display device DD according to an embodiment. Figure 1B is an exploded perspective view of a display device DD according to an embodiment.

[0067] In an embodiment, the display device DD may be a large electronic device such as a television, a monitor, or a billboard. In another embodiment, the display device DD may be a small or medium-sized electronic device such as a personal computer, a notebook computer, a personal digital terminal, a car navigation unit, a game console, a smart phone, a tablet computer, or a camera. However, this is merely illustrative, and the display device DD may be used as other display devices without departing from the spirit and scope of the present invention. Figure 1A and Figure 1B , the display device DD is shown as a smart phone.

[0068] In an embodiment, and with reference to Figure 1A and Figure 1B , the display device DD can display an image IM in a third direction DR3 on a display surface FS oriented parallel to the first direction DR1 and the second direction DR2. The image IM may include a still image as well as a dynamic image. Figure 1A , a clock window and an icon are shown as examples of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0069] In an embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of the member are defined based on the direction along which the image IM is displayed. The front surface and the rear surface may be facing away from each other in the third direction DR3, and the normal directions of the front surface and the rear surface may be oriented parallel to the third direction DR3. At the same time, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3, respectively, may be relative concepts and may be changed to other directions. As used herein, the expression "when viewed from above a plane" may mean that it is viewed in the third direction DR3.

[0070] In an embodiment, the display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to form an external appearance of the display device DD.

[0071] In an embodiment, the window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more.

[0072] In an embodiment, the frame area BZA may be an area having a lower light transmittance than the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be disposed adjacent to the transmission area TA and may surround the transmission area TA. However, this is merely illustrative, and in an embodiment, the frame area BZA of the window WP may be omitted. The window WP may include at least one of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and is not limited to any one embodiment.

[0073] In an embodiment, the display module DM may be disposed under the window WP. The display module DM may be a component that substantially generates an image IM. The image IM generated by the display module DM is displayed on the display surface IS of the display module DM and is visually recognized by the user from the outside through the transmission area TA.

[0074] In an embodiment, the display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area that is activated depending on an electrical signal. The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be an area covered by a bezel area BZA and may not be visible from the outside.

[0075] In an embodiment, the housing HAU may be coupled with the window WP. The housing HAU may be coupled with the window WP to provide an internal space. The display module DM may be accommodated in the internal space.

[0076] In an embodiment, the housing HAU may include a material having relatively high rigidity. For example, the housing HAU may include glass, plastic, or metal, or may include a plurality of frames and / or plates formed of a combination of the foregoing materials. The housing HAU may stably protect the components of the display device DD housed in the internal space from external impacts.

[0077] Figure 2 is a cross-sectional view of a display module DM according to an embodiment.

[0078] In an embodiment, and with reference to Figure 2 , the display module DM may include a display panel DP and an input sensor INS. Although not shown separately, according to an embodiment, the display device DD (refer to Figure 1A ) may further include a protection member disposed on a lower surface of the display panel DP, or an anti-reflection member and / or a window member disposed on an upper surface of the input sensor INS.

[0079] In an embodiment, the display panel DP may be an emissive display panel. However, this is illustrative, and the present invention is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The emissive layer in the organic light-emitting display panel may include an organic light-emitting material. The emissive layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro-LEDs. In the following, the display panel DP is taken as an example of an organic light-emitting display panel.

[0080] In an embodiment, the display panel DP may include a base layer BL and a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE disposed on the base layer BL. The input sensor INS may be directly disposed on the thin film encapsulation layer TFE. As used herein, the expression "component A is directly disposed on component B" means that no adhesive layer is disposed between component A and component B.

[0081] In an embodiment, the base layer BL may include at least one plastic film. The base layer BL may be a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate. Figure 1B Described is a display area DA and a non-display area NDA.

[0082] In an embodiment, the circuit element layer DP-CL may include at least one insulating layer and a circuit element. The insulating layer may include at least one inorganic layer and at least one organic layer. The circuit element includes a signal line and a pixel driving circuit.

[0083] In an embodiment, the display element layer DP-OLED may include a conductive partition wall and a light emitting element. The light emitting element may include an anode, an intermediate layer, and a cathode.

[0084] In an embodiment, the thin film encapsulation layer TFE may include a plurality of thin films, some of which may be provided to improve optical efficiency, and other thin films may be provided to protect the organic light emitting diode.

[0085] In an embodiment, the input sensor INS obtains coordinate information of an external input. The input sensor INS may have a multilayer structure. The input sensor INS may include a single conductive layer or a plurality of conductive layers. In addition, the input sensor INS may include a single insulating layer or a plurality of insulating layers. The input sensor INS may sense the external input in a capacitive type. However, this is illustrative, and the present invention is not limited thereto. For example, in an embodiment, the input sensor INS may sense the external input using an electromagnetic induction method or a pressure sensing method. Meanwhile, in another embodiment, the input sensor INS may be omitted.

[0086] Figure 3is a plan view of a display panel DP according to an embodiment.

[0087] In an embodiment, and with reference to Figure 3 , a display area DA and a non-display area NDA disposed around the display area DA may be defined in the display panel DP. The display panel DP may include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a drive circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA may be distinguished from each other depending on the position where the pixels PX are disposed. The pixels PX may be disposed in the display area DA. The drive circuit GDC and the pad portion PLD may be disposed in the non-display area NDA.

[0088] In an embodiment, the pixels PX may be arranged in the first direction DR1 and the second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0089] In an embodiment, the signal line SGL may include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. Each of the gate lines GL may be connected to a corresponding pixel among the pixels PX, and each of the data lines DL may be connected to a corresponding pixel among the pixels PX. The power line PL may be electrically connected to the pixel PX. The control signal line CSL may be connected to the drive circuit GDC, and may provide a control signal to the drive circuit GDC.

[0090] In an embodiment, the driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and may sequentially output the generated gate signal to the gate line GL. The gate driving circuit may additionally output other control signals to the pixel driving circuit.

[0091] In an embodiment, the pad portion PLD may be a portion connected to a flexible circuit board. The pad portion PLD may include a pixel pad D-PD, and the pixel pad D-PD may be a pad for connecting the flexible circuit board to the display panel DP. Each of the pixel pads D-PD may be connected to a corresponding signal line among the signal lines SGL. The pixel pad D-PD may be connected to a corresponding pixel PX through the signal line SGL. In addition, one of the pixel pads D-PD may be connected to a drive circuit GDC.

[0092] In addition, in an embodiment, the pad portion PLD may further include an input pad. The input pad may be used to connect the flexible circuit board to the input sensor INS (refer to Figure 2However, without limitation thereto, the input pad may be provided at the input sensor INS (reference Figure 2 ) and can be connected to the pixel pad D-PD and a separate circuit board. In another embodiment, the input sensor INS (reference Figure 2 ), and may not include an input pad additionally.

[0093] Figure 4 FIG. 2 is a diagram showing a display panel DP (refer to FIG. 2 ) according to an embodiment. Figure 2 ) display area DA (reference Figure 2 ) is an enlarged plan view of a portion of the ). Figure 4 is from the display module DM (reference Figure 1B ) display surface IS (reference Figure 1B ) is a plan view of the display module DM when viewed from above, and shows the arrangement of the emission areas PXA-R, PXA-G and PXA-B and the conductive partition walls PW.

[0094] In an embodiment, and with reference to Figure 4 , the display area DA may include emission areas PXA-R, PXA-G, and PXA-B and a peripheral area NPXA surrounding the emission areas PXA-R, PXA-G, and PXA-B. The emission areas PXA-R, PXA-G, and PXA-B may correspond to areas through which light provided from the light emitting element is emitted. The first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B may be respectively arranged according to the direction toward the display module DM (reference Figure 2 ) are distinguished from each other by the color of the light emitted externally.

[0095] In an embodiment, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may respectively provide first color light, second color light, and third color light having different colors. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, examples of the first color light, the second color light, and the third color light are not necessarily limited thereto.

[0096] In an embodiment, the emission regions PXA-R, PXA-G, and PXA-B may be defined as regions where the upper surface of the anode is exposed by the light emitting opening to be described below. The peripheral region NPXA may set the boundaries between the corresponding first emission region PXA-R, second emission region PXA-G, and third emission region PXA-B, and may prevent color mixing between the emission regions PXA-R, PXA-G, and PXA-B.

[0097] In an embodiment, a plurality of first emission regions PXA-R, a plurality of second emission regions PXA-G, and a plurality of third emission regions PXA-B may be provided. The plurality of first emission regions PXA-R, the plurality of second emission regions PXA-G, and the plurality of third emission regions PXA-B may have a predetermined arrangement in the display area DA, and may be repeatedly provided. For example, the first emission regions PXA-R and the third emission regions PXA-B may be alternately arranged in the first direction DR1 to form a "first group". The second emission regions PXA-G may be arranged in the first direction DR1 to form a "second group". The number of the "first group" and the "second group" may be set to a plurality, and the "first group" and the "second group" may be alternately arranged in the second direction DR2.

[0098] In an embodiment, one second emission region PXA-G may be spaced apart from one first emission region PXA-R or one third emission region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0099] In an embodiment, and with reference to Figure 4 , the arrangement of the emission regions PXA-R, PXA-G, and PXA-B is shown as an example, but is not limited thereto, and the emission regions PXA-R, PXA-G, and PXA-B may be arranged in various forms. In an embodiment, the emission regions PXA-R, PXA-G, and PXA-B may have a configuration as follows Figure 4 shown In another embodiment, the emission regions PXA-R, PXA-G, and PXA-B may have a stripe arrangement or a diamond arrangement. (Diamond pixel) arrangement.

[0100] In an embodiment, the emission regions PXA-R, PXA-G, and PXA-B may have various shapes when viewed from above a plane. For example, the emission regions PXA-R, PXA-G, and PXA-B may have a polygonal, circular, or elliptical shape. Figure 4 It is shown that when viewed from above a plane, the emission regions PXA-R, PXA-G, and PXA-B have a shape including a circular portion CP and a protruding portion PP extending from one side of the circular portion CP. In an embodiment, when viewed from above a plane, the first electrode AE ​​may also have a shape including a circular portion CP and a protruding portion PP extending from one side of the circular portion CP. A detailed description related to this will be given below.

[0101] In an embodiment, when viewed from above a plane, the emission regions PXA-R, PXA-G, and PXA-B may have the same shape, or at least some of the emission regions PXA-R, PXA-G, and PXA-B may have different shapes. Figure 4 An example is shown in which the emission regions PXA-R, PXA-B, and PXA-G have the same shape when viewed from above a plane, but the present invention is not limited thereto. For example, in an embodiment, when viewed from above a plane, the first emission region PXA-R and the third emission region PXA-B may have the same shape, and the second emission region PXA-G may have a shape different from that of the first emission region PXA-R and the third emission region PXA-B.

[0102] although Figure 4 An example is shown in which the emission regions PXA-R, PXA-G, and PXA-B have the same area when viewed from above a plane, but the present invention is not limited thereto, and at least some of the emission regions PXA-R, PXA-G, and PXA-B may have different areas when viewed from above a plane. In an embodiment, the area of ​​the first emission region PXA-R emitting red light may be greater than the area of ​​the second emission region PXA-G emitting green light, and may be smaller than the area of ​​the third emission region PXA-B emitting blue light.

[0103] In an embodiment, the display module DM (refer to Figure 2 The shape, area and arrangement of the emission regions PXA-R, PXA-G and PXA-B can be determined according to the color of the emitted light or the display module DM (reference Figure 2 ) are designed in various ways and are not limited to Figure 4 The embodiment shown.

[0104] Figure 5 According to the implementation method Figure 4 A cross-sectional view taken along line II'. Figure 6 According to the implementation method Figure 4 A cross-sectional view of a portion of the display panel DP taken along line II-II'. Figure 5 and Figure 6 When Figure 2 The description will be made, and the description of the same figure numerals will be omitted.

[0105] In an embodiment, Figure 5 The display area DA (reference Figure 4 ), and Figure 5 The emission region PXA may correspond to Figure 4In one of the emission regions PXA-R, PXA-G and PXA-B. In an embodiment, Figure 6 1 is an enlarged view of a portion of the display area DA where the first electrode AE ​​(or anode AE) is electrically connected to the transistor TR1. For ease of description, Figure 6 Only a portion of the base layer BL, a portion of the circuit element layer DP-CL and a portion of the display element layer DP-OLED are shown.

[0106] In an embodiment, and with reference to Figure 5 and Figure 6 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0107] In an embodiment, the display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, and signal lines. The insulating layers, semiconductor layers, and conductive layers are formed by coating, deposition, etc. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching. The semiconductor patterns, conductive patterns, and signal lines included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed by the method described above.

[0108] In an embodiment, the circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0109] In an embodiment, a buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve coupling force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked on each other.

[0110] In an embodiment, the semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, not limited thereto, the semiconductor pattern may include amorphous silicon or metal oxide. Figure 6 , a portion of the semiconductor pattern is shown as an example, and the semiconductor pattern may be further provided in a plurality of emission regions PXA-R, PXA-G, PXA-B (refer to Figure 4). The semiconductor pattern may be arranged throughout the plurality of emission regions PXA-R, PXA-G, PXA-B according to a specific rule. Depending on whether the semiconductor pattern is doped, the semiconductor pattern may have different electrical characteristics. The semiconductor pattern may include a first region having a high doping concentration and a second region having a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0111] In an embodiment, the first region has a higher conductivity than the second region and is substantially used as an electrode or a signal line. The second region may substantially correspond to an active region (or channel region) of a transistor. In other words, in an embodiment, one portion of the semiconductor pattern may be an active region of a transistor, another portion may be a source or drain of the transistor, and another portion may be a conductive region.

[0112] In an implementation, the source S, the active region A, and the drain D of the transistor TR1 may be formed of a semiconductor pattern. Figure 6 A portion of the signal transmission region SCL formed of a semiconductor pattern is shown in . Although not separately shown, the signal transmission region SCL may be connected to the drain D of the transistor TR1 when viewed from above a plane.

[0113] In an embodiment, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50 may be respectively disposed on the buffer layer BFL. The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50 may be respectively an inorganic layer or an organic layer.

[0114] In an embodiment, a first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active region A, the drain D, and the signal transmission region SCL of the transistor TR1 disposed on the buffer layer BFL. The gate G of the transistor TR1 may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate G. The electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the electrode EE.

[0115] In an implementation, the first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 and may cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0116] In an embodiment, the second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer. A contact hole CNT-3 passing through the fifth insulating layer 50 may be defined in the fifth insulating layer 50. The first electrode AE, which will be described below, may be connected to the second connection electrode CNE2 through the contact hole CNT-3.

[0117] In an embodiment, the display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include an insulating layer IL, a common electrode BE, a conductive partition wall PW, a partition wall insulating layer IP, a light emitting element ED, and an auxiliary electrode SE.

[0118] In an embodiment, the insulating layer IL may be disposed on the circuit element layer DP-CL. In detail, the insulating layer IL may be disposed on the fifth insulating layer 50 and may cover the fifth insulating layer 50. The insulating layer IL may define a portion of the light emitting contact hole OP-CH. Figure 6 , the light emitting contact hole OP-CH may be an opening through which the first electrode AE ​​is connected to the second connection electrode CNE2.

[0119] In an embodiment, the common electrode BE may be disposed on the insulating layer IL. For example, the common electrode BE may be disposed on the transistor TR1 of the circuit element layer DP-CL. The common electrode BE may be commonly disposed in the entire display area DA (refer to Figure 4 ) and a common voltage may be provided. For example, the common electrode BE may be arranged to overlap all of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B, respectively (refer to Figure 7 ). refer to Figure 6 , the common electrode BE may define a portion of the light emitting contact hole OP-CH.

[0120] In an embodiment, the conductive partition wall PW may be disposed on the common electrode BE. The conductive partition wall PW may have a partition wall opening OP-P (or, the partition wall opening OP-P may be defined in the conductive partition wall PW). The partition wall opening OP-P may not overlap with the light emitting opening OP-E to be described below. Figure 6 , the conductive partition wall PW may define a portion of the light emitting contact hole OP-CH.

[0121] In an embodiment, the conductive partition wall PW may have an undercut shape. The conductive partition wall PW may include a plurality of layers sequentially stacked on each other, and at least one of the plurality of layers may be recessed when compared to the other layers. Therefore, the conductive partition wall PW may include a tip portion.

[0122] In an embodiment, the conductive partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be disposed on the common electrode BE, and the second partition wall layer L2 may be disposed on the first partition wall layer L1. Figure 5 and Figure 6 As shown, the thickness of the first partition wall layer L1 may be greater than the thickness of the second partition wall layer L2. However, the present invention is not limited thereto.

[0123] In an embodiment, the first partition wall layer L1 may be relatively recessed relative to the emission area PXA when compared to the second partition wall layer L2. The first partition wall layer L1 may be undercut relative to the second partition wall layer L2. A portion of the second partition wall layer L2 protruding from the first partition wall layer L1 toward the center of the partition wall opening OP-P may be defined as a tip portion in the conductive partition wall PW.

[0124] In an embodiment, the partition wall opening OP-P defined in the conductive partition wall PW may include a first region A1 defined by the first partition wall layer L1 and a second region A2 defined by the second partition wall layer L2. The second region A2 may be formed integrally with the first region A1. That is, the first region A1 and the second region A2 may be openings formed integrally with each other. The width of the first region A1 may be different from the width of the second region A2. That is, the length of the first region A1 in the first direction DR1 may be greater than the length of the second region A2 in the first direction DR1. In this case, the second region A2 of the partition wall opening OP-P may be a region defining a tip portion. That is, due to the protruding tip portion, the second region A2 may have a narrower width than the first region A1.

[0125] In an embodiment, each of the first partition wall layer L1 and the second partition wall layer L2 may include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide. In an embodiment, the second partition wall layer L2 may include the same material as the common electrode BE, and the first partition wall layer L1 and the second partition wall layer L2 may include different materials. However, this is merely illustrative, and the present invention is not limited thereto.

[0126] In an embodiment, although Figure 5 An example is shown in which the inner surface of the conductive partition wall PW is oriented perpendicular to the upper surface of the common electrode BE, but the present invention is not limited thereto. For example, in another embodiment, the conductive partition wall PW may have a tapered shape or an inverted tapered shape.

[0127] In an embodiment, and with reference to Figure 4 and Figure 5 , when viewed from above a plane, the partition wall opening OP-P and the anode AE ​​may be spaced apart from each other. That is, the partition wall opening OP-P and the anode AE ​​may be formed so as not to overlap each other when viewed from above a plane. The anode AE ​​may overlap the center of the conductive partition wall PW.

[0128] In an embodiment, a partition wall insulating layer IP may be disposed on the conductive partition wall PW. The partition wall insulating layer IP disposed on the conductive partition wall PW may prevent electrical connection between the conductive partition wall PW and the first electrode AE. Figure 6 , the partition wall insulating layer IP may cover side surfaces of the conductive partition wall PW defining the light emitting contact hole OP-CH, side surfaces of the common electrode BE, and side surfaces of the insulating layer IL.

[0129] In an implementation, the light emitting element ED may include an anode AE ​​(or a first electrode AE), an emission pattern EP, and a cathode CE (or a second electrode CE).

[0130] In an embodiment, the anode AE ​​may be disposed on the partition wall insulating layer IP. The anode AE ​​may be disposed between the common electrode BE and the cathode CE to be described below. The anode AE ​​disposed on the partition wall insulating layer IP may contact the contact hole CNT-3 not covered by the partition wall insulating layer IP, and may be connected to the second connection electrode CNE2. Therefore, the anode AE ​​may be electrically connected to the signal transmission region SCL through the first connection electrode CNE1 and the second connection electrode CNE2, respectively, and may be electrically connected to a corresponding circuit element (e.g., transistor TR1).

[0131] In an embodiment, the anode AE ​​may be a transmissive electrode, a semi-transmissive and semi-reflective electrode, or a reflective electrode. The anode AE ​​may include a single-layer structure or a multi-layer structure. The anode AE ​​may include a plurality of layers including ITO and Ag. For example, in an embodiment, the anode AE ​​may include a layer including ITO (hereinafter referred to as a lower ITO layer), a layer disposed on the lower ITO layer and including Ag (hereinafter referred to as an Ag layer), and a layer disposed on the Ag layer and including ITO (hereinafter referred to as an upper ITO layer).

[0132] In an embodiment, the emission pattern EP may be disposed on the anode AE. The emission pattern EP may include an emission layer including a luminescent material. The emission pattern EP may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the anode AE ​​and the emission layer, and may further include an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the emission layer. The emission pattern EP may be referred to as an "organic layer" or an "intermediate layer".

[0133] In an embodiment, the emission pattern EP may be patterned by a tip portion defined in the conductive partition wall PW. The emission pattern EP may be formed to cover the side surface of the second partition wall layer L2. For example, in an embodiment, the emission pattern layer may be patterned by a tip portion defined in the conductive partition wall PW, and the emission pattern layer may form the emission pattern EP covering the side surface of the partition wall insulating layer IP and the side surface of the second partition wall layer L2 and the first dummy layer D1 disposed on the common electrode BE (refer to Fig.11G ).

[0134] In an embodiment, the cathode CE may be disposed on the emission pattern EP. The cathode CE may be patterned by a tip portion defined in the conductive partition wall PW. The cathode CE may cover at least a portion of the upper surface of the emission pattern EP and the side surface of the emission pattern EP. For example, the cathode layer may be patterned by a tip portion defined in the conductive partition wall PW, and the cathode layer may form a cathode CE covering at least a portion of the upper surface of the emission pattern EP and the side surface of the emission pattern EP and disposed on the first dummy layer D1 (reference Fig.11G ) on the second dummy layer D2 (reference Fig.11H ).

[0135] In an embodiment, the cathode CE may include a conductive material. As long as the cathode CE can have conductivity, the cathode CE may be formed of various materials such as metal, transparent conductive oxide (TCO) or conductive polymer material. For example, in an embodiment, the cathode CE may include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu) or a compound thereof. The cathode CE may be electrically connected to the conductive partition wall PW. A detailed description related to this will be given below.

[0136] In an embodiment, the auxiliary electrode SE may be disposed on the cathode CE. The auxiliary electrode SE may cover the cathode CE and may cover the lower surface B_L2 of the second partition wall layer L2 by directly contacting the lower surface B_L2 of the second partition wall layer L2. For example, the auxiliary electrode SE may cover the cathode CE and may extend along the lower surface B_L2 of the second partition wall layer L2 and the side surface S_L1 of the first partition wall layer L1. That is, the auxiliary electrode SE may contact the side surface S_L1 of the first partition wall layer L1. However, this is illustrative, and the shape of the auxiliary electrode SE is not limited to the above example.

[0137] In an embodiment, the auxiliary electrode SE may include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, in an embodiment, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0138] In an embodiment, the auxiliary electrode SE may electrically connect the cathode CE and the conductive partition wall PW by contacting the cathode CE and the conductive partition wall PW. The conductive partition wall PW may receive a driving voltage (or bias voltage), and the cathode CE may receive the driving voltage (or bias voltage) accordingly.

[0139] In an embodiment, the display element layer DP-OLED may further include a pixel defining layer PDL. The pixel defining layer PDL may be disposed on the partition wall insulating layer IP. The pixel defining layer PDL may have a light emitting opening OP-E exposing at least a portion of the anode AE ​​(or, the light emitting opening OP-E exposing at least a portion of the anode AE ​​may be defined in the pixel defining layer PDL). The light emitting opening OP-E may overlap with the anode AE ​​(or correspond to the anode AE), and the pixel defining layer PDL may expose at least a portion of the anode AE ​​through the light emitting opening OP-E. The pixel defining layer PDL may include an inorganic insulating material. For example, the pixel defining layer PDL may include silicon nitride (SiN x ).

[0140] In an embodiment, and with reference to Figure 5 The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower inorganic encapsulation pattern LIL, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL.

[0141] In an embodiment, the lower inorganic encapsulation pattern LIL may be formed to correspond to (or overlap) the light emitting opening OP-E or the conductive partition wall PW. The lower inorganic encapsulation pattern LIL may be disposed on the auxiliary electrode SE and may cover the upper surface of the auxiliary electrode SE. The lower inorganic encapsulation pattern LIL may be spaced apart from the common electrode BE. Figure 5 A space in which the lower inorganic encapsulation pattern LIL and the common electrode BE are spaced apart from each other as shown in the cross-sectional view of FIG. 5 may be defined as a dummy area DMA.

[0142] In an embodiment, the organic encapsulation film OL may be disposed on the lower inorganic encapsulation pattern LIL to cover the lower inorganic encapsulation pattern LIL, and may provide a flat upper surface. A portion of the organic encapsulation film OL may fill the dummy area DMA. However, the shape of the organic encapsulation film OL is illustrative, and the present invention is not limited thereto. For example, in an embodiment, the organic encapsulation film OL may not fill the dummy area DMA, and the dummy area DMA may remain an empty space.

[0143] In an implementation, the upper inorganic encapsulation film UIL may be disposed on the organic encapsulation film OL. The upper inorganic encapsulation film UIL may include an inorganic material.

[0144] In an embodiment, the lower inorganic encapsulation pattern LIL and the upper inorganic encapsulation film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the organic encapsulation film OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0145] In an embodiment, and with reference to Figure 4 and Figure 5 , the circular portion CP of the emission regions PXA-R, PXA-G, and PXA-B may be a region through which light provided from the light emitting element ED is emitted. The protruding portion PP of the emission regions PXA-R, PXA-G, and PXA-B may overlap with the light emitting contact hole OP-CH. The light emitting contact hole OP-CH may be defined to pass through the conductive partition wall PW, the common electrode BE, and the insulating layer IL, and the first electrode AE ​​may be electrically connected to the corresponding transistor TR1 through the light emitting contact hole OP-CH. When viewed from above the plane, the light emitting contact hole OP-CH may overlap with the first electrode AE.

[0146] In an embodiment, the display panel according to the comparative example may include a light emitting element formed in a partition wall opening of a conductive partition wall, and may include a lower inorganic encapsulation pattern having a cantilever shape and covering the light emitting element.

[0147] According to an embodiment, since the light emitting element ED is formed on the conductive partition wall PW rather than in the partition wall opening OP-P of the conductive partition wall PW, the occurrence of a shadow area can be prevented in the deposition process. Therefore, the present invention can provide a display panel DP that helps to achieve high resolution. In addition, since the lower inorganic encapsulation pattern LIL covering the light emitting element ED formed on the conductive partition wall PW is more stable and robust, and the light emitting element ED is not disposed in the partition wall opening OP-P, the thickness of the conductive partition wall PW can be reduced.

[0148] Figure 7 According to the implementation method Figure 4 A cross-sectional view taken along line III-III'. Figure 7 is an enlarged view showing a first emission region PXA-R, a second emission region PXA-G, and a third emission region PXA-B, and Figure 5 The description of the emission region PXA may be similarly applied to the Figure 7 Each of the emission areas PXA-R, PXA-G and PXA-B.

[0149] In an embodiment, and with reference to Figure 7 The display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include an insulating layer IL, a common electrode BE, a conductive partition wall PW, a partition wall insulating layer IP, a pixel defining layer PDL, a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3, and a first auxiliary electrode SE1, a second auxiliary electrode SE2, and a third auxiliary electrode SE3.

[0150] In an embodiment, the light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3. The first light emitting element ED1 may include a first anode AE1, a first emission pattern EP1, and a first cathode CE1. The second light emitting element ED2 may include a second anode AE2, a second emission pattern EP2, and a second cathode CE2. The third light emitting element ED3 may include a third anode AE3, a third emission pattern EP3, and a third cathode CE3. The first anode AE1, the second anode AE2, and the third anode AE3 may be respectively provided in a plurality of patterns. In an embodiment, the first emission pattern EP1 may provide red light, the second emission pattern EP2 may provide green light, and the third emission pattern EP3 may provide blue light.

[0151] In an embodiment, the display element layer DP-OLED may further include a pixel defining layer PDL. The pixel defining layer PDL may be disposed on the partition wall insulating layer IP. A first light emitting opening OP1-E, a second light emitting opening OP2-E, and a third light emitting opening OP3-E may be defined in the pixel defining layer PDL, respectively. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3.

[0152] In an embodiment, the first emission region PXA-R may be defined as a region of the upper surface of the first anode AE1 exposed by the first light emitting opening OP1-E. The second emission region PXA-G may be defined as a region of the upper surface of the second anode AE2 exposed by the second light emitting opening OP2-E. The third emission region PXA-B may be defined as a region of the upper surface of the third anode AE3 exposed by the third light emitting opening OP3-E.

[0153] In an embodiment, a partition wall opening OP-P that does not overlap with the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E, respectively, may be defined in the conductive partition wall PW. The partition wall opening OP-P may not overlap with the anodes AE1, AE2, and AE3. The partition wall opening OP-P may overlap with the peripheral area NPXA surrounding the emission areas PXA-R, PXA-G, and PXA-B. Each of the partition wall openings OP-P may include the above reference Figure 5 The first area A1 described (refer to Figure 5 ) and the second area A2 (reference Figure 5 ).

[0154] In an embodiment, the emission patterns EP1, EP2, and EP3 may be physically separated from each other by forming a second partition wall layer L2 at a tip portion, and the emission patterns EP1, EP2, and EP3 may cover a side surface of the second partition wall layer L2. In addition, the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be physically separated from each other by forming a second partition wall layer L2 at a tip portion, respectively, and the first cathode CE1, the second cathode CE2, and the third cathode CE3 may cover an upper surface of the corresponding emission patterns EP1, EP2, and EP3 and at least a portion of a side surface of the corresponding emission patterns EP1, EP2, and EP3.

[0155] According to an embodiment, a plurality of first emission patterns EP1 may be patterned and deposited in a pixel unit by a tip portion defined in a conductive partition wall PW. That is, the first emission patterns EP1 may be commonly formed using an open mask, but may be easily separated from each other in a pixel unit by a conductive partition wall PW.

[0156] In contrast, when the first emission pattern EP1 is patterned using a fine metal mask (FMM), a spacer for support protruding from the conductive partition wall must be provided to support the fine metal mask. In addition, the fine metal mask may be separated from the base surface on which patterning is performed by the height of the partition wall and the spacer, and therefore there may be limitations in achieving high resolution. In addition, since the fine metal mask is in contact with the spacer, after the patterning process of the first emission pattern EP1, foreign matter may remain on the spacer, or the spacer may be damaged by a dent in the fine metal mask. Therefore, a defective display panel may be formed.

[0157] According to the embodiment, since the conductive partition wall PW is included, physical separation between the light emitting elements ED1, ED2, and ED3 can be easily achieved. Therefore, current leakage or driving error between adjacent emission regions PXA-R, PXA-G, and PXA-B can be prevented, and the light emitting elements ED1, ED2, and ED3 can be driven independently.

[0158] In an embodiment, by making the plurality of first emission patterns EP1 not aligned with the display area DA (reference Figure 1B ) is subjected to patterning without a mask that contacts the internal components in the conductive partition wall ), the defect rate can be reduced, and thus a display panel DP with improved process reliability can be provided. Since a pattern can be formed even without a separate spacer for support protruding from the conductive partition wall PW, the area of ​​the emission regions PXA-R, PXA-G, and PXA-B can be scaled down, and thus a display panel DP that can easily achieve high resolution can be provided.

[0159] In an embodiment, when manufacturing a large-area display panel DP, the manufacture of a large-area mask may be omitted. Therefore, the process cost may be reduced, and the display panel DP may not be affected by defects that may occur in the large-area mask. Therefore, a display panel DP with improved process reliability may be provided. The description of the plurality of first emission patterns EP1 may be similarly applied to the plurality of second emission patterns EP2 and the plurality of third emission patterns EP3.

[0160] In an embodiment, the auxiliary electrodes SE1, SE2, and SE3 may include a first auxiliary electrode SE1, a second auxiliary electrode SE2, and a third auxiliary electrode SE3. The first auxiliary electrode SE1 may cover the first cathode CE1, the second auxiliary electrode SE2 may cover the second cathode CE2, and the third auxiliary electrode SE3 may cover the third cathode CE3. The auxiliary electrodes SE1, SE2, and SE3 may be connected to the lower surface B_L2 (see FIG. 2 ) of the second partition wall layer L2. Figure 5 ) directly contacts and covers the lower surface B_L2 of the second partition wall layer L2 (see Figure 5 ).

[0161] In an embodiment, the first auxiliary electrode SE1 may electrically connect the first cathode CE1 and the conductive partition wall PW by contacting the first cathode CE1 and the conductive partition wall PW. The conductive partition wall PW may receive a driving voltage (or a bias voltage), and the first cathode CE1 may receive the driving voltage (or a bias voltage) accordingly. The second auxiliary electrode SE2 may electrically connect the second cathode CE2 and the conductive partition wall PW by contacting the second cathode CE2 and the conductive partition wall PW. The conductive partition wall PW may receive a driving voltage (or a bias voltage), and the second cathode CE2 may receive a driving voltage (or a bias voltage) accordingly. The third auxiliary electrode SE3 may electrically connect the third cathode CE3 and the conductive partition wall PW by contacting the third cathode CE3 and the conductive partition wall PW. The conductive partition wall PW may receive a driving voltage (or a bias voltage), and the third cathode CE3 may receive a driving voltage (or a bias voltage) accordingly.

[0162] In an implementation, the thin film encapsulation layer TFE may include lower inorganic encapsulation patterns LIL1 , LIL2 , and LIL3 , an organic encapsulation film OL, and an upper inorganic encapsulation film UIL.

[0163] In an embodiment, the lower inorganic encapsulation patterns LIL1, LIL2, and LIL3 may include a first lower inorganic encapsulation pattern LIL1, a second lower inorganic encapsulation pattern LIL2, and a third lower inorganic encapsulation pattern LIL3. The lower inorganic encapsulation patterns LIL1, LIL2, and LIL3 may be spaced apart from the common electrode BE.

[0164] In an embodiment, the first lower inorganic encapsulation pattern LIL1 may be formed to correspond to (or overlap with) the first light emitting opening OP1-E or the conductive partition wall PW. The first lower inorganic encapsulation pattern LIL1 may be disposed on the first auxiliary electrode SE1 and may cover an upper surface of the first auxiliary electrode SE1.

[0165] In an embodiment, the second lower inorganic encapsulation pattern LIL2 may be formed to correspond to (or overlap with) the second light emitting opening OP2-E or the conductive partition wall PW. The second lower inorganic encapsulation pattern LIL2 may be disposed on the second auxiliary electrode SE2 and may cover an upper surface of the second auxiliary electrode SE2.

[0166] In an embodiment, the third lower inorganic encapsulation pattern LIL3 may be formed to correspond to (or overlap with) the third light emitting opening OP3-E or the conductive partition wall PW. The third lower inorganic encapsulation pattern LIL3 may be disposed on the third auxiliary electrode SE3 and may cover an upper surface of the third auxiliary electrode SE3.

[0167] Figure 8 According to the implementation method Figure 4 A cross-sectional view taken along line I-I'. Figure 8 When Figure 5 The description will be made, and the description of the same figure numerals will be omitted.

[0168] In an embodiment, and with reference to Figure 8 The display panel DPa may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFEa. The thin film encapsulation layer TFEa may include a lower inorganic encapsulation pattern LIL, an organic encapsulation film OLa and an upper inorganic encapsulation film UIL.

[0169] In an implementation, the lower inorganic encapsulation pattern LIL may be spaced apart from the common electrode BE. Figure 8 A space in which the lower inorganic encapsulation pattern LIL and the common electrode BE are spaced apart from each other as shown in the cross section of EMBODIMENT 3 may be defined as a dummy area DMA.

[0170] In an embodiment, the organic encapsulation film OLa may be disposed on the lower inorganic encapsulation pattern LIL to cover the lower inorganic encapsulation pattern LIL, and may provide a flat upper surface. The organic encapsulation film OLa may cover the upper surface and the side surface of the lower inorganic encapsulation pattern LIL. That is, the organic encapsulation film OLa may not fill the dummy area DMA. In this case, an additional inorganic film may be disposed between the lower inorganic encapsulation pattern LIL and the organic encapsulation film OLa. However, the shape or arrangement of the organic encapsulation film OLa is illustrative, and the present invention is not limited thereto. For example, the organic encapsulation film OLa may fill the dummy area DMA, or may fill only a portion of the dummy area DMA.

[0171] Fig. 9 According to the implementation method Figure 4 A cross-sectional view taken along line I-I'. Fig. 9 When Figure 5 The description will be made, and the description of the same figure numerals will be omitted.

[0172] In an embodiment, and with reference to Fig. 9 , the display panel DPb may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLEDa, and a thin film encapsulation layer TFE. The display element layer DP-OLEDa may include an insulating layer IL, a common electrode BE, a conductive partition wall PW, a partition wall insulating layer IP, a pixel defining layer PDL, a light emitting element ED, an auxiliary electrode SEa, and a dummy auxiliary electrode SE-D. In another embodiment, in the display element layer DP-OLEDa, the pixel defining layer PDL may be omitted.

[0173] In an implementation, the auxiliary electrode SEa may be disposed on the cathode CE. The auxiliary electrode SEa may cover the cathode CE and may cover the lower surface B_L2 of the second partition wall layer L2 by directly contacting the lower surface B_L2 of the second partition wall layer L2.

[0174] In an implementation, the dummy auxiliary electrode SE-D may be in contact with the side surface S_L1 of the first partition wall layer L1 and may protrude from the side surface S_L1 of the first partition wall layer L1 toward the center of the partition wall opening OP-P.

[0175] In an embodiment, the dummy auxiliary electrode SE-D may be spaced apart from the auxiliary electrode SEa. The dummy auxiliary electrode SE-D may be spaced apart from the auxiliary electrode SEa in the thickness direction (e.g., the third direction DR3) of the display element layer DP-OLEDa. The dummy auxiliary electrode SE-D may include the same material as the auxiliary electrode SEa and may be formed by the same process as the auxiliary electrode SEa. For example, when the auxiliary electrode SE (refer to Figure 5) is formed to be thick, the auxiliary electrode SE can extend from the lower surface B_L2 of the second partition wall layer L2 to the side surface S_L1 of the first partition wall layer L1, and when the auxiliary electrode SEa is formed to be relatively thin, the auxiliary electrode SEa can extend to the lower surface B_L2 of the second partition wall layer L2, and a dummy auxiliary electrode SE-D separated from the auxiliary electrode SEa can be additionally formed.

[0176] In an embodiment, the auxiliary electrode SEa may include a conductive material. The auxiliary electrode SEa may electrically connect the cathode CE and the conductive partition wall PW by contacting the cathode CE and the conductive partition wall PW. The conductive partition wall PW may receive a driving voltage (or a bias voltage), and the cathode CE may receive a driving voltage (or a bias voltage) accordingly.

[0177] Fig. 10A FIG. 2 is a diagram showing a display panel DPc (refer to FIG. 2 ) according to an embodiment. Fig. 10B ) is an enlarged plan view of a portion of the display area DAa. In an embodiment, Fig. 10A is from the display module DM (reference Figure 1B ) display surface IS (reference Figure 1B ) is a plan view of the display module DM when viewed from above, and shows the arrangement of the emission regions PXA-Ra, PXA-Ga and PXA-Ba and the conductive partition walls PWa. Fig. 10B According to the implementation method Fig. 10A A cross-sectional view taken along line IV-IV'. Fig. 10A and Fig. 10B When Figure 4 and Figure 5 The description will be made, and the description of the same figure numerals will be omitted.

[0178] In an embodiment, and with reference to Fig. 10A , the display area DAa may include emission areas PXA-Ra, PXA-Ga and PXA-Ba (or Fig. 10B The emission area PXAa) and the peripheral area NPXAa surrounding the emission areas PXA-Ra, PXA-Ga and PXA-Ba. In addition to the shape, Fig. 10A The emission regions PXA-Ra, PXA-Ga and PXA-Ba can be placed, arranged, area and function with Figure 4 The emission areas PXA-R, PXA-G and PXA-B are basically the same.

[0179] In an embodiment, Fig. 10A Each of the emission regions PXA-Ra, PXA-Ga, and PXA-Ba may include a circular portion CPa. That is, Figure 4The emission areas PXA-R, PXA-G and PXA-B are different. In an embodiment, Fig. 10A The emission regions PXA-Ra, PXA-Ga and PXA-Ba may not include the protruding portion PP (reference Figure 4 ). In an embodiment, Fig. 10B The first electrode AEa may also include the circular portion CPa, but may not include the protruding portion PP (refer to Figure 4 ). In an embodiment, reference Fig. 10B , the display panel DPc may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLEDb and a thin film encapsulation layer TFE. The display element layer DP-OLEDb may include an insulating layer ILa, a common electrode BEa, a conductive partition wall PWa, a partition wall insulating layer IPa, a pixel defining layer PDL, a light emitting element EDa and an auxiliary electrode SE. The light emitting element EDa may include a first electrode AEa (or anode AEa), an emission pattern EPa and a second electrode CE (or cathode CE).

[0180] In an embodiment, and with reference to Fig. 10A and Fig. 10B , the circular portion CPa of the emission regions PXA-Ra, PXA-Ga, and PXA-Ba may be a region through which light provided from the light emitting element EDa is emitted. When viewed from above the plane, the light emitting contact hole OP-CHa may overlap with the center of the circular portion CPa. The light emitting contact hole OP-CHa may be defined to pass through the conductive partition wall PWa, the common electrode BEa, and the insulating layer ILa, and the first electrode AEa may be connected to the corresponding transistor TR1 (reference Figure 6 ) is electrically connected. When viewed from above a plane, the light emitting contact hole OP-CHa may overlap with the first electrode AEa. When viewed from above a plane, the partition wall opening OP-P of the conductive partition wall PWa and the anode AEa may be spaced apart from each other. That is, when viewed from above a plane, the partition wall opening OP-P and the anode AEa may be formed so as not to overlap with each other.

[0181] FIG. 11A to FIG. 11L are cross-sectional views showing some of the steps of a method for manufacturing a display panel according to an embodiment. FIG. 11A to FIG. 11L When compared with the above reference Figures 1A to 7 The same / similar components to the components described will be given the same / similar reference numerals, and duplicate description will be omitted.

[0182] In an embodiment, a display panel manufacturing method may include the steps of forming a common electrode and a circuit element layer including a transistor on a base layer, forming a preliminary conductive partition wall on the common electrode, forming a preliminary partition wall insulating layer, a first electrode and a preliminary pixel defining layer covering the first electrode on the preliminary conductive partition wall, forming a light-emitting opening overlapping the first electrode by etching the preliminary pixel defining layer, forming a conductive partition wall having a partition wall opening defined therein, a partition wall insulating layer and a pixel defining layer by etching the preliminary conductive partition wall, the preliminary partition wall insulating layer and the preliminary pixel defining layer, forming an emission pattern covering the first electrode on the conductive partition wall, and forming a second electrode electrically connected to the conductive partition wall on the emission pattern, wherein the light-emitting opening and the partition wall opening may not overlap with each other when viewed from above a plane.

[0183] In the following, reference will be made to FIG. 11A to FIG. 11L Describes forming a light emitting element (for example, the first light emitting element ED1 (refer to Figure 7 )), and a lower inorganic encapsulation pattern (eg, a first lower inorganic encapsulation pattern LIL1 (refer to Figure 7 )), an organic encapsulation film OL and an upper inorganic encapsulation film UIL. According to the embodiment of the method FIG. 11A to FIG. 11L The display panel formed by the method shown in Figure 5 display panel DP.

[0184] In an embodiment, and with reference to Fig.11A The display panel manufacturing method may include forming a common electrode BE on a base layer BL and a transistor TR1 (reference Figure 6 ) steps of the circuit element layer DP-CL.

[0185] In an embodiment, the circuit element layer DP-CL including the transistor TR1 may be formed by a conventional circuit element manufacturing process, which forms an insulating layer, a semiconductor layer, and a conductive layer by coating, deposition, etc., and forms a semiconductor pattern, a conductive pattern, and a signal line by selectively subjecting the insulating layer, the semiconductor layer, and the conductive layer to patterning by photolithography and etching processes. In an embodiment, the display panel manufacturing method of the present invention may further include a step of depositing an insulating layer IL on the circuit element layer DP-CL.

[0186] In an embodiment, the common electrode BE may be disposed on the base layer BL. In detail, the common electrode BE may be formed on the insulating layer IL. The common electrode BE may be commonly disposed in the entire display area DA (refer to Figure 4 ) and can be formed to provide a common voltage.

[0187] In an embodiment, and with reference to Fig. 11B , the display panel manufacturing method may include the step of forming a preliminary conductive partition wall PW-I on the common electrode BE. The preliminary conductive partition wall PW-I may include a first preliminary partition wall layer L1-I disposed on the common electrode BE and a second preliminary partition wall layer L2-I disposed on the first preliminary partition wall layer L1-I.

[0188] In an embodiment, the steps of forming the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I can be performed by a process of depositing a conductive material. For example, in an embodiment, the conductive material may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, in an embodiment, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide. In an embodiment, the second preliminary partition wall layer L2-I may include the same material as the common electrode BE, and the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may include different materials. However, this is illustrative, and the present invention is not limited thereto.

[0189] In an embodiment, and with reference to Fig. 11C The display panel manufacturing method may include the steps of forming a preliminary partition wall insulating layer IP-I, a first electrode AE ​​(or anode AE), and a preliminary pixel defining layer PDL-I covering the first electrode AE ​​on the preliminary conductive partition wall PW-I.

[0190] In an embodiment, the preliminary partition wall insulating layer IP-I may be formed on the preliminary conductive partition wall PW-I, and the anode AE ​​may be formed on the preliminary partition wall insulating layer IP-I. The preliminary pixel defining layer PDL-I may be formed to cover the anode AE.

[0191] In an embodiment, the display panel manufacturing method may further include the step of forming a first photoresist layer PR1 on the preliminary pixel defining layer PDL-I. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the preliminary pixel defining layer PDL-I, and then subjecting the preliminary photoresist layer to patterning using a photomask. Through the patterning process, a first optical opening OP-PR1 overlapping the anode AE ​​may be formed in the first photoresist layer PR1.

[0192] In an embodiment, and with reference to Fig.11D, the display panel manufacturing method may include a step of forming a light emitting opening OP-E overlapping the anode AE ​​(or the first electrode AE) by etching the preliminary pixel defining layer PDL-I.

[0193] In an embodiment, the step of etching the preliminary pixel defining layer PDL-I may be performed by using a first photoresist layer PR1 (refer to Fig. 11C ) as a mask to dry-etch a portion of the preliminary pixel defining layer PDL-I. The etched portion of the preliminary pixel defining layer PDL-I may be removed, and a light emitting opening OP-E may be formed in the preliminary pixel defining layer PDL-I accordingly. The light emitting opening OP-E may overlap with the anode AE ​​(or the first electrode AE).

[0194] In an embodiment, the display panel manufacturing method may further include a step of forming a second photoresist layer PR2 on the preliminary pixel defining layer PDL-I after removing the first photoresist layer PR1. The second photoresist layer PR2 may be formed by forming a preliminary photoresist layer on the preliminary pixel defining layer PDL-I and then subjecting the preliminary photoresist layer to patterning using a photomask. Through the patterning process, the second photoresist layer PR2 may overlap with the light emitting opening OP-E.

[0195] In an embodiment, reference Fig.11E and Fig.11F , the display panel manufacturing method may include etching a preliminary conductive partition wall PW-I (reference Fig.11D )、Preliminary partition wall insulation layer IP-I (reference Fig.11D ) and the preliminary pixel definition layer PDL-I (reference Fig.11D ) to form a conductive partition wall PW in which a partition wall opening OP-P is defined, a partition wall insulating layer IP, and a pixel defining layer PDL.

[0196] In an embodiment, the preliminary conductive partition wall PW-I (refer to Fig.11D )、Preliminary partition wall insulation layer IP-I (reference Fig.11D ) and the preliminary pixel definition layer PDL-I (reference Fig.11D The step of forming a conductive partition wall PW having a partition wall opening OP-P defined therein, a partition wall insulating layer IP, and a pixel defining layer PDL by etching the conductive partition wall PW-I, the preliminary partition wall insulating layer IP-I, and the preliminary pixel defining layer PDL-I may include a step of primarily etching the preliminary conductive partition wall PW-I, the preliminary partition wall insulating layer IP-I, and the preliminary pixel defining layer PDL-I, and a step of forming a first partition wall layer L1 and a second partition wall layer L2 by secondarily etching the first preliminary partition wall layer L1-I of the preliminary conductive partition wall PW-I. Fig.11E The first etching step is described and will be referred to Fig.11F The second etching step is described.

[0197] In an embodiment, if Fig.11E As shown, the second photoresist layer PR2 can be used as a mask to form a preliminary conductive partition wall PW-I (reference Fig.11D )、Preliminary partition wall insulation layer IP-I (reference Fig.11D ) and the preliminary pixel definition layer PDL-I (reference Fig.11D ) is dry-etched. The etched portions of the preliminary conductive partition wall PW-I, the preliminary partition wall insulating layer IP-I, and the preliminary pixel defining layer PDL-I may be removed, and a preliminary partition wall opening OP-PI may be formed in the preliminary conductive partition wall PW-I.

[0198] In an embodiment, if Fig.11F As shown, the first preliminary partition wall layer L1-I of the preliminary conductive partition wall PW-I may be wet-etched using the second photoresist layer PR2 as a mask. The etched portion of the first preliminary partition wall layer L1-I may be removed, and the first partition wall layer L1 and the second partition wall layer L2 may be formed. The first partition wall layer L1 and the second partition wall layer L2 may be referred to as a conductive partition wall PW. A partition wall opening OP-P may be formed in the conductive partition wall PW. The partition wall opening OP-P may include a first area A1 (reference Figure 5 ) and the second area A2 (reference Figure 5 ). When viewed from above in a plane, the light emitting opening OP-E and the partition wall opening OP-P may not overlap with each other.

[0199] In an embodiment, a wet etching process may be performed in an environment where the etching selectivity between the first partition wall layer L1 and the second partition wall layer L2 is high. Therefore, the inner surface of the conductive partition wall PW defining the partition wall opening OP-P may have an undercut shape. Specifically, since the etching rate of the etchant to the first partition wall layer L1 is higher than the etching rate of the etchant to the second partition wall layer L2, the first partition wall layer L1 may be mainly etched. Therefore, when compared with the inner surface of the second partition wall layer L2, the inner surface of the first partition wall layer L1 may be further recessed inward. A tip portion may be formed in the conductive partition wall PW by a portion of the second partition wall layer L2 that further protrudes when compared with the first partition wall layer L1.

[0200] although Fig.11E and Fig.11F 2 shows an embodiment of forming one partition wall opening OP-P, but the present invention is not limited thereto. In an embodiment, the step of forming the partition wall opening OP-P may include simultaneously forming the emission regions PXA-R, PXA-G, and PXA-B (refer to Figure 7 ) corresponds to the partition wall opening OP-P (reference Figure 7In an embodiment, the step of forming the partition wall opening OP-P may include the step of forming only the partition wall opening OP-P corresponding to the first emission region PXA-R. For example, after forming the partition wall opening OP-P corresponding to the first emission region PXA-R and then forming the first light emitting element ED1 (refer to Figure 7 ) After that, a partition wall opening OP-P corresponding to the second emission region PXA-G may be formed. In addition, through subsequent processes, a second light emitting element ED2 (refer to Figure 7 ), and a partition wall opening OP-P corresponding to the third emission region PXA-B may be formed.

[0201] In an embodiment, and with reference to Fig.11G The display panel manufacturing method may include removing the second photoresist layer PR2 (reference Fig.11F ), after that, a step of forming an emission pattern EP covering the first electrode AE ​​(or anode AE) on the conductive partition wall PW.

[0202] In an embodiment, the step of forming the emission pattern EP may include a deposition process of an emission pattern layer. In an embodiment, the deposition process of the emission pattern layer may be a thermal evaporation process. However, this is illustrative, and the deposition process of the emission pattern layer is not limited to the above example. In an embodiment, the emission pattern layer may be separated by a tip portion formed in the conductive partition wall PW, and the emission pattern EP and the first dummy layer D1 may be formed. The emission pattern EP may be formed to cover the side surface of the partition wall insulating layer IP and the side surface of the second partition wall layer L2, and the first dummy layer D1 may be formed on the common electrode BE.

[0203] In an embodiment, in the step of forming the emission pattern EP, a first dummy layer D1 spaced apart from the emission pattern EP may be formed together. The first dummy layer D1 may include an organic material. For example, the first dummy layer D1 may include the same material as the emission pattern EP. The first dummy layer D1 may be formed simultaneously with the emission pattern EP through one process, and may be separated from the emission pattern EP by the undercut shape of the conductive partition wall PW.

[0204] In an embodiment, and with reference to Fig.11H , the display panel manufacturing method may include a step of forming a second electrode CE (or cathode CE) electrically connected to the conductive partition wall PW on the emission pattern EP.

[0205] In an embodiment, the step of forming the cathode CE may include a deposition process of a cathode layer. In an embodiment, the deposition process of the cathode layer may be a thermal evaporation process. However, this is illustrative, and the deposition process of the cathode layer is not limited to the above example. In an embodiment, the cathode layer may be separated by a tip portion formed in the conductive partition wall PW, and the cathode CE and the second dummy layer D2 may be formed. The cathode CE may be formed to cover at least a portion of the upper surface of the emission pattern EP and the side surface of the emission pattern EP, and the second dummy layer D2 may be formed on the first dummy layer D1.

[0206] In an embodiment, in the step of forming the cathode CE, a second dummy layer D2 spaced apart from the cathode CE may be formed together. The second dummy layer D2 may include a conductive material. For example, the second dummy layer D2 may include the same material as the cathode CE. The second dummy layer D2 may be formed simultaneously with the cathode CE through one process, and may be separated from the cathode CE by the undercut shape of the conductive partition wall PW.

[0207] In an embodiment, the anode AE, the emission pattern EP, and the cathode CE may be sequentially stacked in the third direction DR3. The anode AE, the emission pattern EP, and the cathode CE may form a light emitting element ED. The first dummy layer D1 and the second dummy layer D2 may be sequentially stacked in the third direction DR3.

[0208] In an embodiment, and with reference to Fig.11I , the display panel manufacturing method may include a step of forming an auxiliary electrode SE covering the lower surface of the second electrode CE (or cathode CE) and the second partition wall layer L2.

[0209] In an embodiment, the step of forming the auxiliary electrode SE may include a deposition process of the auxiliary electrode layer. The deposition process of the auxiliary electrode layer may be a sputtering process. However, this is illustrative, and the deposition process of the auxiliary electrode layer is not limited to the above example.

[0210] In an embodiment, the auxiliary electrode layer may include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0211] In an embodiment, the auxiliary electrode SE may be disposed on the cathode CE. The auxiliary electrode SE may cover the cathode CE and may be connected to the lower surface B_L2 (reference numeral 2) of the second partition wall layer L2. Figure 5) to directly contact and cover the lower surface B_L2 of the second partition wall layer L2. In an embodiment, the auxiliary electrode SE may be arranged along the lower surface B_L2 (reference Figure 5 ) and the side surface S_L1 (reference Figure 5 ) extends. That is, the auxiliary electrode SE may be formed to contact the side surface S_L1 of the first partition wall layer L1. However, this is illustrative, and the shape of the auxiliary electrode SE is not limited to the above example. In an embodiment, the auxiliary electrode SE may extend to the lower surface B_L2 of the second partition wall layer L2, and the dummy auxiliary electrode SE-D (see Fig. 9 ) may be formed to be in contact with the side surface S_L1 of the first partition wall layer L1 and to protrude from the side surface S_L1 of the first partition wall layer L1 toward the center of the partition wall opening OP-P.

[0212] In an embodiment, and with reference to Fig.11J and Figure 11K The display panel manufacturing method may include the step of forming a lower inorganic encapsulation pattern LIL covering the auxiliary electrode SE. The step of forming the lower inorganic encapsulation pattern LIL may include the step of depositing a lower inorganic encapsulation layer LIL-I and the step of removing a portion of the lower inorganic encapsulation layer LIL-I that does not overlap with the light emitting element ED.

[0213] In an embodiment, and with reference to Fig.11J , the step of forming the lower inorganic encapsulation pattern LIL may include the step of depositing a lower inorganic encapsulation layer LIL-I. The lower inorganic encapsulation layer LIL-I may be formed by a deposition process. In an embodiment, the lower inorganic encapsulation layer LIL-I may be formed by a chemical vapor deposition (CVD) process. The lower inorganic encapsulation layer LIL-I may be formed to cover the upper surface of the auxiliary electrode SE.

[0214] In an embodiment, and with reference to Figure 11K The step of forming the lower inorganic encapsulation pattern LIL may include the steps of forming a third photoresist layer PR3 and removing the lower inorganic encapsulation layer LIL-I (refer to Fig.11J ) of the part that does not overlap with the light emitting element ED.

[0215] In an embodiment, in the step of forming the third photoresist layer PR3, the third photoresist layer PR3 can be formed by forming a preliminary photoresist layer and subjecting the preliminary photoresist layer to patterning using a photomask. Through the patterning process, the third photoresist layer PR3 can be formed in the form of a pattern corresponding to the light emitting element ED.

[0216] In an embodiment, in the step of removing the portion of the lower inorganic encapsulation layer LIL-I that does not overlap with the light emitting element ED, the lower inorganic encapsulation layer LIL-I may be patterned by dry etching the lower inorganic encapsulation layer LIL-I using the third photoresist layer PR3 as a mask, thereby removing the portion of the lower inorganic encapsulation layer LIL-I that does not overlap with the light emitting element ED. The lower inorganic encapsulation pattern LIL overlapping with the light emitting element ED may be formed by the patterned lower inorganic encapsulation layer LIL-I.

[0217] In an embodiment, the display panel manufacturing method may further include removing the dummy layers D1 and D2 (refer to Fig.11J ) to form a dummy area DMA. The second dummy layer D2 may be removed by wet etching, and the first dummy layer D1 may be removed by a stripper. In an embodiment, by removing the dummy layers D1 and D2, a dummy area DMA may be formed between the conductive partition wall PW and the lower inorganic encapsulation pattern LIL. When the dummy area DMA is formed, the lower inorganic encapsulation pattern LIL may be spaced apart from the common electrode BE by the dummy area DMA.

[0218] In an embodiment, and with reference to Fig.11L The display panel manufacturing method may include removing the third photoresist layer PR3 (reference Figure 11K ) and then forming an organic encapsulation film OL and an upper inorganic encapsulation film UIL to complete the step of display panel DP. The organic encapsulation film OL may be formed by applying an organic material using an inkjet method, but is not limited thereto. The organic encapsulation film OL provides a flat upper surface. The organic encapsulation film OL may fill the dummy area DMA. However, this is illustrative, and the present invention is not limited thereto. For example, the organic encapsulation film OL may not fill the dummy area DMA or may fill only a portion of the dummy area DMA.

[0219] In an embodiment, the upper inorganic encapsulation film UIL may be formed by depositing an inorganic material. Thus, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE may be formed.

[0220] In an embodiment, between the step of forming the lower inorganic encapsulation pattern LIL and the step of completing the display panel DP, a step of forming a partition wall opening and a light emitting opening corresponding to an emission area having other colors in the conductive partition wall PW and the pixel defining layer PDL, a step of forming a light emitting element providing other colors, and a step of forming an auxiliary electrode covering the light emitting element providing other colors and a lower inorganic encapsulation pattern covering the auxiliary electrode may be additionally performed. Figure 7The display panel DP shown includes light emitting elements ED1, ED2, and ED3, auxiliary electrodes SE1, SE2, and SE3, and lower inorganic encapsulation patterns LIL1, LIL2, and LIL3.

[0221] FIG. 12A to FIG. 12D are cross-sectional views showing some of the steps of a method for manufacturing a display panel according to an embodiment. FIG. 12A to FIG. 12D When, with reference Figures 1A to 11L The same / similar components to the components described will be given the same / similar reference numerals, and duplicate description will be omitted.

[0222] In the implementation mode, reference is made to FIG. 12A to FIG. 12D The process of electrically connecting the first electrode AE ​​(or anode AE) in the display area DA to the transistor TR1 will be described. FIG. 12A to FIG. 12D The process described may correspond to reference Fig. 11B and Fig. 11C The process between the processes described. FIG. 12A to FIG. 12D A portion of the display panel formed by the method shown may correspond to Figure 6 part of the display panel.

[0223] In an embodiment, and with reference to Fig. 12A The display panel manufacturing method may include the step of forming a light emitting contact hole OP-CH by etching the preliminary conductive partition wall PW-I, the insulating layer IL, and the common electrode BE. The step of forming the light emitting contact hole OP-CH may be performed using a photoresist layer.

[0224] In an embodiment, the preliminary conductive partition wall PW-I, the common electrode BE, and the insulating layer IL may be etched using a photoresist layer as a mask. The etched portions of the preliminary conductive partition wall PW-I, the common electrode BE, and the insulating layer IL may be removed, and a light emitting contact hole OP-CH may be formed in the preliminary conductive partition wall PW-I, the common electrode BE, and the insulating layer IL.

[0225] In an embodiment, and with reference to Fig. 12B In the display panel manufacturing method, a preliminary partition wall insulating layer IP-I and a first electrode AE ​​(reference Fig. 11C ) and the preliminary pixel definition layer PDL-I (reference Fig. 11C ) may include the step of forming a preliminary partition wall insulating layer IP-I covering the inner surface of the light emitting contact hole OP-CH.

[0226] In an embodiment, the preliminary partition wall insulating layer IP-I may be formed to cover the upper surface of the second preliminary partition wall layer L2-I, the side surface of the second preliminary partition wall layer L2-I, the side surface of the first preliminary partition wall layer L1-I, the side surface of the common electrode BE, the side surface of the insulating layer IL, and the upper surface of the circuit element layer DP-CL. The side surface of the second preliminary partition wall layer L2-I, the side surface of the first preliminary partition wall layer L1-I, the side surface of the common electrode BE, and the side surface of the insulating layer IL may define the inner surface of the light emitting contact hole OP-CH. That is, the preliminary partition wall insulating layer IP-I may be formed to cover the inner surface of the light emitting contact hole OP-CH.

[0227] In an embodiment, and with reference to Fig. 12C , the display panel manufacturing method may include etching the preliminary partition wall insulating layer IP-I (reference Fig. 12B The step of forming a partition wall insulating layer opening OP-IP by etching a portion of the preliminary partition wall insulating layer IP-I. A portion of the upper surface of the circuit element layer DP-CL that covers the preliminary partition wall insulating layer IP-I may be etched and removed. The partition wall insulating layer opening OP-IP may be formed by etching a portion of the preliminary partition wall insulating layer IP-I and removing the etched portion thereof, and the partition wall insulating layer IP may be formed from the preliminary partition wall insulating layer IP-I. A portion of the upper surface of the circuit element layer DP-CL may be exposed through the partition wall insulating layer opening OP-IP.

[0228] In an embodiment, and with reference to Figure 6 and Fig.12D , the display panel manufacturing method may include the step of forming an anode electrode AE ​​and a pixel defining layer PDL on the partition wall insulating layer IP.

[0229] In an embodiment, the anode AE ​​may be formed to overlap with the light emitting contact hole OP-CH. The anode AE ​​may be formed in the light emitting contact hole OP-CH. The anode AE ​​may contact the circuit element layer DP-CL through the light emitting contact hole OP-CH. In an embodiment, the anode AE ​​may contact the contact hole CNT-3 not covered by the partition wall insulating layer IP, and may be connected to the second connection electrode CNE2. Therefore, the anode AE ​​may be electrically connected to the signal transmission region SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and may be electrically connected to the corresponding circuit element (e.g., the transistor TR1).

[0230] In an embodiment, since the light emitting element is formed on the conductive partition wall instead of in the partition wall opening of the conductive partition wall as described above, the occurrence of a shadow area can be prevented during the deposition process. Therefore, the present invention can provide a display panel that helps achieve high resolution.

[0231] In an embodiment, since the lower inorganic encapsulation pattern covering the light emitting element formed on the conductive partition wall is more stable and firm, and the light emitting element is not disposed in the partition wall opening, the thickness of the conductive partition wall may be reduced.

[0232] Although the present invention has been described with reference to embodiments of the present invention, it is apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present invention. Therefore, the present invention should not be limited to any single embodiment or other embodiments described herein. In addition, embodiments or parts of embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. Display panel, including: Base layer; A transistor, disposed on the base layer; A common electrode, disposed on the transistor; A conductive partition wall is disposed on the common electrode, wherein a partition wall opening is defined in the conductive partition wall; A partition wall insulating layer, disposed on the conductive partition wall; as well as A light emitting element is disposed on the partition wall insulating layer, the light emitting element comprising a first electrode electrically connected to the transistor, an emission pattern disposed on the first electrode, and a second electrode disposed on the emission pattern and electrically connected to the conductive partition wall.

2. The display panel according to claim 1, wherein: The conductive partition wall comprises: A first partition wall layer is disposed on the common electrode; and a second partition wall layer, disposed on the first partition wall layer, Wherein, the partition wall opening comprises: a first region defined by the first partition wall layer; and a second region defined by the second partition wall layer and formed integrally with the first region, and The first region has a greater length in the first direction than the second region.

3. The display panel according to claim 2, further comprising: A pixel defining layer is disposed on the partition wall insulating layer, and has a light emitting opening configured to expose at least a portion of the first electrode.

4. The display panel according to claim 3, wherein: The light emitting opening does not overlap with the partition wall opening.

5. The display panel according to claim 2, wherein: The emission pattern covers a side surface of the second partition wall layer, and the second electrode covers an upper surface of the emission pattern and at least a portion of a side surface of the emission pattern.

6. The display panel according to claim 2, further comprising: The auxiliary electrode is configured to cover the second electrode and the lower surface of the second partition wall layer and to be in direct contact with the lower surface of the second partition wall layer.

7. The display panel according to claim 6, wherein: The auxiliary electrode contacts a side surface of the first partition wall layer.

8. The display panel according to claim 6, further comprising: The dummy auxiliary electrode is spaced apart from the auxiliary electrode and is disposed to contact a side surface of the first partition wall layer.

9. The display panel according to claim 6, further comprising: The lower inorganic encapsulation pattern is configured to cover an upper surface of the auxiliary electrode, wherein the lower inorganic encapsulation pattern is spaced apart from the common electrode.

10. The display panel according to claim 1, further comprising: A light emitting contact hole is arranged to pass through the conductive partition wall and the common electrode, and when viewed from above a plane, the light emitting contact hole overlaps with the first electrode.

11. The display panel according to claim 10, wherein: The first electrode includes a circular portion and a protruding portion configured to extend from one side of the circular portion, wherein the light emitting contact hole overlaps the protruding portion when viewed from above the plane.

12. The display panel according to claim 10, wherein: The first electrode includes a circular portion, wherein the light emitting contact hole overlaps with a center of the circular portion when viewed from above the plane.

13. The display panel according to claim 1, wherein: The first electrode is disposed between the second electrode and the common electrode.

14. Display panel, comprising: Base layer; A conductive partition wall is disposed on the base layer, wherein a partition wall opening is defined in the conductive partition wall; A partition wall insulating layer, disposed on the conductive partition wall; as well as a light emitting element including a first electrode disposed on the partition wall insulating layer, an emission pattern configured to cover the first electrode and the partition wall insulating layer, and a second electrode configured to cover the emission pattern and be electrically connected to the conductive partition wall, Wherein, when viewed from above a plane, the partition wall opening and the first electrode are spaced apart from each other.

15. The display panel according to claim 14, wherein: The first electrode overlaps a center of the conductive partition wall.

16. A method for manufacturing a display panel, the method comprising: forming a circuit element layer and a common electrode on the base layer, wherein the circuit element layer includes a transistor; forming a preliminary conductive partition wall on the common electrode; forming a preliminary partition wall insulating layer, a first electrode, and a preliminary pixel defining layer configured to cover the first electrode on the preliminary conductive partition wall; forming a light emitting opening configured to overlap with the first electrode by etching the preliminary pixel defining layer; forming a conductive partition wall, a partition wall insulating layer and a pixel defining layer by etching the preliminary conductive partition wall, the preliminary partition wall insulating layer and the preliminary pixel defining layer, wherein the conductive partition wall defines a partition wall opening; forming an emission pattern configured to cover the first electrode on the conductive partition wall; and forming a second electrode electrically connected to the conductive partition wall on the emission pattern, Wherein, when viewed from above in a plane, the light emitting opening and the partition wall opening do not overlap with each other.

17. The method according to claim 16, wherein: The preliminary conductive partition wall comprises: a first preliminary partition wall layer, disposed on the common electrode; and a second preliminary partition wall layer disposed on the first preliminary partition wall layer, and Wherein, forming the conductive partition wall, the partition wall insulating layer and the pixel defining layer comprises: preliminarily etching the preliminary conductive partition wall, the preliminary partition wall insulating layer, and the preliminary pixel defining layer; and A first partition wall layer and a second partition wall layer are formed by second-etching the first preliminary partition wall layer.

18. The method according to claim 17, further comprising: An auxiliary electrode configured to cover lower surfaces of the second electrode and the second partition wall layer is formed.

19. The method according to claim 18, wherein: The auxiliary electrode contacts a side surface of the first partition wall layer.

20. The method of claim 18, further comprising: forming a lower inorganic encapsulation pattern configured to cover the upper surface of the auxiliary electrode, Wherein, the lower inorganic encapsulation pattern is spaced apart from the common electrode.

21. The method of claim 16, further comprising: forming a light emitting contact hole by etching the preliminary conductive partition wall and the common electrode, The first electrode and the transistor are electrically connected to each other through the light emitting contact hole.

22. The method according to claim 21, wherein: Forming the preliminary partition wall insulating layer, the first electrode, and the preliminary pixel defining layer configured to cover the first electrode on the preliminary conductive partition wall includes: The preliminary partition wall insulating layer configured to cover the inner surface of the light emitting contact hole is formed.

Images