Multi-bit accumulator and in-memory computing processor with multi-bit accumulator

Abstract

A multi-bit accumulator includes: a plurality of 1-bit Wallace trees, each configured to perform an addition operation on single-bit input data; a plurality of three-state logic circuits each configured to output a result of an addition operation of the plurality of 1-bit Wallace trees according to an enable signal provided to the plurality of three-state logic circuits; and a shift adder configured to perform an accumulation operation on a result of the addition operation of the plurality of 1-bit Wallace trees by a shift operation based on a clock signal.

Description

Technical Field

[0001] The following description relates to a multi-bit accumulator, an in-memory computation (IMC) processor including the multi-bit accumulator, and a method of operating the multi-bit accumulator. Background Art

[0002] Deep neural networks (DNNs) are widely used, leading to an industrial revolution based on artificial intelligence (AI). Convolutional neural networks (CNNs), a type of DNN, are widely used in various applications such as image and signal processing. CNNs can perform object recognition, computer vision, etc. In some examples, implementations of CNNs may include repeatedly performing multiply-accumulate (or multiply-add) (MAC) operations on a large number of matrices.

[0003] For example, when a CNN is executed by a general-purpose processor, operations that require a lot of computation but are not complex can be performed by in-memory computation rather than by a general-purpose processor. For example, a MAC operation involving computing the dot product of two vectors and accumulating the resulting values ​​can be performed by in-memory computation (IMC), which is a type of memory device that performs computations on what is stored in memory without having to move data in and out of the memory device just to perform the computation. Summary of the invention

[0004] Solution to the problem

[0005] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0006] In one general aspect, a multi-bit accumulator includes: a plurality of 1-bit Wallace trees, each configured to perform an addition operation on a single-bit input data; a plurality of tri-state logic circuits, each configured to output a result of the addition operation of the plurality of 1-bit Wallace trees according to an enable signal provided to the plurality of tri-state logic circuits; and a shift adder configured to perform an accumulation operation on the results of the addition operation of the plurality of 1-bit Wallace trees through a shift operation based on a clock signal.

[0007] Each of the plurality of 1-bit Wallace trees may include an adder array including a full adder used in a final operation stage among operation stages of an addition operation. Each adder array may include: a first type full adder in which a tri-state logic circuit is connected to an addition operation result of an addition operation between single-bit input data; and a second type full adder in which a tri-state logic circuit is connected to each of an addition operation result corresponding to an operation result of the final operation stage and a carry operation result generated in response to the addition operation result.

[0008] Each of the plurality of tri-state logic circuits may be configured to: output a high impedance state in response to an enable signal having a first logic value; and output a result of the addition operation of the plurality of 1-bit Wallace trees to a shift adder in response to the enable signal having a second logic value, the second logic value being opposite to the first logic value (inversion of the first logic value).

[0009] The multi-bit accumulator may further include: a logic gate configured to perform a logic operation between the signed data and a most significant bit (MSB) in a result of the accumulation operation of the shift adder in response to the multi-bit accumulator performing a signed operation on the signed data.

[0010] The logic gate may include an XOR gate configured to perform an XOR operation between the MSB and the signed data.

[0011] The multi-bit accumulator may further include: a signal generator configured to generate an enable signal that enables the tri-state logic circuit by inverting the clock signal.

[0012] The plurality of 1-bit Wallace trees may be configured to operate in response to an enable signal having a first logic value, and the shift adder may be configured to operate in response to the enable signal having a second logic value opposite to (inverted from) the first logic value.

[0013] The multi-bit accumulator may further include: a plurality of registers configured to store output values ​​of the plurality of 1-bit Wallace trees respectively according to a clock signal to provide a pipeline operation between the plurality of 1-bit Wallace trees and the shift adder by sending the stored output values ​​to the shift adder.

[0014] The plurality of registers may be implemented by parasitic capacitances generated by the plurality of tri-state logic circuits.

[0015] The multi-bit accumulator may further include a multiplier, and the step of transmitting may enable the plurality of 1-bit Wallace trees to perform addition operations concurrently with multiplication operations of the multiplier.

[0016] In another general aspect, an in-memory computing (IMC) processor includes: an IMC device including IMC macros, each IMC macro including a column in a crossbar switch structure; an input controller configured to sequentially input a multi-bit first value to the IMC device bit by bit; and a post-operation circuit configured to output a multi-bit operation result integrating the operation results of each IMC macro. Each of the IMC macros may include: a memory array including bit cells, each bit cell configured to store a second value applied to each of the first values; a binary gate array including operation gates, each operation gate configured to perform a single-bit multiply-accumulate (MAC) operation between the first value and the second value; and a multi-bit accumulator configured to perform a bit-by-bit operation on a result of the single-bit MAC operation through a shift operation based on a clock signal, and perform an accumulation operation on the result of the bit-by-bit operation corresponding to any one of the columns.

[0017] The multi-bit accumulator may include: a plurality of 1-bit Wallace trees, each configured to perform a bitwise operation on a result of a single-bit MAC operation; a plurality of tri-state logic circuits, each configured to output a result of the bitwise operation of a corresponding 1-bit Wallace tree among the plurality of 1-bit Wallace trees according to an enable signal; and a shift adder configured to perform an accumulation operation on a result of the addition operation of a 1-bit Wallace tree corresponding to any one of the columns among the plurality of 1-bit Wallace trees through a shift operation based on a clock signal.

[0018] Each of the plurality of 1-bit Wallace trees may include: an adder array including a full adder used in a final operation stage among operation stages of an addition operation. The adder array may include: a first type full adder in which a tri-state logic circuit is connected to a result of a single-bit MAC operation; and a second type full adder in which a tri-state logic circuit is connected to each of an addition operation result corresponding to an operation result of the final operation stage and a carry operation result generated in response to the addition operation result.

[0019] The multiple tri-state logic circuits can be configured to: output a high impedance state in response to an enable signal having a first logic value; and output the results of the bitwise operation of the multiple 1-bit Wallace trees to a shift adder in response to the enable signal having a second logic value, the second logic value being opposite to the first logic value (the inversion of the first logic value).

[0020] The IMC processor may further include: a logic gate configured to perform a sign operation on the signed data based on the multi-bit accumulator, and to perform a logic operation between the signed data and a MSB in a result of the accumulation operation of the shift adder.

[0021] The logic gate may include an XOR gate configured to perform an XOR operation between the MSB and the signed data.

[0022] The IMC processor may further include a signal generator configured to generate an enable signal for enabling the plurality of tri-state logic circuits by inverting a clock signal.

[0023] The plurality of 1-bit Wallace trees may be configured to operate in response to an enable signal having a first logic value, and the shift adder may be configured to operate in response to the enable signal having a second logic value opposite to (inverted from) the first logic value.

[0024] The IMC processor may be integrated into at least one of a mobile device, a mobile computing device, a mobile phone, a smart phone, a personal digital assistant (PDA), a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, a music player, a video player, an entertainment unit, a navigation device, a communication device, a global positioning system (GPS) device, a television (TV), a tuner, a vehicle, a vehicle component, an avionics system, a drone, a multirotor aircraft, or a medical device.

[0025] On the other hand, a method of operating a multi-bit accumulator includes: receiving single-bit input data; performing an addition operation in 1-bit units on the input data; outputting a result of the addition operation in 1-bit units based on an enable signal; and outputting a result of the multi-bit operation corresponding to the input data by shifting and accumulating the result of the addition operation in 1-bit units.

[0026] The step of outputting the result of the addition operation in 1-bit units may include: outputting a high impedance state in response to an enable signal having a first logic value; and outputting the result of the addition operation of the 1-bit Wallace tree to the shift adder in response to the enable signal having a second logic value, the second logic value being opposite to the first logic value.

[0027] The method may further include, in response to the multi-bit accumulator performing the signed operation on the signed data, performing a logic operation between the signed data and a MSB in a result of the multi-bit operation.

[0028] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 An example multi-bit accumulator is shown according to one or more example embodiments.

[0030] Figure 2a and Figure 2b An example of a multi-bit accumulator in an in-memory computing (IMC) device is shown according to one or more example embodiments.

[0031] Figure 3a An example structure of a multi-bit accumulator and an example operation of a 1-bit Wallace tree included in the multi-bit accumulator according to one or more example embodiments are illustrated.

[0032] Figure 3b An example of switching occurring in a 1-bit Wallace tree according to one or more example embodiments is shown.

[0033] Figure 3c Example timing for a multi-bit accumulator according to one or more example embodiments is shown.

[0034] Figure 4 An example operation of a tri-state logic circuit according to one or more example embodiments is shown.

[0035] Figure 5 An example structure of a multi-bit accumulator configured to perform signed operations according to one or more example embodiments is shown.

[0036] Figure 6 An example structure of a multi-bit accumulator including an adder array according to one or more example embodiments is shown.

[0037] Figure 7 Example circuits of adder arrays according to one or more example embodiments are shown.

[0038] Figure 8 Example circuits of first type full adders and second type full adders included in an adder array according to one or more example embodiments are shown.

[0039] Figure 9a An example pipeline operation of a multi-bit accumulator to which a tri-state logic circuit is applied according to one or more example embodiments is shown.

[0040] Figure 9b An example of generating parasitic capacitance in a multi-bit accumulator according to one or more example embodiments is illustrated.

[0041] Fig.10a An example of performing a row addition operation by a Wallace tree and a shift-add operation by a shift adder through a pipeline in a multi-bit accumulator according to one or more example embodiments is shown.

[0042] Fig.10b Example clock control operations performed when a multi-bit accumulator operates in a switching prevention mode and a pipeline mode according to one or more example embodiments are shown.

[0043] Fig.11 An example method of operating a multi-bit accumulator according to one or more example embodiments is shown.

[0044] Fig.12 An example relationship between operations performed in an IMC macro and a neural network according to one or more example embodiments is shown.

[0045] Fig.13 An example IMC processor including a multi-bit accumulator is shown according to one or more example embodiments.

[0046] Fig.14 An example structure of an IMC processor according to one or more example embodiments is shown.

[0047] Fig.15 An example electronic system including an IMC processor according to one or more example embodiments is shown.

[0048] Throughout the drawings and detailed description, unless otherwise described or provided, the same or similar reference numerals in the drawings may be understood to represent the same or similar elements, features and structures. The drawings may not be drawn to scale, and the relative sizes, proportions and depictions of the elements in the drawings may be exaggerated for clarity, illustration and convenience. DETAILED DESCRIPTION

[0049] The following detailed description is provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the method, device and / or system described herein will be clear. For example, the order of operations described herein is only an example, and is not limited to the order of those operations set forth herein, but can be changed as will be clear after understanding the disclosure of the present application, except for the operations that must occur in a specific order. In addition, for greater clarity and simplicity, the description of features known after understanding the disclosure of the present application may be omitted.

[0050] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein have been provided to illustrate only some of the many possible ways to implement the methods, devices, and / or systems described herein that will be apparent after understanding the disclosure of the present application.

[0051] The terms used herein are only used to describe various examples and are not used to limit the disclosure. Unless the context clearly indicates otherwise, the singular is intended to also include the plural form. As used herein, the term "and / or" includes any one of the relevant listed items and any combination of any two or more. As non-limiting examples, the terms "comprise", "include" and "have" indicate the presence of stated features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.

[0052] Throughout the specification, when a component or element is described as being "connected to," "coupled to," or "engaged to" another component or element, the component or element may be directly "connected to," "coupled to," or "engaged to" the other component or element, or one or more other components or elements may reasonably be present in between. When a component or element is described as being "directly connected to," "directly coupled to," or "directly engaged to" another component or element, there may not be other elements in between. Similarly, expressions such as "between" and "immediately between," and "adjacent to" and "immediately adjacent to" may also be interpreted as described above.

[0053] Although terms such as "first", "second" and "third" or A, B, (a), (b), etc. may be used herein to describe various components, components, regions, layers or parts, these components, components, regions, layers or parts are not limited by these terms. Each of these terms is not used to define, for example, the essence, order or sequence of the corresponding component, component, region, layer or part, but is only used to distinguish the corresponding component, component, region, layer or part from other components, components, regions, layers or parts. Therefore, without departing from the teachings of the examples, the first component, first component, first region, first layer or first part referred to in the examples described herein may also be referred to as the second component, second component, second region, second layer or second part.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs and based on the understanding of the disclosure of the present application. Unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and the disclosure of the present application, and should not be interpreted in an idealized or overly formalized meaning. The use of the term "may" with respect to an example or embodiment herein (e.g., with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment that includes or implements such a feature, and all examples are not limited thereto.

[0055] Figure 1 An example multi-bit accumulator is shown according to one or more example embodiments. Figure 1 The multi-bit accumulator 100 according to example embodiments may include a 1-bit Wallace tree 110, a tri-state logic circuit 130, and a shift adder 150. The multi-bit accumulator 100 may further include a signal generator 170.

[0056] The 1-bit Wallace tree 110 may perform an addition operation on input data including a single bit (e.g., single-bit input data). A single bit may represent 1 bit. Hereinafter, the terms "single bit" and "1 bit" may be understood to have the same meaning. For example, a single-bit of data transmitted as an input to an IMC device via a bitstream.

[0057] Reference Figure 3a to Figure 3c A method of operating the 1-bit Wallace tree 110 is described.

[0058] Reference Figure 3b and Figure 3c The structure and operation timing of the multi-bit accumulator 100 are described.

[0059] The tri-state logic circuit 130 may output the result of the addition operation of the 1-bit Wallace tree 110 (or, as used herein, the “addition operation result”) according to the enable (EN) signal generated by the signal generator 170. The tri-state logic circuit 130 may be, for example, a tri-state buffer, or a switching device that operates in three states similar to a tri-state buffer. The output of the tri-state logic circuit may depend on the enable signal EN supplied to the tri-state logic circuit. For example, when the enable signal EN supplied to the tri-state logic circuit 130 has a first logic value (e.g., a zero (0) value), the tri-state logic circuit 130 may output a high impedance state. The phrase “high impedance state” refers to a state in which a relatively small amount of current passes through per unit of voltage applied to a point in the circuit. The numerical definition of “high impedance” may vary depending on the application. In contrast, when the enable signal EN has a second logic value (e.g., a one (1) value), the tri-state logic circuit 130 may output the result of the addition operation of the 1-bit Wallace tree 110 to the shift adder 150. Reference Figure 4 A method of operating one or more tri-state logic circuits 130 is described.

[0060] In the multi-bit accumulator 100, when the enable signal EN has a first logic value (eg, 0), the 1-bit Wallace tree 110 may have an operational effect. However, when the enable signal EN has a second logic value (eg, 1), the shift adder 150 may have an operational effect.

[0061] The shift adder 150 may perform an accumulation operation on the addition operation result of the 1-bit Wallace tree 110. Specifically, the shift adder 150 may perform a shift operation based on a clock (CLK) signal. Figure 3c Describe the relationship between the clock signal CLK and the enable signal EN.

[0062] For example, in the case where the multi-bit accumulator 100 performs a signed operation on signed data, the multi-bit accumulator 100 may further include a logic gate that performs a logic operation between: (i) the signed data and (ii) the most significant bit (MSB) of the result of the accumulation operation (or, herein, the “accumulation operation result”) of the shift adder 150. The logic gate may include, for example, an exclusive OR (XOR) gate that performs an XOR operation (or, a multiplication operation) between the signed data and the MSB of the accumulation operation result of the shift adder 150.

[0063] Reference Figure 5 and Figure 6 The structure and operation of a multi-bit accumulator 100 that performs signed operations on signed data is described.

[0064] The 1-bit Wallace tree 110 may include an adder array (e.g., Figure 6 The adder array 630 may include full adders used in multiple operation stages for addition operations. The adders of the adder array may include, for example, a first type full adder and a second type full adder. For the first type full adder (e.g., Figure 8 Full adder 710), tri-state logic circuit (e.g., Figure 8 The tri-state logic circuit 813 of the second type is connected to the addition operation result (sum S) between multiple "single bit (or, 1 bit) input data". Figure 8 Full adder 730), tri-state logic circuit (e.g., Figure 8 The tri-state logic circuit 833 and the tri-state logic circuit 835 are connected to (i) the addition operation result (sum S) corresponding to the operation result of the final operation stage among the multiple operation stages and (ii) the result of the carry operation generated according to the addition operation (or, in this case, the carry operation result C). Figure 7 and Figure 8 Describe the structure and circuitry of an adder array.

[0065] The signal generator 170 may generate an enable signal EN that enables the tri-state logic circuit 130 by inverting the clock signal CLK.

[0066] Figure 2a and Figure 2b An example use of a multi-bit accumulator in an in-memory computing (IMC) device is shown according to one or more example embodiments.

[0067] Figure 2a An example case is shown in which a multi-bit accumulator is used as the adder 230 of the IMC device 200. The IMC device 200 may be, for example, a digital IMC device, but is not limited thereto.

[0068] The digital IMC device 200 may include a memory unit 210 , a multiplier unit 220 , and an adder 230 .

[0069] Memory cell 210 may include a static random access memory (SRAM) bit cell that stores, for example, a weight value W (although weights and other neural network data are mentioned herein, such data is merely an example and other types of data may be used). Memory cell 210 may be configured as a 6-transistor (T) SRAM, an 8T SRAM, and a 12T SRAM, but is not limited thereto.

[0070] The multiplier unit 220 may perform a multiplication operation between (i) the input data 205 sequentially applied bit by bit through the input driver 207 and (ii) the weight value stored in the memory unit 210. The input data 205 may be sequentially input bit by bit according to a time order from the least significant bit (LSB) to the MSB of the input data 205. The multiplier unit 220 may output the result of the multiplication operation (also referred to as a "multiplication operation result") between the 1-bit input value and the weight value stored in the memory unit 210 to the adder 230. The adder 230 may perform an addition operation on the multiplication operation results received from the multiplier unit column 220. For example, the adder 230 may perform the addition operation using a full adder and / or a half adder. The multiplication operation results output from the adder 230 may be finally accumulated and output through the accumulator and the output register 240.

[0071] The multi-bit accumulator according to example embodiments may perform the operation of the adder 230 or perform the operation of the adder 230 and the accumulator and output register 240 .

[0072] Figure 2b An example multiply-accumulate (MAC) operation method is shown that is performed when, for example, 64 4-bit input data 205 are applied bit by bit to the multiplier unit 220 and a 4-bit weight is stored in the memory unit 210 in the multiplier unit 220 .

[0073] 64 input data 205 may be sequentially input to the multiplier unit 220 bit by bit according to the time sequence. In this case, the multiplier unit 220 may include 64 memory units 210. When the 64 input data 205 are sequentially input bit by bit, a multiplication operation between 1 bit of input data and 4 bits of weight may be performed for each multiplier unit 220. Therefore, a 4-bit multiplication operation result may be output for each multiplier unit 220. The adder 230 may combine the 4-bit multiplication operation results output from the multiplier unit 220 to perform an addition operation thereon. The addition operation result of the adder 230 may be accumulated and output bit by bit in the accumulator and output register 240.

[0074] In this case, the adder 230 may be in the form of a 4-bit adder including four full adders of 64 columns. In addition, a sign bit for representing a negative value or number in actual operation may be further used, and therefore a full adder for signed data operation of a negative value or number added to the adder 230 may be considered, and therefore a total of 372 full adders may be used. In addition, a ripple carry adder may be used but may generate a maximum delay of 16 full adders, which is the slowest form for a small area.

[0075] Figure 3a An example structure of a multi-bit accumulator according to one or more example embodiments is shown. Figure 3a The structure of the multi-bit accumulator 300 is shown.

[0076] The multi-bit accumulator 300 may include, for example, a plurality of IMC macros (eg, Fig.13 1-bit Wallace tree 307 in a plurality of IMC macros 1330-1), each IMC macro comprising a plurality of columns in a crossbar switch structure. In this case, the plurality of IMC macros (each IMC macro comprising a plurality of columns in a crossbar switch structure) may perform, for example, vector-matrix multiplication operations and generally perform MAC operations. For example, each of the columns may include P bit cells B 1 To B P , and the MAC operation may be performed by P bit cells of each column. For example, a multiplication operation may be performed in units of each bit cell together with the input, and an accumulation operation may be performed in units of columns. The 1-bit Wallace trees 307 may each correspond to a corresponding column.

[0077] In the IMC macro, operations on multi-bit input data and weights may be performed, for example, in the following manner: an H-bit weight and a 1-bit input data may be multiplied, and then an H-bit S corresponding to the multiplication result may be added to the multi-bit accumulator 300. N [H:1] is added. This operation can be repeated H times by changing the bit position of the input data, and then the MAC operation on the H-bit input data and the H-bit weight can be completed.

[0078] For example, when the multi-bit accumulator 300 performs an addition operation on a 4-bit multiplication result of an H-bit weight and 1-bit input data, the 4-bit input data may be input to the multi-bit accumulator 300 .

[0079] In addition, the signed operation of signed data can use sign extension to process the signed data, which can cause one more full adder to be used for the signed operation due to adding 1 bit in each stage to handle overflow. The term "sign extension" means an operation that increases the number of bits of a binary number while maintaining the sign and value of the number represented by the binary number during the operation. For example, when extending a signed number (such as a negative number or a negative value), sign extension can be used, and the sign extension can be performed by including the MSB value in the extension bit. In the case where the additional full adder is used for sign extension, the multiple full adders used can occupy a large area, which can also increase the area of ​​the IMC macro. Therefore, in one example, the multi-bit accumulator 300 based on the 1-bit Wallace tree can improve the area efficiency of the adder tree in the IMC macro.

[0080] Since each 1-bit Wallace tree 307 can apply input data to the carry input of the full adder, a small number of full adders can be used to perform accumulation operations on a large number of input data.

[0081] The 1-bit Wallace tree 307 circuit can be configured to facilitate operations on any number of bits by combining a set of full adders. Figure 3a The symbols shown in Represents a full adder.

[0082] The 1-bit Wallace tree 307 can configure each bit with a full adder and use the second digit of the previous digit of the full adder as the carry digit of the next digit (i.e., as the carry). This may correspond to the same operation as performing calculations for each digit and rounding up each digit during addition. The 1-bit Wallace tree 307 can achieve high-speed operations by performing partial summation between operands and reducing the number of stages. The 1-bit Wallace tree 307 can perform addition operations by combining three input data, each of which is used for partial summation between operands. When the number of input data is less than 3, the 1-bit Wallace tree 307 can transmit multiple input data to the next stage so as to perform partial summation at the next stage. For example, when two of "sum S" and "carry C" are left in the result of the partial sum, the 1-bit Wallace tree 307 can, for example, cause the addition operation of the final operation stage to be performed by a carry propagation adder (CPA) 370, which operates in a manner similar to a bitwise carry adder.

[0083] In the second operation stage, the 1-bit Wallace tree 307 can calculate a single-bit binary number including a lower carry input (e.g., carry input (Ci)). The 1-bit Wallace tree 307 can add a total of three bits including a 1-bit carry input Ci and two 1-bit operands, and output a sum S and a carry output Co. The 1-bit Wallace tree 307 can perform calculations including a lower carry, and thus can perform n-bit binary addition.

[0084] The logic formula of the 1-bit Wallace tree 307 can be expressed as Equation 1 below.

[0085] Equation 1

[0086]

[0087] In Equation 1, A and B represent 2-bit operands, and Ci represents a carry-in, Co represents a carry-out, and Sum represents a binary addition result.

[0088] For example, when Figure 3a When performing a sum operation on 15 operands as shown in FIG, the carry output Cout and the final addition result Sum can be output through five operation stages (stages 0 to 4). The term "operation stage" or "stage" used herein means an operation stage performed by one full adder.

[0089] However, the 1-bit Wallace tree 307 may have a different logic depth for each input data, and unnecessary output switching may occur as described above. Figure 3b Output switching that occurs in a 1-bit Wallace tree 307 is described.

[0090] In one example, to prevent such unnecessary switching, in the adder array, the full adder generating the final output of the Wallace tree (i.e., the operation result of the final operation stage) may connect the tri-state logic circuit 130 to the addition operation result (Sum) and the carry output (Carry out). The multi-bit accumulator 300 may prevent unnecessary output switching by enabling the tri-state logic circuit 130 to output the operation result or the high impedance state according to the enable signal EN 340.

[0091] The multi-bit accumulator 300 may correspond to, for example, an adder tree, but is not limited thereto.

[0092] The multi-bit accumulator 300 may include a 1-bit Wallace tree 110 for first performing an operation on P 1-bit input data X 1 To X P In this case, the tri-state logic circuit 130 that outputs the addition operation result of the 1-bit Wallace tree 110 according to the enable signal EN 340 may be added to the adder of the final operation stage of the Wallace tree 110 .

[0093] The shift adder 150 may output Y 350, which is the result of performing a shift operation and an addition operation on the output of the tri-state logic circuit 130. The shift adder 150 may include, for example, a full adder 310, a full adder 320, and a full adder 330. The full adder 310 performs a first addition operation on the output of the tri-state logic circuit 130 connected to two 1-bit Wallace trees corresponding to the first column and the second column among a total of four 1-bit Wallace trees 110. The full adder 320 performs a second addition operation on the output of the tri-state logic circuit 130 connected to two 1-bit Wallace trees corresponding to the third column and the fourth column. And the full adder 330 performs an addition operation of the first addition operation and the second addition operation. The operation result of the full adder 310 and the operation result of the full adder 320 may each have a logarithm. 2 P+2 bits, and the operation result Y 350 of the full adder 330 may have log 2 P+H position.

[0094] In this case, the shift operation on the output of the tri-state logic circuit 130 may be performed by the full adder 310 and the full adder 330. For example, it is assumed that an addition operation is performed between A (4 bits) of the full adder 310 and B (4 bits) of the full adder 330. In this case, when the shift operation is not performed, when A3 (MSB of A), A2, A1, and A0 (LSB of A) are added with B3 (MSB of B), B2, B1, and B0 (LSB of B), A0 may be first added with B0, and the carry generated at this time may be added together with A1 and B1 when A1 and B1 are added. The addition operation process when the shift operation is not performed may be symbolically represented as follows:

[0095] (A0+B0): generated by summing S0 and carrying C0

[0096] (A1+B1)+C0: S1, C1 generated

[0097] (A2+B2)+C1: S2, C2 generated

[0098] (A3+B3)+C2: S3 generated

[0099] In contrast, the addition process when performing a shift operation (e.g., where A is shifted by 1 bit relative to B) can be represented symbolically as follows:

[0100] B0:S0 generation

[0101] (A0+B1): S1, C1 generated

[0102] (A2+B2)+C1: S2, C2 generated

[0103] (A1+B3)+C2: S3, C3 generated

[0104] (A2)+C3: S4 generated

[0105] In summary, the multi-bit accumulator 300 can be Figure 3a The structure shown in performs an accumulation operation on multi-bit input data.

[0106] Figure 3b An example of switching occurring in a 1-bit Wallace tree according to one or more example embodiments is shown. Figure 3b Shown from R 1 To R 15 An example 380 of the operation of a 1-bit Wallace tree 307 performing an addition operation on 15 operands.

[0107] The 1-bit Wallace tree 307 can use a small number of full adders to implement the adder. However, path delays may occur, and the delays may vary depending on the input data. For example, from X 1 To X 15 Data "1, 1, 0, 1, 1, 0, 0, 0, 1, 1, 1, 0, 1, 0" on 15 operands of may be input in phase 0. The plurality of input data may be applied to four full adders, each of which includes three inputs, and may be applied to X 4 , X 8 and X 12 In this case, X 4 Data "1", X 8 The data "0" and X 12 The data "0" can be calculated together with the addition operation in four full adders in period 1.

[0108] In period 0, the 1-bit Wallace tree 307 can be connected to X 8 The path sequence output is "0000".

[0109] In period 1, X 4 Data "1", X 8 The data "0" and X 12 The data "0" of can be calculated (eg, added) together with the carry C and the addition result (or, sum) S generated in the four full adders receiving the three input data in period 0. Therefore, the X that is "0" in period 0 4 The addition result S can be changed to "1", and X which is "0" in period 0 12 The addition result S can be changed to "1". The 1-bit Wallace tree 307 can output "0001"

[0110] In period 2, the carry C and the addition result S generated in period 1 may be transmitted to the three full adders and calculated therein (eg, addition operation). 8 The carry bit of may become "0" again in period 2, and the 1-bit Wallace tree 307 may output "0000".

[0111] In period 3 , the carry C and the addition result S generated in period 2 may be transferred to a full adder and calculated therein (eg, addition operation). Therefore, the 1-bit Wallace tree 307 may output “0100” in period 3 .

[0112] In period 4 , the carry C and the addition result S generated in period 3 may be transferred to a full adder and calculated therein (eg, addition operation). Therefore, the 1-bit Wallace tree 307 may output “0100” in period 4 .

[0113] As mentioned above, X 4 The data "1" can be output as carry C and final addition result S through the four full adders in period 0 to period 4. In addition, X 8 The data "0" can be output as a carry C and a final addition result S through three full adders. In this case, when the 1-bit Wallace tree 307 is used, there may be a switching in which the output is changed, for example, "0000" → "0001" → "0000" → "0100" → "1000", and each time a new input is applied, the path delay varies according to the input path. That is, although the output data "1000" can be output in response to the input data "0000" in the same manner, a switching in which the output value is changed in the middle of the process may occur.

[0114] The same switching phenomenon may occur in the output of the shift adder that performs the accumulation operation on the addition operation result of the 1-bit Wallace tree due to the switching occurring in the output of the 1-bit Wallace tree 307. The switching phenomenon may increase the amount of calculation (or, operation amount) and thus may increase power consumption.

[0115] However, in some examples, such as reference Figure 4 As described, the use of a tri-state buffer can prevent the occurrence of a switching phenomenon that may be caused by a path delay that varies for each input path when using a 1-bit Wallace tree 307 .

[0116] Figure 3c Example timing for a multi-bit accumulator according to one or more example embodiments is shown. Figure 3c The timing between the clock signal CLK 301, the signal IN 305, the enable signal EN 340 and the output Y 350 of the multi-bit accumulator 300 is shown.

[0117] The clock signal CLK 301 may correspond to the frequency of the system clock. The clock signal CLK 301 may be branched four times at a maximum of 700 megahertz (Mhz), for example, but is not limited thereto. The clock signal CLK 301 may be generated, for example, a number of times corresponding to a multiple (e.g., 1.5 times) of the number N of memory arrays including bit cells.

[0118] Signal IN 305 may correspond to a 1-cycle enable signal of clock signal CLK 301 .

[0119] The enable signal EN 340 may enable one or more tri-state logic circuits 130. When a signal generator (e.g., Figure 1 When the signal generator 170 of FIG. 1 inverts the clock signal CLK 301, the enable signal EN 340 may be generated.

[0120] like Figure 3c As shown in , when the enable signal EN 340 is equal to “0”, the multi-bit accumulator 300 may enable the Wallace tree 110 (as shown as “WT”) to operate, and when the enable signal EN 340 is equal to “1”, the multi-bit accumulator 300 may enable the shift adder 150 (or, as shown as “SA”) to operate.

[0121] In addition, when the enable signal EN 340 is equal to "1", the output of the tri-state logic circuit 130 may be transmitted to the shift adder 150. In this case, the output of the tri-state logic circuit 130 wired in an actual chip may generate a parasitic capacitance including an input capacitance of the shift adder 150. In this case, data may be stored in the generated parasitic capacitance, and the generated parasitic capacitance may be used to enable the shift adder 150 to be executed in a pipeline manner.

[0122] The multi-bit accumulator 300 can reduce the number of full adders corresponding to various numbers (eg, P) of 4-bit input data of signed data described below by pipeline operation of the shift adder 150, and can also improve the speed by pipeline operation at the same time. Figures 9a to 10b Describe pipelining.

[0123] Figure 4 An example operation of a tri-state logic circuit according to one or more example embodiments is shown. Figure 4 A diagram 400 illustrating the operation of one of the tri-state logic circuits 130 (eg, a tri-state buffer) is included. Although an example case where the tri-state logic circuit is a tri-state buffer is described below, the example is not limited thereto.

[0124] Diagram 400 illustrates operations performed when an enable signal EN is applied to a tri-state buffer. Diagram 430 illustrates operations performed when an enable signal EN is applied to an inverting tri-state buffer.

[0125] For example, as shown in table 420 associated with diagram 410, when an enable signal EN of "0" is applied to the tri-state buffer, the tri-state buffer outputs a high impedance state (or, as shown, "Hi-Z") regardless of the input data. Alternatively, when an enable signal EN of "1" is applied, the tri-state buffer may output the value of the input data A as is.

[0126] Alternatively, as shown in table 440 associated with diagram 430, when an enable signal EN of "0" is applied to the inverting tri-state buffer, the tri-state buffer may output the value of the input data A. Alternatively, when an enable signal EN of "1" is applied, the tri-state buffer may output a high impedance state (or, as shown, "Hi-Z") regardless of the input data A.

[0127] In summary, when the enable signal EN has a second logic value (e.g., 1) which is the inversion of the first logic value, the tri-state logic circuit 130 outputs the addition operation result of the 1-bit Wallace tree 110 to the shift adder 150, and when the enable signal EN has a first logic value (e.g., 0), the tri-state logic circuit 130 outputs a high impedance state so as to maintain the addition operation result of the previous stage (or, time period) until all the addition operation results of the 1-bit Wallace tree 110 arrive.

[0128] In an example embodiment, since the addition operation results of the previous stage (or, period) are not transmitted to the shift adder 150 until all the addition operation results of the 1-bit Wallace tree 110 arrive, a switching phenomenon that may occur in the output of the 1-bit Wallace tree 110 can be prevented, and power consumption of such unnecessary switching phenomenon can be reduced.

[0129] Figure 5 An example structure of a multi-bit accumulator configured to perform signed operations according to one or more example embodiments is shown. Figure 5 An example structure of a multi-bit accumulator 500 configured to perform signed operations is shown. The multi-bit accumulator 500 has a structure similar to that of the multi-bit accumulator 300 described above, and thus descriptions of components redundant with the multi-bit accumulator 300 are omitted.

[0130] For example, the multi-bit accumulator 500 may perform a signed operation on the signed data. In this case, the multi-bit accumulator 500 may further include a logic gate 510 that performs a logic operation between the signed data and the MSB of the accumulated operation result of the shift adder 150. The logic gate 510 may be, for example, Figure 6 The XOR gate shown in performs an XOR operation between the MSB and the signed data, but is not limited thereto.

[0131] In one example, the logic gate 510 may perform an XOR logic operation on the MSB portion of the accumulated operation result of the shift adder 150 in order to perform a signed operation, and the number of full adders used for the signed operation may be reduced.

[0132] Figure 6 An example structure of a multi-bit accumulator including an adder array according to one or more example embodiments is shown. Figure 6 The structure of a multi-bit accumulator 600 including an adder array is shown.

[0133] The multi-bit accumulator 600 may include an adder array 630 including a full adder used in a final operation stage among a plurality of operation stages of addition operation in each 1-bit Wallace tree 110. The above-mentioned tri-state logic circuit 130 may be embedded in a separate adder Add of the adder array 630. LST 635.

[0134] For two's complement operations on the multi-bit accumulator 600, the negative operation of the signed data corresponding to the MSB of the final operation stage can be implemented by the XOR gate 610. Figure 7 and Figure 8 DescriptionAdd LST 635 structure and circuit.

[0135] Figure 7 shows an example circuit of an adder array according to one or more example embodiments, and Figure 8 Example circuits of first type full adders and second type full adders included in an adder array according to one or more example embodiments are shown.

[0136] Figure 7 The individual adders Add included in the adder array 630 are shown. LST 635 of the circuit 700. In addition, Figure 8 Shown includes a separate adder Add LST The first type of full adder FA in 635 S 710 and the second type full adder FA S&C Circuit 800 of 730 .

[0137] The individual adders Add included in the adder array 630 LST 635 may include a first type full adder FA S 710 and the second type full adder FA S&C 730, in the first type full adder FA S In 710, the tri-state logic circuit 720 is connected to the addition operation result S (between a plurality of 1-bit input data) in the second type full adder FAS&C In 730 , the tri-state logic circuit 720 is connected to each of the addition operation result S (corresponding to the operation result of the final operation stage) and the carry operation result C generated in response to the addition operation result S (corresponding to the operation result of the final operation stage).

[0138] Separate adder Add LST 635 may be, for example, a tri-state logic circuit 720 added to the log 2 The output of the full adder FA is a circuit in the form of a P-bit carry-by-bit adder. For example, in the case where the full adder and the tri-state logic circuit 720 are designed separately and attached to each other, the number of transistors used can be increased. In one example, Figure 8 As shown in Figure 8 The full adder shown in FIG. 8 (eg, full adder 811 or full adder 831) adds tri-state logic circuits 813, 833, and 835 (each including two transistors or four transistors), and the tri-state logic circuit 720 may be included in a separate adder Add LST 635 without losing a large area.

[0139] Reference Figure 8 , the first type full adder FA S 710 may have a form in which a tri-state logic circuit 813 is connected to the addition operation result S between a plurality of single-bit input data through a full adder 811. Second type full adder FA S&C The 730 may have a form in which a tri-state logic circuit 833 is connected to an addition operation result S (corresponding to the operation result of the full adder 831 in the final operation stage) and a tri-state logic circuit 835 is connected to a carry operation result C generated in response to the addition operation result S of the full adder 831 in the final operation stage. S&C 730 may output the operation result of the MSB of the final operation stage.

[0140] Figure 9a An example pipeline operation of a multi-bit accumulator to which a tri-state logic circuit is applied according to one or more example embodiments is shown. Figure 9a , it is assumed that there is an operation device 901 including a block 910 that performs an addition operation (ADD) and a block 930 that performs a multiplication operation (MUL). A timing diagram 903 shows a method of providing input to each block according to a clock (CLK) 925 of the operation device 901. In this case, at the rising edge of the clock 925, the input can be applied to each of the blocks 910 and 930.

[0141] Block 910 may process the input (X 1 , X 2) performs an addition operation (ie, A+B). For example, block 910 may correspond to a 1-bit Wallace tree 110, but is not limited thereto.

[0142] Block 930 may perform an addition operation on the result obtained from the addition operation (A+B) and the input X. 3 A multiplication operation is performed. For example, block 930 may correspond to the shift adder 150, but is not limited thereto.

[0143] In this case, the operation of each block of the operation device 901 may vary depending on whether the register 920 storing the addition operation result of the block 910 is included between the block 910 and the block 930 .

[0144] For example, in the absence of a pipeline, when the operation device 901 does not include the register 920, as shown in the timing diagram 940 of "without pipeline", the block 930 can perform a multiplication operation by receiving the addition operation result of the block 910. In this example, the inputs of the blocks 910 and 930 are sequentially provided to the blocks 910 and 930 within one clock, which corresponds to the case where the pipeline method is not used. Therefore, there may be a delay before the block 930 receives the addition operation result of the block 910, and such a delay may be repeated in each operation, thereby generating a significant cumulative delay.

[0145] In contrast, in the case of a pipeline, when the operation device 901 includes a register 920, the addition operation result of block 910 can be stored in the register 920, and block 930 can perform a multiplication operation by receiving the value stored in the register 920 instead of the value directly output from block 910. In this case, the inputs of blocks 910 and 930 can be provided simultaneously within one clock, which corresponds to the case of using a pipeline. Therefore, when a pipeline operation is performed as shown in the timing diagram 950 of "with a pipeline", block 930 can perform an operation simultaneously when block 910 performs an operation, without waiting for the addition operation result of block 910 to be received.

[0146] Figure 9b An example case of generating parasitic capacitance in a multi-bit accumulator according to one or more example embodiments is shown. Figure 9b , diagram 905 shows a situation where a parasitic capacitance 970 is generated for performing the function of a register (e.g., "holding" data (as described above)) when two transistors 960 are added to the multi-bit accumulator 300. Although the parasitic capacitance 970 is not an actual circuit element, the dotted line indicating the parasitic capacitance 970 schematically shows the parasitic capacitance 970 as a physical circuit element.

[0147] For example, when the output of the tri-state logic circuit 130 of the multi-bit accumulator 300 is wired in an actual chip, the parasitic capacitance 970 (including the input capacitance of the shift adder 150) may be generated. In this case, when data is effectively stored (retained) in the generated parasitic capacitance 970, a pipeline operation may be performed in the shift adder 150. The state in which the parasitic capacitance 970 is charged may be "1", and the state in which the parasitic capacitance 970 is discharged may be "0".

[0148] In one example, during a period in which the value (e.g., "1") charged in the parasitic capacitor 970 is maintained even if the connection is disconnected momentarily, the value of the parasitic capacitor 970 may be functionally used as a latch. A latch is a logic circuit that can maintain a current state as long as power is supplied until an input signal for changing the state is generated. A latch may have an output value that changes according to a change in an input value only when a clock is high or low.

[0149] The register 920 may store the output value of each 1-bit Wallace tree 110 according to the clock signal for the pipeline operation between the 1-bit Wallace tree 110 and the shift adder 150, and send the output value to the shift adder 150. The register 920 may be implemented by a parasitic capacitor 970 generated by the tri-state logic circuit 130. In one example, when the parasitic capacitor 970 performs the function of the register 920 described above, the multi-bit accumulator 300 may perform a pipeline operation without an additional device. The parasitic capacitor 970 may unexpectedly experience leakage in a low-speed circuit, and therefore the multi-bit accumulator 300 may be driven by a high-speed clock signal sufficient to prevent a certain amount of charge charged in the parasitic capacitor 970 from being leaked and exhausted.

[0150] The multi-bit accumulator 300 can reduce the number of full adders corresponding to 4-bit input data for various numbers (eg, P) of signed input data through pipeline operations in the shift adder 150 while increasing speed with pipeline operations.

[0151] Fig.10a An example of performing a row addition operation by a Wallace tree and a shift-add operation by a shift adder through a pipeline in a multi-bit accumulator according to one or more example embodiments is shown.

[0152] Reference Fig.10a , diagram 1000 shows a 1-bit Wallace tree 1010 that performs a row addition operation in a multi-bit accumulator 300 and a shift adder 1020 that performs a shift-add operation in the multi-bit accumulator 300. Timing diagram 1005 shows the process of performing a pipeline operation between the row addition operation and the shift-add operation.

[0153] For example, referring to the timing diagram 1005 , the 1-bit Wallace tree 1010 may perform a row addition operation at a rising edge of the clock signal 1030 , and the shift adder 1020 may perform a shift-add operation at a falling edge of the clock signal 1030 .

[0154] The multi-bit accumulator 300 may input the input data to the 1-bit Wallace tree 1010 according to the rising edge of the clock signal 1030 in the timing diagram 1005 to allow the 1-bit Wallace tree 1010 to perform a row addition operation, thereby preventing the above-mentioned switching phenomenon and reducing power consumption. In this case, the length of the input data applied to the 1-bit Wallace tree 1010 may change for each clock signal 1030 in the timing diagram 1005, and this may indicate that the time for the row addition operation has changed according to the pattern of the input data (e.g., the number of "1"s).

[0155] The row addition operation may start according to the rising edge of the clock signal 1030, but may end after the falling edge of the corresponding clock signal (e.g., the first clock signal) passes a predetermined time period, rather than immediately ending according to the falling edge of the clock signal. In this case, the predetermined time period may correspond to time borrowing (TB). TB is the time ensured by the TB method for latch-based digital circuits. TB may correspond to the property of the latch, which allows the path ending at the latch to borrow time from the next path in the pipeline so that the total time of the two paths remains the same. The time in the next step of the pipeline borrowed by the latch can be subtracted from the time in the next path. Such TB properties of the latch stem from the latch being sensitive to signal levels. Therefore, the multi-bit accumulator 300 can capture data during a time period within a specific range, rather than only capturing data during a single time slot.

[0156] Since the shift adder 1020 can operate according to the falling edge of the clock signal 1030, the multi-bit accumulator 300 may not allow the shift adder 1020 to exceed the falling edge of the second clock signal for the shift-and-add operation in the timing diagram 1005. In this case, the pipeline operation can be performed during the time from the rising edge of the second clock signal to the end of the shift-and-add operation.

[0157] Fig.10b 1 shows example clock control operations performed when a multi-bit accumulator operates in a switching prevention mode and a pipeline mode according to one or more example embodiments. Fig.10b , timing diagram 1007 shows clock control performed when the multi-bit accumulator 300 operates in the switching prevention mode, and timing diagram 1009 shows clock control performed when the multi-bit accumulator 300 operates in the pipeline mode. Fig.10b The accumulator shown in FIG. 1 may correspond to the accumulator shown in FIG. Figure 2aThe accumulator and output register 240 are depicted.

[0158] The multi-bit accumulator 300 may be operated in a switch prevention mode without pipelining as shown in timing diagram 1007, or in a pipeline mode as shown in timing diagram 1009. The mode may be controlled by adjusting the operation time of the accumulator.

[0159] As shown in the timing diagram 1007 , the multi-bit accumulator 300 can prevent the switching phenomenon by outputting the output value Y of the multi-bit accumulator 300 through the accumulator according to the rising edge of the clock signal 1030 .

[0160] Referring to timing diagram 1007 , a row add operation may start at a rising edge of clock signal 1030 , and a shift add operation may start at a falling edge of clock signal 1030 .

[0161] Furthermore, as shown in the timing diagram 1009 , the multi-bit accumulator 300 can perform a pipeline operation by outputting the output value Y of the multi-bit accumulator 300 through the accumulator according to the falling edge of the clock signal 1030 while preventing a switching phenomenon.

[0162] For example, when the row addition operation ends after the falling edge of the clock signal 1030 (eg, Row-Add 2 In timing diagrams 1007 and 1009, the multi-bit accumulator 300 may perform a shift-and-add operation starting from the time when the row addition operation ends.

[0163] In summary, the multi-bit accumulator 300 can adjust the output Y of the multi-bit accumulator 300 to be output after one clock according to the rising edge of the clock signal 1030 (as shown in the timing diagram 1007), thereby preventing the switching phenomenon and reducing power consumption. Optionally, the multi-bit accumulator 300 can adjust the output Y of the multi-bit accumulator 300 to be output after 1.5 clocks according to the falling edge of the clock signal 1030 (as shown in the timing diagram 1009), thereby improving the operation speed of the multi-bit accumulator 300 through pipeline operation.

[0164] Fig.11 An example method of operating a multi-bit accumulator according to one or more example embodiments is shown.

[0165] Reference Fig.11 , a multi-bit accumulator according to an example embodiment (e.g., Figure 1 The multi-bit accumulator 100) can output a multi-bit operation result corresponding to a single-bit input signal through operations 1110 to 1140.

[0166] In operation 1110 , a multi-bit accumulator may receive a plurality of single-bit input data.

[0167] In operation 1120 , the multi-bit accumulator may perform an addition operation in 1-bit units on the input data received in operation 1110 .

[0168] In operation 1130, the multi-bit accumulator may output the result of the addition operation in 1-bit units performed in operation 1120 based on the enable signal. For example, when the enable signal has a first logic value (e.g., "0"), the multi-bit accumulator may output a high impedance state. When the enable signal has a second logic value (e.g., "1") opposite to the first logic value, the multi-bit accumulator may output the addition operation result of the 1-bit Wallace tree to the shift adder.

[0169] In operation 1140 , the multi-bit accumulator may output a multi-bit operation result corresponding to the input data by shifting and accumulating the result of the addition operation in 1-bit units output in operation 1130 .

[0170] For example, when the multi-bit accumulator performs a signed operation on signed data, the multi-bit accumulator may perform a logical operation (eg, an XOR logical operation) between the signed data and the MSB in the multi-bit operation result.

[0171] Fig.12 An example neural network performing operations in an IMC circuit according to one or more example embodiments is shown. Fig.12 , neural network 1210 is shown.

[0172] IMC is generally a computing architecture that allows operations to be performed directly inside a memory where data (e.g., before, during, and after an operation) is persistently stored to overcome the performance and power limitations caused by the frequent data movement between memory and operating units (e.g., processors) that occurs in a von Neumann architecture. Depending on the domain in which the operation is to be performed, IMC macros can be divided into analog IMC macros and digital IMC macros. Analog IMC macros can, for example, perform operations in an analog domain (such as current, charge, time, etc.). Digital IMC macros can use logic circuits to perform operations in the digital domain. The description herein relates to digital IMC circuits.

[0173] The IMC may accelerate matrix operations and / or MAC operations that perform addition of multiple products at a time, which may be generally used for artificial intelligence (AI) learning and inference. The MAC operations for learning and inference of the neural network 1210 may be performed by a memory array, and the memory array may include bit cells of a memory device in an IMC macro. Hereinafter, for ease of description, an example case where the neural network 1210 includes a fully connected layer will be described, but the example is not limited thereto. The neural network 1210 may be, for example, a convolutional neural network (CNN) including a convolutional layer. The IMC circuit may perform MAC operations by an operation function performed by a memory array including a bit cell, thereby achieving efficient machine learning and inference of the neural network 1210.

[0174] Neural network 1210 may be, for example, a deep neural network (DNN) or an n-layer neural network including two or more hidden layers. Neural network 1210 may be, for example, a DNN including an input layer (layer 1), two hidden layers (layers 2 and 3), and an output layer (layer 4), but is not limited thereto. For example, when neural network 1210 is implemented in a DNN architecture, neural network 1210 may include a greater number of layers that can process effective information, and thus may process more complex data sets than a neural network having a single layer. Although neural network 1210 is shown as including four layers, this is provided only as an example, and neural network 1210 may include fewer or more layers or channels. That is, neural network 1210 may include layers or channels that are related to Fig.12 The structures shown in the figure are different layers of various structures.

[0175] Each of the layers included in the neural network 1210 may include a plurality of nodes 1215. The nodes may correspond to processing elements (PEs), units, channels, or units referred to as similar terms. The example neural network 1210 includes, for example, an input layer including three nodes, hidden layers each including five nodes, and an output layer including three nodes, but is not limited thereto. However, Fig.12 The neural network 1210 shown in FIG. 1 is provided only as an example, and each of the layers included in the neural network 1210 may include various numbers of nodes. The nodes 1215 included in each layer of the neural network 1210 may be connected to each other to process data. For example, one node may receive data from other nodes to perform operations, and may output the results of the operations to other nodes.

[0176] A plurality of nodes 1215 of a layer may be connected to nodes of another layer through connection lines, and weights w may be set for the connection lines. For example, the weights w may be set based on input values ​​propagated from other nodes of the previous layer connected to the node (e.g., i 1 、i 2 and i 3 ) and the weights of the nodes’ connecting lines (e.g., w11 、w 21 、w 31 and w 41 ) to determine the output o of a node 1 .

[0177] For example, the lth output o among L output values l It can be represented by the following equation 2. In this example, "L" may be an integer greater than or equal to "1" and "l" may be an integer greater than or equal to "1" and less than or equal to "L".

[0178] Equation 2

[0179] o l =∑i k w kl

[0180] In equation 2, i k can represent the kth input among P inputs, and w kl may represent a weight set between the kth input and the lth output. "P" may be an integer greater than or equal to "1", and "k" may be an integer greater than or equal to "1" and less than or equal to "P".

[0181] That is, the input and output between the nodes 1215 in the neural network 1210 can be expressed as a weighted sum between the input (i) and the weight (w). The weighted sum can also be referred to as a MAC operation, which is a multiplication operation and iterative accumulation operation between multiple inputs and multiple weights. Since the MAC operation is performed using a memory with an added operation function, the circuit that performs the MAC operation can be referred to as an "IMC macro".

[0182] For example, the neural network 1210 may be based on input data (e.g., i 1 、i 2 、i 3 、i 4 and i 5 ) performs a weighted sum operation in the layer, and based on the result of the operation (e.g., o 1 , o 2 , o 3 , o 4 and 5 ) to generate output data (e.g., u 1 、u 2 and u 3 ).

[0183] Fig.13 An example IMC processor including a multi-bit accumulator is shown according to one or more example embodiments. Fig.13, the IMC processor 1300 according to example embodiments may include an input controller 1310 , an IMC device 1330 including a plurality of IMC macros 1330 - 1 , and a post-operation circuit 1350 .

[0184] The input controller 1310 may sequentially input a multi-bit first value bit by bit to the IMC device 1330. For example, the first value may correspond to input data or weight data.

[0185] The IMC device 1330 may include, for example, a plurality of IMC macros 1330-1, wherein the plurality of IMC macros 1330-1 include Fig.14 The multiple columns in the crossbar switch structure shown in Col 1 、Col 2 , ..., and Col H .

[0186] Each of the IMC macros 1330 - 1 may include a memory array 1331 , a binary gate array 1333 , and a multi-bit accumulator 1335 . Each of the IMC macros 1330 - 1 may include a plurality of memory banks of the memory array 1331 .

[0187] The memory array 1331 may include a bit cell storing a second value applied to each first value. The second value may correspond to, for example, weight data or input data. The memory array 1331 may include a plurality of bit cells. The bit cells connected to the same bit line of the memory array 1331 may receive the same single bit (or, 1 bit) data.

[0188] The memory array 1331 may include a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of bit cells disposed at intersections between the plurality of word lines and the plurality of bit lines. For example, the memory array 1331 may include 64 word lines and 64 bit lines. In this example, the size of the memory array 1331 may be expressed as 64×64. The word lines and column lines in the memory array 1331 may be implemented by changing each other. However, the example is not necessarily limited thereto.

[0189] The binary gate array 1333 may include an operation gate that performs a single-bit binary operation or a MAC operation between a first value and a second value. The operation gate may be, for example, an AND gate, but is not limited thereto.

[0190] The multi-bit accumulator 1335 may perform a bit-by-bit operation on a result of a single-bit binary operation or a result of a MAC operation of the binary gate array 1333 , and may perform an accumulation operation on an operation result corresponding to any one of the columns through a shift operation based on a clock signal.

[0191] The multi-bit accumulator 1335 may include a 1-bit Wallace tree (e.g., Figure 1 , Figure 3a, Figure 5 or Figure 6 Wallace tree 110), tri-state logic circuit (e.g., Figure 1 , Figure 3a , Figure 5 or Figure 6 tri-state logic circuit 130) and a shift adder (e.g., Figure 1 , Figure 3a , Figure 5 or Figure 6 Shift adder 150).

[0192] The 1-bit Wallace tree may perform a bitwise operation on a single-bit MAC operation result. Each 1-bit Wallace tree may include an adder array, which includes a full adder for a final operation stage among a plurality of operation stages for an addition operation. The adder array may include a first type full adder and a second type full adder, in which a tri-state logic circuit is connected to the single-bit MAC operation result and in which a tri-state logic circuit is connected to an addition operation result (e.g., sum) corresponding to the operation result of the final operation stage and a carry operation result generated in response to the addition operation result.

[0193] The tri-state logic circuit can output the bitwise operation result of the 1-bit Wallace tree according to the enable signal. When the enable signal has a first logic value (e.g., 0), the tri-state logic circuit can output a high impedance state, and when the enable signal has a second logic value (e.g., 1) opposite to the first logic value, the tri-state logic circuit can output the bitwise operation result of the 1-bit Wallace tree to the shift adder.

[0194] The shift adder may perform an accumulation operation on the addition operation result of the 1-bit Wallace tree corresponding to any one column through a shift operation based on a clock signal. The 1-bit Wallace tree may operate according to an enable signal having a first logic value (e.g., 0), and the shift adder may operate according to an enable signal having a second logic value (e.g., 1) opposite to the first logic value.

[0195] The multi-bit accumulator 1335 may correspond to, but is not limited to, Figure 1 , Figure 3a , Figure 5 or Figure 6 . For example, when the multi-bit accumulator 1335 performs a signed operation on the signed data, the multi-bit accumulator 1335 may include a logic gate that performs a logic operation between the signed data and the MSB in the accumulated operation result. The logic gate may be, for example, an XOR gate that performs an XOR operation between the MSB and the signed data, but is not limited thereto.

[0196] The multi-bit accumulator 1335 may further include a signal generator that generates an enable signal for enabling the tri-state logic circuit by inverting the clock signal.

[0197] The post-operation circuit 1350 can output a multi-bit operation result by integrating the operation results of the multiple IMC macros 1330-1. Fig.14 The detailed configuration of the post-operation circuit 1350 is described.

[0198] Fig.14 An example structure of an IMC processor according to one or more example embodiments is shown. Fig.14 , showing an example structure of the IMC processor 1400.

[0199] The IMC processor 1400 may correspond to, for example, Fig.13 The IMC processor 1300 is described, but is not necessarily limited thereto.

[0200] The IMC processor 1400 may include an input controller 1410 , an IMC device 1330 including a plurality of IMC macros 1330 - 1 , and a post-operation circuit 1350 .

[0201] The input controller 1410 may sequentially input the multi-bit first value bit by bit to the IMC device 1330. The input controller 1410 may input the H-bit first value X 1 To X P is applied to each column of the IMC device 1330. That is, the input controller 1410 may input the P H-bit first values ​​X one bit at a time according to the time sequence. 1 To X P is sequentially applied to each of the IMC macros 1330-1. In this case, the first value may correspond to, for example, input data or weight data.

[0202] The IMC device 1330 may include, for example, a plurality of IMC macros 1330-1, wherein the plurality of IMC macros 1330-1 include Fig.14 The multiple columns in the crossbar switch structure shown in Col 1 、Col 2 , ..., and Col H .

[0203] Each of the IMC macros 1330 - 1 may include a memory array 1331 , a binary gate array 1333 , and a multi-bit accumulator 1335 . Each of the IMC macros 1330 - 1 may include a plurality of memory banks of the memory array 1331 .

[0204] The memory array 1331 may include a memory array 1331 storing “P first values ​​(eg, X 1 To X P ) are applied to the second value of "amount P" (for example, W 1 To W P) bit unit. For example, the second value may correspond to weight data W or input data X. The memory array 1331 may have, for example, Fig.12 The memory array 1230 is of the same form, but is not limited thereto.

[0205] The binary gate array 1333 may include an operation gate that performs a single-bit binary operation or a MAC operation between a first value input by the input controller 1410 through a 1-bit gate and a second value stored in the memory array 1331. The operation gate may be, for example, an AND gate 1420, but is not limited thereto. The operation gate may correspond to a 1-bit multiplication operation.

[0206] The multi-bit accumulator 1335 can process the single-bit MAC operation results (eg, P MAC operation results s) outputted by the binary gate array 1333. 1 to P ) performs statistical processing. "Statistical processing" can be, for example, a single bit MAC operation result s 1 to P The number of "1" or "0" in the count and / or the single-bit MAC operation result s 1 to P The statistical processing may be performed by, for example, a 1-bit adder tree including a full adder, but is not necessarily limited thereto. The 1-bit adder tree may be implemented, for example, in the form of the above-mentioned Wallace tree.

[0207] The multi-bit accumulator 1335 may include a Wallace tree 1430, a tri-state logic circuit 1440, and a shift adder 1450. The Wallace tree 1430 and the tri-state logic circuit 1440 may correspond to a bit statistics module that performs the above-described statistical processing.

[0208] The shift adder 1450 may combine operation results corresponding to any one of the N columns through a shift operation and an addition operation based on a clock signal. The shift adder 1450 may correspond to, for example, the above reference Figure 1 The shift adder 150 is described.

[0209] For example, the shift adder 1450 may perform a bitwise operation result (eg, log 2 The shift adder 1450 can output the bitwise operation results (e.g., log P+1 bits) corresponding to the N columns through the shift operation and the addition operation. 2 P+H bits). The shift adder 1450 can be Fig.14 The shown may be shared by each column, or may be set individually for each column.

[0210] The post-operation circuit 1350 can convert the outputs O of the N columns into 1 ToN Combine them into one and output them as a multi-bit MAC operation result. In this case, the multi-bit MAC operation result can be log 2 P+2H position.

[0211] For example, the post-operation circuit 1350 may receive the outputs of the H IMC macros 1330-1 and perform a shift operation and accumulation. The post-operation circuit 1350 may perform a shift operation on the partial sum corresponding to the respective MAC operation results of the H IMC macros 1330-1 and accumulate the shift operation results. The post-operation circuit 1350 may log 2 The P+2H-bit accumulated result is stored in, for example, a buffer and / or an output register, but is not limited thereto.

[0212] Fig.15 An example electronic system including an IMC processor according to one or more example embodiments is shown. Fig.15 , the electronic system 1500 may be based on a neural network (e.g., Fig.12 The neural network 1210 of the present invention analyzes input data in real time and extracts effective information, determines a situation based on the extracted information, or controls components of an electronic device on which the electronic system 1500 is set. For example, the electronic system 1500 can be applied to mobile devices, mobile computing devices, mobile phones, smart phones, personal digital assistants (PDAs), fixed location terminals, tablet computers, computers, wearable devices, laptop computers, servers, music players, video players, entertainment units, navigation devices, communication devices, Internet of Things (IoT) devices, global positioning system (GPS) devices, televisions (TVs), tuners, vehicles, vehicle components, avionics systems, drones, multi-rotor aircraft, electric vertical take-off and landing (eVTOL) aircraft, and medical devices, and can be installed on at least one of other various types of electronic devices.

[0213] The electronic system 1500 may include a processor 1510, a random access memory (RAM) 1520, an IMC processor 1530, a memory 1540, a sensor module 1550, and a transmission / reception module 1560. The electronic system 1500 may further include an input / output module, a security module, a power control device, etc. Some of the hardware components of the electronic system 1500 may be mounted on at least one semiconductor chip.

[0214] The processor 1510 may control the overall operation of the electronic system 1500. The processor 1510 may include one processor core (e.g., single core) or multiple processor cores (e.g., multi-core). The processor 1510 may process or execute programs and / or data stored in the memory 1540. The processor 1510 may control the functions of the IMC processor 1530 by executing the programs stored in the memory 1540. The processor 1510 may be implemented as a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), etc.

[0215] The RAM 1520 may temporarily store programs, data, or instructions. For example, the programs and / or data stored in the memory 1540 may be temporarily stored in the RAM 1520 according to the control or boot code of the processor 1510. The RAM 1520 may be implemented as a memory such as a dynamic RAM (DRAM) or a static RAM (SRAM).

[0216] The IMC processor 1530 may execute a neural network (e.g., Fig.12 The IMC processor 1530 may be, for example, a hardware accelerator dedicated to the neural network itself and / or a device including the neural network. The information signal may include, for example, one of various types of recognition signals (such as, for example, a speech recognition signal, an object recognition signal, a video recognition signal, and a biometric information recognition signal).

[0217] The IMC processor 1530 may control the IMC macro (e.g., Fig.13 The SRAM bit cell circuits of the IMC macro 1330-1 in the SRAM bit cell circuits can share and / or process the same input data and select at least part of the operation results output from the SRAM bit cell circuits.

[0218] The IMC processor 1530 may be, for example, Fig.14 The IMC processor 1400 may be, but is not necessarily limited to, this.

[0219] For example, the IMC processor 1530 may receive or store frame data included in a video stream as input data, and generate a recognition signal for an object included in an image represented by the frame data from the frame data. Alternatively, the IMC processor 1530 may receive various types of input data, and generate a recognition signal according to the input data based on the type or function of the electronic system 1500 on which the IMC processor 1530 is disposed.

[0220] The memory 1540 , which is a storage device configured to store data, may store an operating system (OS), various types of programs, and various types of data. In an example embodiment, the memory 1540 may store intermediate results generated during the operation of the IMC processor 1530 .

[0221] The memory 1540 may include at least one of a volatile memory or a non-volatile memory. As a non-limiting example, the non-volatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrical EPROM (EEPROM), a flash memory, a magnetic RAM (MRAM), a phase change memory (PCM) RAM (PRAM), a resistive RAM (RRAM) and / or a ferroelectric RAM (FRAM). As a non-limiting example, the volatile memory may include a DRAM, a SRAM, a SDRAM, etc. According to an example, the memory 1540 may include at least one of a hard disk drive (HDD), a solid state drive (SSD), a compact flash (CF) card, a secure digital (SD) card, a micro SD card, a mini SD card, an extreme digital (Xd) picture card, or a memory stick.

[0222] The sensor module 1550 may collect information around the electronic device on which the electronic system 1500 is set. The sensor module 1550 may sense or receive a signal (e.g., an image signal, a voice signal, a magnetic signal, a bio-signal, a touch signal, etc.) from the outside of the electronic system 1500, and convert the sensed or received signal into data. The sensor module 1550 may include at least one of various sensing devices (such as, for example, a microphone, an imaging device, an image sensor, a light detection and ranging (LIDAR) sensor, an ultrasonic sensor, an infrared sensor, a bio-sensor, and a touch sensor).

[0223] The sensor module 1550 may provide the data obtained by the conversion as input data to the IMC processor 1530. For example, the sensor module 1550 may include an image sensor, generate a video stream by capturing an image of the external environment of the electronic system 1500, and provide continuous data frames of the video stream as input data to the IMC processor 1530. However, the sensor module 1550 may not be limited thereto, and may provide various types of data to the IMC processor 1530.

[0224] The sending / receiving module 1560 may include various types of wired or wireless interfaces configured to communicate with external devices. For example, as a non-limiting example, the sending / receiving module 1560 may include a wired local area network (LAN), a wireless LAN (WLAN) (such as wireless fidelity (Wi-Fi)), a wireless personal area network (WPAN) (such as Bluetooth), a wireless universal serial bus (USB), ZigBee, a near field communication (NFC), a radio frequency identification (RFID), a power line communication (PLC), a communication interface that can access a mobile cellular network (such as a third generation (3G), a fourth generation (4G), and a long term evolution (LTE)), etc.

[0225] Here about Figures 1 to 15The computing devices, electronic devices, processors, memories, information output systems and hardware, storage devices and other devices, devices, units, modules and components described are implemented by hardware components or represent hardware components. Examples of hardware components that can be used to perform the operations described in this application include, where appropriate, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components that perform the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer may be implemented by one or more processing elements (such as logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices configured to respond and execute instructions in a limited manner to achieve desired results). In one example, a processor or computer includes or is connected to one or more memories storing instructions or software executed by a processor or computer. The hardware components implemented by a processor or a computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) for performing the operations described in this application. The hardware components can also access, manipulate, process, create and store data in response to the execution of instructions or software. For simplicity, the singular term "processor" or "computer" can be used in the description of the examples described in this application, but in other examples, multiple processors or computers can be used, or the processor or computer can include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component or two or more hardware components can be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components can be implemented by one or more processors, or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors, or another processor and another controller. One or more processors or a processor and a controller can implement a single hardware component, or two or more hardware components. The hardware components may have any one or more of different processing configurations, examples of which include a single processor, independent processors, parallel processors, single instruction single data (SISD) multiprocessing, single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.

[0226] Figures 1 to 15The method for performing the operations described in the present application shown in the embodiment is performed by computing hardware (e.g., by one or more processors or computers), which is implemented as executing instructions or software as described above to perform the operations performed by the method described in the present application. For example, a single operation or two or more operations may be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be performed by one or more processors, or a processor and a controller, and one or more other operations may be performed by one or more other processors, or another processor and another controller. One or more processors or a processor and a controller may perform a single operation, or two or more operations.

[0227] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform methods as described above may be written as computer programs, code segments, instructions, or any combination thereof, for individually or collectively instructing or configuring one or more processors or computers to operate as machines or special-purpose computers to perform operations performed by hardware components and methods as described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) directly executed by one or more processors or computers. In another example, the instructions or software include high-level code executed by one or more processors or computers using an interpreter. Instructions or software may be written in any programming language based on the block diagrams and flow charts shown in the accompanying drawings and the corresponding descriptions herein, and the block diagrams and flow charts shown in the accompanying drawings and the corresponding descriptions herein disclose algorithms for performing operations performed by hardware components and methods as described above.

[0228] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above, as well as any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disk storage device, hard disk drive (HDD), solid state drive (SSD), flash memory, card memory (such as, MultiMediaCard micro or card (e.g., Secure Digital (SD) or Extreme Digital (XD))), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk, and any other device configured to store instructions or software and any associated data, data files and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files and data structures to one or more processors or computers so that the one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files and data structures are distributed on a networked computer system so that the instructions and software and any associated data, data files and data structures are stored, accessed and executed in a distributed manner by one or more processors or computers.

[0229] Although the present disclosure includes specific examples, it will be clear after understanding the disclosure of the present application that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered merely descriptive and not for limiting purposes. The description of features or aspects in each example should be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and / or if components in the described systems, architectures, devices, or circuits are combined in different ways, and / or replaced or supplemented by other components or their equivalents.

[0230] Therefore, the scope of the disclosure may be defined by the claims and their equivalents in addition to the above disclosure, and all variations within the scope of the claims and their equivalents should be construed as being included in the disclosure.

Claims

1. A multi-bit accumulator, comprising: a plurality of 1-bit Wallace trees, each configured to perform an addition operation on a single bit of input data; a plurality of tri-state logic circuits, each configured to output a result of an addition operation of the plurality of 1-bit Wallace trees according to an enable signal provided to the plurality of tri-state logic circuits; as well as The shift adder is configured to perform an accumulation operation on the results of the addition operation of the plurality of 1-bit Wallace trees through a shift operation based on a clock signal.

2. The multi-bit accumulator of claim 1, wherein: Each of the plurality of 1-bit Wallace trees includes an adder array including a full adder, the full adder being used for a final operation stage among operation stages of an addition operation, Wherein, each adder array includes: A first type full adder in which a tri-state logic circuit is connected to an addition operation result of an addition operation between single-bit input data; and A second type full adder in which a tri-state logic circuit is connected to each of an addition operation result corresponding to an operation result of a final operation stage and a carry operation result generated in response to the addition operation result.

3. The multi-bit accumulator of claim 2, wherein: Each of the plurality of tri-state logic circuits is configured as: In response to the enable signal having a first logic value, outputting a high impedance state; and In response to the enable signal having a second logic value, a result of the addition operation of the plurality of 1-bit Wallace trees is output to the shift adder, the second logic value being an inversion of the first logic value.

4. The multi-bit accumulator of claim 1 , further comprising: A logic gate is configured to perform a logic operation between the signed data and a most significant bit (MSB) of a result of the accumulation operation of the shift adder in response to the multi-bit accumulator performing a signed operation on the signed data.

5. The multi-bit accumulator of claim 4, wherein: Logic gates include: An XOR gate is configured to perform an XOR operation between the MSB and the signed data.

6. The multi-bit accumulator of claim 1 , further comprising: A signal generator is configured to generate an enable signal by inverting a clock signal.

7. The multi-bit accumulator of claim 1, wherein: The plurality of 1-bit Wallace trees are configured to operate in response to an enable signal having a first logic value, and wherein, The shift adder is configured to operate in response to the enable signal having a second logic value, the second logic value being an inversion of the first logic value.

8. The multi-bit accumulator of claim 1 , further comprising: A plurality of registers are configured to store output values ​​of the plurality of 1-bit Wallace trees respectively according to a clock signal to provide a pipeline operation between the plurality of 1-bit Wallace trees and the shift adder by sending the stored output values ​​to the shift adder.

9. The multi-bit accumulator of claim 8, wherein: The plurality of registers are implemented by parasitic capacitances generated by the plurality of tri-state logic circuits.

10. The multi-bit accumulator of claim 8, further comprising: A multiplier, wherein the step of transmitting enables the plurality of 1-bit Wallace trees to perform addition operations concurrently with multiplication operations of the multiplier.

11. An in-memory computing (IMC) processor, comprising: An IMC device including IMC macros, each IMC macro including a column in a crossbar switch structure; an input controller configured to sequentially input the multi-bit first value to the IMC device bit by bit; and The post-operation circuit is configured to output a multi-bit operation result integrating the operation results of each IMC macro, Each of the IMC macros includes: a memory array including bit cells, each bit cell configured to store a second value applied to each of the first values; a binary gate array including arithmetic gates, each arithmetic gate configured to perform a single-bit multiply-accumulate (MAC) operation between a first value and a second value; and A multi-bit accumulator is configured to perform a bit-by-bit operation on a result of the single-bit MAC operation and to perform an accumulation operation on a result of the bit-by-bit operation corresponding to any one of the columns.

12. The IMC processor of claim 11, wherein: Multi-bit accumulators include: a plurality of 1-bit Wallace trees, each configured to perform a bit-by-bit operation on a result of a single-bit MAC operation; a plurality of tri-state logic circuits, each configured to output a result of a bitwise operation of a corresponding 1-bit Wallace tree among the plurality of 1-bit Wallace trees according to an enable signal; and A shift adder is configured to perform an accumulation operation on a result of an addition operation of one 1-bit Wallace tree corresponding to any one of the columns among the plurality of 1-bit Wallace trees through a shift operation based on a clock signal.

13. The IMC processor of claim 12, wherein: Each of the plurality of 1-bit Wallace trees comprises: an adder array including a full adder used in a final operation stage among operation stages of addition operations, Among them, the adder array includes: A first type full adder in which a tri-state logic circuit is connected to a result of a single-bit MAC operation; and A second type full adder in which a tri-state logic circuit is connected to each of an addition operation result corresponding to an operation result of a final operation stage and a carry operation result generated in response to the addition operation result.

14. The IMC processor of claim 12, wherein: Each of the plurality of tri-state logic circuits is configured as: In response to the enable signal having a first logic value, outputting a high impedance state; and In response to the enable signal having a second logic value, the results of the bitwise operation of the plurality of 1-bit Wallace trees are output to the shift adder, the second logic value being an inversion of the first logic value.

15. The IMC processor of claim 12, further comprising: The logic gate is configured to perform a signed operation on the signed data based on the multi-bit accumulator, and perform a logic operation between the signed data and the most significant bit (MSB) of the result of the accumulation operation of the shift adder.

16. The IMC processor of claim 15, wherein: Logic gates include: An XOR gate is configured to perform an XOR operation between the MSB and the signed data.

17. The IMC processor of claim 12, further comprising: A signal generator is configured to generate an enable signal for enabling the plurality of tri-state logic circuits by inverting a clock signal.

18. The IMC processor of claim 12, wherein: Each of the plurality of 1-bit Wallace trees is configured to operate in accordance with an enable signal having a first logic value, and wherein, The shift adder is configured to operate in response to the enable signal having a second logic value, the second logic value being an inversion of the first logic value.

19. The IMC processor of claim 11, wherein: The IMC processor is integrated into at least one of: a mobile device, a mobile computing device, a mobile phone, a smart phone, a personal digital assistant (PDA), a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, a music player, a video player, an entertainment unit, a navigation device, a communication device, a global positioning system (GPS) device, a television (TV), a tuner, a vehicle, a vehicle component, an avionics system, a drone, a multirotor aircraft, or a medical device.

20. A method of operating a multi-bit accumulator, the method comprising: Receives a single bit of input data; Perform an addition operation on the input data in 1-bit units; The result of the addition operation is output in 1-bit units based on the enable signal; as well as The result of the multi-bit operation corresponding to the input data is output by shifting and accumulating the result of the addition operation in 1-bit units.

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