Device for integrating front end circuit

Abstract

The wireless front end may include a plurality of circuits including a power amplifier (PA), a low noise amplifier (LNA), and an RF switch. To reduce the size of the front end and improve its performance, various circuits of the front end may include N-polarity III-N transistors, all formed of the same epitaxial material structure and monolithically integrated onto a single chip. Due to different performance requirements of various transistors in different circuits, parameters in the access region of the device, such as gate length, gate-channel spacing, and surface-channel spacing, may be varied to meet desired performance requirements.

Description

Technical Field

[0001] The present disclosure relates to semiconductor material structures and devices, and in particular, devices formed from N-polar Group III-nitride layers. Background Art

[0002] III-N nitride semiconductor devices, such as III-N high electron mobility transistors (HEMTs), are typically formed from a III-N material structure grown on a substrate in a III-polar orientation (i.e., in the [0 0 0 1] direction). An example III-polar III-N HEMT device 100 is shown in FIG. 1 . In device 100 , III-N layers 111 , 112 , and 113 are formed on a suitable substrate 110 , such as silicon (Si), silicon carbide (SiC), sapphire, or GaN, in a III-polar orientation (i.e., in the [0 0 0 1] direction as shown). III-N layer 111 is a buffer layer and may be formed of AlN, AlGaN, GaN, or a combination thereof. III-N layer 112 is a channel layer, such as GaN. III-N layer 113 is a barrier layer, such as AlGaN. The composition of the III-N layers 112 and 113 is selected such that a two-dimensional electron gas (2DEG) channel 120 is induced in the III-N channel layer 112 extending from the source 121 to the drain 122. A gate insulator 132 is formed on the III-N barrier layer 113, and a gate 123 is formed on the gate insulator 132. A voltage applied to the gate 123 relative to the source 121 modulates the charge in the 2DEG 120 directly beneath the gate 123, thereby modulating the device current flowing between the source 121 and the drain 122 during operation.

[0003] A nitrogen-polarity (N-polarity) III-N HEMT device 200 (i.e., a device in which III-N layers 211, 213, and 212 are oriented along the [0 0 0 -1] direction on substrate 210) is shown in FIG. 2. In device 200, a III-N channel layer 212 (i.e., a layer containing a 2DEG channel 220) is formed on a III-N barrier layer 213 (thus, in an N-polarity III-N HEMT, the barrier layer is often referred to as a "back barrier"). A gate insulator 232 can be used to reduce gate leakage, which can be more persistent in an N-polarity device than in a III-polarity device because, in an N-polarity device, the III-N barrier layer (e.g., layer 213) is not between the gate 223 and the channel. Depending on the specific device geometry, an N-polarity III-N transistor can have properties and characteristics that are well suited for many circuit applications. Summary of the invention

[0004] In a first aspect, a semiconductor device includes a semiconductor wafer including a III-N material structure, the III-N material structure including: a III-N back barrier; and a III-N channel layer on an N-face of the III-N back barrier, the III-N channel layer having a group III face adjacent to the III-N back barrier and an N-face on a side opposite to the group III face, wherein a band gap of the III-N back barrier is greater than a band gap of the III-N channel layer. The semiconductor device includes a first transistor in a first region of the semiconductor wafer, the first transistor including: a first portion of the III-N back barrier; a first portion of the III-N channel layer, the first portion of the III-N channel layer having a first 2DEG channel therein, wherein the first portion of the III-N channel layer has a first recess adjacent to its N-face, the first recess having a first bottom surface; a first gate at least partially located in the first recess; and a first source and a first drain, wherein the first gate is located between the first source and the first drain. The semiconductor device includes a second transistor in a second region of the semiconductor wafer, the second transistor including: a second portion of a III-N back barrier; a second portion of a III-N channel layer, the second portion of the III-N channel layer having a second 2DEG channel therein, wherein the second portion of the III-N channel layer has a second groove adjacent to its N-face, the second groove having a second bottom surface; a second gate at least partially located in the second groove; and a second source and a second drain, wherein the second gate is located between the second source and the second drain; wherein a thickness of the first portion of the III-N channel layer in a region between the first gate and the first drain is greater than 1.2 times a thickness of the second portion of the III-N channel layer in a region between the second gate and the second drain. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1 is a cross-sectional view of a Group III polarity III-N transistor device.

[0006] FIG. 2 is a cross-sectional view of an N-polar III-N transistor device.

[0007] Figure 3 is a block diagram of an example transmit / receive front-end circuit.

[0008] Figure 4 It is a plan view of a semiconductor device.

[0009] Figure 5 It is a cross-sectional view of the epitaxially formed N-polar III-N material structure.

[0010] Fig. 6A , 6B , 6C, 6D and 6E can be monolithically integrated and used Figure 4 A cross-sectional view of an N-polarity III-N transistor structure in a semiconductor device.

[0011] Figure 7 A method of forming a semiconductor device is shown.

[0012] Figure 8 FIG. 1 is a cross-sectional view of another epitaxially formed N-polar III-N material structure.

[0013] Fig.9A , 9B , 9C, 9D and 9E can be monolithically integrated and used Figure 4 A cross-sectional view of another N-polarity III-N transistor structure in a semiconductor device.

[0014] Fig.10 Another method of forming a semiconductor device is shown.

[0015] Fig.11 FIG. 1 is a cross-sectional view of another epitaxially formed N-polar III-N material structure.

[0016] Fig. 12A , 12B and 12C can be monolithically integrated and used Figure 4 A cross-sectional view of another N-polarity III-N transistor structure in a semiconductor device.

[0017] Fig.13 Another method of forming a semiconductor device is shown.

[0018] Fig.14A and 14B is a cross-sectional view of an N-polarity III-N transistor structure in which one or more secondary 2DEGs are formed.

[0019] Fig.15 is a cross-sectional view of an epitaxially formed N-polar III-N material structure including one or more p-type III-N layers.

[0020] Fig.16 It can be done by Fig.15 A cross-sectional view of another N-polar III-N transistor structure formed by a material structure.

[0021] Fig.17 A plan view of a semiconductor device including two or more monolithically integrated transistors.

[0022] Fig.18 is a cross-sectional view of another N-polar III-N transistor structure.

[0023] Like numbers in the drawings represent like elements. DETAILED DESCRIPTION

[0024] A wireless front-end typically includes multiple circuits, including both active-transistor-based and diode-based circuits as well as passive electromagnetic or acoustic-based circuits. Examples of transistor-based circuits that can be used include power amplifiers (PAs), low-noise amplifiers (LNAs), switches (e.g., RF switches), active filters (e.g., N-path filters), frequency conversion circuits such as multipliers or mixers, and / or beamforming circuits including phase shifters, variable gain amplifiers, or variable attenuators, and / or switched delay lines. Examples of passive electromagnetic or acoustic-based circuits that can be used include filters (e.g., bandpass, highpass, or lowpass filters), multiplexing filters (e.g., diplexers, triplexers, n-plexers), and / or antennas. For transistor-based circuits, each circuit includes transistors that are specifically designed and configured to meet the performance requirements of a particular circuit. Since the performance requirements vary between different circuits, each circuit is typically designed and fabricated separately and then interconnected to form the front-end. Figure 3 FIG. shows a block diagram of an exemplary transmit / receive (T / R) front-end 300 connected to an antenna 308. As shown, the T / R front-end 300 includes a PA 302, an LNA 304, and a T / R switch 306.

[0025] In Figure 3 the front-end 300 shown, the PA 302 can be formed of or include an N-polarity III-N transistor having a first geometry that provides optimal performance for the PA, the LNA 304 can be formed of or include an N-polarity III-N transistor having a second geometry that provides optimal performance for the LNA, and the switch 306 can be formed of or include an N-polarity III-N transistor having a third geometry that provides optimal performance for the switch. As used herein, the term group III nitride or III-N material, layer, device, etc. refers to a material or device composed of a compound semiconductor material according to the stoichiometric formula Sc v B w Al x In y Ga z N a (D) b where v + w + x + y + z is about 1, 0 ≤ v ≤ 1, 0 ≤ w ≤ 1, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1, a + b is about 1, 0.9 < a ≤ 1, 0 ≤ b < 0.1, and (D) is any group V element other than nitrogen. In a III-N transistor device, the channel through which current conduction occurs can be included in one or more III-N layers of the device.

[0026] Semiconductor devices are described herein that include transistors from two or more circuits (e.g., front-end circuits) monolithically integrated on a single semiconductor wafer. That is, a set of common semiconductor material layers such as N-polarity III-group nitride layers formed (e.g., epitaxially grown) on a common substrate are used to form transistors of two or more circuits. The design and geometry of each transistor can be optimized for a specific circuit or portion of a circuit in which it is used. Optionally, interconnect metals that connect transistors to each other or to other circuit components are also formed on the common semiconductor material layer. Integrating these transistors onto a single wafer can reduce overall cost, reduce size or floor space, and / or improve the performance of the front end.

[0027] Figure 4 4 is a plan view of a semiconductor device 400 formed from a semiconductor wafer 410. The semiconductor wafer 410 includes a plurality of III-N semiconductor layers (eg, Figure 5 ). The semiconductor device 400 includes a first transistor 600A formed by a first portion of a III-N material structure (a portion contained within region 420A), a second transistor 600B formed by a second portion of the III-N material structure (a portion contained within region 420B), and a third transistor 600C formed by a third portion of the III-N material structure (a portion contained within region 420C). As shown, transistors 600A, 600B, and 600C are monolithically integrated on semiconductor wafer 410. Transistors 600A, 600B, and 600C can each be a component of a different circuit of the front end. For example, as further described below, transistor 600A can be part of a PA, transistor 600B can be part of an LNA, and transistor 600C can be part of a switch (e.g., an RF switch that can operate as a T / R switch). Although Figure 4 All three transistors 600A-600C are shown integrated on the semiconductor wafer 410, but a semiconductor device including any two of the three transistors integrated on the semiconductor wafer may also be formed. As used herein, a "semiconductor wafer" refers to a continuous structure including one or more semiconductor layers, wherein for each semiconductor layer, the layer (and each portion of the layer) is formed via a single epitaxial growth.

[0028] Figure 5 is a cross-sectional view of an epitaxially formed N-polar III-N material structure 500, Figure 4The semiconductor wafer 410 may be formed from the material structure. The material structure 500 includes a substrate 510 and a plurality of III-N layers 511, 513, and 512 formed on the substrate 510 with an N-polarity orientation (i.e., along the [0 0 0 -1] direction as shown). The substrate 510 may be any substrate suitable for epitaxial growth of III-N layers thereon, such as silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), or sapphire (Al). 2 O 3 ). The III-N layer 511 is a buffer layer and may be formed of AlN, AlGaN, GaN or a combination thereof. The III-N layer 513 formed on the N-face of the III-N buffer layer 511 serves as a back barrier. The III-N layer 512 is formed on the N-face of the III-N back barrier 513, with its III-group face adjacent to the III-N back barrier 513 and its N-face on the opposite side of its III-group face, and the III-N layer 512 serves as a channel layer.

[0029] The compositions of the III-N back barrier 513 and the III-N channel layer 512 are selected such that a two-dimensional electron gas (2DEG) channel 520 is induced in the III-N channel layer 512 adjacent to the interface between the III-N channel layer 512 and the III-N back barrier 513. To induce the 2DEG channel 520, the compositions of the III-N layers 512 and 513 may be selected such that the conduction band energy in the III-N back barrier 513 is greater than the conduction band energy in the III-N channel layer 512 adjacent to the interface between the layers 512 and 513. That is, at the interface between the III-N layers 512 and 513, the conduction band energy may be discontinuous, wherein the conduction band energy on the back barrier side of the interface is greater than the conduction band energy on the channel layer side of the interface. Such conduction band energy discontinuity may generally be achieved by selecting a material for the III-N channel layer 512 that has a smaller band gap than the band gap of the III-N back barrier 513. For example, the III-N channel layer 512 may be formed of GaN, and the III-N back barrier 513 may be formed of Al x Ga 1-x N is formed, wherein the aluminum fraction composition x may be in the range of 0.1≤x≤0.6 (eg, in the range of 0.2≤x≤0.4).

[0030] The III-N back barrier 513 may be formed as a single III-N layer or multiple III-N layers. Figure 5As seen in FIG. 5 , where the back barrier 513 is implemented as a plurality of III-N layers, the III-N back barrier 513 may include a first III-N layer 541 and a second III-N layer 542. In the case where the III-N back barrier 513 is formed as a single layer, the entire III-N back barrier 513 is implemented as the first III-N layer. In the case where the III-N back barrier 513 is formed as a plurality of III-N layers, the first III-N layer 541 may be adjacent to the III-N channel layer 512 and may directly contact the III-N channel layer 512, such that the 2DEG channel 520 is adjacent to the interface between the III-N channel layer 512 and the first III-N layer 541 of the III-N back barrier 513. In this case, the first III-N layer 541 has a band gap that may be greater than the band gap of the III-N channel layer 512. In some embodiments, the first III-N layer 541 is formed of AlN.

[0031] Fig. 6A , 6B , 6C, 6D and 6E are cross-sectional views of N-polarity III-N transistor structures 600A, 600B, 600C, 600D and 600E, respectively. Any two or more of these transistor structures may be formed by Figure 5 The N-polar III-N material structure is monolithically integrated and used to form Figure 4 Device 400. Reference Fig. 6A , transistor 600A includes a first portion 513A of a III-N back barrier 513 (i.e., a portion of the back barrier 513 in a first region 420A of the semiconductor wafer 410) and a first portion 512A of a channel layer 512, wherein the portion 512A of the channel layer has a first 2DEG channel 520A therein. The first portion 512A of the III-N channel layer has a first recess 551A formed adjacent to its N-face 515A, the first recess having a first bottom surface 552A. The first recess 551A can be formed by etching into the first portion 512A of the III-N channel layer. The transistor 600A also includes a first gate 533A, which is formed of a metal or other conductive material and is at least partially located in the first recess 551A. The transistor 600A also includes a first source 531A and a first drain 532A, each of which is formed of a metal or other conductive material and is positioned such that the first gate 533A is located between the first source 531A and the first drain 532A. Optionally, a regrown n+ region 530A is formed under each of the source contact 531A and the drain contact 532A to reduce the contact resistance between the source / drain contacts and the first 2DEG channel 520A.

[0032] refer to Figure 6B, similar to transistor 600A, transistor 600B includes a second portion 513B of the III-N back barrier 513 (i.e., a portion of the back barrier 513 in the second region 420B of the semiconductor wafer 410) and a second portion 512B of the channel layer 512, wherein the portion 512B of the channel layer has a second 2DEG channel 520B therein. Also similar to transistor 600A, in transistor 600B, the second portion 512B of the III-N channel layer has a second recess 551B formed therein adjacent to its N-face 515B, the second recess having a second bottom surface 552B. The second recess 551B can be formed by etching into the second portion 512B of the III-N channel layer. Transistor 600B also includes a second gate 533B, which is formed of a metal or other conductive material and is at least partially located in the second recess 551B. The transistor 600B also includes a second source 531B and a second drain 532B, each of which is formed of a metal or other conductive material and is positioned so that the second gate 533B is located between the second source 531B and the second drain 532B. Optionally, a regrown n+ region 530B is formed under each of the second source 531B and the second drain 532B to reduce the contact resistance between the second source / drain contact and the second 2DEG channel 520B.

[0033] Still reference Figure 6B In the transistor 600B of FIG. 600A, the second portion 512B of the III-N channel layer may be thinned, for example, by etching, before forming the second recess 551B. In this way, the total thickness of the channel layer in the access region of the device 600A (i.e., the thickness 516A of the first portion 512A of the III-N channel layer in the region between the first gate 533A and the first drain 532A) is thicker than the total thickness of the channel layer in the access region of the device 600B (i.e., the thickness 516B of the second portion 512B of the III-N channel layer in the region between the second gate 533B and the second drain 532B). For example, the thickness 516A may be greater than 1.1 times (e.g., greater than 1.2 times, greater than 1.3 times, greater than 1.4 times, greater than 1.5 times, greater than 1.6 times, greater than 1.8 times, or greater than 2 times) the thickness 516B. As used herein, a "gate region" of a transistor refers to the region below the gate, a "contact region" of a transistor refers to the region below the source and drain contacts, and an "access region" of a transistor refers to the region between the gate region and the contact region. A "source access region" refers to the access region between the source contact region and the gate region, and a "drain access region" refers to the access region between the drain contact region and the gate region.

[0034] Reference now Figure 6C, similar to transistors 600A and 600B, transistor 600C includes a third portion 513C of the III-N back barrier 513 (i.e., the portion of the back barrier 513 in the third region 420C of the semiconductor wafer 410) and a third portion 512C of the channel layer 512, wherein the portion 512C of the channel layer has a third 2DEG channel 520C therein. Also similar to transistors 600A and 600B, in transistor 600C, the third portion 512C of the III-N channel layer has a third recess 551C formed therein adjacent to its N-face 515C, the third recess having a third bottom surface 552C. The third recess 551C can be formed by etching into the third portion 512C of the III-N channel layer. Transistor 600C also includes a third gate 533C, which is formed of a metal or other conductive material and is at least partially located in the third recess 551C. The transistor 600C further includes a third source 531C and a third drain 532C, each of which is formed of a metal or other conductive material and is positioned such that the third gate 533C is located between the third source 531C and the third drain 532C. Optionally, a regrown n+ region 530C is formed under each of the third source 531C and the third drain 532C to reduce the contact resistance between the third source / drain contact and the third 2DEG channel 520C.

[0035] Transistor 600C differs from transistor 600A in that a thickness of channel layer 512C removed to form third recess 551C is smaller than a thickness of channel layer 512A removed to form first recess 551A. Thus, spacing 561A between bottom surface 552A of first recess 551A and a III-group face of first portion 513A of III-N back barrier in transistor 600A is greater than spacing 561C between bottom surface 552C of third recess 551C and a III-group face of third portion 513C of III-N back barrier in transistor 600C. For example, spacing 561C may be greater than 1.1 times, greater than 1.2 times, greater than 1.3 times, greater than 1.4 times, greater than 1.5 times, greater than 1.6 times, greater than 1.8 times, or greater than 2 times spacing 561A. Optionally, gate length 562C of transistor 600C may be greater than gate length 562A of transistor 600A, for example greater than 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.8, 2, 2.5 or 3 times greater than gate length 562A of transistor 600A.

[0036] Reference now Fig.6D, transistor 600D is similar to transistor 600B, except that instead of thinning the entire channel layer 512D before forming recess 551D, the channel layer is thinned in the source access region (i.e., between source 531D and gate 533D), but not in the drain access region (i.e., between drain 532D and gate 533D). Therefore, the thickness 516DA of the channel layer 512D in the drain access region may be equal to Fig. 6A The thickness 516DB of the channel layer 512D in the source access region may be the same as the thickness 516A, and the thickness 516DB of the channel layer 512D in the source access region may be less than the thickness 516DA. In some cases, the thickness 516DB may be the same as the thickness 516A of the channel layer 512D in the source access region. Figure 6B The thickness 516B in is substantially the same.

[0037] In some embodiments, the spacing 561C in transistor 600C is approximately the same as the thickness 516B of the thinned channel layer 512B in transistor 600B. For example, the thickness 516B can be between 0.9 times the spacing 561C and 1.1 times the spacing 561C. When the two devices are monolithically integrated on the same wafer, making the two thicknesses approximately the same allows the same etching to form both the groove 551C in transistor 600C and the thinned channel layer 512B in transistor 600B, thereby simplifying the manufacturing process. For similar reasons, the channel layer 512D in transistor 600D can have a thickness 516DB approximately the same as the spacing 561C in transistor 600C in the source access region. That is, the thickness 516DB can be between 0.9 times the spacing 561C and 1.1 times the spacing 561C.

[0038] Reference now Fig. 6E , except that the shape of the groove 551E of transistor 600E is different from the shape of the groove of transistor 600A, transistor 600E is the same as transistor 600A. Specifically, as shown in the figure, groove 551E includes one or more steps. Groove 551E can be formed in multiple steps. First, the upper part of the groove (i.e., above the step) can be formed by etching down to the depth of the step. Then a second etching can be performed to form the bottom of groove 551E. In some embodiments, the etching for forming the upper part of groove 551E is the same as the etching for forming groove 551C in transistor 600C (i.e., the upper part of groove 551E and groove 551C are formed simultaneously). Therefore, the interval 561EC between the step in transistor 600E and the interface between layers 512E and 541E can be approximately the same as the interval 561C in transistor 600C. For example, interval 561EC can be between 0.9 times of interval 561C and 1.1 times of interval 561C.

[0039] The structure of any of transistors 600A, 600D, or 600E may be optimized for use in a power amplifier (PA) because the small gate-channel spacing provides high gain, while the thick channel layer in the access region (particularly the drain access region) provides good dispersion control (i.e., minimizes dispersion) under high power operation. The structure of transistor 600B may be optimized for use in a low noise amplifier (LNA). Similar to the PA, the LNA requires a transistor with high gain, and transistor 600B obtains high gain as a result of the small gate-channel spacing. However, in the LNA, dispersion control is not as important as in the PA, but lower capacitance is desired to give higher gain and lower noise figure. This is achieved in transistor 600B with the help of a thinner channel layer in the access region. The structure of transistor 600C may be optimal for use in an RF switch because the larger gate-channel spacing (relative to transistors 600A and 600B) increases channel conductivity and maximum device current while also allowing a longer gate length, which can lead to higher gains, and the thick channel layer in the access region provides good dispersion control under high current operation.

[0040] Figure 7 A method 700 of forming a semiconductor device (e.g., device 400) having monolithically integrated transistors 600A, 600B, and / or 600C is shown. First, a semiconductor wafer including a III-N material structure is formed or provided, wherein the III-N material structure includes an N-polarity III-N channel layer on an N-face of an N-polarity III-N back barrier (step 701). The III-N material structure may be Figure 5. A first transistor (e.g., transistor 600A) is formed in a first region of a semiconductor wafer by (i) etching through a portion of the III-N channel layer to form a first recess, (ii) depositing a first gate at least partially in the first recess, and (iii) depositing a first source and a first drain on opposite sides of the first gate (step 702). A second transistor (e.g., transistor 600B) is formed in a second region of a semiconductor wafer by (i) thinning the entire III-N channel layer in the second region by etching, (ii) etching through a portion of the III-N channel layer in the second region to form a second recess, (iii) depositing a second gate at least partially in the second recess, and (iv) depositing a second source and a second drain on opposite sides of the second gate (step 703). A third transistor (e.g., transistor 600C) is formed in a third region of the semiconductor wafer by (i) etching through a portion of the III-N channel layer in the third region to form a third recess having a depth different from the first recess, (ii) depositing a third gate at least partially in the third recess, and (iii) depositing a third source and a third drain on opposite sides of the third gate (step 704). In some embodiments, the gates of two or more transistors are deposited simultaneously, and / or the source and drain of two or more transistors are deposited simultaneously, and / or the gate recesses of two or more transistors are at least partially formed (e.g., by etching) simultaneously, and / or thinning the III-N channel layer in one transistor and forming the gate recess in another transistor are performed simultaneously (e.g., by etching both simultaneously).

[0041] The above-described monolithically integrated semiconductor device 400 and method of forming device 400 are made possible by the fact that, in an N-polarity III-N transistor, the (back) barrier is below the channel layer. Thus, unlike a III-polarity III-N transistor, the thickness of the channel layer in the access region can be easily changed by etching the (uncovered) channel layer, thereby allowing both transistor 600A and transistor 600B to be formed from a single common epitaxial material structure. Furthermore, in an N-polarity transistor, thinning the semiconductor material (e.g., by etching) to form transistor 600B from the same epitaxial material as transistor 600A may not significantly change the 2DEG charge density in the access region, thereby allowing transistor 600B to maintain a low on-resistance. In a III-polarity transistor, thinning the semiconductor material by etching will result in a thinner barrier layer (rather than a thinner channel layer) in the access region of the device, which may result in a significant reduction in the 2DEG charge density in the access region, thereby resulting in an increase in on-resistance and a reduction in maximum current density during device operation.

[0042] Despite Figure 5 , Fig. 6A , Figure 6B or Figure 6C 600A, 600B, and 600C may each further include a dielectric layer formed on the upper surface of the transistor, the dielectric layer serving as a passivation layer. In some embodiments, the same dielectric layer is formed on all three transistors, wherein the first portion of the dielectric layer is on transistor 600A, the second portion of the dielectric layer is on transistor 600B, and the third portion of the dielectric layer is on transistor 600C. The first portion of the dielectric layer may optionally be thicker than the second portion of the dielectric layer. Having a thicker dielectric layer may provide better passivation and dispersion control, which is generally preferred. However, when transistor 600B is used in an LNA, a thinner passivation layer may result in higher gain. Because dispersion control may not be as critical in an LNA as in a PA, in some cases, if the first portion of the dielectric layer is thicker than the second portion of the dielectric layer, the overall device performance may be improved.

[0043] Figure 8 is a cross-sectional view of another epitaxially formed N-polar III-N material structure 800, Figure 4 The semiconductor wafer 410 may be formed of the material structure, and Fig.9A , 9B 9C, 9D, and 9E show the resulting monolithically integrated transistor structures 900A, 900B, 900C, 900D, and 900E, respectively, that can be obtained from material structure 800. Figure 5 The material structure 500 of FIG. 800 includes a substrate 810 and a plurality of III-N layers on the substrate 810 in an N-polar orientation (i.e., along the [0 0 0 -1] direction as shown). The substrate 810 may be the same as the substrate 510 of the material structure 500. The plurality of N-polar III-N layers on the substrate 810 may include a III-N buffer layer 811, a III-N back barrier 813, and a III-N channel layer 812. The compositions of the layers 811, 813, and 812 may be the same as the compositions of the layers 511, 513, and 512, respectively.

[0044] The material structure 800 further includes an III-N etch stop layer 814 on the N surface of the III-N channel layer 812 and an III-N cap layer 817 on the N surface of the III-N etch stop layer 814. The total thickness 816 of the III-N channel layer 812, the III-N etch stop layer 814, and the III-N cap layer 817 in the material structure 800 may be similar to or approximately the same as the thickness 516 of the III-N channel layer 512 in the material structure 500. The compositions of the III-N cap layer 817 and the III-N etch stop layer 814 may be selected such that the III-N cap layer 817 can be selectively etched at a higher rate than the III-N etch stop layer 814 using an etching process suitable for forming a gate recess (such as an F-containing plasma or an HCl-containing aqueous solution). For example, the III-N cap layer 817 may be formed of GaN, and the III-N etch stop layer 814 may be formed of Al y Ga 1-y N, where the aluminum fraction composition y may be in the range of 0 < y ≤ 1 (e.g., in the range of 0.05 ≤ y ≤ 0.6). The bandgap of the III-N etch stop layer 814 may be greater than the bandgap of the III-N cap layer 817. The bandgap and / or composition of the III-N cap layer 817 may be the same as or substantially the same as the bandgap and / or composition of the III-N channel layer 812. In some embodiments, the III-N etch stop layer 814 is formed of Al y Ga 1-y N (0 < y ≤ 1), and both the III-N channel layer 812 and the III-N cap layer 817 are formed of GaN.

[0045] Now referring to Fig.9A , the transistor 900A includes a first portion 813A of the III-N back barrier 813 (i.e., the portion of the back barrier 813 in the first region 420A of the semiconductor wafer 410) and a first portion 812A of the III-N channel layer 812, wherein the portion 812A of the channel layer has a first 2DEG channel 820A therein. The transistor 900A further includes a first portion 814A of the III-N etch stop layer 814 and a first portion 817A of the III-N cap layer 817. The first portion 817A of the III-N cap layer has a first recess 851A formed therein adjacent to its N surface 825A, and the first recess has a first bottom surface 852A. The first recess 851A extends at least partially through the thickness of the first portion 817A of the III-N cap layer. In some embodiments, the first recess 851A extends through the entire thickness of the first portion 817A of the III-N cap layer but does not extend into the first portion 812A of the III-N channel layer.

[0046] The first recess 851A can be formed by etching into the first portion 817A of the III-N cap layer using an etching process that etches material of the III-N cap layer at a rate that is higher than the rate of the III-N etch stop layer 814A. Thus, the etching can be "stopped" at or near the surface of the etch stop layer 814A adjacent to the III-N cap layer 817. In this way, the depth of the first recess 851A and the corresponding spacing 861A between the bottom surface 852A of the first recess 851A and the III-group face of the first portion 813A of the III-N back barrier can be epitaxially controlled. This can result in improved uniformity and / or reproducibility compared to transistor 600A. Although the etch stop layer can provide precise control of depth and a smooth etched surface, residual byproducts from the selective etching that remain in the near-surface region (such as fluoride ions) can cause undesirable electrical instabilities for transistors using SF-based 6 Similar behavior has been observed for N-polar transistors fabricated by plasma etching of . These instabilities can be removed by removing the near-surface region with the aid of additional etching using plasma etching and / or wet chemical etching that leaves no residual F.

[0047] The transistor 900A also includes a first gate 833A formed of a metal or other conductive material and at least partially located in the first recess 851A. The transistor 900A also includes a first source 831A and a first drain 832A, each of which is formed of a metal or other conductive material and is positioned such that the first gate 833A is located between the first source 831A and the first drain 832A. Optionally, a regrown n+ region 830A is formed under each of the source contact 831A and the drain contact 832A to reduce the contact resistance between the source / drain contacts and the first 2DEG channel 820A.

[0048] refer to Fig. 9B, transistor 900B includes a second portion 813B of the III-N back barrier 813 (i.e., the portion of the back barrier 813 in the second region 420B of the semiconductor wafer 410) and a second portion 812B of the III-N channel layer 812, wherein the portion 812B of the channel layer has a second 2DEG channel 820B therein. Transistor 900B also includes a second portion 814B of the III-N etch stop layer 814 and a second portion 817B of the III-N capping layer 817, wherein the second portion 817B of the III-N capping layer in transistor 900B is thinner than the first portion 817A of the III-N capping layer in transistor 900A. The second portion 817B of the III-N capping layer has a second recess 851B formed therein adjacent to its N-face 825B, the second recess having a first bottom surface 852B. The second recess 851B extends at least partially through the thickness of the second portion 817B of the III-N capping layer. In some embodiments, the second recess 851B extends through the entire thickness of the second portion 817B of the III-N cap layer, but does not extend into the second portion 812B of the III-N channel layer.

[0049] The transistor 900B also includes a second gate 833B formed of a metal or other conductive material and at least partially located in the second recess 851B. The transistor 900B also includes a second source 831B and a second drain 832B, each of which is formed of a metal or other conductive material and is positioned so that the second gate 833B is located between the second source 831B and the second drain 832B. Optionally, a regrown n+ region 830B is formed under each of the second source 831B and the second drain 832B to reduce the contact resistance between the second source / drain contact and the second 2DEG channel 820B.

[0050] Transistor 900B is similar to transistor 600B, except that the total thickness 816B of layers 812B, 814B, and 817B in the access region of transistor 900B is less than the total thickness 816A of layers 812A, 814A, and 817A in the access region of transistor 900A. Transistor 900B is similar to transistor 600B in that it can be formed by thinning the second portion 817B of the III-N cap layer (e.g., by etching) and then subsequently forming a transistor identical to transistor 900A. Similar to transistor 900A, a spacing 861B between a bottom surface 852B of second recess 851B and a III-group face of second portion 813B of the III-N back barrier can be epitaxially controlled by using an etching process for the gate recess that etches the material of the III-N cap layer 817 at a higher rate than the material of the III-N etch stop layer 814. In some embodiments, the thickness 816A is greater than 1.1 times (e.g., greater than 1.2 times, greater than 1.3 times, greater than 1.4 times, greater than 1.5 times, greater than 1.6 times, greater than 1.8 times, or greater than 2 times) the thickness 816B. In some embodiments, the thickness of the first portion 817A of the III-N capping layer in the region between the first gate 833A and the first drain 832A of the transistor 900A is greater than 1.1 times (e.g., greater than 1.2 times, greater than 1.3 times, greater than 1.4 times, greater than 1.5 times, greater than 1.6 times, greater than 1.8 times, or greater than 2 times) the thickness of the second portion 817B of the III-N capping layer in the region between the second gate 833B and the second gate 834B of the transistor 900B.

[0051] Reference now Fig. 9C, similar to transistors 900A and 900B, transistor 900C includes a third portion 813C of III-N back barrier 813 (i.e., a portion of back barrier 813 in third region 420C of semiconductor wafer 410), a third portion 812C of channel layer 812 (wherein portion 812C of channel layer has third 2DEG channel 520C therein), a third portion 814C of III-N etch stop layer 814, and a third portion 817C of III-N cap layer. Also similar to transistors 900A and 900B, in transistor 900C, the third portion 817C of III-N cap layer has a third recess 851C formed therein adjacent to its N-face 825C, the third recess having a third bottom surface 852C. The third recess 851C can be formed by etching into the third portion 817C of the III-N cap layer. Transistor 900C also includes a third gate 833C formed of metal or other conductive material and at least partially located in the third recess 851C. The transistor 900C also includes a third source 831C and a third drain 832C, each of which is formed of a metal or other conductive material and is positioned such that the third gate 833C is located between the third source 831C and the third drain 832C. Optionally, a regrown n+ region 830C is formed under each of the third source 831C and the third drain 832C to reduce the contact resistance between the third source / drain contact and the third 2DEG channel 820C.

[0052] Similar to the case of transistor 600C, in transistor 900C, the thickness of the III-N capping layer 817C that is removed to form the third recess 851C is smaller than the thickness of the capping layer 817A that is removed to form the first recess 851A in transistor 900A. Therefore, a spacing 861C between a bottom surface 852C of the third recess 851C and a group III plane of a third portion 813C of the III-N back barrier in transistor 900C is greater than a spacing 861A between a bottom surface 852A of the first recess 851A and a group III plane of a first portion 813A of the III-N back barrier in transistor 900A. For example, the spacing 861C may be greater than 1.1 times, greater than 1.2 times, greater than 1.3 times, greater than 1.4 times, greater than 1.5 times, greater than 1.6 times, greater than 1.8 times, or greater than 2 times the spacing 861A. Optionally, gate length 862C of transistor 900C may be greater than gate length 562A of transistor 900A, for example, greater than 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.8, 2, 2.5 or 3 times gate length 862A of transistor 900A.

[0053] Reference now Fig.9D, transistor 900D is similar to transistor 900B, except that instead of thinning the entire cap layer 817D before forming recess 851D, the cap layer is thinned in the source access region (i.e., between source 831D and gate 833D), but not in the drain access region (i.e., between drain 832D and gate 833D). Thus, the total thickness 816DA of layers 817D, 814D, and 812D in the drain access region may be equal to Figure 8 A, and the total thickness 816DB of layers 817D, 814D, and 812D in the source access region may be less than thickness 816DA. In some cases, thickness 816DB may be equal to Figure 6B The thickness 816B is substantially the same.

[0054] In some embodiments, the spacing 861C in transistor 900C is approximately the same as the thickness 816B in transistor 900B. For example, the thickness 816B can be between 0.9 times the thickness 861C and 1.1 times the spacing 861C. When the two devices are monolithically integrated on the same wafer, making the two thicknesses approximately the same allows the same etch to be used to form both the groove 851C in transistor 900C and the cap layer 817B in thinned transistor 900B, thereby simplifying the manufacturing process. For similar reasons, the thickness 816DB in the source access region of transistor 900D can be approximately the same as the spacing 861C in transistor 900C. That is, the thickness 816DB can be between 0.9 times the spacing 861C and 1.1 times the spacing 861C.

[0055] Reference now Fig.9E , except that the shape of the groove 851E of transistor 900E is different from the shape of the groove of transistor 900A, transistor 900E is the same as transistor 900A. Specifically, as shown in the figure, groove 851E includes one or more steps. Groove 851E can be formed in multiple steps. First, the upper part of the groove (i.e., above the step) can be formed by etching down to the depth of the step. Then a second etching can be performed to form the bottom of groove 851E. In some embodiments, the etching for forming the upper part of groove 851E is the same as the etching for forming groove 851C in transistor 900C (i.e., the upper part of groove 851E and groove 851C are formed simultaneously). Therefore, the interval 861EC between the step in transistor 900E and the interface between layers 812E and 841E can be approximately the same as the interval 861C in transistor 900C. For example, interval 861EC can be between 0.9 times of interval 861C and 1.1 times of interval 861C.

[0056] For the same reasons described above with respect to transistors 600A, 600B, 600C, 600D, and 600E, the structure of any one of transistors 900A, 900D, or 900E may be optimized for use in a power amplifier (PA), the structure of transistor 900B may be optimized for use in a low noise amplifier (LNA), and the structure of transistor 900C may be optimized for use in an RF switch. In addition, because the depth of the gate recess of transistors 900A and 900B is determined by the thickness of the epitaxially grown cap layer 817, the reproducibility and yield of these transistors may be improved compared to the reproducibility and yield of transistors 600A and 600B.

[0057] Fig.10 A method 1000 of forming a semiconductor device (e.g., device 400) having monolithically integrated transistors 900A, 900B, and / or 900C is shown. First, a semiconductor wafer including a III-N material structure is formed or provided, wherein the III-N material structure includes an N-polarity III-N channel layer on an N-face of an N-polarity III-N back barrier, an N-polarity III-N etch stop layer on the III-N channel layer, and an N-polarity III-N cap layer on the III-N etch stop layer (step 1001). The III-N material structure may be formed with Figure 8The III-N material structures shown are the same. A first transistor (e.g., transistor 900A) is formed in a first region of a semiconductor wafer by etching through the III-N capping layer in the first region to form a first recess, depositing a first gate at least partially in the first recess, and depositing a first source and a first drain on opposite sides of the first gate (step 1002). A second transistor (e.g., transistor 900B) is formed in a second region of a semiconductor wafer by thinning the entire III-N capping layer in the second region by etching, etching through the III-N capping layer in the second region to form a second recess, depositing a second gate at least partially in the second recess, and depositing a second source and a second drain on opposite sides of the second gate (step 1003). A third transistor (e.g., transistor 900C) is formed in a third region of a semiconductor wafer by etching through a portion of the III-N capping layer in the third region to form a third recess having a depth different from the first recess, depositing a third gate at least partially in the third recess, and depositing a third source and a third drain on opposite sides of the third gate (step 1004). In some embodiments, gates of two or more transistors are deposited simultaneously, and / or sources and drains of two or more transistors are deposited simultaneously, and / or gate recesses of two or more transistors are at least partially formed (e.g., by etching) simultaneously, and / or thinning the III-N channel layer in one transistor and forming a gate recess in another transistor are performed simultaneously (e.g., by etching both simultaneously).

[0058] Similar to transistors 600A, 600B, 600C, 600D, and 600E, although not in Figure 8 , 9A , 9B, 9C, 9D or 9E, but transistors 900A, 900B, 900C, 900D and 900E may each further include a dielectric layer formed on the upper surface of the transistor, which serves as a passivation layer. The thickness and other properties of the dielectric layer may be the same as described with respect to transistors 600A, 600B and 600C.

[0059] Fig.11 is a cross-sectional view of another epitaxially formed N-polar III-N material structure 1100, Figure 4 The semiconductor wafer 410 may be formed of the material structure, and Fig. 12A , 12B 1200A, 1200B, and 1200C, respectively, are shown as the resulting monolithically integrated transistor structures 1200A, 1200B, and 1200C that can be obtained from material structure 1100. Figure 8The material structure 1100, the material structure includes a substrate 1110 and a plurality of III-N layers on the substrate 1110 in an N-polarity orientation (i.e., as shown in the figure, along the [0 0 0 -1] direction). The substrate 1110 can be the same as the substrate 510 of the material structure 500. The plurality of N-polar III-N layers on the substrate 1110 can include a III-N buffer layer 1111, a III-N back barrier 1113, a III-N channel layer 1112, a first III-N etch stop layer 1114, and a first III-N cap layer 1117. The compositions of the layers 1111, 1113, 1112, 1114, and 1117 can be the same as the compositions of the layers 811, 813, 812, 814, and 817, respectively.

[0060] The material structure 1100 further includes a second III-N etch stop layer 1124 on the N-face of the first III-N cap layer 1117 and a second III-N cap layer 1127 on the N-face of the second III-N etch stop layer 1124. The total thickness 1116 of the III-N layers 1112, 1114, 1117, 1124, 1127 in the material structure 1100 can be similar or approximately the same as the thickness 816 in the material structure 800. The compositions of the first and second III-N cap layers 1117 and 1127 can be selected respectively, and the compositions of the first and second III-N etch stop layers 1114 and 1124 can be selected respectively, such that the III-N cap layers 1117 and 1127 can be selectively etched at a higher rate than the III-N etch stop layers 1114 and 1124 using an etching process suitable for forming a gate trench. For example, each of the III-N cap layers 1117 and 1127 can be formed of GaN, and each of the III-N etch stop layers 1114 and 1124 can be formed of Al y Ga 1-y N, where the aluminum fraction composition y can be in the range of 0 < y ≤ 1 (e.g., in the range of 0.1 ≤ y ≤ 0.6). The bandgap of each III-N etch stop layer can be greater than the bandgap of each III-N cap layer. The bandgap and / or composition of each III-N cap layer can be the same or approximately the same as the bandgap and / or composition of the III-N channel layer 1112. In some embodiments, each of the III-N etch stop layers 1114 and 1117 is formed of Al y Ga 1-y N (0 < y ≤ 1), and each of the III-N channel layer 1112 and the III-N cap layers 1117 and 1127 is formed of GaN.

[0061] Now refer to Fig. 12A and the transistor 1200A is similar to Fig.9A900A, except that the first recess 1151A is formed both through the III-N capping layers 1117A and 1127A and through the second etch stop layer 1124A. As with transistor 900A, the etch used to form the first recess 1151A can be "stopped" at or near the surface of the first etch stop layer 1114C adjacent to the first III-N capping layer 1117C. In this way, the depth of the first recess 1151A and the corresponding spacing 1161A between the bottom surface 1152A of the first recess 1151A and the III-group face of the first portion 1113A of the III-N back barrier can be epitaxially controlled.

[0062] refer to Fig. 12B , transistor 1200B is similar to Fig. 9B The transistor 900B is formed by removing (eg, by etching) the entire second III-N capping layer ( Fig.11 In the embodiment of the present invention, the first III-N etch stop layer 1124B is formed in the second III-N etch stop layer 1127, and the second recess 1151B is formed through the layers 1124B and 1117B. When forming the transistor 1200B, the second III-N etch stop layer 1124B can be used as an etch stop layer for removing the second III-N capping layer, and the first III-N etch stop layer can be used as an etch stop layer for forming the second recess 1151B.

[0063] refer to Fig. 12C , transistor 1200C is similar to Fig. 9C 900C, except that a third recess 1151C is formed through the second III-N capping layer 1127C and may “stop” at or near a surface of the second etch stop layer 1124C adjacent to the second III-N capping layer 1127C. In this way, the depth of the third recess 1151C and the corresponding spacing 1161C between the bottom surface 1152C of the third recess 1151C and the III-group face of the first portion 1113C of the III-N back barrier may be epitaxially controlled.

[0064] Similar to the transistors 900A, 900B, and 900C, the spacing 1161A between the bottom surface 1152A of the first recess 1151A and the III-group plane of the first portion 1113A of the III-N back barrier in the transistor 1200A is greater than the spacing 1161C between the bottom surface 1152C of the third recess 1151C and the III-group plane of the third portion 1113C of the III-N back barrier in the transistor 1200C. For example, the spacing 1161A may be greater than 1.1 times, greater than 1.2 times, greater than 1.3 times, greater than 1.4 times, greater than 1.5 times, greater than 1.6 times, greater than 1.8 times, or greater than 2 times the spacing 1161C. Optionally, the gate length 1162C of transistor 1200C can be greater than the gate length 1162A of transistor 1200A, for example, greater than 1.1 times, 1.2 times, 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.8 times, 2 times, 2.5 times or 3 times the gate length 1162A of transistor 1200A.

[0065] For the same reasons described above with respect to transistors 900A, 900B, and 900C, the structure of transistor 1200A may be optimized for use in a power amplifier (PA), the structure of transistor 1200B may be optimized for use in a low noise amplifier (LNA), and the structure of transistor 1200C may be optimized for use in an RF switch. In addition, because the depth of the gate recesses of all three transistors is determined by the thickness of the epitaxial layer, the reproducibility and yield of these transistors may be even further improved compared to the reproducibility and yield of transistors 900A, 900B, and 900C.

[0066] Fig.13 A method 1300 of forming a semiconductor device (e.g., device 400) having monolithically integrated transistors 1200A, 1200B, and / or 1200C is shown. First, a semiconductor wafer including a III-N material structure is formed or provided, wherein the III-N material structure includes an N-polarity III-N channel layer on an N-face of an N-polarity III-N back barrier, a first N-polarity III-N etch stop layer on the III-N channel layer, a first N-polarity III-N cap layer on the first III-N etch stop layer, a second N-polarity III-N etch stop layer on the first III-N cap layer, and a second N-polarity III-N cap layer on the second III-N etch stop layer (step 1301). The III-N material structure may be formed with Fig.11The III-N material structures shown are the same. A first transistor (e.g., transistor 1200A) is formed in a first region of a semiconductor wafer by etching through first and second III-N capping layers and a second III-N etch stop layer in the first region to form a first recess, depositing a first gate at least partially in the first recess, and depositing a first source and a first drain on opposite sides of the first gate (step 1302). A second transistor (e.g., transistor 1200B) is formed in a second region of the semiconductor wafer by etching away the entire second III-N capping layer in the second region, etching through the second III-N etch stop layer and the first III-N capping layer in the second region to form a second recess, depositing a second gate at least partially in the second recess, and depositing a second source and a second drain on opposite sides of the second gate (step 1303). A third transistor (e.g., transistor 1200C) is formed in a third region of the semiconductor wafer by etching through the second III-N capping layer in the third region to form a third recess having a depth different from the first recess, depositing a third gate at least partially in the third recess, and depositing a third source and a third drain on opposite sides of the third gate (step 1304). In some embodiments, the gates of two or more transistors are deposited simultaneously, and / or the sources and drains of two or more transistors are deposited simultaneously.

[0067] Similar to transistors 600A, 600B, and 600C, although not in Fig.11 , 12A , 12B or 12C, but transistors 1200A, 1200B and 1200C may each further include a dielectric layer formed on the upper surface of the transistor, the dielectric layer serving as a passivation layer. The thickness and other properties of the dielectric layer may be the same as described with respect to transistors 600A, 600B and 600C.

[0068] Depending on the specific composition and thickness of the etch stop layer and the cap layer in the above transistor, one or more secondary 2DEGs may be formed in the III-N cap layer of the transistor. Fig.14A The location of the secondary 2DEG 860C that may be induced in the III-N cap layer 817C of the transistor 900C is shown (from Fig. 9C ),and Fig. 14B The location of the secondary 2DEG 1160C that may be induced in the first III-N cap layer 1117C of the transistor 1200C is shown (from Fig. 12C). When the transistor is biased on (i.e., when the gate-source voltage is greater than the threshold voltage of the transistor), the secondary 2DEGs 860C and 1160C may extend continuously from the source region to the drain region, and the secondary 2DEGs 860C and 1160C may be under the gate of each of their respective transistors. Fig.14A and 14B In a transistor used in an RF switch, this secondary 2DEG can increase the overall channel conductivity of the transistor, thereby improving the switching performance, although a larger gate voltage swing may be required to switch the transistor from the on state to the off state.

[0069] In some cases, it may be desirable to inhibit or prevent the formation of one or more secondary 2DEGs. This may be achieved by including one or more p-type layers directly overlying any etch stop layer. Fig.15 is a cross-sectional view of another epitaxially formed N-polar III-N material structure 1500 that is the same as material structure 1100, but further includes a first p-type III-N layer 1564 between etch stop layer 1514 and cap layer 1517, and a second p-type III-N layer 1574 between etch stop layer 1524 and cap layer 1527. Each of p-type layers 1564 and 1574 may be formed of the same semiconductor material or have the same bandgap as the overlying cap layers 1517 and 1527, respectively. Fig.16 is a cross-sectional view of a transistor 1600 that may be formed from material structure 1500. As shown, transistor 1600 is the same as transistor 1200A, but further includes p-type layers 1564A and 1574A in the access region. Similarly, any transistor described herein that includes one or more etch stop layers may further include a p-type III-N layer directly on the etch stop layer (e.g., between the etch stop layer and an overlying cap layer).

[0070] Fig.17 A plan view of a semiconductor device 1700 is shown, wherein Fig. 6A and 6C The transistors 600A and 600C are monolithically integrated on the substrate 1710 and are also combined into a single hybrid device. In the configuration of the semiconductor device 1700, the two transistors share a common drain 532A / 532C, the source pad 1731 connects the sources 531A and 531C of the transistors to form a common source, and the gate pad 1733 connects the gates 533A and 533C of the transistors to form a common gate. The active area of ​​the hybrid device (i.e., including Fig. 6A and 6C1775. In the inactive region surrounding the active region, the 2DEG channel is eliminated or becomes non-conductive, for example by etching away some III-N layers or by ion implantation. The hybrid device is configured so that the gate width 1771 of transistor 600A is different from the gate width 1772 of transistor 600C. Although the gate width 1771 of transistor 600A is shown as being less than the gate width 1772 of transistor 600C, it can also be made to be greater than the gate width 1772 of transistor 600C instead. In addition, any combination of transistors 600A, 600B and 600C can be combined to form a hybrid device as shown. Similarly, any combination of transistors 900A, 900B and 900C can be combined to form a hybrid device as shown. Similarly, any combination of transistors 1200A, 1200B and 1200C can be combined to form a hybrid device as shown. As used herein, the "gate width" of a transistor is the width (eg, in a direction substantially perpendicular to the direction of current flow) of the gate metal portion directly over the active region of the transistor (eg, the region containing the transistor channel).

[0071] In some cases, for any transistor described herein in which one or more etch stop layers are included in a semiconductor material structure, the etch used to form a recess (e.g., a gate recess) into the semiconductor material may not stop precisely at the upper surface of the etch stop layer. Fig.18 Shown with Fig. 12B 1800 is a cross-sectional view of transistor 1200B that is identical to transistor 1800, except that recess 1851 extends at least partially through or through the entire thickness of etch stop layer 1814. In forming recess 1851, etch stop layer 1814 may still allow for increased precision in the depth of etching as compared to the recess formed in transistor 1200B. Additionally, for any other transistor herein that includes one or more etch stop layers in a semiconductor material structure, any gate or access region recess etching that is illustrated as stopping at an upper surface of the etch stop layer may alternatively be formed at least partially through or through the entire thickness of the etch stop layer, and in some cases at least partially through any layer underlying the etch stop layer.

[0072] Various devices and material structures thereof, as well as methods of forming the devices and material structures, have been described above. However, it should be understood that they are presented by way of example only and are not limiting. Embodiments have been specifically shown and described, but it will be understood that various changes in form and detail may be made. For example, for any transistor described herein, a gate insulator or gate dielectric may be included between the gate metal and the underlying semiconductor material. Therefore, other embodiments are also within the scope of the following claims.

Claims

1. A semiconductor device, comprising: A semiconductor wafer comprising a III-N material structure, the III-N material structure comprising: III-N back barrier; and a III-N channel layer located on an N-face of the III-N back barrier, the III-N channel layer having a group III face adjacent to the III-N back barrier and an N-face on a side opposite to the group III face, wherein a band gap of the III-N back barrier is greater than a band gap of the III-N channel layer; A first transistor in a first region of the semiconductor wafer, the first transistor comprising: The first part of III-N back barrier; a first portion of a III-N channel layer, the first portion of the III-N channel layer having a first 2DEG channel therein, wherein the first portion of the III-N channel layer has a first recess adjacent to an N-face thereof, the first recess having a first bottom surface; a first gate at least partially located in the first recess; and a first source and a first drain, wherein the first gate is located between the first source and the first drain; and a second transistor in a second region of the semiconductor wafer, the second transistor comprising: The second part of III-N back barrier; a second portion of the III-N channel layer, the second portion of the III-N channel layer having a second 2DEG channel therein, wherein the second portion of the III-N channel layer has a second recess adjacent to an N-face thereof, the second recess having a second bottom surface; a second gate at least partially located in the second recess; and a second source and a second drain, wherein the second gate is located between the second source and the second drain; A thickness of a first portion of the III-N channel layer in a region between the first gate and the first drain is greater than 1.2 times a thickness of a second portion of the III-N channel layer in a region between the second gate and the second drain.

2. The semiconductor device according to claim 1, wherein The first transistor is part of a first circuit and the second transistor is part of a second circuit.

3. The semiconductor device according to claim 2, wherein: The first circuit is a power amplifier or an RF switch, and the second circuit is a low noise amplifier.

4. The semiconductor device according to claim 1, wherein: The first transistor further includes a first portion of a dielectric layer on the first portion of the III-N channel layer, the second transistor further includes a second portion of the dielectric layer on the second portion of the III-N channel layer, and the first portion of the dielectric layer is thicker than the second portion of the dielectric layer.

5. The semiconductor device according to claim 1, wherein A spacing between the first bottom surface and a Group III plane of a first portion of the III-N channel layer is at least 1.2 times a spacing between the second bottom surface and a Group III plane of a second portion of the III-N channel layer.

6. A semiconductor device comprising: A semiconductor wafer comprising a III-N material structure, the III-N material structure comprising: III-N back barrier; and a III-N channel layer located on an N-face of the III-N back barrier, the III-N channel layer having a group III face adjacent to the III-N back barrier and an N-face on a side opposite to the group III face, wherein a band gap of the III-N back barrier is greater than a band gap of the III-N channel layer; A first transistor in a first region of a semiconductor wafer, the first transistor comprising: The first part of III-N back barrier; a first portion of a III-N channel layer, the first portion of the III-N channel layer having a first 2DEG channel therein, wherein the first portion of the III-N channel layer has a first recess adjacent to an N-face thereof, the first recess having a first bottom surface; a first gate at least partially located in the first recess; and a first source and a first drain, wherein the first gate is located between the first source and the first drain; and a second transistor in a second region of the semiconductor wafer, the second transistor comprising: The second part of III-N back barrier; a second portion of the III-N channel layer, the second portion of the III-N channel layer having a second 2DEG channel therein, wherein the second portion of the III-N channel layer has a second recess adjacent to an N-face thereof, the second recess having a second bottom surface; a second gate at least partially located in the second recess; and a second source and a second drain, wherein the second gate is located between the second source and the second drain; A spacing between the first bottom surface and a Group III plane of a first portion of the III-N channel layer is at least 1.2 times a spacing between the second bottom surface and a Group III plane of a second portion of the III-N channel layer.

7. The semiconductor device according to claim 6, wherein: The first transistor is part of a first circuit and the second transistor is part of a second circuit.

8. The semiconductor device according to claim 7, wherein: The first circuit is an RF switch and the second circuit is a power amplifier or a low noise amplifier.

9. A semiconductor device comprising: A semiconductor wafer comprising a III-N material structure, the III-N material structure comprising: III-N back barrier; a III-N channel layer located on an N-face of the III-N back barrier, the III-N channel layer having a group III face adjacent to the III-N back barrier and an N-face on a side opposite to the group III face, wherein a band gap of the III-N back barrier is greater than a band gap of the III-N channel layer; a III-N etch stop layer on the N-face of the III-N channel layer; and a III-N capping layer on the N-side of the III-N etch stop layer; A first transistor in a first region of the semiconductor wafer, the first transistor comprising: The first part of III-N back barrier; a first portion of a III-N channel layer, wherein the first portion of the III-N channel layer has a first 2DEG channel therein; a first portion of a III-N etch stop layer; a first portion of a III-N capping layer, wherein the first portion of the III-N capping layer includes a first recess extending at least partially through a thickness of the first portion of the III-N capping layer, the first recess having a first bottom surface; a first gate at least partially located in the first recess; and a first source and a first drain, wherein the first gate is located between the first source and the first drain; and a second transistor in a second region of the semiconductor wafer, the second transistor comprising: The second part of III-N back barrier; a second portion of the III-N channel layer, wherein the second portion of the III-N channel layer has a second 2DEG channel therein; a second portion of the III-N etch stop layer; a second portion of the III-N capping layer, wherein the second portion of the III-N capping layer includes a second recess extending at least partially through a thickness of the second portion of the III-N capping layer, the second recess having a second bottom surface; a second gate at least partially located in the second recess; and a second source and a second drain, wherein the second gate is located between the second source and the second drain; A thickness of the first portion of the III-N capping layer in a region between the first gate and the first drain is greater than 1.2 times a thickness of the second portion of the III-N capping layer in a region between the second gate and the second drain.

10. The semiconductor device according to claim 9, wherein The first recess partially extends through a thickness of a first portion of the III-N capping layer without extending through an entire thickness of the first portion of the III-N capping layer, and the second recess extends through an entire thickness of a second portion of the III-N capping layer.

11. The semiconductor device according to claim 10, wherein: A spacing between the first bottom surface and a Group III plane of a first portion of the III-N channel layer is at least 1.2 times a spacing between the second bottom surface and a Group III plane of a second portion of the III-N channel layer.

12. The semiconductor device according to claim 9, wherein: The first transistor is part of a first circuit and the second transistor is part of a second circuit.

13. The semiconductor device according to claim 12, wherein: The first circuit is a power amplifier or an RF switch, and the second circuit is a low noise amplifier.

14. The semiconductor device according to claim 9, wherein: The first transistor also includes a first portion of a dielectric layer on the first portion of the III-N capping layer, the second transistor also includes a second portion of a dielectric layer on the second portion of the III-N capping layer, and the first portion of the dielectric layer is thicker than the second portion of the dielectric layer.

15. The semiconductor device according to claim 9, wherein: A spacing between the first bottom surface and a Group III plane of a first portion of the III-N channel layer is at least 1.2 times a spacing between the second bottom surface and a Group III plane of a second portion of the III-N channel layer.

16. A semiconductor device comprising: A semiconductor wafer comprising a III-N material structure, the III-N material structure comprising: III-N back barrier; a III-N channel layer located on an N-face of the III-N back barrier, the III-N channel layer having a group III face adjacent to the III-N back barrier and an N-face on a side opposite to the group III face, wherein a band gap of the III-N back barrier is greater than a band gap of the III-N channel layer; a III-N etch stop layer on the N-face of the III-N channel layer; and a III-N capping layer on the N-side of the III-N etch stop layer; A first transistor in a first region of the semiconductor wafer, the first transistor comprising: a first portion of the III-N back barrier; a first portion of the III-N channel layer, wherein the first portion of the III-N channel layer has a first 2DEG channel therein; a first portion of the III-N etch stop layer; a first portion of the III-N capping layer, wherein the first portion of the III-N capping layer includes a first groove extending partially through a thickness of the first portion of the III-N capping layer but not through the entire thickness of the first portion of the III-N capping layer, the first groove having a first bottom surface; a first gate at least partially located in the first recess; and a first source and a first drain, wherein the first gate is located between the first source and the first drain; and a second transistor in a second region of the semiconductor wafer, the second transistor comprising: a second portion of the III-N back barrier; a second portion of the III-N channel layer, wherein the second portion of the III-N channel layer has a second 2DEG channel therein; a second portion of the III-N etch stop layer; a second portion of the III-N capping layer, wherein the second portion of the III-N capping layer includes a second groove extending through an entire thickness of the second portion of the III-N capping layer, the second groove having a second bottom surface; a second gate at least partially located in the second recess; and a second source and a second drain, wherein the second gate is located between the second source and the second drain.

17. The semiconductor device according to claim 16, wherein: A spacing between the first bottom surface and a Group III plane of a first portion of the III-N channel layer is at least 1.2 times a spacing between the second bottom surface and a Group III plane of a second portion of the III-N channel layer.

18. The semiconductor device according to claim 16, wherein: The first transistor is part of a first circuit and the second transistor is part of a second circuit.

19. The semiconductor device according to claim 18, wherein: The first circuit is an RF switch and the second circuit is a power amplifier or a low noise amplifier.

20. A semiconductor device comprising: A semiconductor wafer comprising a III-N material structure, the III-N material structure comprising: III-N back barrier; a III-N channel layer located on an N-face of the III-N back barrier, the III-N channel layer having a group III face adjacent to the III-N back barrier and an N-face on a side opposite to the group III face, wherein a band gap of the III-N back barrier is greater than a band gap of the III-N channel layer; a first III-N etch stop layer on the N-surface of the III-N channel layer; a first III-N capping layer on the N-face of the first III-N etch stop layer; and a second III-N etch stop layer on the N-face of the first III-N cap layer; A first transistor in a first region of the semiconductor wafer, the first transistor comprising: a first portion of the III-N back barrier; a first portion of the III-N channel layer, wherein the first portion of the III-N channel layer has a first 2DEG channel therein; a first portion of the first III-N etch stop layer; a first portion of the first III-N cap layer; a first portion of the second III-N etch stop layer; a second III-N capping layer on the N-face of the second III-N etch stop layer; a first groove extending through the entire thickness of the second III-N capping layer, the first groove having a first bottom surface; a first gate at least partially located in the first recess; and a first source and a first drain, wherein the first gate is located between the first source and the first drain; and A second transistor comprising: a second portion of the III-N back barrier; a second portion of the III-N channel layer, wherein the second portion of the III-N channel layer has a second 2DEG channel therein; a second portion of the first III-N etch stop layer; a second portion of the first III-N cap layer; a second portion of the second III-N etch stop layer; a second recess extending through the entire thickness of both a second portion of the second III-N etch stop layer and a second portion of the first III-N capping layer, the second recess having a second bottom surface; a second gate at least partially located in the second recess; and a second source and a second drain, wherein the second gate is located between the second source and the second drain.

21. The semiconductor device according to claim 20, wherein: The second III-N capping layer is not on the second portion of the second III-N etch stop layer.

22. The semiconductor device according to claim 21, wherein The first recess further extends through an entire thickness of the first portion of the second III-N etch stop layer.

23. The semiconductor device according to claim 22, wherein: The first recess further extends through an entire thickness of the first portion of the first III-N capping layer.

24. The semiconductor device according to claim 20, wherein: The first transistor is part of a first circuit and the second transistor is part of a second circuit.

25. The semiconductor device according to claim 24, wherein: The first circuit is a power amplifier or an RF switch, and the second circuit is a low noise amplifier.

26. The semiconductor device according to claim 20, wherein: The first transistor also includes a first portion of a dielectric layer on the second III-N cap layer, the second transistor also includes a second portion of a dielectric layer on a second portion of the second III-N etch stop layer, and the first portion of the dielectric layer is thicker than the second portion of the dielectric layer.

27. The semiconductor device according to claim 20, wherein: A spacing between the first bottom surface and a Group III plane of a first portion of the III-N channel layer is at least 1.2 times a spacing between the second bottom surface and a Group III plane of a second portion of the III-N channel layer.

28. A method of forming a semiconductor device, comprising: A semiconductor wafer is provided that includes a III-N material structure, the III-N material structure including: III-N back barrier; and a III-N channel layer located on an N-face of the III-N back barrier, the III-N channel layer having a group III face adjacent to the III-N back barrier and an N-face on a side opposite to the group III face, wherein a band gap of the III-N back barrier is greater than a band gap of the III-N channel layer; In a first region of the semiconductor wafer, forming a first transistor, the first transistor comprising a first portion of the III-N back barrier and a first portion of the III-N channel layer, the first portion of the III-N channel layer having a first 2DEG channel therein, the forming of the first III-N transistor comprising: etching through a portion of the first portion of the III-N channel layer adjacent to an N-face thereof to form a first recess having a first bottom surface; depositing a first gate at least partially in the first recess; and depositing a first source electrode and a first drain electrode, wherein the first gate electrode is deposited between the first source electrode and the first drain electrode; and In a second region of the semiconductor wafer, forming a second transistor, the second transistor comprising a second portion of the III-N back barrier and a second portion of the III-N channel layer, the second portion of the III-N channel layer having a second 2DEG channel therein, the forming of the second III-N transistor comprising: thinning a second portion of the III-N channel layer by etching; etching through a portion of the second portion of the III-N channel layer adjacent to an N-face thereof to form a second recess having a second bottom surface; depositing a second gate at least partially in the second recess; and depositing a second source and a second drain, wherein the second gate is deposited between the second source and the second drain; A thickness of a first portion of the III-N channel layer in a region between the first gate and the first drain is greater than 1.2 times a thickness of a second portion of the III-N channel layer in a region between the second gate and the second drain.

29. The method according to claim 28, wherein: Thinning the second portion of the III-N channel layer includes thinning the entire second portion of the III-N channel layer.

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