Internal integrated circuit bus system, address conflict processing method and product

Abstract

The present application relates to the field of server technology and discloses an internal integrated circuit bus system, an address conflict handling method, and a product. The system includes an I2C bus, a conflict handling unit, and an address configuration unit; the I2C bus is connected to a BMC, at least one first slave device, and an external card; the external card integrates a second slave device; the conflict handling unit includes a control circuit between the BMC and each first slave device; the BMC is used to cut off the power supply to all first slave devices through the control circuit, or to cut off the link connecting all first slave devices to the I2C bus through the control circuit; the address configuration unit includes the same number of configuration circuits as all first slave devices; the BMC is also used to send a first signal to the first slave device to modify the address of the first slave device when an address conflict is detected between any first slave device and a second slave device. The present application can detect and self-repair address conflict problems in the I2C bus.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to an internal integrated circuit bus system, an address conflict processing method, and a product. Background Art

[0002] The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus consisting of a serial data line (SDA) and a serial clock line (SCL). It transmits information between connected I2C devices. Each device on the I2C bus has a unique 7-bit binary address. Slave devices connected to the I2C bus communicate with the host by identifying and responding to the address code sent by the master device.

[0003] In the server field, a BMC (Baseboard Management Controller) is typically used as the master device of the I2C bus, and the BMC manages the server through the I2C bus. For I2C devices deployed on the motherboard, the device address can be modified by setting the address configuration pins on the device. An AIC (Add-in Card) is a commonly used expansion device in servers. It usually integrates some external I2C devices and connects to the server's I2C bus through the interface on the PCIE (Peripheral Component Interconnect Express) slot of the add-in card. The BMC cannot modify the address of the add-in card. Since the devices inserted into the add-in card are usually purchased or configured by the user, there is a possibility of address conflicts with the I2C devices on the motherboard. If there are two or more devices with the same address on the I2C bus, it will cause a bus error, unable to communicate normally, causing server failure and affecting business operations. Therefore, it is necessary to find a method to avoid address conflicts on the I2C bus and improve the stability of server operation. Summary of the Invention

[0004] In view of this, the present application aims to propose an internal integrated circuit bus system, an address conflict handling method and a product to avoid address conflicts in the internal integrated circuit bus and improve the stability of server operation.

[0005] To achieve the above objectives, the technical solutions of this application are as follows:

[0006] A first aspect of an embodiment of the present application provides an inter-integrated circuit bus system, comprising: an inter-integrated circuit bus, a conflict handling unit, and an address configuration unit;

[0007] The internal integrated circuit bus is connected to: a baseboard management controller, at least one first slave device and an external plug-in card; at least one second slave device is integrated in the external plug-in card;

[0008] The conflict handling unit includes a control circuit between the baseboard management controller and each first slave device; the baseboard management controller is configured to cut off power to all first slave devices or cut off links connecting all first slave devices to the inter-integrated circuit bus through the control circuit before detecting whether there is an address conflict between the first slave device and the second slave device;

[0009] The address configuration unit includes the same number of configuration circuits as all the first slave devices, and each first slave device is connected to the baseboard management controller via a first signal line; the baseboard management controller is further configured to send a first signal to the first slave device via the first signal line to modify the address of the first slave device when an address conflict is detected between any first slave device and any second slave device.

[0010] Optionally, a protection chip is provided in the control circuit;

[0011] Each first slave device is connected to the protection chip respectively, and the protection chip is also connected to the mainboard power supply;

[0012] The baseboard management controller is connected to the protection chip through a second signal line; the baseboard management controller is specifically used to send a second signal through the second signal line to control the protection chip to cut off or restore its own output power supply.

[0013] Optionally, cutting off the power supply to all first slave devices by the control circuit specifically includes: setting the second signal to a low level to control the protection chip to cut off the power supply of the mainboard power supply to the first slave devices;

[0014] The baseboard management controller is also used to restore the power supply of all first slave devices through the control circuit when it is detected that there is no address conflict between all first slave devices and the second slave devices, specifically including: setting the second signal to a high level to control the protection chip to restore the power supply of the mainboard power supply to the first slave devices.

[0015] Optionally, the control circuit is provided with: transistors having the same number as that of all first slave devices;

[0016] The baseboard management controller is connected to the G pole of each transistor through a third signal line; the D pole of each transistor is connected to the internal integrated circuit bus, and the S pole of each transistor is connected to a first slave device;

[0017] The baseboard management controller is specifically configured to send a third signal through the third signal line to control the transistor to be in an on state or an off state.

[0018] Optionally, cutting off the links connecting all first slave devices to the inter-integrated circuit bus by the control circuit specifically includes: setting a third signal to a low level so that transistors in the links connecting each first slave device to the inter-integrated circuit bus are in an off state;

[0019] The baseboard management controller is further configured to, upon detecting that no address conflict exists between all first slave devices and the second slave devices, restore, through the control circuit, the links connecting all first slave devices to the internal integrated circuit bus, specifically by setting the third signal to a high level so that transistors in the links connecting each first slave device to the internal integrated circuit bus are in an on state.

[0020] Optionally, the configuration circuit is provided with: a motherboard power supply, a transistor, a pull-up resistor, and a pull-down resistor; the baseboard management controller is connected to the G terminal of the transistor via a first signal line; one end of the pull-up resistor is connected to the motherboard power supply, and the other end is connected to the D terminal of the transistor; one end of the pull-down resistor is connected to the S terminal of the transistor, and the other end is connected to an address configuration pin of a first slave device;

[0021] Sending a first signal to the first slave device through the first signal line to modify the address of the first slave device includes:

[0022] Obtaining a current address of the first slave device; the address of the first slave device is determined based on a level state of an address configuration pin of the first slave device;

[0023] determining, based on a current address of the first slave device, a transistor in a configuration circuit connected to an address configuration pin of the first slave device;

[0024] Modifying a first signal output to the transistor so as to switch a level state of an address configuration pin connected to the transistor, specifically comprising:

[0025] Setting the first signal to a high level to turn on the transistor, connecting the address configuration pin to the mainboard power supply through the pull-up resistor, and switching the level of the address configuration pin to a high level;

[0026] Alternatively, the first signal is set to a low level to put the transistor in a cut-off state, the address configuration pin of the first slave device is grounded through the pull-down resistor, and the level state of the address configuration pin is switched to a low level.

[0027] Optionally, the first slave device carries one or three address configuration pins; in the configuration circuit, the number of pull-down resistors is the same as the number of address configuration pins carried by the first slave device.

[0028] Optionally, the resistance ratio of the pull-up resistor to the pull-down resistor is 1:10.

[0029] According to a second aspect of an embodiment of the present application, there is provided an address conflict handling method, which is applied to the inter-integrated circuit bus system provided in the first aspect of the embodiment of the present application, the method comprising:

[0030] After the server is powered on, each first slave device is controlled to initialize its own address;

[0031] Reading and storing the addresses of all first slave devices through the baseboard management controller;

[0032] Cutting off power supply to all first slave devices by the control circuit, or cutting off links connecting all first slave devices to the internal integrated circuit bus by the control circuit;

[0033] Reading addresses of all second devices and detecting whether there is an address conflict between all first slave devices and all second slave devices;

[0034] In the case that an address conflict exists between any first slave device and any second slave device, a first signal is sent to the first slave device via a first signal line to modify the address of the first slave device.

[0035] According to a third aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the address conflict handling method described in the second aspect of the embodiment of the present application are implemented.

[0036] According to the fourth aspect of the embodiments of the present application, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and runnable on the processor. When the processor executes the computer program, the steps in the address conflict handling method described in the second aspect of the embodiments of the present application are implemented.

[0037] The internal integrated circuit bus system provided in the present application includes an I2C bus, a conflict handling unit and an address configuration unit. Wherein, the I2C bus is connected to a baseboard management controller (BMC), one or more first slave devices (slave devices on the mainboard) and an external card, and one or more second slave devices (external slave devices) are integrated in the external card. The conflict handling unit includes a control circuit between the BMC and each first slave device. In this solution, the BMC performs address conflict detection on the first slave device and the second slave device, and controls all first slave devices to stop running through the control circuit before the detection, thereby isolating the first slave device from the second slave device. In the case of an address conflict between the first slave device and the second slave device, the BMC also modifies the address of the first slave device with the address conflict through the configuration circuit in the address configuration unit to achieve address conflict repair.

[0038] In the present application, a conflict processing unit is used to isolate the first slave device on the mainboard before confirming that there are no duplicate addresses on the I2C bus, so as to prevent devices with address conflicts from running together and causing malfunctions. After isolating the first slave device, if there is an address conflict, the address of the first slave device is modified through the configuration circuit, thereby repairing the address conflict problem on the bus, thereby realizing the detection and self-repair of the address conflict problem in the I2C bus, avoiding management failure of the server due to address conflicts in the I2C bus, and improving the stability of the server. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 This is a schematic diagram of the I2C bus architecture in the server;

[0041] Figure 2 This is a framework diagram of an internal integrated circuit bus system proposed in one embodiment of the present application;

[0042] Figure 3 This is one of the architectural diagrams of the I2C bus system proposed in one embodiment of the present application;

[0043] Figure 4 This is the second architectural diagram of the I2C bus system proposed in one embodiment of the present application;

[0044] Figure 5 is a schematic diagram of a configuration circuit in an embodiment of the present application;

[0045] Figure 6 This is a flowchart of an address conflict handling method proposed in one embodiment of the present application;

[0046] Figure 7 FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0048] It should be understood that references throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0049] In the various embodiments of the present application, it should be understood that the size of the serial numbers of the following processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0050] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with certain aspects as detailed herein.

[0051] It should be noted that, unless there is any conflict, the embodiments and features in the embodiments of this application can be combined with each other.

[0052] Figure 1 This is a schematic diagram of the I2C bus architecture in the server. Figure 1The figure shows an I2C bus architecture, where the I2C bus is connected to slave devices (1, 2, 3) on the mainboard side and external slave devices (a, b, c) integrated in plug-in cards. In related art, before a server leaves the factory, when configuring the addresses of slave devices 1, 2, and 3 on the mainboard side, which includes the plug-in card, to avoid address conflicts, an exhaustive method is used to list all possible AIC cards and determine the addresses of the I2C devices that may be integrated thereon. Based on this, the addresses of slave devices 1, 2, and 3 are configured, making the addresses of each device different. However, due to the wide variety of types and models of AIC cards, the addresses of the I2C devices that can be selected on them are also diverse. Using an exhaustive method cannot ensure that address conflicts will not occur. The model of the plug-in card that is preset for the server before leaving the factory may not be the same as the model after leaving the factory. After the server leaves the factory, the user may reconfigure and replace the AIC card, making it difficult to avoid address conflicts on the I2C bus. If an address conflict occurs, communication between devices on the entire bus will be disrupted, and the BMC will be unable to manage the server. For example, if a temperature sensor is installed on the I2C bus, the BMC will be unable to read the temperature and thus unable to adjust the cooling, causing serious problems such as overheating of the server.

[0053] The inter-integrated circuit bus system provided by the present application can avoid address conflicts in the I2C bus, thereby preventing the BMC from failing to manage the server due to address conflicts in the I2C bus.

[0054] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0055] Figure 2 This is a framework diagram of the internal integrated circuit bus system proposed in one embodiment of the present application. Figure 2 As shown, the internal integrated circuit bus system includes: an internal integrated circuit bus, a conflict processing unit and an address configuration unit;

[0056] The internal integrated circuit bus is connected to: a baseboard management controller, at least one first slave device and an external plug-in card; at least one second slave device is integrated in the external plug-in card;

[0057] The conflict handling unit includes a control circuit between the baseboard management controller and each first slave device; the baseboard management controller is configured to cut off power to all first slave devices or cut off links connecting all first slave devices to the inter-integrated circuit bus through the control circuit before detecting whether there is an address conflict between the first slave device and the second slave device;

[0058] The address configuration unit includes the same number of configuration circuits as all the first slave devices, and each first slave device is connected to the baseboard management controller via a first signal line; the baseboard management controller is further configured to send a first signal to the first slave device via the first signal line to modify the address of the first slave device when an address conflict is detected between any first slave device and any second slave device.

[0059] In this embodiment, the internal integrated circuit bus system includes an I2C bus, a conflict handling unit and an address configuration unit. Among them, the I2C bus is connected to the BMC, one or more first slave devices, and an external card. One or more second slave devices are inserted into the slot of the external card. The first slave device is a slave device deployed on the mainboard before the server leaves the factory, and the second slave device is an external slave device. Common first slave devices include: temperature sensor chips for temperature monitoring, FRU (Field Replaceable Unit) chips for board information storage, power monitoring chips for monitoring power supply, etc. Common external cards include: GPU (Graphics Processing Unit, graphics processor) card, FPGA (Field Programmable Gate Array, field programmable logic array) card, NIC (Network Interface Card, network card) and storage expansion card, etc.

[0060] The BMC control conflict handling unit isolates the first slave devices on the motherboard to prevent simultaneous operation of the first and second slave devices in the event of an address conflict between the two, potentially leading to an I2C bus failure. The conflict handling unit includes control circuitry between the BMC and each first slave device. After the server is powered on, the BMC uses this control circuitry to stop all first slave devices. This allows the server to detect the addresses of all first and second slave devices on the bus and determine whether there is an address conflict between them. If an address conflict exists, the configuration circuitry in the address configuration unit modifies the address of the conflicting first slave device.

[0061] The address configuration unit includes multiple configuration circuits, where the number of configuration circuits is equal to the number of first slave devices in the bus. The BMC is connected to a first slave device through each configuration circuit. Each configuration circuit is provided with a first signal line. The BMC sends a first signal via the first signal line to the first slave device whose address needs to be modified, thereby modifying the address of the first slave device and resolving address conflicts in the I2C bus.

[0062] In this embodiment, the BMC, acting as the master device on the I2C bus, uses a conflict handling unit to isolate all first slave devices, preventing the simultaneous operation of first and second slave devices without detecting address conflicts. If an address conflict is detected between a first slave device and a second slave device, the configuration circuit modifies the address of the conflicting first slave device, thereby repairing the address conflict. This enables detection and self-repair of address conflicts on the I2C bus, preventing server management failures caused by address conflicts on the I2C bus and improving server stability.

[0063] As an embodiment of the present application, a protection chip is provided in the control circuit;

[0064] Each first slave device is connected to the protection chip respectively, and the protection chip is also connected to the mainboard power supply;

[0065] The baseboard management controller is connected to the protection chip through a second signal line; the baseboard management controller is specifically used to send a second signal through the second signal line to control the protection chip to cut off or restore its own output power supply.

[0066] Figure 3 This is one of the schematic diagrams of the I2C bus system proposed in one embodiment of the present application. Figure 3 As shown, in one embodiment, the I2C bus is connected to the BMC, three first slave devices (slave 1, slave 2, and slave 3), and three second slave devices (slave a, slave b, and slave c). A protection chip is provided in the control circuit to power devices 1, 2, and 3. The protection chip's input is connected to the motherboard power supply, and its output is connected to each first slave device. The BMC accesses the protection chip via a second signal line and sends a second signal to the protection chip to control the protection chip to output power from the motherboard power supply to each first slave device, or to cut off power to each first slave device.

[0067] As an embodiment of the present application, cutting off the power supply of all first slave devices by the control circuit specifically includes: setting the second signal to a low level to control the protection chip to cut off the power supply of the mainboard power supply to the first slave devices;

[0068] The baseboard management controller is also used to restore the power supply of all first slave devices through the control circuit when it is detected that there is no address conflict between all first slave devices and the second slave devices, specifically including: setting the second signal to a high level to control the protection chip to restore the power supply of the mainboard power supply to the first slave devices.

[0069] In one embodiment, a protection chip is provided in the control circuit, and its output is simultaneously connected to all first slave devices. The baseboard management controller sends a second signal to control the protection chip to uniformly cut off or restore power to all first slave devices. In this embodiment, the control circuit detects the addresses of the first slave devices and the second slave devices in the bus, and the specific steps are as follows:

[0070] (1) After the server is powered on, each first slave device initializes its own communication address through a pull-up or pull-down resistor connected to the motherboard power supply or ground. It is worth noting that the initialization address of each first slave device is different;

[0071] (2) The BMC scans all first slave devices in the link, reads the address of each first slave device, and writes it into the memory;

[0072] (3) On the second signal line connecting the BMC to the protection chip, a pull-down resistor is set to ground, and the second signal is configured to a low level by default. At this time, the protection chip has no output, and slave devices 1, 2, and 3 are not powered. In other words, all first slave devices in the bus are isolated and each first slave device stops operating;

[0073] (4) After the server is powered on, the BMC scans the addresses of all second slave devices (slave device a, slave device b, slave device c) integrated on the AIC plug-in card and compares them with the addresses of all first slave devices previously stored. If the same address appears, it is determined that there is an address conflict between the first slave device and the second slave device; if the same address does not exist, it means that there is no address conflict between the first slave device and the second slave device in the bus.

[0074] (5) When there is no address conflict between the first slave device and the second slave device, the BMC sends a second signal to the protection chip through the second signal line, sets the second signal to a high level, and the protection chip starts to output power, restoring power to slave device 1, slave device 2, and slave device 3, and all first slave devices start to operate.

[0075] In this embodiment, by including a protection chip in the control circuit, the BMC can uniformly control the power supply status (power on or off) of all first slave devices. The BMC only needs to send the second signal once to uniformly isolate or release all first slave devices, which facilitates operation, eliminates the need for complex circuit layout, and reduces equipment costs.

[0076] In one embodiment, the control circuit is provided with the same number of protection chips as first slave devices to increase the flexibility of the control circuit. Specifically, the BMC is connected to each protection chip via a second signal line, and the output of each protection chip is connected to a corresponding first slave device. In this embodiment, the baseboard management controller can send a second signal to one or more protection chips via the second signal line, thereby controlling the protection chips to cut off or restore power to one or more first slave devices.

[0077] Based on the control circuit structure of this embodiment, if the BMC needs to modify the address of a first slave device with an address conflict, it can send a second signal to the protection chip connected to other first slave devices that do not require address modification. This control chip then restores power to the other first slave devices on the bus that do not have address conflicts, allowing them to resume operation. This allows the majority of devices without address conflicts to quickly operate after power is applied to the server, reducing latency and eliminating the need to wait for individual first slave devices to modify their addresses, thereby improving the server's overall response efficiency.

[0078] As an embodiment of the present application, the control circuit is provided with: transistors having the same number as all first slave devices;

[0079] The baseboard management controller is connected to the G pole of each transistor through a third signal line; the D pole of each transistor is connected to the internal integrated circuit bus, and the S pole of each transistor is connected to a first slave device;

[0080] The baseboard management controller is specifically configured to send a third signal through the third signal line to control the transistor to be in an on state or an off state.

[0081] Figure 4 This is the second schematic diagram of the I2C bus system architecture proposed in one embodiment of the present application. Figure 4As shown, in one embodiment, the I2C bus is connected to the BMC, three first slave devices (slave device 1, slave device 2, slave device 3) and three second slave devices (slave device a, slave device b, slave device c). The control circuit is provided with multiple NMOS (N-Metal Oxide Semiconductor) tubes, each of which is provided in the circuit where a first slave device is connected to the I2C bus. The D pole of each NMOS tube is connected to a serial data line SDA and a serial clock line SCL of the I2C bus, the S pole of the NMOS tube is connected to a first slave device, and the G pole of each NMOS tube is connected to the BMC via a third signal line. The BMC sends a third signal via the third signal line to control each NMOS tube to be in the on or off state, thereby controlling the on and off state of the two links (SDA / SCL) of each first slave device connected to the I2C bus.

[0082] As an embodiment of the present application, cutting off the links connecting all first slave devices to the internal integrated circuit bus by the control circuit specifically includes: setting the third signal to a low level so that the crystals in the links connecting each first slave device to the internal integrated circuit bus are in a cut-off state;

[0083] The baseboard management controller is further configured to, upon detecting that no address conflict exists between all first slave devices and the second slave devices, restore, through the control circuit, the links connecting all first slave devices to the internal integrated circuit bus, specifically by setting the third signal to a high level so that transistors in the links connecting each first slave device to the internal integrated circuit bus are in an on state.

[0084] In one embodiment, a third signal line is provided in the control circuit and is simultaneously connected to each NMOS transistor. The BMC sends a third signal based on the third signal line to control each NMOS transistor to be simultaneously turned on or off. In this embodiment, the control circuit detects the addresses of the first and second slave devices in the bus, and the specific steps are as follows:

[0085] (1) After the server is powered on, each first slave device initializes its own communication address through a pull-up or pull-down resistor connected to the motherboard power supply or ground. It is worth noting that the initialization address of each first slave device is different;

[0086] (2) The BMC scans all first slave devices in the link, reads the address of each first slave device, and writes it into the memory;

[0087] (3) A pull-down resistor connected to the ground is set on the third signal line, and the third signal is configured to a low level by default through the BMC. At this time, all NMOS transistors are in the cut-off state, and slave devices 1, 2, and 3 are not connected to the I2C bus. Each first slave device stops running;

[0088] (4) After the server is powered on, the BMC scans the addresses of all second slave devices (slave device a, slave device b, slave device c) integrated on the AIC plug-in card and compares them with the addresses of all first slave devices previously stored. If the same address appears, it is determined that there is an address conflict between the first slave device and the second slave device; if the same address does not exist, it means that there is no address conflict between the first slave device and the second slave device in the bus;

[0089] (5) When there is no address conflict between the first slave device and the second slave device, the BMC sends a third signal through the third signal line, sets the third signal to a high level to turn on all NMOS transistors, connects slave device 1, slave device 2, and slave device 3 to the I2C bus, and all first slave devices start to operate.

[0090] In this embodiment, by providing a third signal line in the control circuit and connecting all NMOS transistors to this third signal line, the BMC can uniformly control the link status of all first slave devices connected to the I2C bus. The BMC only needs to send the third signal once to uniformly isolate or release all first slave devices, which facilitates operation, eliminates the need for complex circuitry and multiple protection chips, and reduces equipment costs.

[0091] In one embodiment, multiple third signal lines are configured in the circuit to increase the flexibility of the control circuit. Specifically, the BMC accesses the G terminal of the NMOS transistor connected to each first slave device via multiple third signal lines. The BMC sends a third signal via each third signal line to control the on / off state of each NMOS transistor. In this embodiment, the BMC can control the on / off state of the link connecting one or more first slave devices to the I2C bus by sending a third signal to one or more NMOS transistors.

[0092] Based on the control circuit structure of this embodiment, if the BMC needs to modify the address of a first slave device with an address conflict, it can send a third signal to the NMOS transistor connected to the first slave device that does not need address modification, thereby controlling the corresponding NMOS transistor to conduct, thereby connecting the first slave device without an address conflict to the I2C bus. This allows the majority of devices without address conflicts to operate quickly after the server is powered on, reducing latency and eliminating the need to wait for individual first slave devices to modify their addresses, thereby improving the server's overall response efficiency.

[0093] As an embodiment of the present application, the configuration circuit is provided with: a motherboard power supply, a transistor, a pull-up resistor, and a pull-down resistor; the baseboard management controller is connected to the G terminal of the transistor via a first signal line; one end of the pull-up resistor is connected to the motherboard power supply, and the other end is connected to the D terminal of the transistor; one end of the pull-down resistor is connected to the S terminal of the transistor, and the other end is connected to an address configuration pin of a first slave device;

[0094] Sending a first signal to the first slave device through the first signal line to modify the address of the first slave device includes:

[0095] Obtaining a current address of the first slave device; the address of the first slave device is determined based on a level state of an address configuration pin of the first slave device;

[0096] determining, based on a current address of the first slave device, a transistor in a configuration circuit connected to an address configuration pin of the first slave device;

[0097] Modifying a first signal output to the transistor so as to switch a level state of an address configuration pin connected to the transistor, specifically comprising:

[0098] Setting the first signal to a high level to turn on the transistor, connecting the address configuration pin to the mainboard power supply through the pull-up resistor, and switching the level of the address configuration pin to a high level;

[0099] Alternatively, the first signal is set to a low level to put the transistor in a cut-off state, the address configuration pin of the first slave device is grounded through the pull-down resistor, and the level state of the address configuration pin is switched to a low level.

[0100] Figure 5 Schematic diagram of the configuration circuit in one embodiment of the present application. Figure 5 As shown, in this embodiment, the configuration circuit includes a mainboard power supply, an NMOS tube, a pull-up resistor and a pull-down resistor; the baseboard management controller is connected to the G pole of the NMOS tube through a first signal line; one end of the pull-up resistor is connected to the mainboard power supply, and the other end is connected to the D pole of the NMOS tube; one end of the pull-down resistor is connected to the S pole of the NMOS tube, and the other end is connected to an address configuration pin of a first slave device.

[0101] In the above embodiment, when the BMC detects an address conflict between the first slave device and the second slave device, the BMC modifies the address of the first slave device through the configuration circuit. Specifically, the steps to modify the address of the first slave device are as follows:

[0102] (1) Obtain the current address of the first slave device whose address needs to be modified;

[0103] (2) determining an NMOS transistor of a configuration circuit connected to an address configuration pin of the first slave device based on the current address of the first slave device;

[0104] (3) Modify the first signal output to the G terminal of the NMOS transistor in the configuration circuit to change the level state of each address configuration pin of the first slave device. Specifically, set the first signal to a high level to turn on the NMOS transistor; set the first signal to a low level to turn off the NMOS transistor.

[0105] The address configuration pin carried by the first slave device indicates the upper limit of the number of addresses that the device can configure, and the number of address configuration pins connected to the NMOS tube in the configuration circuit is the number of different addresses that can be modified at present. Figure 5 As an example, the configuration circuit shown in the figure has 3 address configuration pins, which means that it can achieve 2^3 address switching, but Figure 5 In the circuit, only the NMOS tube is connected to the A0 pin, and the A1 and A2 pins are fixed to the ground. Therefore, the only pin with a variable level state is A0. Figure 5 The first slave device can only switch between two different addresses. If you want to change the voltage level of pins A1 and A2 to switch between eight different addresses, you need to add two NMOS transistors to the configuration circuit and connect them to pins A1 and A2 respectively.

[0106] Specifically, when the NMOS is in the off state, the three address configuration pins A0, A1, and A2 are grounded by pull-down resistors R2, R3, and R4, respectively. That is, pins A0, A1, and A2 are all low, and the address (last three digits) of the first slave device is configured as 1010_000. When the BMC sets the first signal output to the G electrode of the NMOS tube to a high level, the NMOS tube is in the on state, connecting the A0 pin of the first slave device to the motherboard power supply through R1, setting the input level of the A0 pin to a high level, and thus configuring the address (last three digits) of the first slave device to 1010_001.

[0107] As an implementation manner of the present application, the first slave device carries one or three address configuration pins; in the configuration circuit, the number of pull-down resistors is the same as the number of address configuration pins carried by the first slave device.

[0108] In the above embodiment, the address configuration of the first slave device is achieved by setting the high and low levels of the address configuration pins on the chip. Specifically, the addresses that can be configured by the first slave device are pre-set and correspond to the level states of the respective address configuration pins. By changing the level states of the address configuration pins, the first slave device is controlled to switch its own address. For example, Figure 5 For the first slave device in the example, the levels of pins A0, A1, and A2 are "high, low, low", and the corresponding address is "1010_001".

[0109] The number of selectable addresses is related to the number of address configuration pins carried by the first slave device. One address configuration pin can distinguish between two different addresses based on a high level or a low level. For a first slave device with three address configuration pins, 2^3 = 8 different address switching options can be achieved. In this embodiment, the first slave device has one or three address configuration pins, and the number of pull-down resistors is the same as the number of address configuration pins.

[0110] As an implementation manner of the present application, the resistance ratio of the pull-up resistor to the pull-down resistor is 1:10.

[0111] In the above embodiment, the voltage level of the address configuration pin is actually determined by the ratio of the pull-up resistor to the pull-down resistor. When the motherboard power supply voltage is 3.3V, the pull-up resistor and the pull-down resistor are connected in parallel and each receives a portion of the voltage component. To set the address configuration pin to a high level, the voltage component allocated to the pull-down resistor only needs to exceed the threshold for determining a high level. Typically, a voltage exceeding 2V is considered a high level. Therefore, using 2V as the threshold, the ratio of the pull-up resistor to the pull-down resistor needs to be less than approximately 0.65.

[0112] In order to facilitate the selection of resistor elements with corresponding resistance values ​​when laying out the configuration circuit, facilitate calculation, increase the redundancy of the device in judging the level state, and prevent the level state recognition error caused by voltage instability, in one embodiment, the resistance ratio of the pull-up resistor to the pull-down resistor is set to 1:10. That is, Figure 5 The input level of the A0 pin is 3V, which is recognized as a high level by the first slave device.

[0113] Based on the same inventive concept, an embodiment of the present application provides a method for handling address conflicts. Figure 6 , Figure 6 This is a flow chart of the address conflict handling method proposed in one embodiment of the present application. Figure 6 As shown, the method includes:

[0114] S1: After the server is powered on, each first slave device is controlled to initialize its own address;

[0115] S2: Read and store the addresses of all first slave devices through the baseboard management controller;

[0116] S3: Cutting off power supply to all first slave devices by the control circuit, or cutting off links connecting all first slave devices to the internal integrated circuit bus by the control circuit;

[0117] S4: Reading the addresses of all second devices and detecting whether there is an address conflict between all first slave devices and all second slave devices;

[0118] S5: When there is an address conflict between any first slave device and any second slave device, send a first signal to the first slave device via a first signal line to modify the address of the first slave device.

[0119] As an implementation manner of the present application, cutting off power supply to all first slave devices by the control circuit includes:

[0120] The second signal is set to a low level to control the protection chip to cut off the power supply of the mainboard power supply to the first slave device.

[0121] As an embodiment of the present application, cutting off the links connecting all first slave devices to the internal integrated circuit bus by the control circuit includes:

[0122] The third signal is set to a low level to turn off transistors in the link connecting each first slave device to the inter-IC bus.

[0123] As an embodiment of the present application, when an address conflict is detected between any first slave device and any second slave device, sending a first signal to the first slave device through the first signal line to modify the address of the first slave device includes:

[0124] Obtaining a current address of the first slave device; the address of the first slave device is determined based on a level state of an address configuration pin of the first slave device;

[0125] determining, based on a current address of the first slave device, a transistor in a configuration circuit connected to an address configuration pin of the first slave device;

[0126] Modifying a first signal output to the transistor so as to switch a level state of an address configuration pin connected to the transistor, specifically comprising:

[0127] Setting the first signal to a high level to turn on the transistor, connecting the address configuration pin to the mainboard power supply through the pull-up resistor, and switching the level of the address configuration pin to a high level;

[0128] Alternatively, the first signal is set to a low level to put the transistor in a cut-off state, the address configuration pin of the first slave device is grounded through the pull-down resistor, and the level state of the address configuration pin is switched to a low level.

[0129] As an implementation manner of the present application, the address conflict handling method further includes:

[0130] After modifying the address of the first slave device, re-detecting whether there is an address conflict between all the first slave devices and all the second slave devices;

[0131] When it is detected that there is no address conflict between all the first slave devices and the second slave device, the control circuit restores power to all the first slave devices or restores the links of all the first slave devices connected to the internal integrated circuit bus.

[0132] As an implementation manner of the present application, restoring power to all first slave devices by the control circuit includes:

[0133] The second signal is set to a high level to control the protection chip to restore the power supply of the mainboard power supply to the first slave device.

[0134] As an embodiment of the present application, restoring the links of all first slave devices connected to the internal integrated circuit bus by the control circuit includes:

[0135] The third signal is set to a high level to turn on transistors in a link connecting each first slave device to the inter-IC bus.

[0136] Based on the same inventive concept, an embodiment of the present application provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements the steps of the address conflict handling method described in any of the above embodiments of the present application.

[0137] Based on the same inventive concept, an embodiment of the present application provides a readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps of the address conflict handling method described in any of the above embodiments of the present application are implemented.

[0138] Based on the same inventive concept, an embodiment of the present application provides an electronic device. Figure 7 Schematic diagram of an electronic device according to an embodiment of the present application. Figure 7 As shown, the electronic device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the address conflict handling method described in any of the above embodiments of the present application are implemented.

[0139] Regarding the method in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the internal integrated circuit bus system and will not be elaborated here.

[0140] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

[0141] For the sake of simplicity, the method embodiments are described as a series of action combinations. However, those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and components involved are not necessarily required by this application.

[0142] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0143] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0144] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0145] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0146] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the underlying inventive concepts. Therefore, this application is intended to include the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0147] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0148] The above is a detailed introduction to the internal integrated circuit bus system, address conflict handling method and product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An intra-integrated circuit bus system, characterized in that: include: Inter-IC bus, conflict handling unit and address configuration unit; The internal integrated circuit bus is connected to: a baseboard management controller, at least one first slave device and an external plug-in card; at least one second slave device is integrated in the external plug-in card; The conflict processing unit includes a control circuit between the baseboard management controller and each first slave device; The baseboard management controller is configured to, before detecting whether there is an address conflict between the first slave device and the second slave device, cut off power to all first slave devices through the control circuit, or cut off links connecting all first slave devices to the internal integrated circuit bus through the control circuit; The address configuration unit includes the same number of configuration circuits as all the first slave devices, and each first slave device is connected to the baseboard management controller via a first signal line; the baseboard management controller is further configured to send a first signal to the first slave device via the first signal line to modify the address of the first slave device when an address conflict is detected between any first slave device and any second slave device.

2. The intra-IC bus system according to claim 1, wherein: A protection chip is provided in the control circuit; Each first slave device is connected to the protection chip respectively, and the protection chip is also connected to the mainboard power supply; The baseboard management controller is connected to the protection chip through a second signal line; The baseboard management controller is specifically configured to send a second signal through the second signal line to control the protection chip to cut off or restore its own output power supply.

3. The intra-IC bus system according to claim 2, wherein: Cutting off the power supply of all first slave devices by the control circuit specifically includes: setting the second signal to a low level to control the protection chip to cut off the power supply of the mainboard power supply to the first slave devices; The baseboard management controller is also used to restore the power supply of all first slave devices through the control circuit when it is detected that there is no address conflict between all first slave devices and the second slave devices, specifically including: setting the second signal to a high level to control the protection chip to restore the power supply of the mainboard power supply to the first slave devices.

4. The intra-IC bus system according to claim 1, wherein: The control circuit is provided with: transistors having the same number as all the first slave devices; The baseboard management controller is connected to the G pole of each transistor through a third signal line; the D pole of each transistor is connected to the internal integrated circuit bus, and the S pole of each transistor is connected to a first slave device; The baseboard management controller is specifically configured to send a third signal through the third signal line to control the transistor to be in an on state or an off state.

5. The inter-IC bus system according to claim 4, wherein: Cutting off the links connecting all first slave devices to the internal integrated circuit bus by the control circuit specifically includes: setting the third signal to a low level so that the transistors in the links connecting each first slave device to the internal integrated circuit bus are in a cut-off state; The baseboard management controller is further configured to, upon detecting that no address conflict exists between all first slave devices and the second slave devices, restore, through the control circuit, the links connecting all first slave devices to the internal integrated circuit bus, specifically by setting the third signal to a high level so that transistors in the links connecting each first slave device to the internal integrated circuit bus are in an on state.

6. The inter-IC bus system according to claim 1, wherein: The configuration circuit is provided with: a motherboard power supply, a transistor, a pull-up resistor, and a pull-down resistor; the baseboard management controller is connected to the G terminal of the transistor via a first signal line; one end of the pull-up resistor is connected to the motherboard power supply, and the other end is connected to the D terminal of the transistor; one end of the pull-down resistor is connected to the S terminal of the transistor, and the other end is connected to an address configuration pin of a first slave device; Sending a first signal to the first slave device through the first signal line to modify the address of the first slave device includes: Obtaining a current address of the first slave device; the address of the first slave device is determined based on a level state of an address configuration pin of the first slave device; determining, based on a current address of the first slave device, a transistor in a configuration circuit connected to an address configuration pin of the first slave device; Modifying a first signal output to the transistor so as to switch a level state of an address configuration pin connected to the transistor, specifically comprising: Setting the first signal to a high level to turn on the transistor, connecting the address configuration pin to the mainboard power supply through the pull-up resistor, and switching the level of the address configuration pin to a high level; Alternatively, the first signal is set to a low level to put the transistor in a cut-off state, the address configuration pin of the first slave device is grounded through the pull-down resistor, and the level state of the address configuration pin is switched to a low level.

7. The inter-IC bus system according to claim 6, wherein: The first slave device carries one or three address configuration pins; in the configuration circuit, the number of pull-down resistors is the same as the number of address configuration pins carried by the first slave device.

8. The inter-IC bus system according to claim 6, wherein: The resistance ratio of the pull-up resistor to the pull-down resistor is 1:

10.

9. A method for handling address conflicts, characterized in that: The intra-integrated circuit bus system according to any one of claims 1 to 8 comprises: After the server is powered on, each first slave device is controlled to initialize its own address; Reading and storing the addresses of all first slave devices through the baseboard management controller; Cutting off power supply to all first slave devices by the control circuit, or cutting off links connecting all first slave devices to the internal integrated circuit bus by the control circuit; Reading addresses of all second devices and detecting whether there is an address conflict between all first slave devices and all second slave devices; In the case that an address conflict exists between any first slave device and any second slave device, a first signal is sent to the first slave device via a first signal line to modify the address of the first slave device.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the method according to claim 9 are implemented.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps in the method according to claim 9 are implemented.

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