Semiconductor device and manufacturing method thereof

Abstract

A method of fabricating a semiconductor device includes providing a substrate, forming a first trench in the substrate, the top width of the first trench being greater than the bottom width of the first trench, forming a well and a source region on one side of the first trench, the source region on the well, forming a hard mask stack along a surface of the substrate, forming a second trench in the hard mask stack, and forming a second trench in the second trench. The bottom of the second trench is located above the corner of the first trench, performing an ion implantation process to form a shielding doped region in a region of the substrate close to the corner of the first trench, removing the hard mask stack, forming a gate dielectric layer along a surface of the substrate, the gate dielectric layer covering the shielding doped region, and forming a gate in the first trench. Some embodiments of the invention can be used for forming a gate with a wide upper part and a narrow lower part, so that the shielding doped region formed at the corner of the gate is not easy to shield the path of an electron flow, thereby reducing the resistance of the semiconductor device.

Description

Technical Field

[0001] Some embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Trench gate is one of the most common gate types in semiconductor devices. Compared with planar gate, trench gate can be used to save the distance between gates to increase the number of gates per unit area. A strong electric field is easily generated at the bottom of the trench gate, which increases the leakage current and even damages the insulating layer. Generally speaking, a shielding doping region is formed at the bottom of the trench gate to eliminate the strong electric field, so that the leakage current of the semiconductor device is reduced. Summary of the invention

[0003] Some embodiments of the present invention provide a method for manufacturing a semiconductor device, including providing a substrate, forming a first trench in the substrate, wherein the top width of the first trench is greater than the bottom width of the first trench, forming a well and a source region on one side of the first trench, wherein the source region is on the well, forming a hard mask stack along the surface of the substrate, defining a second trench by a mask, and wherein the bottom of the second trench is located above a corner of the first trench; performing an ion implantation process to form a shielding doped region at the corner of the first trench, removing the hard mask stack, forming a gate dielectric layer along the surface of the substrate, and wherein the gate dielectric layer covers the shielding doped region, and forming a gate in the first trench.

[0004] Some embodiments of the present invention provide a semiconductor device, comprising a substrate, a gate dielectric layer, a shielding doping, a well and a source region. The gate extends downward from the surface of the substrate, and the top width of the gate is wider than the bottom width of the gate. The gate dielectric layer is between the substrate and the gate. The shielding doping region is in the substrate and at the corner of the gate and under the gate dielectric layer. The well is in the substrate and on one side of the gate dielectric layer. The source region is in the substrate and on one side of the gate dielectric layer, and the source region is on the well.

[0005] Some embodiments of the present invention may be used to form a gate that is wide at the top and narrow at the bottom, so that the shielding doping region formed at the corner of the gate is less likely to block the path of electron flow, thereby reducing the resistance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 5 A cross-sectional view illustrating a process of manufacturing a semiconductor device according to some embodiments of the present invention is shown.

[0007] Figure 6 A cross-sectional view is shown of another embodiment of forming a first trench according to the present invention.

[0008] Figures 7 to 13 A cross-sectional view is shown of another embodiment of forming a first trench according to the present invention. DETAILED DESCRIPTION

[0009] Some embodiments of the present invention may be used to form a gate that is wide at the top and narrow at the bottom, so that the shielding doping region formed at the corner of the gate is less likely to block the path of electron flow, thereby reducing the resistance of the semiconductor device.

[0010] Figures 1 to 5 FIG. 1 is a cross-sectional view showing a process of a semiconductor device 100 according to some embodiments of the present invention. Figure 1 , providing a substrate 102, which can be made of silicon carbide, silicon, gallium nitride, gallium arsenide, indium phosphide. In some embodiments, the substrate 102 is N-type and can include N-type dopants, such as arsenic, phosphorus, and nitrogen. The substrate 102 can be a lightly doped substrate.

[0011] A hard mask layer 110 is formed on the substrate 102 . The hard mask layer 110 may be made of silicon dioxide, silicon nitride, or a combination thereof. The total thickness of the hard mask layer 110 is 1 micrometer to 5 micrometers, for example, 3 micrometers.

[0012] Next, the hard mask layer 110 is patterned. The hard mask layer 110 can be patterned in the following manner: a patterned photoresist layer is formed on the hard mask layer 110. In some embodiments, a spin coating process can be used to form the patterned photoresist layer. In some embodiments, the total thickness of the patterned photoresist layer is greater than 3 microns. In some embodiments, the total thickness of the patterned photoresist layer is 1 micron to 3 microns greater than the total thickness of the hard mask layer 110. Next, the patterned photoresist layer is exposed using a photomask, and the patterned photoresist layer PR1 is developed to remove the exposed area and leave the unexposed area. Next, a first etching process is performed on the hard mask layer 110 through the patterned photoresist layer to form an inverted trapezoidal opening O1 in the hard mask layer 110. Performing the first etching process includes adjusting at least one of a plurality of etching parameters, and the etching parameters include etching gas concentration and etching energy. For example, the etching parameters may be adjusted as the etching depth of the hard mask layer 110 changes, so that the etching gas in the etching process has different etching capabilities on the hard mask layer 110 at different etching depths, thereby forming an inverted trapezoidal opening O1. In some embodiments, as the etching depth of the hard mask layer 110 becomes deeper and deeper, the etching gas concentration may become smaller and smaller or the etching energy may become smaller and smaller. After patterning the hard mask layer 110, the patterned photoresist layer may be removed.

[0013] Next, a second etching process is performed on the substrate 102 through the hard mask layer 110 to form a first trench T1 in the substrate 102, wherein the top width of the first trench T1 is greater than the bottom width of the first trench T1. During the second etching process, multiple etching parameters of the second etching process are maintained consistent. The etching parameters include etching gas concentration and etching energy. In this way, the etching gas can naturally etch the first trench T1 in the substrate 102. In some embodiments, the first trench T1 can have an inclined sidewall like the sidewall of the inverted trapezoidal opening O1 of the hard mask layer 110. After the first trench T1 is formed, the hard mask layer 110 can be removed.

[0014] In some embodiments, after removing the hard mask layer 110, a thermal oxidation process may be used to form a sacrificial oxide layer on the substrate 102, and the sacrificial oxide layer may be used to repair the surface of the substrate 102 damaged when etching the substrate 102, so that the surface of the substrate 102 may become smoother. Then, a wet etching process may be used to remove the sacrificial oxide layer.

[0015] refer to Figure 2 , a well 132, a source region 134, and a base region 136 are formed on one side of the first trench T1, the source region 134 is on the well 132, and the base region 136 is on the well 132 and adjacent to the source region 134. The bottom of the well 132 may be higher than the bottom of the first trench T1. The well 132 and the base region 136 may have the second semiconductor type, and the source region 134 may have the first semiconductor type. In some embodiments, the well 132 and the base region 136 may be P-type and include P-type dopants, such as boron, gallium, and aluminum. The well 132 may be a lightly doped region, and the base region 136 may be a heavily doped region. The source region 134 may be N-type and include N-type dopants, such as arsenic, phosphorus, and nitrogen. The source region 134 may be a heavily doped region. The well 132 , the source region 134 , and the base region 136 may be formed in any suitable order. For example, the well 132 may be formed in the substrate 102 first, followed by the source region 134 , and finally the base region 136 .

[0016] Next, a hard mask stack 140 is formed along the surface of the substrate 102, wherein the hard mask stack 140 includes, from bottom to top, a first hard mask sublayer, a second hard mask sublayer, and a third hard mask sublayer, the first hard mask sublayer and the third hard mask sublayer are made of a first material, and the second hard mask sublayer is made of a second material different from the first material. In some embodiments, the first hard mask sublayer is made of silicon dioxide and has a thickness of 50 nanometers, the second hard mask sublayer is made of silicon nitride and has a thickness of 50 nanometers, and the third hard mask sublayer is made of silicon dioxide and has a thickness of 1 micrometer to 2 micrometers.

[0017] refer to Figure 3A second trench T2 is formed in the hard mask stack 140, and the bottom of the second trench T2 is located above the corner C of the first trench T1. Specifically, a photoresist layer is formed on the hard mask stack 140, and then the photoresist layer is exposed using a photomask, and the photoresist layer is developed to leave an unexposed area of ​​the photoresist layer.

[0018] Next, a second trench T2 is formed in the hard mask stack 140 using the photoresist layer as an etching mask. In some embodiments, the bottom of the second trench T2 is on the upper surface of the first hard mask sublayer, that is, the second trench T2 penetrates the second hard mask sublayer and the third hard mask sublayer but does not penetrate the first hard mask sublayer. In some embodiments, the bottom of the second trench T2 may also be on the upper surface of the second hard mask sublayer, that is, the second trench T2 penetrates the third hard mask sublayer but does not penetrate the first hard mask sublayer and the second hard mask sublayer. In this way, when the second trench T2 is formed and the subsequent ion implantation process is performed, the surface of the substrate 102 will not be damaged. After the second trench T2 is formed, the photoresist layer can be removed.

[0019] Next, an ion implantation process is performed, using the hard mask stack 140 as a mask to implant ions from the second trench T2 into the region of the substrate 102 near the corner C of the first trench T1 to form a shielding doping region 138. The shielding doping region 138 may be P-type and include P-type dopants, such as boron, gallium, and aluminum. The shielding doping region 138 may be a heavily doped region. In some embodiments, the shielding doping region 138 may be lower than the well 132. The shielding doping region 138 may be used to increase the breakdown voltage and mitigate the gate leakage problem during the operation of the semiconductor device 100.

[0020] Next, refer to Figure 4 , remove the hard mask stack 140, and perform an annealing process to activate the doped regions, such as the well 132, the source region 134, the base region 136, and the shielding doped region 138. The annealing process can be performed at a temperature of 1500 to 1800 degrees Celsius. In some embodiments, before the annealing process, a graphite protective layer can be formed on the substrate 102 to prevent atoms of the substrate 102 from desorbing at high temperatures to form a rough surface. The graphite protective layer can be made by baking a photoresist material. After the annealing process, the graphite protective layer is removed.

[0021] refer to Figure 4 , a gate dielectric layer 150 is formed along the surface of the substrate 102 to cover the shielding doped region 138, the source region 134, and the base region 136. In some embodiments, a thermal oxidation process can be used to form the gate dielectric layer 150 on the substrate 102. In some embodiments, the thickness of the gate dielectric layer 150 is between 40 nanometers and 50 nanometers. In some embodiments, the gate dielectric layer 150 can be made of silicon dioxide or other high-k oxides, and the gate dielectric layer 150 can also be made of a composite material.

[0022] Next, a gate 160 is formed in the first trench T1. The gate 160 may be formed by depositing a gate material layer on the gate dielectric layer 150 and completely filling the first trench T1. Next, the gate material layer 162 is etched back to form the gate 160 in the first trench T1. The upper surface of the gate 160 may be 40 nanometers to 50 nanometers lower than the upper surface of the gate material layer 162. In some embodiments, the gate 160 may be made of polysilicon, tantalum silicide, titanium silicide, or tungsten silicide.

[0023] Next, a thermal oxidation process may be used to form a sacrificial oxide layer 170 on the upper surface of the gate 160. In some embodiments, the thickness of the sacrificial oxide layer 170 is between 40 nanometers and 50 nanometers. In some embodiments, the upper surface of the sacrificial oxide layer 170 is flush with the upper surface of the gate dielectric layer 150. The sacrificial oxide layer 170 may be used to repair the surface of the gate 160 that is damaged when etching the gate 160, so that the surface of the gate 160 may become smoother.

[0024] refer to Figure 5 A planarization process is performed to remove the redundant gate dielectric layer 150 and the sacrificial oxide layer 170 to expose the source region 134, the base region 136 and the gate 160. Then, a source contact 180 is formed on the base region 136, and a drain electrode 190 is formed under the substrate 102. Thus, the semiconductor device 100 is obtained.

[0025] The semiconductor device 100 includes a substrate 102, a gate 160, a gate dielectric layer 150, a shielding doped region 138, a well 132, a source region 134, and a base region 136. The gate 160 extends downward from the surface of the substrate 102, and the top width of the gate 160 is greater than the bottom width of the gate 160. The gate dielectric layer 150 is between the substrate 102 and the gate 160. The shielding doped region 138 is in the substrate 102 and under the corner C of the gate 160 and the gate dielectric layer 150. The well 132 is in the substrate 102 and on one side of the gate dielectric layer 150. The source region 134 is in the substrate 102 and on one side of the gate dielectric layer 150, and the source region 134 is on the well 132. The base region 136 is on the well 132 and adjacent to the source region 134. The bottom of the well 132 is higher than the shielding doped region 138, and the bottom of the well 132 is higher than the bottom of the gate 160. The substrate 102 and the source region 134 have a first semiconductor type, and the shielding doped region 138, the well 132 and the base region 136 have a second semiconductor type, and the first semiconductor type is different from the second semiconductor type. The semiconductor device 100 may further include a source contact 180 and a drain electrode 190. The source contact 180 is on the base region 136, and the drain electrode 190 is below the substrate 102.

[0026] When voltage is applied to the gate 160 and the source contact 180, the direction of the electron flow EF of the semiconductor device 100 is as follows: Figure 5 As shown. Since the gate 160 of the semiconductor device 100 is a trapezoid, the shielding doping region 138 formed at the corner C of the gate 160 will not block the direction of the electron flow EF. In this way, the shielding doping region 138 can not only be used to increase the breakdown voltage during the operation of the semiconductor device 100, but also alleviate the gate leakage problem. The shielding doping region 138 will not block the direction of the electron flow EF, so the resistance of the semiconductor device 100 can also be reduced. In some embodiments, the gate 160 has an inclined sidewall, and the sidewall of the gate 160 forms an angle a1 with the bottom of the gate 160, and the angle a1 is between 100 degrees and 130 degrees, for example, 113 degrees. When the angle a1 is within the above-disclosed range, the shielding doping region 138 is not easy to block the electron flow EF, so the resistance of the semiconductor device 100 can be reduced. If the angle a1 is less than the above-disclosed range, the shielding doping region 138 may block the electron flow EF, so the resistance of the semiconductor device 100 cannot be reduced. If the angle a1 is larger than the above-disclosed range, the distance between the gates 160 cannot be reduced, so that the number of the gates 160 contained per unit area is also reduced.

[0027] Figure 6 FIG. 2 is a cross-sectional view showing another embodiment of forming the first trench T1 according to the present invention.

[0028] A first etching process is performed on the hard mask layer 110 through the patterned photoresist layer, and an opening O2 having a vertical sidewall is formed in the hard mask layer 110. During the first etching process, etching parameters are maintained consistent, and the etching parameters include etching gas concentration and etching energy, so that the etching gas in the etching process has the same etching ability on the hard mask layer 110 at different etching depths, thereby forming an opening O2 having a vertical sidewall.

[0029] Next, a second etching process is performed on the substrate 102 through the hard mask layer 110 to form a first trench T1 in the substrate 102. Performing the second etching process includes adjusting at least one of the etching parameters, and the etching parameters include etching gas concentration and etching energy. For example, the etching parameters can be adjusted as the etching depth of the substrate 102 changes, so that the etching gas in the etching process has different etching capabilities on the substrate 102 at different etching depths, thereby forming the first trench T1. In some embodiments, as the etching depth of the substrate 102 becomes deeper and deeper, the etching gas concentration can become smaller and smaller or the etching energy can become smaller and smaller.

[0030] Figures 7 to 13 FIG. 4 is a cross-sectional view of another embodiment of forming the first trench T1 of the present invention. Specifically, Figures 7 to 12In the embodiment, a stepped dielectric layer stack 200 is formed on the substrate 102, and then, referring to Fig.13 The substrate 102 is etched through the stepped dielectric layer stack 200 to form a first trench T1 in the substrate 102 .

[0031] refer to Figure 7 , a dielectric layer stack 210 is formed on the substrate 102, the dielectric layer stack 210 includes a plurality of first dielectric layers 212 and a plurality of second dielectric layers 214 stacked in an alternating manner, the first dielectric layer 212 is made of a third material, the second dielectric layer 214 is made of a fourth material different from the third material, and the third material and the fourth material have a high etching selectivity. In some embodiments, the first dielectric layer 212 is made of silicon nitride, and the second dielectric layer 214 is made of polysilicon. The uppermost second dielectric layer 214 of the dielectric layer stack 210 has a greater thickness than the other second dielectric layers 214, which is 3 to 10 times the thickness of any of the other second dielectric layers 214, and in some embodiments, the thickness of each layer in the dielectric layer stack 210 is between 0.05 microns and 2 microns. In some embodiments, the total number of first dielectric layers 212 and second dielectric layers 214 in the dielectric layer stack 210 is 6 to 10 layers.

[0032] Next, a photoresist layer is formed and patterned on the dielectric layer stack 210. In some embodiments, the total thickness of the photoresist layer is greater than 3 microns. In some embodiments, the total thickness of the photoresist layer is 1 micron to 3 microns greater than the total thickness of the dielectric layer stack 210. In some embodiments, a spin coating process can be used to form the photoresist layer. Next, the photoresist layer is exposed using a photomask, and the photoresist layer is developed to leave unexposed areas of the photoresist layer.

[0033] refer to Figure 8 , the uppermost second dielectric layer 214 and the uppermost first dielectric layer 212 are patterned through the photoresist layer. Specifically, the uppermost second dielectric layer 214 may be patterned through the photoresist layer first, and then the uppermost first dielectric layer 212 may be patterned through the uppermost second dielectric layer 214. Since the second dielectric layer 214 and the first dielectric layer 212 are made of different materials, when the second dielectric layer 214 is patterned, the first dielectric layer 212 may serve as an etch stop layer, and when the first dielectric layer 212 is patterned, the second dielectric layer 214 may serve as an etch stop layer.

[0034] refer to Fig. 9, a first spacer 220 is formed on the sidewalls of the uppermost second dielectric layer 214 and the uppermost first dielectric layer 212. The first spacer 220 may be formed by the following method: a first spacer material layer may be formed along the surface of the dielectric layer stack 210. Before forming the first spacer material layer 222, the photoresist layer may be removed. The first spacer material layer is made of a material different from the first dielectric layer 212 and the second dielectric layer 214, and the material of the first spacer material layer has a high etching selectivity with the materials of the first dielectric layer 212 and the second dielectric layer 214. In some embodiments, the first spacer material layer is made of silicon dioxide, and the thickness of the first spacer material layer is 0.5 micrometers to 2 micrometers.

[0035] Next, the horizontal portion of the first spacer material layer is etched, and the vertical portion of the first spacer material layer is left to form the first spacer 220. In this way, the first spacer 220 is formed on the sidewalls of the uppermost second dielectric layer 214 and the uppermost first dielectric layer 212. Since the material of the first spacer 220 is different from that of the second dielectric layer 214, when forming the first spacer 220, the second dielectric layer 214 can also serve as an etching stop layer to prevent the surface of the dielectric layer stack 210 from being damaged. The thickness of the first spacer 220 is the same as the thickness of the first spacer material layer.

[0036] refer to Fig.10 , the second dielectric layer 214 of the second layer and the first dielectric layer 212 of the second layer are patterned through the first spacer 220. Specifically, the second dielectric layer 214 of the second layer can be patterned through the first spacer 220 first, and then the first dielectric layer 212 of the second layer can be patterned through the second dielectric layer 214 of the second layer. Therefore, the width of the second dielectric layer 214 and the first dielectric layer 212 of the second layer is greater than the width of the second dielectric layer 214 and the first dielectric layer 212 of the uppermost layer. When the second dielectric layer 214 of the second layer is patterned through the first spacer 220, the uppermost second dielectric layer 214 will also be etched. However, since the thickness of the uppermost second dielectric layer 214 is sufficient, it will not be completely removed. After the patterning of the second dielectric layer 214 of the second layer and the first dielectric layer 212 of the second layer is completed, the first spacer 220 can be removed.

[0037] refer to Fig.11, forming a second spacer 230 on the sidewalls of the second dielectric layer 214 of the second layer and the first dielectric layer 212 of the second layer. The second spacer 230 may be formed by the following method: forming a second spacer material layer along the surface of the dielectric layer stack 210. Etching the second spacer material layer in the horizontal portion and leaving the second spacer material layer in the vertical portion to form the second spacer 230. The method of forming the second spacer 230 is the same as the method of forming the first spacer 220, so the relevant details are not repeated here.

[0038] refer to Fig.12 , the second dielectric layer 214 of the third layer and the first dielectric layer 212 of the third layer are patterned through the second spacer 230 to form a stepped dielectric layer stack 200. Specifically, the second dielectric layer 214 of the third layer can be patterned through the second spacer 230 first, and then the first dielectric layer 212 of the second layer can be patterned through the second dielectric layer 214 of the third layer. Therefore, the width of the second dielectric layer 214 and the first dielectric layer 212 of the third layer is greater than the width of the second dielectric layer 214 and the first dielectric layer 212 of the second layer. When the second dielectric layer 214 of the third layer is patterned through the second spacer 230, the second dielectric layer 214 of the uppermost layer is also etched. After the patterning of the second dielectric layer 214 of the third layer and the first dielectric layer 212 of the third layer is completed, the second spacer 230 can be removed. In this way, a stepped dielectric layer stack 200 can be formed on the substrate 102.

[0039] When forming the stepped dielectric layer stack 200, the uppermost second dielectric layer 214 will be etched in a specific step. Therefore, when the thickness of the uppermost second dielectric layer 214 is within the disclosed range, the uppermost second dielectric layer 214 can be prevented from being completely removed during the process. If the thickness is less than the disclosed range, it may be completely removed during the process. If the thickness is greater than the disclosed range, the stepped dielectric layer stack 200 with the desired shape cannot be formed. When the dielectric layer stack 210 includes more layers, the uppermost second dielectric layer 214 can be completely removed during the process. Figures 7 to 12 The dielectric layer stack 210 is patterned in the manner described above to form a stepped dielectric layer stack 200 including more layers. Figures 7 to 12 When manufacturing the patterned dielectric layer stack 210 , a plurality of dielectric layer stacks 210 may be formed on the substrate 102 at the same time.

[0040] refer to Fig.13, etching the substrate 102 through the two-step dielectric layer stack 200 separated by a distance to form a first trench T1 in the substrate 102. When etching the substrate 102, the etching parameters are kept consistent. The etching parameters include etching gas concentration and etching energy. In this way, the etching gas can naturally etch the first trench T1 in the substrate 102. In some embodiments, the first trench T1 can have a stepped sidewall like the sidewall of the stepped dielectric layer stack 200.

[0041] In some embodiments, after removing the stepped dielectric layer stack 200, a thermal oxidation process may be used to form a sacrificial oxide layer 240 on the substrate 102. Then, a wet etching process may be used to remove the sacrificial oxide layer 240. After removing the sacrificial oxide layer 240, the sacrificial oxide layer 240 may be removed. Figures 2 to 5 The semiconductor device 100 is completed by performing the process of Figure 5 The semiconductor device 100 is similar to the semiconductor device 100 of FIG. 1 , except that the gate 160 has a stepped sidewall or an inclined sidewall.

[0042] In summary, some embodiments of the present invention can be used to form a gate that is wide at the top and narrow at the bottom. Different methods can be used to form a gate trench that is wide at the top and narrow at the bottom. For example, a hard mask layer with a conical opening can be used to etch a substrate to form a trapezoidal gate trench. A hard mask layer with an opening with vertical sidewalls can be used, and the etching parameters can be changed when etching the substrate to form a trapezoidal gate trench. A stepped dielectric layer stack can also be used to etch a substrate to form a stepped gate trench. Therefore, the shielding doping region formed at the corner of the gate is not easy to block the path of the electron flow, thereby reducing the resistance of the semiconductor device.

[0043]

Explanation of symbols

[0044] 100: Semiconductor devices

[0045] 102: Substrate

[0046] 110: Hard mask layer

[0047] 132: Trap

[0048] 134: Source region

[0049] 136: Base region

[0050] 138: Shielding doping area

[0051] 140: Hard Mask Stacking

[0052] 150: Gate dielectric layer

[0053] 160: Gate

[0054] 170: Sacrificial oxide layer

[0055] 180: Source contact

[0056] 190: Drain electrode

[0057] 200: Stepped dielectric layer stack

[0058] 210: Dielectric layer stack

[0059] 212: First dielectric layer

[0060] 214: Second dielectric layer

[0061] 220: First spacer

[0062] 230: Second spacer

[0063] 240: Sacrificial oxide layer

[0064] a1: angle

[0065] C: Corner

[0066] EF: Electron Flow

[0067] O1: Inverted trapezoidal opening

[0068] O2: Opening

[0069] T1: First groove

[0070] T2: Second trench.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: providing a substrate; forming a first trench in the substrate, wherein a top width of the first trench is greater than a bottom width of the first trench; forming a well and a source region on one side of the first trench, the source region being on the well; forming a hard mask stack along a surface of the substrate; forming a second trench in the hard mask stack, wherein a bottom of the second trench is located above a corner of the first trench; Performing an ion implantation process to form a shielding doping region in a region of the substrate close to the corner of the first trench; Remove the hard mask stack; forming a gate dielectric layer along the surface of the substrate, wherein the gate dielectric layer covers the shielding doped region; as well as A gate is formed in the first trench.

2. The method of claim 1 , wherein forming the first trench in the substrate comprises: forming a hard mask layer on the substrate; forming a patterned photoresist layer over the hard mask layer; performing a first etching process on the hard mask layer through the patterned photoresist layer to form an inverted trapezoidal opening in the hard mask layer; and A second etching process is performed on the substrate through the hard mask layer to form the first trench in the substrate.

3. The method according to claim 2, wherein performing the first etching process includes adjusting at least one of a plurality of etching parameters of the first etching process, wherein the plurality of etching parameters include etching gas concentration and etching energy, and during the second etching process, the plurality of etching parameters of the second etching process remain consistent.

4. The method of claim 1 , wherein forming the first trench in the substrate comprises: forming a hard mask layer on the substrate; forming a patterned photoresist layer over the hard mask layer; performing a first etching process on the hard mask layer through the patterned photoresist layer to form an opening in the hard mask layer, the opening having a vertical sidewall; and A second etching process is performed on the substrate through the hard mask layer to form the first trench in the substrate.

5. The method according to claim 4, wherein during the first etching process, multiple etching parameters of the first etching process are maintained consistent, the multiple etching parameters including etching gas concentration and etching energy, and performing the second etching process includes adjusting at least one of the multiple etching parameters of the second etching process.

6. The method of claim 1 , wherein forming the first trench in the substrate comprises: forming a two-step dielectric layer stack separated by a distance on the substrate; and The substrate is etched through the two stepped dielectric layer stacks to form the first trench in the substrate.

7. The method according to claim 6, wherein forming the two-step dielectric layer stack separated by a distance on the substrate comprises: Forming a dielectric layer stack on the substrate, the dielectric layer stack comprising a plurality of first dielectric layers and a plurality of second dielectric layers stacked alternately, the plurality of first dielectric layers being made of a first material, and the plurality of second dielectric layers being made of a second material different from the first material; forming a photoresist layer on the dielectric layer stack and patterning the photoresist layer; patterning the second dielectric layer and the first dielectric layer on the top through the photoresist layer; forming a plurality of first spacers on a plurality of sidewalls of the second uppermost dielectric layer and the first uppermost dielectric layer; patterning the second dielectric layer of the second layer and the first dielectric layer of the second layer through the plurality of first spacers; removing the plurality of first spacers; forming a plurality of second spacers on a plurality of sidewalls of the second dielectric layer of the second layer and the first dielectric layer of the second layer; as well as The second dielectric layer of the third layer and the first dielectric layer of the third layer are patterned by the plurality of second spacers to form the two-step dielectric layer stack.

8. A semiconductor device, characterized in that: Include: substrate; A gate extending downward from the surface of the substrate, wherein a top width of the gate is wider than a bottom width of the gate; a gate dielectric layer between the substrate and the gate; shielding doped regions in the substrate at corners of the gate and beneath the gate dielectric layer; a well in the substrate and on one side of the gate dielectric layer; A source region is in the substrate and on the well. 9 . The semiconductor device according to claim 8 , wherein a sidewall of the gate forms an angle with a bottom of the gate, and the angle is between 100 degrees and 130 degrees. 10 . The semiconductor device according to claim 8 , wherein a bottom of the well is higher than a bottom of the gate.

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