Package with stepped conductive terminals

Abstract

The invention relates to a package with stepped conductive terminals. In an example, a method (200) for manufacturing a package includes: coupling a first semiconductor die and a second semiconductor die to a first surface (202) of a conductive terminal; applying a dry film to a second surface of the conductive terminal opposite the first surface (204); removing a portion of the dry film contacting the second surface to form a dry film opening having a linear non-curved edge (206) extending along a width of the conductive terminal; etching the second surface through the dry film opening (208); removing the dry film (210); plating the second surface (212); and sawing through the conductive terminals to form the package (214).

Description

Technical Field

[0001] The present disclosure relates to a package having stepped conductive terminals. Background Art

[0002] A semiconductor wafer is a circular piece of semiconductor material, such as silicon, used to make semiconductor chips. In general, complex manufacturing processes are used to form many integrated circuits on a single wafer. Forming such circuits on a wafer is called fabrication. After wafer fabrication, the wafer is cut into multiple pieces, called semiconductor dies, each of which contains one of the circuits. Cutting or sawing the wafer into individual dies is called singulation. The dies are then coupled to a lead frame and covered with a molding compound, which is then sawn to create a package. Summary of the invention

[0003] In an example, the package includes a die pad exposed to a bottom surface of the package, a semiconductor die coupled to the die pad, and a conductive terminal coupled to the semiconductor die. The conductive terminal includes a first surface exposed to the bottom surface of the package, a second surface exposed to a lateral surface of the package orthogonal to the bottom surface of the package, and a third surface extending from the first surface toward the second surface. The third surface intersects the first surface along an edge of the first surface extending substantially parallel to the lateral surface of the package. The package also includes a molding compound component extending between the conductive terminal and the second conductive terminal, wherein the molding compound component includes a side surface orthogonal to the lateral surface and the bottom surface of the package, and wherein at least a portion of the side surface is not covered by the conductive terminal.

[0004] In an example, a method for manufacturing a package includes: coupling a first semiconductor die and a second semiconductor die to a first surface of a conductive terminal; applying a dry film to a second surface of the conductive terminal opposite the first surface; removing a portion of the dry film contacting the second surface to form a dry film opening, the dry film opening having a linear non-curved edge extending along a width of the conductive terminal; etching the second surface through the dry film opening; removing the dry film; plating the second surface; and sawing through the conductive terminal to form a package. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A is a perspective view of a package having stepped conductive terminals according to various embodiments.

[0006] Figure 1B is a top view of a package having stepped conductive terminals according to various embodiments.

[0007] Figure 1C is a cross-sectional view of a package having stepped conductive terminals according to various embodiments.

[0008] Figure 1Dis a bottom-up view of a package with stepped conductive terminals according to various embodiments.

[0009] Figure 1E is a cutaway cross-sectional view of a package having stepped conductive terminals according to various embodiments.

[0010] Figure 2 is a flow chart of a method for manufacturing a semiconductor package having stepped conductive terminals according to various examples.

[0011] Figures 3A1 to 3F3 The present invention is a process flow of a method for manufacturing a semiconductor package with a stepped conductive terminal according to various examples. If the content under the sub-title is missing in a general new application, the sub-title above should still be retained, but the Institute must be notified. DETAILED DESCRIPTION

[0012] The package is typically coupled to a printed circuit board (PCB) to enable communication with other electronic devices that are also coupled to the PCB. The package may have conductive terminals, sometimes also referred to as pins or leads, that are exposed to the bottom surface and / or lateral surfaces of the package and that may be soldered to traces or pads on the PCB (e.g., in a quad flat no-lead (QFN) package). Because the conductive terminals are electrically coupled to the die within the package, soldering the conductive terminals to the PCB provides an electrical path between the die and other electronic devices coupled to the PCB.

[0013] It is important to form strong and reliable solder connections between the conductive terminals and the PCB. Without these strong and reliable solder connections, the package can become at least partially detached from the PCB, thereby compromising the communication between the package and other devices coupled to the PCB. Such failures can be significant because the failure can cause the entire electronic device to become inoperative.

[0014] Various techniques can be used to measure the integrity of the solder connection between the conductive terminal and the PCB. In some applications, such as in automotive applications, the solder connection can be visually inspected from above the package. The solder connection can be formed in a specific manner to facilitate such visual inspection. For example, in some cases, the package may have a plurality of conductive terminals, and each conductive terminal may be exposed to the bottom surface of the package and the lateral surface of the package, which means that the conductive terminal spans the edge of the package. Pits may be formed in such conductive terminals, and these pits are formed along the edge of the package so that the pits are cavities exposed to the bottom surface of the package and the lateral surface of the package. Solder is applied at these pits to form the solder into a specific shape, called a solder angle, which has an inclined shape. An inclined surface is formed on the PCB and extends into the pit, and the inclined surface can be used to effectively and visually evaluate the mechanical integrity of the solder connection with the conductive terminal. Such conductive terminals are sometimes referred to as "wettable flanks".

[0015] Packages with such conductive terminal pits are subject to many technical challenges. First, in order to be fully visible for optical inspection, the solder fillet must have a specified height, and in order to achieve this height, the pit (and more specifically, the conductive terminal in which the pit is formed) must have specific physical dimensions. But achieving these conductive terminal physical dimensions involves the use of expensive lead frames that must be etched multiple times, which is cumbersome, inefficient and expensive. Second, the pits are susceptible to mold flash, in which case the material within the package escapes from the outside (e.g., is squeezed out), causing functional, mechanical and appearance challenges. Third, the shape of the pits is circular, leaving thin metal areas in the conductive terminals, and these thin metal areas are prone to deformation. Fourth, the pits are prone to burrs, which require a complex and challenging sawing process to remove. In summary, the pits conventionally used in package conductive terminals to form solder fillets are structurally flawed and cause many technical problems.

[0016] The present disclosure describes various examples of packages with stepped conductive terminals that provide technical solutions to the technical challenges described above. More specifically, the package has a conductive terminal that lacks the aforementioned pits, and instead has a stepped feature that alleviates each of the challenges described above. For example, the stepped conductive terminal: does not require an expensive lead frame; does not require a multi-pass etching technique; is structurally not susceptible to mold flash; does not have a rounded shape and therefore does not have a thin metal area that is susceptible to deformation; and is not prone to burr formation because the etching that forms the stepped features occurs after the molding compound is applied. An example of a package with stepped conductive terminals is now described with reference to the accompanying drawings.

[0017] Figure 1A 1 is a perspective view of a package 100 having stepped conductive terminals according to various examples. The package 100 may be any suitable type of package, such as a quad flat no-lead (QFN) package. The package 100 includes a mold compound 102, a die pad 104 exposed from a bottom surface 106 of the mold compound 102, a lateral surface 108 intersecting the bottom surface 106 at an edge 109 and substantially orthogonal to the bottom surface 106, a plurality of conductive terminals (e.g., leads or pins) 110, a terminal surface 112 exposed to and substantially flush with the bottom surface 106, a terminal surface 114 exposed to and substantially flush with the lateral surface 108, a terminal surface 116, an edge 118 where the terminal surfaces 112, 116 contact each other, and an edge 120 where the terminal surfaces 114, 116 contact each other. The die pad 104 and portions of the conductive terminals 110 (excluding the terminal surface 114) may be plated with a tin plating layer 310. Figure 1A The various reference numerals used in the drawings refer to the structure itself rather than the tin plating 310 .

[0018] As depicted, the terminal surface 112 is substantially flush with the bottom surface 106. The terminal surface 112 does not extend to the edge 109. Instead, the terminal surface 112 terminates at an edge 118 that is set back from the edge 109 by a distance in the range of 50 microns to 100 microns, wherein a distance below this range is disadvantageous because it unacceptably reduces solder wettability, and wherein a distance greater than this range is also disadvantageous because the difficulty of mounting the package 100 to the PCB becomes unacceptable. In an example, the terminal surface 112 has a thumbnail shape, wherein the edge 118 extends linearly across the width of the conductive terminal 110 / terminal surface 112, and wherein the remaining perimeter of the terminal surface 112 has a curved shape, as shown.

[0019] The terminal surface 114 is substantially flush with the lateral surface 108. The edge 120 of the terminal surface 114 does not extend to the edge 109. Instead, the terminal surface 114 terminates at the edge 120, which is set back from the edge 109 by a distance ranging from 75 microns to 190 microns, wherein a distance below this range is disadvantageous because it will cause an automatic optical inspection (AOI) to fail from a top view, and wherein a distance greater than this range is also disadvantageous because excessive etching will result in a surface of the terminal 110 without plating, making the terminal 110 susceptible to damage. The terminal surface 114 has a rectangular shape, wherein the perimeter has four linear (i.e., straight, non-curved) edges. The height of the terminal surface 114 is in the range of 10 microns to 125 microns, wherein a height below this range is disadvantageous because there will be no plating and therefore the terminal 110 will be susceptible to damage, and wherein a height above this range is also disadvantageous because it will cause an AOI to fail from a top view.

[0020] The edge 118 is linear, meaning that the edge 118 extends across the width of the conductive terminal 110 substantially parallel to the edge 109, the lateral surface 108, and / or the edge 120 without significant curvature in the horizontal plane. Each conductive terminal 110 is located between two sections of the bottom surface 106, and the edge 118 extends linearly between the two sections of the bottom surface 106, as shown. Similarly, the edge 120 is linear, meaning that the edge 120 extends substantially parallel to the edge 109, the surface 106, and / or the edge 118. Each conductive terminal 110 is located between two sections of the lateral surface 108, and the edge 120 extends linearly between the two sections of the lateral surface 108, as shown. The horizontal distance between edge 118 and edge 120 is in the range of 50 microns to 75 microns, wherein a distance below this range is unfavorable because it unacceptably reduces solder wettability, and wherein a distance above this range is also unfavorable because it becomes unacceptably difficult to mount package 100 to a PCB.

[0021] The terminal surface 116 extends between edge 118 and edge 120. The terminal surface 116 is curved, where the degree of curvature depends on the etching technique used to form the terminal surface 116, as described below. The various structures and edges forming the conductive terminal 110 can give the conductive terminal 110 a stepped appearance, but the term "stepped" should not be interpreted as referring to any particular physical feature or configuration.

[0022] Each conductive terminal 110 is placed in a cavity of the package 100. In each cavity, just above the terminal surface 116, the walls of the cavity formed by the molding compound 102 face each other along a line of sight. This line of sight between the molding compound 102 walls of each cavity extends parallel to the corresponding edges 118 and 120. The spacing between consecutive conductive terminals 110 is equal to or less than 0.5 mm. For example, the molding compound part 111 extends between two conductive terminals in the conductive terminals 110. The molding compound part 111 includes a side surface 113. The side surface 113 is orthogonal to the lateral surface 108 and the bottom surface 106. The conductive terminal 110 closest to the side surface 113 does not cover all of the surface 113. In other words, at least a portion of the surface 113 is not covered by the conductive terminal 110 closest to the surface 113. The same molding compound component 111 may have a similar side surface opposite to the side surface 113 (orthogonal to the lateral surface 108 and the bottom surface 106), and the side surface is also at least partially uncovered by the conductive terminals 110 closest to the side surface. The side surface 113 may face another side surface of the molding compound component 115 (orthogonal to the bottom surface 106 and the lateral surface 108), which is uncovered by the conductive terminals 110 closest to the side surface of the molding compound component 115.

[0023] Figure 1B is a top view of a package 100 having stepped conductive terminals according to various embodiments. Figure 1C is a cross-sectional view of a package 100 having stepped conductive terminals according to various embodiments. Figure 1D is a bottom-up view of a package 100 having stepped conductive terminals according to various embodiments. Figure 1E is a cutaway cross-sectional view of a portion of a package 100 having stepped conductive terminals according to various examples. Figure 1E The conductive terminals 110 are shown coupled to the PCB 150 via example solder fillets 152 .

[0024] Figure 2 is a flow chart of a method 200 for fabricating a semiconductor package (eg, package 100 ) having stepped conductive terminals according to various examples. Figures 3A1 to 3F3is a process flow of a method for manufacturing a semiconductor package (eg, package 100) having stepped conductive terminals according to various embodiments. Figure 2 and Figures 3A1 to 3F3 .

[0025] The method 200 includes coupling a first semiconductor die and a second semiconductor die to a first surface of a conductive terminal (202). A mold compound 102 may also be applied. The method 200 also includes applying a dry film to a second surface of the conductive terminal opposite the first surface (204). Figure 3A1 1 is a cross-sectional view of a plurality of semiconductor dies 300 coupled to a die pad 104. Bond wires 302 couple the device side of the semiconductor die 300, on which the circuitry is formed, to a first surface of a conductive terminal 110. A dry film 304 is applied to a second surface of the conductive terminal 110 and a surface of the die pad 104 opposite the semiconductor die 300, as shown. The dry film 304 may be applied using any suitable technique, such as film forming, printing, and embossing. A mold compound 102 is also applied to cover the conductive terminal 110. Figure 3A1 At least a portion of all structures shown in . Figure 3A2 Based on various examples Figure 3A1 Top view of the structure. Figure 3A3 Based on various examples Figure 3A1 perspective view of the structure.

[0026] Method 200 includes removing a portion of the dry film contacting the second surface using any suitable technique, such as by laser, to form a dry film opening (206). The dry film opening has a linear (i.e., straight, non-curved) edge (206) extending along a width (e.g., at least a width) of the conductive terminal. Figure 3B1 for Figure 3A1 1, except that the dry film 304 has openings 306 formed therein. Each opening 306 is formed in a region of the dry film 304 that is vertically aligned with a corresponding conductive terminal 110. Figure 3B1 The conductive terminals 110 shown in FIG. 3 have not yet been sawn, but after the conductive terminals are sawn, they will produce conductive terminals 110 incorporated into separate packages. More specifically, each opening 306 is centered above the approximate horizontal midpoint of the corresponding conductive terminal 110. Each opening 306 is defined by edges 308 and 309. Crucially, the edges 308 and 309 are linear (i.e., non-curved) so that the edge 118 subsequently formed using the edges 308, 309 is also linear and has the specific physical characteristics described above. Figure 3B2 It is based on examples Figure 3B1As shown, the opening 306 is vertically aligned with a plurality of conductive terminals 110 (eg, a row of conductive terminals 110 ), and thus the opening 306 spans the width of the plurality of conductive terminals 110 in a row. Figure 3B3 Based on various examples Figure 3B1 perspective view of the structure.

[0027] The method 200 includes etching the second surface through the dry film opening (208). Fig.3C1 yes Figure 3B1 , except that each of the conductive terminals 110 has been etched through a corresponding opening 306 in the dry film 304. Any suitable etching technique may be useful, such as acid etching, chemical etching, electrolytic etching, laser etching, ultrasonic etching, physical etching, etc. The remaining dry film 304 protects Fig.3C1 The etchant may form a cavity 307 in each of the conductive terminals 110. Etching must be carefully controlled because the manner in which each conductive terminal 110 is etched will affect the physical characteristics of the terminal surface 116, edge 120, and terminal surface 114 of each conductive terminal 110. For example, the rate and / or depth of etching will affect the curvature of the cavity 307 (and therefore, by extension, the curvature of the terminal surface 116 to be formed by the cavity 307 described below) and the depth of the cavity 307 (and therefore, by extension, the height of the terminal surface 116, the position of the edge 120, and the height of the terminal surface 114). The curvature of the cavity 307 is the same as the curvature of the terminal surface 116 described above. The depth of the cavity 307 is in the range of 0.075 mm to 0.19 mm, wherein a depth below this range is disadvantageous because AOI will fail, and wherein a depth above this range is disadvantageous because there will be no plating and the terminal will be more easily damaged. The horizontal width of cavity 307 at the widest point is in the range of 350 microns to 550 microns, where widths below this range are disadvantageous because they reduce solder wettability, and where widths above this range are disadvantageous because mounting the package to the PCB becomes unacceptably difficult. Figure 3C2 Based on various examples Fig.3C1 Top view of the structure. Figure 3C3 Based on various examples Fig.3C1 perspective view of the structure.

[0028] The method 200 includes removing (eg, stripping) the dry film ( 210 ). Figure 3D1 Based on various examples Fig.3C1 , except that the dry film 304 has been removed. Figure 3D2 Based on various examples Figure 3D1 Top view of the structure. Figure 3D3Based on various examples Figure 3D1 perspective view of the structure.

[0029] The method 200 includes plating the second surface (212). Fig.3E1 for Figure 3D1 1, except that the second surface of the conductive terminal 110 and the exposed surface of the die pad 104 are plated with a protective metal or alloy, such as a tin plating layer 310. Other metals and alloys can also be used for plating, such as nickel-palladium-gold. The thickness of the tin plating layer 310 (or other plating layer) is in the range of 7 microns to 20 microns, wherein a thickness below this range is unfavorable because it causes AOI failure, and a thickness above this range is unfavorable because it causes deburring challenges. Figure 3E2 Based on various examples Fig.3E1 Top view of the structure. Figure 3E3 Based on various examples Fig.3E1 perspective view of the structure.

[0030] The method 200 includes sawing through the conductive terminals to form a package ( 214 ). Figure 3F1 yes Fig.3E1 The structure of FIG. 1 is a cross-sectional view of the structure of FIG. 1 , except that the structure has been sawn through the conductive terminal 110, for example at the horizontal midpoint of the conductive terminal 110, as shown. The sawing forms a gap 312. In this way, Fig.3E1 The structure is divided into a plurality of separate packages, and the plurality of separate packages are the same as those mentioned above. Figures 1A to 1E The packages described are similar or identical. The width of the saw cut is in the range of 270 microns to 350 microns, wherein a saw cut width below this range is disadvantageous because the package size will be unacceptably large, and wherein a saw cut width above this range is disadvantageous because it can cut into significant components of the package. Singulation exposes the terminal surfaces 114, and because the terminal surfaces are not exposed before singulation, there is no plating (e.g., tin plating 310) on the terminal surfaces 114. Figure 3F2 Based on various examples Figure 3F1 Top view of the structure. Figure 3F3 Based on various examples Figure 3F1 perspective view of the structure.

[0031] In this specification, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in the first instance, device A is coupled to device B through a direct connection; or (b) in the second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A through the control signal generated by device A.

[0032] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components and interconnection of the device, or a combination thereof.

[0033] In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter. Modifications may be made in the described examples, and other examples may be made within the scope of the claims.

Claims

1. A method for manufacturing a package, comprising: coupling a first semiconductor die and a second semiconductor die to a first surface of a conductive terminal; applying a dry film to a second surface of the conductive terminal opposite the first surface; removing a portion of the dry film contacting the second surface to form a dry film opening having a linear non-curved edge extending along a width of the conductive terminal; etching the second surface through the dry film opening; removing the dry film; plating the second surface; and The conductive terminals are sawed through to form the package. 2 . The method of claim 1 , wherein removing the portion of the dry film comprises forming a pattern on the dry film using a laser. The method of claim 1 , wherein etching the second surface comprises performing an acid etch. The method of claim 1 , wherein plating the second surface comprises plating tin on the second surface. The method of claim 4 , wherein sawing through the conductive terminal exposes a third surface of the conductive terminal, and wherein the third surface is unplated. The method of claim 1 , wherein the package is a Quad Flat No-Lead (QFN) package.

7. The method of claim 1 , further comprising applying a molding compound, the molding compound comprising a molding compound portion extending between the conductive terminal and a second conductive terminal, wherein the molding compound portion comprises a side surface orthogonal to the lateral surface and the bottom surface of the package, and wherein at least a portion of the side surface is not covered by the conductive terminal.

8. The method of claim 7, wherein the molding compound component includes a second side surface opposite the side surface, the second side surface being orthogonal to the lateral surface and the bottom surface of the package, and wherein at least a portion of the second side surface is not covered by the second conductive terminal.

9. A package comprising: a die pad exposed on a bottom surface of the package; a semiconductor die coupled to the die pad; a conductive terminal coupled to the semiconductor die, the conductive terminal comprising: a first surface exposed to the bottom surface of the package; a second surface exposed to a lateral surface of the package, the lateral surface being orthogonal to the bottom surface of the package; and a third surface extending from the first surface toward the second surface, the third surface intersecting the first surface along an edge of the first surface, the edge extending substantially parallel to the lateral surface of the package; and A molding compound member extends between the conductive terminal and a second conductive terminal, wherein the molding compound member includes a side surface orthogonal to the lateral surface and the bottom surface of the package, and wherein at least a portion of the side surface is not covered by the conductive terminal.

10. The package of claim 9, wherein the package is a Quad Flat No-Lead (QFN) package. The package of claim 9 , wherein the third surface is a curved surface.

12. The package of claim 9, wherein the first surface is substantially flush with the bottom surface.

13. The package of claim 9, wherein the second surface is substantially flush with the lateral surface.

14. The package of claim 9, wherein the first surface and the third surface are plated with tin. The package of claim 14 , wherein the second surface is not plated with tin.

16. The package of claim 9, wherein the first surface and the third surface are plated and the second surface is unplated.

17. The package of claim 9, further comprising a second molding compound member extending between the conductive terminal and a third conductive terminal, the conductive terminal being positioned between the second conductive terminal and the third conductive terminal, wherein: the second molding compound component comprising a second side surface orthogonal to the lateral surface and the bottom surface of the package, At least a portion of the second side surface is not covered by the conductive terminal, and The side surface and the second side surface face each other.

18. The package of claim 9, wherein the edge is not curved.

19. A package comprising: Semiconductor die; and a conductive terminal coupled to the semiconductor die, the conductive terminal comprising: a first surface that is substantially flush with a bottom surface of the package; a second surface that is substantially flush with a lateral surface of the package, the lateral surface being orthogonal to the bottom surface of the package; and A curved surface extends from the first surface to the second surface, the curved surface intersecting the first surface along a first edge and intersecting the second surface along a second edge, the first edge and the second edge being parallel to the lateral surface.

20. The package of claim 19, wherein the first edge and the second edge are not curved.

21. The package of claim 19, wherein the first surface and the curved surface are plated with tin, and wherein the second surface is not plated with tin.

22. The package of claim 19, wherein the first surface and the curved surface are plated and the second surface is unplated.

23. The package of claim 19, wherein the package is a Quad Flat No-Lead (QFN) package.

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