Package device and method of forming same

Abstract

Packaging devices and methods of forming the same are disclosed herein. The package device includes a first substrate having a first die layer, a second substrate having a second die layer, and a third die layer contacting the first die layer and the second die layer. The third grain layer has a smaller average grain size than the first grain layer and the second grain layer.

Description

Technical Field

[0001] The subject matter disclosed herein relates to packaged devices and methods of forming the same. More particularly, the subject matter disclosed herein relates to techniques for bonding devices between substrates. Background Art

[0002] Semiconductor devices can be connected to additional devices and circuits on different substrates. Conductors such as metals can be used to form connections on substrates, such as in the form of traces. However, forming connections between substrates may cause difficulties. It is also noted that the background concepts discussed herein are for informational purposes only and are not intended to limit the present disclosure. Summary of the invention

[0003] Example embodiments provide a packaged device, the packaged device comprising a first substrate, the first substrate comprising a first conductive region and a first insulating region. The packaged device further comprises a second substrate, the second substrate comprising a second conductive region contacting the first conductive region and a second insulating region contacting the first insulating region. In some embodiments, the first conductive region has a first grain layer and a second grain layer contacting the first grain layer, the second grain layer having an average grain size larger than the first grain layer. In some embodiments, the second conductive region has a third grain layer and a fourth grain layer contacting the third grain layer, the fourth grain layer having an average grain size larger than the third grain layer. In some embodiments, at least one of the first grain layer and the third grain layer has a thickness of a single grain layer.

[0004] In some embodiments, the crystal orientation of the first grain layer and the crystal orientation of the second grain layer may be different, and the crystal orientation of the third grain layer and the crystal orientation of the fourth grain layer may be different. In some embodiments, the crystal orientation of the first grain layer and the crystal orientation of the second grain layer may be substantially the same, and the crystal orientation of the third grain layer and the crystal orientation of the fourth grain layer may be substantially the same. In some embodiments, the crystal orientation of the first grain layer and the crystal orientation of the third grain layer may be substantially the same, and the crystal orientation of the second grain layer and the crystal orientation of the fourth grain layer may be different. In some embodiments, the first grain layer and the third grain layer may have substantially the same average grain size. In some embodiments, the first grain layer may include a first copper layer, and the second grain layer may include a second copper layer different from the first copper layer. In some embodiments, the third grain layer may include a third copper layer, and the fourth grain layer may include a fourth copper layer different from the third copper layer. In some embodiments, the second copper layer is different from the fourth copper layer. In some embodiments, at least one of the first grain layer and the third grain layer may form an electromigration barrier between the second grain layer and the fourth grain layer. In some embodiments, an average grain size of at least one of the first and third grain layers may be less than about 10 nanometers, and an average grain size of each of the second and fourth grain layers may be greater than about 0.1 micrometers.

[0005] In some embodiments, a package device includes a first grain layer contacting a first substrate, a second grain layer contacting a second substrate, and a third grain layer contacting the first grain layer and the second grain layer, the third grain layer having an average grain size smaller than the first grain layer and the second grain layer. In some embodiments, the crystallographic orientation of the first grain layer, the crystallographic orientation of the second grain layer, and the crystallographic orientation of the third grain layer may be substantially the same. In some embodiments, the crystallographic orientation of the first grain layer and the crystallographic orientation of the second grain layer may be different, and the crystallographic orientation of the third grain layer may be different from the crystallographic orientation of both the first grain layer and the second grain layer. In some embodiments, the crystallographic orientation of the first grain layer and the crystallographic orientation of the second grain layer may be different, and the crystallographic orientation of the third grain layer is different from the crystallographic orientation of at least one of the first grain layer and the second grain layer. In some embodiments, the average grain size of the third grain layer may be less than about 10 nanometers. In some embodiments, the average grain size of at least one of the first grain layer and the second grain layer may be greater than about 0.1 micrometers.

[0006] In some embodiments, a method of forming a packaged device includes depositing a first insulating region on a first substrate, forming a first groove in the first insulating region, and depositing a first conductive layer in the first groove. The method further includes depositing a second insulating region on a second substrate, forming a second groove in the second insulating region, and depositing a second conductive layer in the second groove. The method further includes forming a third conductive layer on the first conductive layer and forming a fourth conductive layer on the second conductive layer, at least one of the third conductive layer and the fourth conductive layer having a different grain orientation from the first conductive layer and the second conductive layer. The first insulating region can be bonded to the second insulating region. The first substrate and the second substrate can be annealed at a temperature below 250°C to bond the third conductive layer and the fourth conductive layer into a single layer.

[0007] In some embodiments, the first conductive layer and the second conductive layer can be formed using electrochemical deposition plating, and the third conductive layer and the fourth conductive layer can be formed using at least one of physical vapor deposition and atomic layer deposition. In some embodiments, annealing the first substrate and the second substrate can be completed at a temperature below 200°C. In some embodiments, before forming the third conductive layer, the first conductive layer can be polished to expose the surface of the first insulating region. In some embodiments, before forming the fourth conductive layer, the second conductive layer can be polished to expose the surface of the second insulating region. In some embodiments, before bonding the first insulating region to the second insulating region, the third conductive layer can be polished to expose the surface of the first insulating region and the fourth conductive layer can be polished to expose the surface of the second insulating region. In some embodiments, the first conductive layer and the third conductive layer can be polished together to expose the surface of the first insulating region, and the second conductive layer and the fourth conductive layer can be polished together to expose the surface of the second insulating region. In some embodiments, forming a first groove in the first insulating region and forming a second groove in the second insulating region can be completed using photolithography, and the third conductive layer and the fourth conductive layer can be unpatterned when bonding. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the following section, aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the accompanying drawings, in which:

[0009] Figure 1 depicts a cross-sectional view of an example implementation of a package structure according to various implementations of the subject matter disclosed herein;

[0010] Figure 2 depicts a cross-sectional view of an example implementation of a package structure according to various implementations of the subject matter disclosed herein;

[0011] Figure 3Adepicts a cross-sectional view of an example embodiment of an assembly of a package structure in a first state according to various embodiments of the subject matter disclosed herein;

[0012] Figure 3B depicts a cross-sectional view of an example implementation of an assembly of a package structure in a second state according to various implementations of the subject matter disclosed herein;

[0013] Figure 3C depicts a cross-sectional view of an example implementation of an assembly of a package structure in a third state according to various implementations of the subject matter disclosed herein;

[0014] Figure 4A depicts a cross-sectional view of an example embodiment of an assembly of a package structure in a first state according to various embodiments of the subject matter disclosed herein;

[0015] Figure 4B depicts a cross-sectional view of an example implementation of an assembly of a package structure in a second state according to various implementations of the subject matter disclosed herein;

[0016] Figure 4C depicts a cross-sectional view of an example implementation of an assembly of a package structure in a third state according to various implementations of the subject matter disclosed herein;

[0017] Figure 5A depicts a cross-sectional view of an example embodiment of an assembly of a package structure in a first state according to various embodiments of the subject matter disclosed herein;

[0018] Figure 5B depicts a cross-sectional view of an example implementation of an assembly of a package structure in a second state according to various implementations of the subject matter disclosed herein;

[0019] Figure 5C depicts a cross-sectional view of an example implementation of an assembly of a package structure in a third state according to various implementations of the subject matter disclosed herein;

[0020] Figure 5D depicts a cross-sectional view of an example implementation of an assembly of a package structure in a fourth state according to various implementations of the subject matter disclosed herein;

[0021] Figure 5E depicts a cross-sectional view of an example implementation of an assembly of a package structure in a fifth state according to various implementations of the subject matter disclosed herein;

[0022] Fig. 5F depicts a cross-sectional view of an example embodiment of an assembly of a package structure in a sixth state according to various embodiments of the subject matter disclosed herein;

[0023] Figure 5G depicts a cross-sectional view of an example implementation of an assembly of a package structure in a seventh state according to various implementations of the subject matter disclosed herein;

[0024] Figure 5H depicts a cross-sectional view of an example embodiment of an assembly of a package structure in an eighth state according to various embodiments of the subject matter disclosed herein;

[0025] Fig.5I depicts a cross-sectional view of an example embodiment of an assembly of a package structure in a ninth state according to various embodiments of the subject matter disclosed herein;

[0026] Figure 5J depicts a cross-sectional view of an example embodiment of an assembly of a package structure in a tenth state according to various embodiments of the subject matter disclosed herein;

[0027] Figure 5K depicts a cross-sectional view of an example embodiment of an assembly of a package structure in an eleventh state according to various embodiments of the subject matter disclosed herein;

[0028] Figure 6 Depicted are example embodiments of methods of preparing a substrate for packaging in accordance with various embodiments of the subject matter disclosed herein;

[0029] Figure 7 depicts an example implementation of a method of bonding two substrates according to various implementations of the subject matter disclosed herein; and

[0030] Figure 8 An example implementation of a method of packaging two substrates according to various implementations of the subject matter disclosed herein is depicted. DETAILED DESCRIPTION

[0031] In the following detailed description, in order to provide a thorough understanding of the present disclosure, many specific details are set forth. However, it will be appreciated by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other examples, well-known methods, processes, components and circuits are not described in detail to avoid obscuring the subject matter disclosed herein.

[0032] References throughout this specification to "one embodiment" or "an embodiment" mean that specific features, structures, or characteristics described in conjunction with the embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment" or "in an embodiment" or "according to an embodiment" (or other phrases with similar meanings) appearing throughout this specification may not necessarily refer to the same embodiment. In addition, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "used as an example, instance, or illustration." Any embodiment described herein as "exemplary" will not be interpreted as necessarily being preferred or advantageous over other embodiments. In addition, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In addition, depending on the context discussed herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional", "pre-determined", etc.) may occasionally be used interchangeably with corresponding non-hyphenated versions (e.g., "two dimensional", "predetermined", etc.), and capitalized terms (e.g., "Counter Clock", "Row Select", "PIXOUT", etc.) may be used interchangeably with corresponding non-capitalized versions (e.g., "counter clock", "row select", "pixout", etc.). Such occasional interchangeable usage should not be considered inconsistent with each other.

[0033] In addition, depending on the context discussed herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It is also noted that the various drawings (including component drawings) shown and discussed herein are for illustrative purposes only and are not drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, reference numerals are repeated between the drawings to indicate corresponding and / or similar elements, if deemed appropriate.

[0034] The terms used herein are for the purpose of describing some example embodiments only and are not intended to limit the claimed subject matter. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "include" and / or "comprise" indicate the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof.

[0035] It will be understood that when an element or layer is referred to as being on, "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. The same reference numerals always refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerated items.

[0036] As used herein, the terms "first," "second," and the like are used as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly so defined. In addition, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such use is only for simplicity of illustration and ease of discussion; this does not imply that the construction or architectural details of such components or units are the same in all embodiments, or that such commonly referenced parts / modules are the only way to implement some example embodiments disclosed herein.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

[0038] As used herein, dielectric may refer to a variety of materials, alone or in combination, including various forms of silicon (such as SiO 2In some embodiments, the dielectric material may be formed from a surface of a substrate. In other embodiments, the dielectric material may be deposited onto a surface of a substrate. In some embodiments, the dielectric material may be formed via a combination of growing material from a substrate and depositing material. In some embodiments, the dielectric material may be referred to as an electrically insulating material, an insulating region, or an insulator. In some embodiments, the amount of insulation provided may be relative to another material that may be referred to as a conductive material or conductor.

[0039] As used herein, substrates may refer to various materials and structures, including wafers using silicon, wafers using silicon on insulators (such as glass) (SOI), wafers of other semiconductor materials (such as germanium), and other semiconductor materials on insulators. In some embodiments, the substrate may include organic materials. In some embodiments, the substrate may be referred to as a wafer, a die, and a chip individually or in combination. Therefore, in some embodiments, the bonding substrate may be referred to as a die-to-die (D2D) bonding, a wafer-to-wafer bonding (W2W), or a die-to-wafer bonding (D2W). In some embodiments, the substrate may include circuits, such as integrated circuits, including a central processing unit (CPU), a logic chip, a memory (such as a static random access memory (SRAM), a dynamic random access memory (DRAM)), an application processor (AP), a graphics processing unit (GPU), an artificial intelligence (AI) chip, a high bandwidth memory (HBM) interface, and other application-specific integrated circuits (ASICs). In some embodiments, a combination of circuits may be present on a substrate. In some embodiments, the substrate may include a packaged chip.

[0040] As used herein, packaging refers to the process of forming interconnections between substrates. In some embodiments, interconnections can be between surfaces that are in direct contact with each other and involve W2W, D2D and D2W bonding. In other embodiments, the technology including wire bonding and other forms of indirect bonding can be performed alone or in combination with W2W, D2D and D2W bonding. In some embodiments, circuits can be bonded directly face to face with each other, and in other embodiments, flip chip bonding can be used. In some embodiments, interconnections can be performed between substrates on the front or circuit surface of the substrate. In other embodiments, interconnections can be performed on the back or back of the substrate opposite to the circuit structure. In some embodiments, interconnections can include through silicon vias (TSV) or other forms of through chip vias, wherein one or more substrates can be connected using a path that travels through an interposer (such as another substrate or chip). In some embodiments, interconnections can be formed using connections (such as pads) on the surface of the substrate, and additional materials (such as solder) between the pads can be used to form.

[0041] As used herein, conductors may refer to various conductive materials, including materials that may be used alone or in combination with other materials, such as in alloy form. In some embodiments, the conductor is copper (Cu). In some embodiments, copper (Cu) may be in the form of Cu (II), Cu (III), or other forms of copper, alone or in combination with additional elements, including cobalt (Co) and ruthenium (Ru). Such an enumeration of elements is not intended to be exhaustive, and in other embodiments, any other known type of conductive material may be used.

[0042] As used herein, the terms "single grain layer" and "single layer" may both refer to a layer having an average thickness of a single grain in a direction perpendicular to a major surface. As used herein, the term "single grain" may refer to a single crystal structure or a single layer of crystals. For example, a single grain layer having an average grain size of 5 nanometers (nm) will have an average thickness of 5 nm. In some embodiments, a surface interface may exist between the single grain layer and any surrounding material.

[0043] Various devices, structures and methods for forming a conductive interface between two or more substrates using a multilayer conductive material (such as a metal material) are disclosed herein. For example, the conductive material may include a multilayer copper for forming an interconnection between two wafers. Different manufacturing techniques may be used to form a conductive material layer to produce different characteristics and properties in the interconnection. For example, some layers may be formed using processes such as physical vapor deposition (PVD) or atomic layer deposition (ALD) and electrochemical deposition plating (ECD). In some embodiments, the interconnection may include a bond between the conductive material at the surface of the substrate and a bond between the dielectric material on the surface of the substrate. In some embodiments, the bonding process may use a hybrid bonding process in which both dielectric regions and conductive regions are bonded together between substrates.

[0044] Figure 1 Exemplary embodiments of a package structure 100 including a first substrate 102 and a second substrate 202 are disclosed. The first substrate 102 is shown as having a dielectric layer including a first dielectric portion 104, a second dielectric portion 114, and a third dielectric portion 124 in contact with the first substrate 102. In some embodiments, additional layers and structures may be placed between the dielectric layer and the first substrate 102. The first substrate 102 is also shown as having a base conductive layer having a first base conductive portion 106 and a second base conductive portion 116 in contact with the first substrate 102. In some embodiments, additional layers and structures may be placed between the base conductive layer and the first substrate 102, for example, a portion of the dielectric layer may be between one or more of the first base conductive portion 106 and the second base conductive portion 116 and the first substrate 102. In addition, the first base conductive portion 106 and the second base conductive portion 116 are in contact with the first outer conductive portion 108 and the second outer conductive portion 118, respectively.

[0045] Figure 12, and a second substrate 202 is also shown having a dielectric layer including a fourth dielectric portion 204, a fifth dielectric portion 214, and a sixth dielectric portion 224 in contact with the second substrate 202. In some embodiments, additional layers and structures may be placed between the dielectric layer and the second substrate 202. The second substrate 202 is also shown having a base conductive layer having a third base conductive portion 206 and a fourth base conductive portion 216 in contact with the second substrate 202. In some embodiments, additional layers and structures may be placed between the base conductive layer and the second substrate 202, for example, a portion of the dielectric layer may be between one or more of the third base conductive portion 206 and the fourth base conductive portion 216 and the second substrate 202. In addition, the third base conductive portion 206 and the fourth base conductive portion 216 are in contact with the third outer conductive portion 208 and the fourth outer conductive portion 218, respectively.

[0046] In the package structure 100, the first substrate 102 and the second substrate 202 are bonded using the contact between the corresponding dielectric parts and the corresponding conductive parts on the substrates. Therefore, the first dielectric part 104 is bonded to the fourth dielectric part 204, the second dielectric part 114 is bonded to the fifth dielectric part 214, and the third dielectric part 124 is bonded to the sixth dielectric part 224. Therefore, the first outer conductive part 108 is bonded to the third outer conductive part 208, and the second outer conductive part 118 is bonded to the fourth outer conductive part 218. Figure 1 As shown, the first base conductive portion 106, the second base conductive portion 116, the third base conductive portion 206 and the fourth base conductive portion 216 are not in direct contact with each other, but are between the substrate and the additional conductive layer (ie, the outer conductive portions 108, 118, 208 and 218).

[0047] The first substrate conductive portion 106, the second substrate conductive portion 116, the third substrate conductive portion 206, and the fourth substrate conductive portion 216 can be formed using a bulk process such as electrochemical deposition plating to produce a large grain structure. In some embodiments, the large grain structure can have an average grain size in the range of 0.5 microns to 5 microns. For example, the average grain size of each of the first substrate conductive portion 106 and the third substrate conductive portion 206 is greater than about 0.1 microns. For example, the average grain size of each of the second substrate conductive portion 116 and the fourth substrate conductive portion 216 is greater than about 0.1 microns. In addition, the thickness of the large grain structure can be in the range of 0.5 microns to 5 microns. In some embodiments, based on the improvement of manufacturing capabilities, the size of the large grain structure can be further reduced.

[0048] In contrast, the first outer conductive portion 108, the second outer conductive portion 118, the third outer conductive portion 208, and the fourth outer conductive portion 218 can be formed using a process such as PVD or ALD, allowing for a smaller grain structure compared to the grain structure of the large grain structure. For example, using ALD, the average grain size of the small grain structure can be 2-5nm, or using PVD, the average grain size of the small grain structure can be 5-10nm. In addition, the small grain structure can have a thickness between 2-10nm. For example, the average grain size of at least one of the first outer conductive portion 108 and the third outer conductive portion 208 is less than about 10nm. For example, the average grain size of at least one of the second outer conductive portion 118 and the fourth outer conductive portion 218 is less than about 10nm. In some embodiments, based on the improvement of manufacturing capabilities, the size of the small grain structure can be further reduced.

[0049] In addition, the relative portions of the small grain structures of the first outer conductive portion 108 and the third outer conductive portion 208 and the relative portions of the small grain structures of the second outer conductive portion 118 and the fourth outer conductive portion 218 may form a single layer of a single grain thickness. For example, at least one of the first outer conductive portion 108 and the third outer conductive portion 208 has a thickness of a single grain layer. For example, at least one of the second outer conductive portion 118 and the fourth outer conductive portion 218 has a thickness of a single grain layer.

[0050] In addition, although Figure 1 Three dielectric portions and two conductive portions on each substrate are shown, but in other embodiments, the number of dielectric portions and conductive portions can be increased as needed. In addition, the dishing size defining the grooves within the conductive portions can vary, for example, between 1-10 nm, and in some embodiments, the dishing size is equal to the size of the pitch between the conductive portions.

[0051] Figure 2 Exemplary embodiments of a second package structure 200 are provided. Figure 2 The second packaging structure 200 and Figure 1The package structure 100 in the embodiment is different in that an intermediate conductive layer is included between the large grain structure layer and the small grain structure layer, the first intermediate conductive portion 107 is between the first substrate conductive portion 106 and the first outer conductive portion 108, the second intermediate conductive portion 117 is between the second substrate conductive portion 116 and the second outer conductive portion 118, the third intermediate conductive portion 207 is between the third substrate conductive portion 206 and the third outer conductive portion 208, and the fourth intermediate conductive portion 217 is between the fourth substrate conductive portion 216 and the fourth outer conductive portion 218. In some embodiments, the intermediate conductive layer can be used to reduce electromigration between the substrate conductive layer including the first to fourth substrate conductive portions 106, 116, 206 and 216 and the outer conductive layer including the first to fourth outer conductive portions 108, 118, 208 and 218, forming an electromigration barrier. In some embodiments, the intermediate conductive layer can be formed using a process such as PVD or ALD. In some embodiments, the intermediate conductive layer can include multiple layers. In some embodiments, the intermediate conductive layer may be formed on only one of the first substrate 102 and the second substrate 202 , rather than on both the first substrate 102 and the second substrate 202 .

[0052] FIG. 3A to FIG. 3C An example implementation of a first bond between the first substrate 102 and the second substrate 202 is provided. Figure 3A A pre-bonding state 302 is shown in which the substrates are spaced apart such that surface layers of the first substrate 102 and the second substrate 202 do not contact each other. Figure 3A In the example of FIG. 1 , the outer conductive layer including the first outer conductive portion 108, the second outer conductive portion 118, the third outer conductive portion 208 and the fourth outer conductive portion 218 exhibits small pits in the shape of a small concave surface within the structure. This can be formed, for example, in a polishing process, as described below with respect to FIG. 5A to FIG. 5K discussed.

[0053] In state 312, if Figure 3B As shown, the first substrate 102 and the second substrate 202 are moved so that the dielectric layers can contact. The contact between the dielectric layers can result in a dielectric melt bond at room temperature between the opposing dielectric portions. Thus, in state 312, the first dielectric portion 104 can be bonded to the fourth dielectric portion 204, the second dielectric portion 114 can be bonded to the fifth dielectric portion 214, and the third dielectric portion 124 can be bonded to the sixth dielectric portion 224. However, the first outer conductive portion 108 and the third outer conductive portion 208 that are opposite to each other have not yet been bonded, and the second outer conductive portion 118 and the fourth outer conductive portion 218 that are opposite to each other have not yet been bonded, and the aforementioned dished recess in the outer conductive layer prevents contact.

[0054] In state 312 with Figure 3C Between the states 322 shown, the package structure can be subjected to an annealing process such that in state 322, the first outer conductive portion 108 and the third outer conductive portion 208 relative to each other are bonded, and the second outer conductive portion 118 and the fourth outer conductive portion 218 relative to each other are bonded. Due to the small grain size in the outer conductive layer, the length of the grain boundary (observed on the surface before bonding) can be increased, acting as an efficient mass transfer channel across the interface, so that the grains can be able to grow across the initial bonding interface. In some embodiments, the reduction in grain boundary area can reduce the Gibbs free energy of the grain structure and can drive subsequent microstructural evolution (grain growth) during thermal annealing. In addition, the difference between the base conductive layer and the outer conductive layer can compensate for the mismatch in the coefficient of thermal expansion (CTE).

[0055] FIG. 4A to FIG. 4C An example embodiment of a second bond between the first substrate 102 and the second substrate 202 is shown when an intermediate conductive layer is included between the outer conductive layer and the base conductive layer. Figure 4A As shown, the elements can be the same as the pre-joined state 302 except that a first intermediate conductive portion 107 is added between the first base conductive portion 106 and the first outer conductive portion 108, a second intermediate conductive portion 117 is added between the second base conductive portion 116 and the second outer conductive portion 118, a third intermediate conductive portion 207 is added between the third base conductive portion 206 and the third outer conductive portion 208, and a fourth intermediate conductive portion 217 is added between the fourth base conductive portion 216 and the fourth outer conductive portion 218. Thus, in state 402, the first intermediate conductive portion 107, the second intermediate conductive portion 117, the third intermediate conductive portion 207, and the fourth intermediate conductive portion 217 experience the pits in the base conductive layer and the outer conductive layer. In state 412, the first dielectric portion 104 can be joined to the fourth dielectric portion 204, the second dielectric portion 114 can be joined to the fifth dielectric portion 214, and the third dielectric portion 124 can be joined to the sixth dielectric portion 224. However, the first outer conductive portion 108 and the third outer conductive portion 208 that are opposite to each other have not yet been joined, and the second outer conductive portion 118 and the fourth outer conductive portion 218 that are opposite to each other have not yet been joined, and the dished recess in the outer conductive layer prevents contact. In state 422, after the annealing process, the first outer conductive portion 108 and the third outer conductive portion 208 that are opposite to each other are joined, and the second outer conductive portion 118 and the fourth outer conductive portion 218 that are opposite to each other are joined, and the intermediate conductive layer remains between the base conductive layer and the outer conductive layer.

[0056] FIG. 5A to FIG. 5K An illustrative embodiment of a packaging process is provided. Figure 6 shows the method for forming FIG. 5A to FIG. 5KThe illustrative embodiments of the corresponding packaging structures are described in detail in detail with reference to an example embodiment of a process 600 .

[0057] Figure 5A Shown in Figure 6 At S610 in the step, a dielectric layer 502 is deposited onto the substrate 500. The dielectric layer 502 may be deposited directly onto the substrate 500, or may have an intervening structure on which the dielectric layer 502 is deposited. In some embodiments, the dielectric layer 502 may alternatively be grown onto the substrate 500, for example, via a diffusion process to obtain a silicon oxide layer on a silicon substrate. In some embodiments, a combination of materials and techniques may be used to form multiple dielectric layers on the substrate 500.

[0058] Figure 5B Shown in Figure 6 At S620 and S630 in the process, a photoresist layer 504 is deposited on the dielectric layer 502 and then patterned. The photoresist layer 504 is patterned to form a series of patterned grooves 506H that expose the surface of the dielectric layer 502.

[0059] Figure 5C Shown in Figure 6 An etching process is performed on the exposed surface of the dielectric layer 502 using the patterned grooves 506H in the photoresist layer at S640 in the embodiment. For example, the dielectric layer is partially removed using chemical wet etching, dry etching such as using plasma, or another process such as using laser exposure to form a groove 510H in the dielectric layer 502. The groove 510H may have a width of 50nm to 5μm depending on the desired pitch and bonding process. For W2W bonding, the pitch may be in the range of from 100nm to 1μm, so the width of the interconnect may be in the range of from 50nm to 500μm. For D2W bonding, the pitch may be in the range of from 1μm to 10μm, so the width of the interconnect may be as high as 5μm. In addition, in some embodiments, the groove 510H may have a depth equal to the thickness of the dielectric layer 502. However, in some embodiments, the groove 510H may have a depth that is only a fraction of the thickness of the dielectric layer 502 , and in other embodiments, the groove 510H may have a depth greater than the thickness of the dielectric layer 502 and penetrate into the substrate 500 .

[0060] Figure 5D Shown in Figure 6 At S650 in the process, the remaining portion of the photoresist layer 504 is removed from the dielectric layer 502. This removal can be performed chemically, physically, or thermally. The portion of the dielectric layer 502 remaining between the grooves 510H may be referred to as an unpatterned region in addition to being referred to as the dielectric layer 502.

[0061] Figure 5E Shown in Figure 6 At S660 in the process, a seed layer or barrier layer 512 is conformally deposited on the surface of the dielectric layer 502 and the recess 510H. The seed layer 512 may be deposited using various processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, the seed layer 512 may provide an interface to allow a larger grain base conductive layer 514 to be formed later to be bonded to the substrate 500 or the dielectric layer 502. In some embodiments, the seed layer 512 may be used to impart a specific orientation to the larger grain base conductive layer. In some embodiments, the seed layer 512 may be optional, and the larger grain base conductive layer 514 may be directly bonded to the substrate 500 or the dielectric layer 502.

[0062] Fig. 5F Shown in Figure 6 At S670 in the process, a larger grain base conductive layer 514 is deposited onto the seed layer 512. The deposition may be conformal, so that the recess 510H is filled with the material of the larger grain base conductive layer 514. The deposition may be performed by a process that may produce grains having an average grain size of about 0.5 to 5 microns, such as an ECD plating process. The thickness of the larger grain base conductive layer 514 is sufficient to completely cover the surface of the seed layer 512 on the dielectric layer 502 and the recess 510H. Alternatively, in some embodiments without a seed layer 512, the larger grain base conductive layer 514 may directly cover the dielectric layer 502.

[0063] Figure 5G Shown in Figure 6 At S680 in FIG. 5 , the surface of the substrate 500 is polished after depositing the larger grain base conductive layer 514. A polishing process such as chemical mechanical polishing (CMP) removes excess portions of the larger grain base conductive layer 514 and any portion of the seed layer 512 outside the recess 510H. The remaining portion of the larger grain base conductive layer 514 forms a large grain portion 520. Therefore, after removing the seed layer 512 and the portion of the larger grain base conductive layer 514 outside the recess 510H, a portion of the surface of the dielectric layer 502 may be exposed. The large grain portion 520 may exhibit a pit.

[0064] Reference Figure 6 In S685, a process of depositing an intermediate layer on the surface of the larger grain base conductive layer and the dielectric layer may be added. Specifically, the intermediate layer may be deposited on the surface of the larger grain base conductive layer 514 and the dielectric layer 502. The intermediate layer may be, for example, the first intermediate conductive portion 107, the second intermediate conductive portion 117, the third intermediate conductive portion 207, or the fourth intermediate conductive portion 217. In some embodiments, the intermediate layer may be an intermediate grain layer.

[0065] Figure 5H Shown in Figure 6 At S690 in the process, a smaller grain outer conductive layer 522 is deposited on the exposed surface of the substrate 500. The smaller grain outer conductive layer 522 may be deposited using PVD or ALD. Using the ALD process, the average grain size of the smaller grain outer conductive layer 522 may be 2-5 nm, and using the PVD process, the average grain size of the smaller grain outer conductive layer 522 may be 5-10 nm. The thickness of the smaller grain outer conductive layer 522 may be comparable to the grain size, 2-10 nm or thicker. In some embodiments, the smaller grain outer conductive layer 522 may be a single monolayer thick.

[0066] Fig.5I Shown in Figure 6 An additional polishing step at S695 in the embodiment for removing those portions of the smaller grain outer conductive layer 522 above the dielectric layer 502. In some embodiments, only a portion of the smaller grain outer conductive layer 522 (i.e., the remaining portion 530) remains in the recess 510H in contact with the large grain portion 520. The remaining portion 530 can exhibit a pit in which the CMP process previously removed an excess portion of the larger grain base conductive layer 514. This polishing step can also be a CMP process and is compatible with large-scale manufacturing. In some embodiments, a single polishing process can be used to remove portions of both the larger grain base conductive layer 514 and the smaller grain outer conductive layer 522. For example, the larger grain base conductive layer 514 and the smaller grain outer conductive layer 522 are polished together to expose the surface of the dielectric layer 502. In some embodiments, a single lithography process can be used to define the grooves in both the larger grain base conductive layer 514 and the smaller grain outer conductive layer 522, while in some embodiments, multiple lithography steps can be used. In some embodiments, lithography can be photolithography.

[0067] Figure 7 A process 700 for bonding two substrates to form a package is described. The second substrate 202 is added to Figure 7 In the processing at S710 in Fig.5I After the polishing shown, the first substrate 102 and the second substrate 202 are prepared for bonding. That is, at S710, the first substrate 102 and the second substrate 202 are prepared. Figure 7 The substrates are aligned at S720 such that, when the substrate is moved into position at S730, corresponding dielectric and conductive portions will be in contact, allowing the dielectric regions to be joined using diffusion bonding at S740. Figure 5Jshows the result of diffusion bonding between dielectric regions and can be similar to Figure 3B Consistent. Figure 7 At S750, an annealing process is used to bond the conductive areas of the first substrate 102 and the second substrate 202. Figure 5K shown. Figure 7 The results of the S750 are Figure 1 and Figure 3C The annealing process is consistent, indicating that the package structure 100 completed after the annealing process has the smaller off-grain conductive layer 522 of each substrate bonded to the relative structure, for example, the relative smaller off-grain conductive layers 522 of the first substrate 102 and the second substrate 202 are bonded to each other. The relative smaller off-grain conductive layers 522 of the first substrate 102 and the second substrate 202 are not patterned when bonded. For example, the portion of the smaller off-grain conductive layer 522 that remains in the groove 510H can be referred to as an unpatterned area. In some embodiments, the smaller off-grain conductive layers 522 of the first substrate 102 and the second substrate 202 can be effectively merged into a single crystal layer. The method for bonding the smaller off-grain conductive layers 522 is as follows: Figure 7 The annealing process at S750 may be performed at a lower temperature than the equivalent annealing for the larger grain base conductive layer 514. For example, the smaller grain outer conductive layer 522 may be joined at an annealing temperature that is 50-100°C lower than the larger grain base conductive layer 514. For example, when the conductive layer is made of copper, the larger grain base conductive layer 514 may be annealed at a temperature of 350°C. In contrast, the smaller grain outer conductive layer 522 may be annealed at a temperature of 300°C or less, 250°C or less, 200°C or less, or 150°C or less. For example, the first substrate 102 and the second substrate 202 are annealed at a temperature between 150°C and 250°C. In addition, at these temperatures, the conductive layer may undergo structural changes in the grains and may diffuse into the surrounding substrate or dielectric material.

[0068] Although Figure 1The example embodiments of the present invention and the like show the first substrate 102 and the second substrate 202 as being the same, but in other embodiments, the first substrate 102 and the second substrate 202 may be different from each other. For example, the number of dielectric layers, conductive layers, and materials used in one substrate may be different from the number of dielectric layers, conductive layers, and materials used in the other substrate. For example, the smaller grain outer conductive layer 522 in the first substrate 102 and the second substrate 202 may be different or substantially the same in composition, average grain size, and orientation. For example, the larger grain base conductive layer 514 in the first substrate 102 and the second substrate 202 may be different or substantially the same in composition, average grain size, and orientation. In addition, the orientation of the base conductive layer may be different from the outer conductive layer and the intermediate conductive layer. As disclosed herein, the orientation of each conductive layer may be random. As used herein, orientation may refer to grain orientation or crystallographic orientation, for example, based on the direction of the crystals oriented within the lattice forming the wafer, a silicon wafer may have a crystallographic orientation including 100, 111, 110, 112, 211, and 511. In some embodiments, a layer may be formed with the same orientation as the underlying layer, and in some embodiments, a layer may be formed with a different orientation than the underlying layer. For example, the smaller grain outer conductive layer 522 and the larger grain base conductive layer 514 in each substrate may be different or substantially the same in orientation.

[0069] Figure 8 A high-level view of a process 800 for forming a packaged device is shown. At S810, for example, Figure 6 In the process 600, a first substrate having at least one conductive region and at least one dielectric region is prepared. At S820, for example, according to Figure 6 In process 600, a second substrate having at least one conductive region and at least one dielectric region is prepared. At S830, the first substrate and the second substrate are aligned, for example, the at least one conductive region and the at least one dielectric region of the first substrate are respectively opposite to the at least one conductive region and the at least one dielectric region of the second substrate. At S840, the first substrate and the second substrate are bonded together, for example, by moving one substrate onto the other substrate, so that the at least one dielectric region of each substrate is in contact. At room temperature, a fusion bonding process will occur between the two dielectric regions in contact. At S850, the substrates are then subjected to an annealing process to bond the at least one conductive region of the first substrate to the at least one conductive region of the second substrate.

[0070] In some embodiments, the bonding temperature required to anneal the copper surfaces together can correspond to the roughness of each of the copper surfaces. In some embodiments, a larger grain copper layer can be deposited via an ECD process, and a smaller grain copper layer can be deposited via a PVD process. Compared with the grain boundaries on the surface before bonding, the smaller grain copper layer formed by PVD can increase the length of the grain boundaries, acting as an efficient mass transfer channel across the interface, so the grains can be able to grow above the initial bonding interface. In some embodiments, the reduction of the grain boundary area can be the main driving force to reduce the Gibbs free energy of the structure, and can drive subsequent microstructural evolution (grain growth) during thermal annealing. In some embodiments, reducing the surface roughness of Cu can also reduce the thermal budget in Cu to Cu bonding, because the annealing temperature can decrease corresponding to a lower surface roughness.

[0071] Thus, in some embodiments, the packaging process disclosed herein can allow low temperature Cu-Cu bonding, enabling the use of a wide range of substrate types, such as organic substrates. The bonding can also be independent of the orientation of the grains, and the thin interface between the smaller grain conductive layers allows the smaller grain conductive layers to mix during annealing to form a single monolayer.

[0072] Although this specification may include many specific implementation details, these implementation details should not be interpreted as limitations on the scope of any claimed subject matter, but should be interpreted as descriptions of features specific to a particular embodiment. Certain features described in the context of separate embodiments in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0073] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring to perform these operations in the particular order shown or in a sequential order or requiring to perform all the operations shown to achieve the desired result. In some cases, multitasking and parallel processing can be advantageous. In addition, the separation of the various system components in the above-mentioned embodiments should not be understood as requiring this separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or encapsulated in multiple software products.

[0074] Thus, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims may be performed in a different order and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain implementations, multitasking and parallel processing may be advantageous.

[0075] Those skilled in the art will recognize that the innovative concepts described herein can be modified and varied over a wide range of applications. Therefore, the scope of the claimed subject matter should not be limited to any specific exemplary teachings discussed above, but rather is defined by the appended claims.

[0076] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 541,776 filed on September 29, 2023 and U.S. Non-Provisional Patent Application No. 18 / 655,217 filed on May 3, 2024, the disclosures of which are hereby incorporated by reference in their entirety.

Claims

1. A packaging device, comprising: A first substrate including a first conductive region and a first insulating region; as well as a second substrate including a second conductive region contacting the first conductive region and a second insulating region contacting the first insulating region, The first conductive region comprises a first grain layer and a second grain layer contacting the first grain layer, and the second grain layer has an average grain size larger than that of the first grain layer. wherein the second conductive region has a third grain layer and a fourth grain layer contacting the third grain layer, the fourth grain layer having an average grain size larger than that of the third grain layer, and Wherein, at least one of the first grain layer and the third grain layer has a thickness of a single grain layer.

2. The packaged device according to claim 1, wherein: The crystal orientation of the first grain layer is different from the crystal orientation of the second grain layer, and Wherein, the crystal orientation of the third crystal grain layer is different from the crystal orientation of the fourth crystal grain layer.

3. The packaged device according to claim 1, wherein: The crystal orientation of the first grain layer is substantially the same as the crystal orientation of the second grain layer, and Wherein, the crystal orientation of the third crystal grain layer is substantially the same as the crystal orientation of the fourth crystal grain layer.

4. The packaged device according to claim 1, wherein: The crystal orientation of the first grain layer is substantially the same as the crystal orientation of the third grain layer, and Wherein, the crystal orientation of the second crystal grain layer is different from the crystal orientation of the fourth crystal grain layer.

5. The packaged device according to claim 1, wherein: The first grain layer and the third grain layer have substantially the same average grain size.

6. The packaged device according to claim 1, wherein: The first seed layer includes a first copper layer, the second seed layer includes a second copper layer different from the first copper layer, and The third grain layer includes a third copper layer, and the fourth grain layer includes a fourth copper layer different from the third copper layer.

7. The packaged device according to claim 6, wherein: The second copper layer is different from the fourth copper layer.

8. The packaged device according to claim 7, wherein: At least one of the first seed layer and the third seed layer forms an electromigration barrier between the second seed layer and the fourth seed layer.

9. The packaged device according to claim 1, wherein: An average grain size of at least one of the first grain layer and the third grain layer is less than about 10 nanometers, and Wherein, the average grain size of each of the second grain layer and the fourth grain layer is greater than about 0.1 micrometers.

10. A packaging device, comprising: A first seed layer, contacting the first substrate; a second seed layer contacting the second substrate; as well as A third grain layer contacts the first grain layer and the second grain layer, and the third grain layer has an average grain size smaller than that of the first grain layer or the second grain layer.

11. The packaged device according to claim 10, wherein: The crystal orientation of the first crystal grain layer, the crystal orientation of the second crystal grain layer, and the crystal orientation of the third crystal grain layer are substantially the same.

12. The packaged device according to claim 10, wherein: The crystal orientation of the first grain layer is different from the crystal orientation of the second grain layer, and The crystal orientation of the third crystal grain layer is different from the crystal orientations of the first crystal grain layer and the second crystal grain layer.

13. The packaged device according to claim 10, wherein: The crystal orientation of the first grain layer is different from the crystal orientation of the second grain layer, and The crystal orientation of the third crystal grain layer is different from the crystal orientation of at least one of the first crystal grain layer and the second crystal grain layer.

14. A method of forming a packaged device, comprising: Depositing a first insulating region on a first substrate, forming a first groove in the first insulating region, and depositing a first conductive layer in the first groove; Depositing a second insulating region on a second substrate, forming a second groove in the second insulating region, and depositing a second conductive layer in the second groove; forming a third conductive layer on the first conductive layer and forming a fourth conductive layer on the second conductive layer, at least one of the third conductive layer and the fourth conductive layer having a different grain orientation from the first conductive layer and the second conductive layer; bonding the first insulating region to the second insulating region; as well as The first substrate and the second substrate are annealed at a temperature lower than 250° C. to bond the third conductive layer and the fourth conductive layer into a single layer.

15. The method according to claim 14, wherein: The first conductive layer and the second conductive layer are formed using electrochemical deposition plating, and The third conductive layer and the fourth conductive layer are formed by at least one of physical vapor deposition and atomic layer deposition.

16. The method of claim 14, further comprising annealing the first substrate and the second substrate at a temperature below 200°C.

17. The method of claim 14, further comprising annealing the first substrate and the second substrate at a temperature between 150°C and 250°C.

18. The method according to claim 14, further comprising: polishing the first conductive layer to expose the surface of the first insulating region before forming the third conductive layer; polishing the second conductive layer to expose a surface of the second insulating region before forming the fourth conductive layer; as well as Before bonding the first insulating region to the second insulating region, the third conductive layer is polished to expose the surface of the first insulating region, and the fourth conductive layer is polished to expose the surface of the second insulating region.

19. The method of claim 14, further comprising: polishing the first conductive layer and the third conductive layer together to expose a surface of the first insulating region; as well as The second conductive layer and the fourth conductive layer are polished together to expose a surface of the second insulating region.

20. The method according to claim 14, wherein: forming the first groove in the first insulating region and forming the second groove in the second insulating region is performed using photolithography, and The third conductive layer and the fourth conductive layer are not patterned when they are joined.

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