Trench structure, power device and preparation method thereof

Abstract

The present invention provides a groove structure, a power device and a preparation method thereof, the preparation method comprising: forming a graphic hard mask on a semiconductor substrate; performing a first etching on the semiconductor substrate, performing a first etching stage under a first gas pressure to form a plurality of grooves and semiconductor sidewalls in the semiconductor substrate, and then performing a second etching stage in situ under a second gas pressure to form an arc-shaped bottom in the groove, the second gas pressure being greater than the first gas pressure; removing the graphic hard mask; filling the groove with organic matter, removing the organic matter on the upper part of the groove to reveal the top corner area of ​​the semiconductor sidewall; performing a second etching on the top corner area of ​​the exposed semiconductor sidewall to form a rounded corner structure in the top corner area; removing the organic matter. The present invention can effectively reduce the problem of high cost caused by etching silicon carbide grooves in multiple steps and multiple reaction chambers, and avoid the problems of wafer contamination and reduced production efficiency caused by etching in multiple reaction chambers, while improving the performance of trench gate material filling.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a groove structure, a power device and a preparation method thereof. Background Art

[0002] As one of the representative materials of the third-generation semiconductors, silicon carbide (SiC) has been widely used in power chips. Silicon carbide power devices are very suitable for high-frequency, high-voltage, high-temperature and other applications, which help to improve the efficiency and power density of power electronic systems. In order to obtain better performance and higher channel mobility, silicon carbide field-effect transistors (SiCMOSFET) use a silicon carbide trench gate structure to achieve lower on-resistance and improve device performance, but silicon carbide trench etching and morphology improvement are very challenging. How to obtain faster etching rate, higher etching selectivity, smoother sidewall roughness, and better etching morphology is a very important technical difficulty.

[0003] Existing silicon carbide trench gate preparation usually has the following shortcomings and technical difficulties:

[0004] First, the formation of silicon carbide grooves usually adopts a two-step process: the first step is to etch the groove, and the second step is to process the bottom of the groove to form an arc bottom. The above two steps usually need to be performed in two reaction chambers, resulting in high process costs, as well as increased difficulty in etching process and increased difficulty in maintenance.

[0005] Second, the top corners of silicon carbide trenches are usually rounded by high-temperature heat treatment. The maintenance of high-temperature equipment is challenging and has high maintenance costs. At the same time, high temperatures can easily have adverse effects on silicon carbide devices, resulting in reduced production yields.

[0006] Third, the rounding method formed at high temperature has a limited adjustment range for the width and curvature of the arc, and has low adjustability, which will cause difficulties in the subsequent growth of the gate oxide layer on the surface of the groove and the filling of the polysilicon gate material. After filling, problems such as gaps or cavities are likely to occur.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a trench structure, a power device and a preparation method thereof, so as to solve the problems in the prior art of complex silicon carbide trench gate preparation process, high equipment maintenance cost and difficulty in filling trench gate material.

[0009] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing a groove structure of a power device, the preparation method comprising the following steps: providing a semiconductor substrate, forming a graphic hard mask on the semiconductor substrate; performing a first etching on the semiconductor substrate based on the graphic hard mask, the first etching comprising a first etching stage under a first gas pressure to form a plurality of grooves and semiconductor sidewalls located between adjacent grooves in the semiconductor substrate, and then performing a second etching stage in situ under a second gas pressure to form an arc-shaped bottom in the groove, the second gas pressure being greater than the first gas pressure; removing the graphic hard mask; filling the groove with organic matter, removing the organic matter on the upper part of the groove to expose the top corner area of ​​the semiconductor sidewall; performing a second etching on the top corner area of ​​the exposed semiconductor sidewall to form a rounded corner structure in the top corner area; removing the organic matter.

[0010] Optionally, the semiconductor substrate is a silicon carbide substrate.

[0011] Optionally, forming a pattern hard mask on a semiconductor substrate comprises: forming a silicon dioxide layer on the semiconductor substrate; forming a photoresist layer on the silicon dioxide layer, and forming a photoresist window in the photoresist layer by a photolithography process; transferring the photoresist window to the silicon dioxide layer by a dry etching process to form an etching window; the gas used in the dry etching process comprises a carbon fluorine gas, an oxygen-containing gas, a diluent gas and an inert gas, the etching temperature is 0°C to 60°C, the etching pressure is 1mtorr to 1Torr, and the etching power is 10W to 2000W, wherein the carbon fluorine gas comprises CF 4 , CHF 3 , C 4 F 6 and C 4 F 8 The oxygen-containing gas comprises at least one of oxygen and carbon monoxide, the diluent gas comprises nitrogen, and the inert gas comprises argon.

[0012] Optionally, the first gas pressure is less than 100 mtorr, and the second gas pressure is greater than 100 mtorr.

[0013] Optionally, the first etching stage and the second etching stage are performed in situ in the same reaction chamber, and the gases used in the first etching stage and the second etching stage include etching source gas, oxygen-containing gas, dilution gas and inert gas, the etching temperature is 0°C to 60°C, and the etching power is 50W to 3000W, wherein the etching source gas includes SiF 4 、SiCl 4 , SF 6 、HBr、Cl 2 , and BCl 3 At least one of the oxygen-containing gas comprises oxygen, and the diluent gas comprises N 2 and H2 At least one of the inert gas includes at least one of Ar and He.

[0014] Optionally, an organic substance is filled in the groove by a spin coating process, and the organic substance includes one of a spin-coated carbon-based material and a bottom anti-reflection film material.

[0015] Optionally, the organic matter on the upper part of the groove is removed by a dry etching process, the etching source gas used in the dry etching process includes oxygen, the etching temperature is 10° C. to 80° C., the etching pressure is 1 mTorr to 500 mTorr, and the etching power is 1 W to 500 W.

[0016] Optionally, the height of the top corner region exposed by the semiconductor sidewall is controlled by controlling the height of the organic matter retained in the groove, and the ratio of the height of the top corner region exposed by the semiconductor sidewall to the groove depth is between 1:100 and 1:5.

[0017] Optionally, the second etching includes isotropic dry etching, and the second etching is performed under a gas pressure greater than 100 mtorr.

[0018] Optionally, the gas used in the second etching includes an etching source gas, an oxygen-containing gas, a diluent gas and an inert gas, the etching temperature is 10° C. to 100° C., and the etching power is 10W to 2500W, wherein the etching source gas includes CF 4 , C 4 F 8 , Cl 2 and BCl 3 At least one of the oxygen-containing gas comprises oxygen, and the diluent gas comprises N 2 and H 2 At least one of the inert gases includes He.

[0019] Optionally, the method further includes a step of repairing the rounded corner structure.

[0020] Optionally, the width of the rounded structure is one tenth to one half of the lateral width of the groove.

[0021] Optionally, a high temperature ashing process is used to remove organic matter, and the gas of the high temperature ashing process includes O 2 、F 2 , H 2 、N 2 and NH 3 For all the gases in the ashing, the ashing temperature is 50℃~350℃, the ashing pressure is 1mtorr~10torr, and the ashing power is 10W~6000W.

[0022] Optionally, the method further includes the steps of: forming a gate oxide layer at the bottom and sidewalls of the trench; and filling the trench with a gate material, such as a polysilicon layer.

[0023] The present invention also provides a method for preparing a power device, the method comprising the method for preparing a power device trench structure as described in any one of the above schemes.

[0024] The present invention also provides a power device, which is prepared by the method for preparing the power device as described above.

[0025] As described above, the trench structure, power device and preparation method thereof of the present invention have the following beneficial effects:

[0026] The present invention realizes the steps of etching a vertical silicon carbide groove and rounding the bottom corners in situ in the same reaction chamber, which can effectively reduce the high cost problem caused by etching the silicon carbide groove in multiple steps and multiple reaction chambers, and avoid the problems of wafer contamination and reduced production efficiency caused by etching in multiple reaction chambers.

[0027] The present invention achieves the rounding of the top corners of the groove by trench filling and etching the top of the groove, which has the following advantages: First, it can avoid the process difficulties and high cost of process equipment caused by the use of high-temperature annealing equipment, which is conducive to reducing costs, reducing process difficulty and improving process efficiency. Second, by rounding the top corners through trench filling and etching, the height and width of the fillet can be effectively adjusted, increasing the process window for subsequent trench filling. Third, it can make the vertical sidewall morphology of the groove and the different arc degrees of the top corner of the groove flexible to achieve customized solutions, greatly expanding the scope of application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0029] Figure 1 to Figure 9 It is a schematic structural diagram showing the various steps of the method for preparing the trench structure according to an embodiment of the present invention.

[0030] Fig.10 An enlarged schematic diagram showing the rounded corner structure at the top of the trench structure prepared according to an embodiment of the present invention.

[0031] Description of component numbers: 101 semiconductor substrate, 102 silicon dioxide layer, 103 photoresist layer, 104 graphic hard mask, 105 etching window, 106 groove, 107 semiconductor sidewall, 108 arc-shaped bottom, 109 organic matter, 110 top corner region, 111 rounded corner structure, 112 gate oxide layer, 113 polysilicon layer. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0034] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0035] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0036] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0037] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0038] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0039] like Figure 1 to Figure 10As shown, this embodiment provides a method for preparing a trench structure of a power device, and the preparation method comprises the following steps:

[0040] like Figure 1~Figure 2 As shown, firstly, step 1) is performed to provide a semiconductor substrate 101 and form a pattern hard mask 104 on the semiconductor substrate 101.

[0041] In one embodiment, the semiconductor substrate 101 is a silicon carbide (SiC) substrate. The SiC substrate may be undoped or doped, and may be formed with specific doping regions, such as N-type doping regions or P-type doping regions, and the doping regions may have the same doping concentration or different doping concentrations.

[0042] In one embodiment, forming a patterned hard mask 104 on a semiconductor substrate 101 includes:

[0043] like Figure 1 As shown, first, a silicon dioxide layer 102 is formed on a semiconductor substrate 101. For example, the silicon dioxide layer 102 can be formed on the semiconductor substrate 101 by a process such as plasma enhanced chemical vapor deposition (PECVD).

[0044] like Figure 1 As shown, a photoresist layer 103 is then formed on the silicon dioxide layer 102 , such as by a spin coating process, and a photolithography window is formed in the photoresist layer 103 by a photolithography process.

[0045] like Figure 2 As shown, the photolithography window is finally transferred to the silicon dioxide layer 102 by a dry etching process to form an etching window 105. The gas used in the dry etching process includes carbon fluorine gas, oxygen-containing gas, diluent gas and inert gas, the etching temperature is 0°C~60°C, the etching pressure is 1mtorr~1Torr, and the etching power is 10W~2000W, wherein the carbon fluorine gas includes CF 4 , CHF 3 , C 4 F 6 and C 4 F 8 The oxygen-containing gas includes at least one of oxygen and carbon monoxide, the diluent gas includes nitrogen, and the inert gas includes argon. In a specific embodiment, the gas used in the etching process includes CF 4 , O 2 、N 2 and Ar, the etching temperature is 40°C, the etching pressure is 10 mtorr, and the etching power is 500 W. In another specific embodiment, the gas used in the etching process includes CF 4 , C 4 F6 , O 2 、N 2 and Ar, the etching temperature is 20° C., the etching pressure is 15 mtorr, and the etching power is 800 W. The parameters of the etching process can be set according to actual needs and are not limited to the examples listed above.

[0046] like Figure 3 As shown, step 2 is then performed), the semiconductor substrate 101 is first etched based on the graphic hard mask 104, the first etching includes a first etching stage under a first gas pressure to form a plurality of grooves 106 and semiconductor sidewalls 107 located between adjacent grooves 106 in the semiconductor substrate 101, and then a second etching stage is performed in situ under a second gas pressure to form an arc-shaped bottom 108 in the groove 106, and the second gas pressure is greater than the first gas pressure.

[0047] The first etching stage is performed at a relatively low pressure, so that the byproducts (such as carbon-based polymers, etc.) generated by the etching can be quickly extracted from the surface of the groove 106, so that a relatively vertical groove sidewall can be obtained, and the etching has a high efficiency, which is conducive to improving production efficiency. Then, in situ in the same reaction chamber, by controlling the pressure of the reaction chamber, the second etching stage is performed at a relatively high pressure. At this time, the carbon-based polymers will adhere to the sidewalls and bottom of the groove, especially gather at the bottom of the groove, so that the etching rate becomes smaller, and the carbon-based polymers are more likely to gather at the corners of the bottom and the sidewalls. At the same time, the etching gas is more likely to reach the middle area of ​​the bottom, so that the etching rate of the bottom of the groove gradually decreases from the middle area of ​​the bottom toward the two side walls, and finally a circular arc bottom 108 is formed in the groove 106.

[0048] In one embodiment, the first gas pressure is less than 100 mtorr, and the second gas pressure is greater than 100 mtorr. For example, the first gas pressure may be 1 mtorr, 5 mtorr, 10 mtorr, 20 mtorr, 50 mtorr, etc., and the second gas pressure may be 120 mtorr, 200 mtorr, 300 mtorr, 500 mtorr, etc., and is not limited to the examples listed here.

[0049] In one embodiment, the first etching stage and the second etching stage are performed in situ in the same reaction chamber, and the gases used in the first etching stage and the second etching stage include etching source gas, oxygen-containing gas, dilution gas and inert gas, the etching temperature is 0°C to 60°C, and the etching power is 50W to 3000W, wherein the etching source gas includes SiF 4 、SiCl 4 , SF 6 、HBr、Cl 2 , and BCl 3At least one of the oxygen-containing gas comprises oxygen, and the diluent gas comprises N 2 and H 2 In one embodiment, the gas used in the first etching stage includes SF 6 , O 2 、N 2 and Ar, the etching temperature is 40°C, the etching pressure is 5mtorr, the etching power is 1500W, and the gases used in the second etching stage include SF 6 , O 2 、N 2 and Ar, the etching temperature is 40°C, the etching pressure is 200 mtorr, and the etching power is 800 W. In another specific example, the gas used in the first etching stage includes BCl 3 , O 2 , SF 6 、N 2 and Ar, the etching temperature is 30°C, the etching pressure is 10mtorr, the etching power is 2000W, and the gases used in the second etching stage include BCl 3 , O 2 , SF 6 、N 2 and Ar, the etching temperature is 40°C, the etching pressure is 300 mtorr, and the etching power is 1000 W. In another specific embodiment, the gas used in the first etching stage includes Cl 2 , O 2 and N 2 The etching temperature is 20°C, the etching pressure is 5mtorr, the etching power is 1500W, and the gases used in the second etching stage include Cl 2 , O 2 and N 2 , the etching temperature is 20° C., the etching pressure is 200 mtorr, and the etching power is 800 W. The parameters of the above etching process can be set according to actual needs and are not limited to the examples listed above.

[0050] The present invention realizes the steps of etching a vertical silicon carbide groove and rounding the bottom corners in situ in the same reaction chamber, which can effectively reduce the high cost problem caused by etching the silicon carbide groove in multiple steps and multiple reaction chambers, and avoid the problems of wafer contamination and reduced production efficiency caused by etching in multiple reaction chambers.

[0051] like Figure 4 As shown, step 3 is then performed to remove the graphic hard mask 104.

[0052] In one embodiment, the patterned hard mask 104 may be removed by a wet etching or dry etching process.

[0053] like Figure 5~Figure 6 As shown, step 4 is then performed to fill the trench 106 with organic matter 109 , and remove the organic matter 109 on the upper portion of the trench 106 to expose the top corner region 110 of the semiconductor sidewall 107 .

[0054] In one embodiment, the organic matter 109 may be filled in the groove 106 by a spin coating process. The organic matter 109 includes one of a spin-coated carbon-based material and a bottom anti-reflection film material. In this embodiment, the organic matter 109 is a spin-coated carbon-based material (SOC).

[0055] In one embodiment, the organic matter 109 on the upper part of the groove 106 is removed by a dry etching process, wherein the etching source gas used in the dry etching process includes oxygen, the etching temperature is 10° C. to 80° C., the etching pressure is 1 mTorr to 500 mTorr, and the etching power is 1 W to 500 W. By controlling the time or process parameters of the dry etching process, the height of the organic matter 109 finally retained in the groove 106 can be controlled.

[0056] In one embodiment, the height h of the top corner region 110 exposed by the semiconductor sidewall 107 is controlled by controlling the height of the organic matter 109 retained in the groove 106, and the ratio of the height h of the top corner region 110 exposed by the semiconductor sidewall 107 to the depth of the groove 106 is between 1:100 and 1:5. For example, for a groove 106 with a depth of 10 microns, the height of the exposed top corner region 110 can be 0.5 microns; for a groove 106 with a depth of 5 microns, the height of the exposed top corner region 110 can be 0.2 microns; for a groove 106 with a depth of 30 microns, the height of the exposed top corner region 110 can be 3 microns, etc., and the examples listed here are not limited thereto.

[0057] like Figure 7 As shown, step 5 is then performed to perform a second etching on the exposed corner region 110 of the semiconductor sidewall 107 to form a rounded corner structure 111 in the corner region 110 .

[0058] In one embodiment, the second etching includes isotropic dry etching. For example, the second etching can be chemical etching, using an external electric field to ionize the etching gas into plasma, the plasma contains free electrons, charged ions, molecules and highly reactive groups, which diffuse to the surface of the etched film and react with the atoms on the surface of the film to generate volatile reaction products, and are extracted from the reaction chamber. The reaction is more intense in the top corner area 110, so a rounded corner structure 111 is finally formed in the top corner area 110. At the same time, during the above reaction process, the organic matter 109 in the groove 106 can effectively protect the side wall of the groove 106 below. For another example, the second etching can also be an etching method similar to isotropic etching achieved by a combination of anisotropic etching in multiple directions, and a rounded corner structure 111 is finally formed in the top corner area 110 by etching the top corner area 110 in multiple directions.

[0059] In one embodiment, the second etching is performed at a pressure greater than 100 mtorr, such as 120 mtorr, 200 mtorr, 300 mtorr, 500 mtorr, etc., and is not limited to the examples listed here. A higher pressure can reduce the etching rate during the second etching process, making the surface of the rounded structure 111 smoother and facilitating the control of the morphology of the rounded structure 111.

[0060] In one embodiment, the gas used in the second etching includes an etching source gas, an oxygen-containing gas, a diluent gas, and an inert gas, the etching temperature is 10° C. to 100° C., and the etching power is 10 W to 2500 W. The etching source gas includes CF 4 , C 4 F 8 , Cl 2 and BCl 3 At least one of the oxygen-containing gas comprises oxygen, and the diluent gas comprises N 2 and H 2 In one embodiment, the second etching gas comprises CF 4 , O 2 、N 2 and He, the etching temperature is 40°C, the etching pressure is 120 mtorr, and the etching power is 300 W; in another specific example, the gas used in the second etching includes BCl 3 , O 2 、N 2 and He, the etching temperature is 50°C, the etching pressure is 200mtorr, and the etching power is 500W.

[0061] In one embodiment, the step of repairing the rounded structure 111 is also included. The repairing may be, for example, annealing in a certain protective atmosphere.

[0062] In one embodiment, Fig.10 As shown, by filling and etching the groove 106 to form the rounded structure 111, the height and width of the rounded structure 111 can be effectively adjusted, and the width D2 of the rounded structure 111 can be one tenth to one half of the lateral width D1 of the groove 106. In one embodiment, the width D2 of the rounded structure 111 can be 0.01 micrometers to 5 micrometers.

[0063] The present invention achieves the rounding of the top corners of the groove 106 by filling the groove 106 and etching the top of the groove 106, which has the following advantages: First, it can avoid the process difficulties and high cost of process equipment caused by the use of high-temperature annealing equipment, which is conducive to reducing costs, reducing process difficulties and improving process efficiency. Second, by filling and etching the groove 106 to achieve the rounding of the top corners, the height and width of the fillet can be effectively adjusted, and the process window for subsequent filling of the groove 106 can be increased. Third, the vertical sidewall morphology of the groove 106 and the different arc degrees of the top corners of the groove 106 can be flexibly combined to achieve a customized solution, greatly expanding the scope of application of the present invention.

[0064] like Figure 8 As shown, step 6 is then performed to remove organic matter 109.

[0065] In one embodiment, a high temperature ashing process is used to remove the organic matter 109, and the gas of the high temperature ashing process includes O 2 、F 2 , H 2 、N 2 and NH 3 The ashing temperature is 50°C to 350°C, the ashing pressure is 1mtorr to 10torr, and the ashing power is 10W to 6000W. The present invention is filled with organic matter 109, and its removal process is relatively simple, which can effectively reduce the process difficulty and improve the process efficiency.

[0066] like Fig. 9 As shown, step 7 is finally performed to form a gate oxide layer 112 at the bottom and sidewalls of the trench 106, and fill the trench 106 with a gate material, such as a polysilicon layer 113.

[0067] The present embodiment also provides a method for preparing a power device, and the preparation method includes the method for preparing a power device groove structure as described in the above embodiment scheme. Further, the present embodiment also provides a power device, and the power device is prepared by the method for preparing a power device as described in the above embodiment. Since the prepared groove structure has an arc-shaped bottom 108 and a top rounded structure 111, the filling quality of the polysilicon layer 113 is effectively improved, and the arc-shaped bottom 108 and the rounded structure 111 can effectively improve the voltage resistance of the device, thereby comprehensively improving the overall performance of the silicon carbide power device.

[0068] As described above, the trench structure, power device and preparation method thereof of the present invention have the following beneficial effects:

[0069] The present invention realizes the steps of etching and bottom rounding of vertical silicon carbide grooves in situ in the same reaction chamber, which can effectively reduce the high cost problem caused by etching silicon carbide grooves in multiple steps and multiple reaction chambers, avoid wafer contamination and reduced production efficiency caused by etching in multiple reaction chambers, and significantly improve the gate material filling effect.

[0070] The present invention achieves the rounding of the top corners of the groove by trench filling and etching the top of the groove, which has the following advantages: First, it can avoid the process difficulties and high cost of process equipment caused by the use of high-temperature annealing equipment, which is conducive to reducing costs, reducing process difficulty and improving process efficiency. Second, by rounding the top corners through trench filling and etching, the height and width of the fillet can be effectively adjusted, increasing the process window for subsequent trench filling. Third, it can make the vertical sidewall morphology of the groove and the different arc degrees of the top corner of the groove flexible to achieve customized solutions, greatly expanding the scope of application of the present invention.

[0071] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a trench structure of a power device, characterized in that: The preparation method comprises: providing a semiconductor substrate, and forming a patterned hard mask on the semiconductor substrate; Performing a first etching on the semiconductor substrate based on the pattern hard mask, the first etching comprising performing a first etching stage under a first gas pressure to form a plurality of trenches and semiconductor sidewalls between adjacent trenches in the semiconductor substrate, and then performing a second etching stage in situ under a second gas pressure to form an arc-shaped bottom in the trench, the second gas pressure being greater than the first gas pressure; removing the graphic hard mask; Filling the trench with organic matter, and removing the organic matter on the upper portion of the trench to expose the top corner region of the semiconductor sidewall; Performing a second etching on the exposed top corner region of the semiconductor sidewall to form a rounded corner structure in the top corner region; The organic matter is removed.

2. The method for preparing a power device trench structure according to claim 1, characterized in that: The semiconductor substrate is a silicon carbide substrate.

3. The method for preparing a power device trench structure according to claim 1, characterized in that: Forming a patterned hard mask on the semiconductor substrate includes: forming a silicon dioxide layer on the semiconductor substrate; forming a photoresist layer on the silicon dioxide layer, and forming a photolithography window in the photoresist layer by a photolithography process; Transferring the photolithography window to the silicon dioxide layer by a dry etching process to form an etching window; The gases used in the dry etching process include carbon fluorine gas, oxygen-containing gas, diluent gas and inert gas, the etching temperature is 0°C~60°C, the etching pressure is 1mtorr~1Torr, and the etching power is 10W~2000W, wherein the carbon fluorine gas includes at least one of CF4, CHF3, C4F6 and C4F8, the oxygen-containing gas includes at least one of oxygen and carbon monoxide, the diluent gas includes nitrogen, and the inert gas includes argon.

4. The method for preparing a power device trench structure according to claim 1, characterized in that: The first gas pressure is less than 100 mtorr, and the second gas pressure is greater than 100 mtorr.

5. The method for preparing a power device trench structure according to claim 1, characterized in that: The first etching stage and the second etching stage are performed in situ in the same reaction chamber. The gases used in the first etching stage and the second etching stage include etching source gas, oxygen-containing gas, dilution gas and inert gas. The etching temperature is 0°C~60°C, and the etching power is 50W~3000W. The etching source gas includes at least one of SiF4, SiCl4, SF6, HBr, Cl2, and BCl3, the oxygen-containing gas includes oxygen, the dilution gas includes at least one of N2 and H2, and the inert gas includes at least one of Ar and He.

6. The method for preparing a power device trench structure according to claim 1, characterized in that: The groove is filled with an organic substance by a spin coating process, wherein the organic substance comprises one of a spin-coated carbon-based material and a bottom anti-reflection film material.

7. The method for preparing a power device trench structure according to claim 1, characterized in that: The organic matter on the upper part of the groove is removed by a dry etching process, wherein the etching source gas used in the dry etching process includes oxygen, the etching temperature is 10° C. to 80° C., the etching pressure is 1 mTorr to 500 mTorr, and the etching power is 1 W to 500 W.

8. The method for preparing a power device trench structure according to claim 1, characterized in that: The height of the top corner area exposed by the semiconductor sidewall is controlled by controlling the height of the organic matter retained in the groove, and the ratio of the height of the top corner area exposed by the semiconductor sidewall to the depth of the groove is between 1:100 and 1:

5.

9. The method for preparing a power device trench structure according to claim 1, characterized in that: The second etching includes isotropic dry etching, and the second etching is performed under a gas pressure greater than 100 mtorr.

10. The method for preparing a power device trench structure according to claim 9, characterized in that: The gas used in the second etching includes an etching source gas, an oxygen-containing gas, a dilution gas and an inert gas, the etching temperature is 10°C~100°C, and the etching power is 10W~2500W, wherein the etching source gas includes at least one of CF4, C4F8, Cl2 and BCl3, the oxygen-containing gas includes oxygen, the dilution gas includes at least one of N2 and H2, and the inert gas includes He.

11. The method for preparing a power device trench structure according to claim 1, characterized in that: The method also includes a step of repairing the rounded corner structure.

12. The method for preparing a power device trench structure according to claim 1, characterized in that: The width of the rounded corner structure is one tenth to one half of the lateral width of the groove.

13. The method for preparing a power device trench structure according to claim 1, characterized in that: A high-temperature ashing process is used to remove the organic matter. The gas of the high-temperature ashing process includes all gases of O2, F2, H2, N2 and NH3. The ashing temperature is 50°C~350°C, the ashing pressure is 1mtorr~10torr, and the ashing power is 10W~6000W.

14. The method for preparing a power device trench structure according to claim 1, characterized in that: Also includes the steps: forming a gate oxide layer at the bottom and sidewalls of the trench; The trench is filled with a gate material.

15. A method for preparing a power device, characterized in that: The preparation method includes the preparation method of the power device trench structure according to any one of claims 1 to 14.

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