Display substrate and display panel

Abstract

This application provides a display substrate and a display panel. The display substrate includes a substrate and a display area; a first metal layer disposed on the substrate, the first metal layer including multiple data traces located within the display area; and a second metal layer disposed on the first metal layer. The first and second metal layers are insulated from each other, and the second metal layer includes multiple fan-out traces that are bent within the display area. This application simplifies the film structure of the traces and the fabrication process by providing a first and second metal layer that are insulated from each other on the substrate. The first metal layer includes data traces, and the second metal layer includes fan-out traces bent within the display area. The data traces and fan-out traces are connected, and only the second metal layer is used to form the fan-out traces within the display area. This simplifies the fabrication process of the traces and reduces the manufacturing cost of the display substrate.

Description

Technical Field

[0001] This application relates to the field of display device technology, and in particular to a display substrate and a display panel. Background Technology

[0002] AMOLED display substrates are gradually becoming the next-generation display technology due to their high contrast, wide color gamut, and low power consumption. Compared with traditional LCD panels, OLED display substrates are easier to make flexible, making them a key technology for wearable and foldable products. With the development of OLED panel technology, narrow bezel technology has become a differentiating factor to attract users.

[0003] One design solution to address the difficulty of fanout routing in narrow or ultra-narrow bezels is to place some of the fanout traces in the display area (Fanout in AA, FIAA). However, in related technologies, the FIAA contains many film layers constituting the data traces, requiring at least three metal film layers, resulting in a complex data trace structure and high manufacturing costs. Summary of the Invention

[0004] This application provides a display substrate and a display panel to solve the problem of high manufacturing cost of data traces on the display substrate.

[0005] On one hand, this application provides a display substrate, comprising:

[0006] Substrate, including the display area;

[0007] A first metal layer is disposed on the substrate, and the first metal layer includes multiple data traces located within the display area;

[0008] A second metal layer is disposed on the first metal layer. The first metal layer and the second metal layer are insulated from each other. The second metal layer includes multiple fan-out traces, which are bent within the display area.

[0009] In one possible implementation of this application, the fan-out trace includes a first fan-out segment and a second fan-out segment. The first fan-out segment extends along the first direction, and the second fan-out segment extends along the second direction. The second fan-out segment is connected to the data trace, and the first direction and the second direction intersect.

[0010] In one possible implementation of this application, the second metal layer further includes:

[0011] At least one virtual trace, which is spaced apart from the fan-out trace. The virtual trace is located on the extension line of the fan-out trace, or the virtual trace and the fan-out trace are spaced apart in the same direction.

[0012] In one possible implementation of this application, the display substrate further includes a power supply voltage signal terminal, and the virtual trace is electrically connected to the power supply voltage signal terminal.

[0013] In one possible implementation of this application, the display area includes a fan-out routing area and a fan-out routing clearance area, wherein the fan-out routing area includes a first routing area and a second routing area;

[0014] The first fan-out section is located within the first routing area, the second fan-out section is located within the second routing area, and the virtual routing is located within the fan-out routing area and / or the fan-out routing clearance area.

[0015] In one possible implementation of this application, the virtual trace includes a first virtual trace extending along a first direction, the first virtual trace including at least two first sub-virtual segments, with adjacent first sub-virtual segments spaced apart; and / or,

[0016] The virtual trace includes a second virtual trace that extends along a second direction. The first direction and the second direction intersect. The second virtual trace includes at least two second sub-virtual segments, with adjacent second sub-virtual segments spaced apart.

[0017] In one possible implementation of this application, within the first routing area, the second virtual routing is located on the extension line of the second fan-out segment;

[0018] The second sub-virtual segment is located between two adjacent first fan-out segments, the second sub-virtual segment is connected to the first fan-out segment, and / or the second sub-virtual segment is spaced apart from the first fan-out segment.

[0019] In one possible implementation of this application, the second sub-virtual segment is spaced apart from the first fan-out segment, and a first via is provided on the second sub-virtual segment, the first via being connected to a power supply voltage signal.

[0020] In one possible implementation of this application, adjacent first sub-virtual segments are spaced apart within the second routing area, each second sub-virtual segment is connected between two adjacent first sub-virtual segments, and each second sub-virtual segment is spaced apart in the second direction.

[0021] In one possible implementation of this application, one of the two first sub-virtual segments connected to the second sub-virtual segment is provided with a second via, and the second via is connected to a power supply voltage signal.

[0022] In one possible implementation of this application, within the fan-out routing clearance area, the first virtual routing is located on the extension line of the first fan-out segment, the second virtual routing is located on the extension line of the second fan-out segment, and the first virtual routing and the second virtual routing are arranged to intersect each other.

[0023] In one possible implementation of this application, at least one of the first virtual traces is provided with a third via, and the second via is connected to a power supply voltage signal.

[0024] In one possible implementation of this application, the first metal layer further includes:

[0025] A power supply voltage signal line is located within the display area. Both the power supply voltage signal line and the data trace extend along a first direction, and the power supply voltage signal line and the data trace are spaced apart.

[0026] Along the first direction, the orthographic projection of the power supply voltage signal line on the substrate coincides with the orthographic projection of the fan-out trace on the substrate, and the orthographic projection of the data trace on the substrate coincides with the orthographic projection of the fan-out trace on the substrate.

[0027] In one possible implementation of this application, the display substrate further includes:

[0028] Thin-film transistors, at least disposed within the display area, the thin-film transistors comprising:

[0029] An active pattern is disposed on the substrate;

[0030] A gate is disposed on the active pattern;

[0031] The source and drain electrodes are disposed on the gate and are located in the first metal layer.

[0032] In one possible implementation of this application, the second metal layer further includes: a transition trace, wherein the transition trace is spaced apart from the fan-out trace;

[0033] The display substrate further includes: an electrode layer disposed on the second metal layer, wherein the second metal layer and the electrode layer are insulated from each other, and one end of the adapter trace is connected to the electrode layer and the other end is connected to the source and drain electrodes.

[0034] On the other hand, this application also provides a display panel, including the aforementioned display substrate.

[0035] This application provides a display substrate and a display panel. By providing a first metal layer and a second metal layer that are mutually insulated on the substrate, wherein the first metal layer includes data traces and the second metal layer includes fan-out traces that are bent within the display area, and the data traces and fan-out traces are connected, and only the second metal layer is used to form the fan-out traces within the display area, it is beneficial to simplify the film layer structure of the traces, simplify the fabrication process of the traces, and thus help reduce the manufacturing cost of the display substrate. Attached Figure Description

[0036] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0037] Figure 1 This is a top view of the display substrate provided in an embodiment of this application.

[0038] Figure 2 Examples of this application Figure 1 A schematic diagram of the film layer structure of the display substrate.

[0039] Figure 3 This is a schematic diagram of the partition structure of the display substrate provided in an embodiment of this application.

[0040] Figure 4 Examples of this application Figure 3 A schematic diagram of the structure of the first and second wiring areas.

[0041] Figure 5 Examples of this application Figure 3 A schematic diagram of the structure of the second wiring area and the first clearance area.

[0042] Figure 6 Examples of this application Figure 3 A schematic diagram of the structure of the first wiring area and the second clearance area.

[0043] Figure 7 Examples of this application Figure 3 A schematic diagram of the structure of the second wiring area and the second clearance area.

[0044] Figure 8 This is a top view schematic diagram of the first and second metal layers in the embodiments of this application.

[0045] Figure 9 This is a top view schematic diagram of the film layer of the display substrate provided in the embodiments of this application.

[0046] Figure 10 Examples of this application Figure 7 A schematic diagram of the film layer structure of the display substrate. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0048] In the description of this application, it should be understood that the features referred to by the terms "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified. It should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly; for example, they may refer to a direct connection or an indirect connection through an intermediate medium, or they may refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0049] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0050] Please refer to Figures 1-9 This application provides a display substrate, which includes a substrate 10, a first metal layer 20 and a second metal layer 30.

[0051] A first metal layer 20 is disposed on a substrate 10. The first metal layer 20 includes a data trace 110, which is located within the display area AA.

[0052] Specifically, data traces 110 extend along a first direction Y, and there are multiple data traces 110. Adjacent data traces 110 are spaced apart along a second direction X. The first direction Y and the second direction X intersect. In this embodiment, the first direction Y and the second direction X can be mutually perpendicular directions; correspondingly, the first direction Y can be a vertical direction, and the second direction X can be a horizontal direction. For example, the first direction Y can be the length direction of the display substrate, and the second direction X can also be the width direction of the display substrate.

[0053] The second metal layer 30 is disposed on the first metal layer 20. The first metal layer 20 and the second metal layer 30 are insulated from each other. Specifically, the display substrate includes a first planarization layer 40, which is disposed between the first metal layer 20 and the second metal layer 30. The first metal layer 20 and the second metal layer 30 are insulated from each other through the first planarization layer 40.

[0054] The second metal layer 30 includes fan-out traces 120, which are bent within the fan-out trace area 101. Specifically, a portion of the fan-out traces 120 extends along a first direction Y, and a portion extends along a second direction X. In this embodiment, there are multiple fan-out traces 120, with those extending along the first direction Y spaced apart in the second direction X, and those extending along the second direction X spaced apart in the first direction Y.

[0055] Data trace 110 and fan-out trace 120 are connected. Since data trace 110 is located in the first metal layer 20 and fan-out trace 120 is located in the second metal layer 30 in this embodiment, the second metal layer 30 and the first metal layer 20 can be connected via a first connection hole 401. Specifically, the first connection hole 401 is formed on the first planarization layer 40. Data trace 110 in the first metal layer 20 is exposed through the first connection hole 401, and a portion of fan-out trace 120 in the second metal layer 30 is located within the first connection hole 401, thereby connecting fan-out trace 120 and data trace 110.

[0056] In this embodiment, the multiple data traces 110 and multiple fan-out traces 120 are connected in a one-to-one correspondence, meaning each data trace 110 is connected to one fan-out trace 120. One end of each data trace 110 is connected to multiple data signal lines in the fan-out trace area 101, and then to the integrated circuit (IC) in the bonding area 104. Since the width of the display area is greater than the width of the integrated circuit, the distribution of the ends of the multiple fan-out traces 120 connected to the integrated circuit needs to be restricted, causing the fan-out traces 120 to shrink from wide to narrow. Therefore, in this embodiment, the second fan-out trace 120 is a fan-out trace, and the second fan-out trace 120 is generally fan-shaped. Because there is no need to set up an additional bonding area or form a fan-shaped diagonal line in the bonding area, the width of the bonding area is reduced, thereby effectively reducing the width of the bottom bezel.

[0057] In this embodiment, the display area AA includes a fan-out routing area 101 and a fan-out routing clearance area 102. The display area AA can be a symmetrical structure. Specifically, the fan-out routing area 101 and the fan-out routing clearance area 102 can have a symmetry line BB'. Multiple data routing lines 110 and multiple fan-out routing lines 120 can be symmetrically distributed relative to the symmetry line BB'. The symmetry line BB' can be a straight line that bisects the fan-out routing area 101 and the fan-out routing clearance area 102 and extends along the second direction Y.

[0058] The display substrate of this application embodiment has a first metal layer 20 and a second metal layer 30 that are mutually insulated on the substrate 10. The first metal layer 20 includes multiple data traces 110, and the second metal layer 30 includes fan-out traces 120 that are bent in the fan-out trace area 101. The data traces 110 and the fan-out traces 120 are connected. The data traces are formed in the fan-out trace clearance area 102 using only the first metal layer 20 and the second metal layer 30. This simplifies the film structure of the traces, simplifies the fabrication process of the traces, and thus helps to reduce the manufacturing cost of the display substrate.

[0059] In some embodiments, such as Figure 2 As shown, the display substrate also includes a driving circuit layer, wherein a plurality of thin film transistors 100 are disposed in the driving circuit layer, and the thin film transistors 100 are disposed at least in the display area AA, wherein the thin film transistors 100 include an active pattern 141, a gate 142 and a source / drain electrode 143.

[0060] Specifically, the active pattern 141 of the thin-film transistor 100 is disposed on the substrate 10, the gate 142 is disposed on the active pattern 141, and the source / drain electrode 143 is disposed on the gate 142, which is located in the first metal layer 20. The gate 142 has a dual-gate structure; specifically, the gate 142 includes a first gate 1421 and a second gate 1422 stacked on top of each other. In this embodiment, the first metal layer 20 includes the source / drain electrode 143 and the data trace 110. That is, by using the same material to form both the source / drain electrode 143 and the data trace 110 in the same film layer patterning process, it is beneficial to save fabrication steps and reduce the manufacturing cost of the display substrate.

[0061] In this embodiment, the first metal layer 20 and the second metal layer 30 can be made of the same material. Specifically, the first metal layer 20 and the second metal layer 30 can be a single-layer metal structure or a metal stack structure. For example, the first metal layer 20 and the second metal layer 30 can be made of elemental metals such as aluminum (Al), molybdenum (Mo), and titanium (Ti), or both the first metal layer 20 and the second metal layer 30 can be made of a titanium / aluminum / titanium metal stack structure. Of course, the first metal layer 20 and the second metal layer 30 can also be made of any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals. This embodiment does not impose specific limitations on this.

[0062] In some embodiments, please refer to Figure 2 The display substrate also includes an electrode layer 60 disposed on the second metal layer 30, and the second metal layer 30 and the electrode layer 60 are insulated from each other. The electrode layer 60 can be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multi-layer composite structure, such as ITO / Ag / ITO. Taking an OLED display substrate as an example in this embodiment, the electrode layer 60 is an anode layer. The display substrate includes at least an anode layer, a pixel definition layer 70, an organic light-emitting layer 80, and a cathode layer 90 sequentially disposed from bottom to top along the thickness direction of the substrate 10. The organic light-emitting layer 80 is connected to the anode layer, and the cathode layer 90 is connected to the organic light-emitting layer 80. The organic light-emitting layer 80 emits light of a corresponding color under the drive of the anode layer and the cathode layer 90.

[0063] Combination Figure 2 and Figure 4 As shown, the second metal layer 30 also includes a transition trace 144, which is formed using the same material and in the same patterning process as the fan-out trace 120. The transition trace 144 is used to achieve electrical connection between the source / drain electrode 143 and the electrode layer 60. The transition trace 144 and the fan-out trace 120 are spaced apart. One end of the transition trace 144 is connected to the electrode layer 60, and the other end is connected to the source / drain electrode 143. Specifically, a second connection hole 402 is also provided on the first planarization layer 40 of the display panel. The source / drain electrode 143 in the first metal layer 20 is exposed through the second connection hole 402, and the transition trace 144 is connected to the source / drain electrode 143 through the second connection hole 402. The display panel also includes a second planarization layer 50, which is disposed between the electrode layer 60 and the second metal layer 30. A third connection hole 501 is provided on the second planarization layer 50, and the adapter trace 144 is exposed in the third connection hole 501. The electrode layer 60 is connected to the adapter trace 144 through the third connection hole 501.

[0064] In some embodiments, combined with Figure 1 and Figure 2 As shown, the substrate 10 of the display substrate also includes a bonding region 104, which is disposed adjacent to the fan-out trace clearance region 102. Specifically, in this embodiment, the bonding region 104 is located in the lower region of the substrate 10. The bonding region 104 includes multiple bonding leads 140 located on the substrate 10. One end of the bonding lead 140 is connected to the fan-out trace 120, and the other end of the bonding lead 140 is bonded to an external integrated circuit (IC) chip.

[0065] In some embodiments, such as Figure 1 As shown, the fan-out trace 120 is a bent trace. In this embodiment, the fan-out trace 120 has a broken line segment structure. Specifically, the fan-out trace 120 includes a first fan-out segment 121 and a second fan-out segment 122. The first fan-out segment 121 extends along the first direction Y, and the second fan-out segment 122 extends along the second direction X. The second fan-out segment 122 is connected to the data trace 110.

[0066] In some embodiments, such as Figures 3-7 As shown, the second metal layer 30 also includes at least one virtual trace 130, that is, the virtual trace 130 and the fan-out trace 120 are formed using the same material and in the same patterning process. In the embodiments of this application, the virtual trace 130 may be located on the extension line of the fan-out trace 120, or the virtual trace 130 may be arranged in the same direction and spaced apart from the fan-out trace 120.

[0067] There are multiple virtual traces 130, which can extend along a first direction Y or a second direction X. Specifically, virtual traces 130 can be located simultaneously within the fan-out trace area 101 and the fan-out trace clearance area 102. For example, virtual traces 130 extend from the fan-out trace clearance area 102 to the fan-out trace area 101 along the first direction Y. Alternatively, virtual traces 130 can also be formed only within the fan-out trace clearance area 102. For example, in combination with... Figure 4 and Figure 5 As shown, the fan-out routing clearance area 102 is the area where no fan-out routing 120 is installed, and the fan-out routing area 101 is the area where the fan-out routing 120 is formed. That is, the area in the fan-out routing clearance area 102 other than the fan-out routing area 101.

[0068] The virtual trace 130 may be located only within the fan-out trace clearance area 102. The orthographic projection of the virtual trace 130 on the substrate 10 is spaced apart from the orthographic projection of the data trace 110 on the substrate 10, and the virtual trace 130 is located on the extension line of the fan-out trace 120. The virtual trace 130 may be connected to the fan-out trace 120 or may be spaced apart from the fan-out trace 120; this embodiment does not impose specific limitations on this.

[0069] In this embodiment, the virtual traces 130 allow the traces in the fan-out trace area 101 and the fan-out trace clearance area 102 to have substantially similar morphologies, resulting in a uniform trace arrangement structure. This not only improves the uniformity of the manufacturing process but also ensures that different areas achieve substantially the same display effect under transmitted and reflected light. Consequently, it effectively avoids defects in the appearance of the display substrate, thereby improving display quality and display performance.

[0070] In some embodiments, the display substrate further includes a power supply voltage signal terminal (not shown), and both the data trace 110 and the virtual trace 130 are connected to the power supply voltage signal terminal. In this embodiment, the power supply voltage signal terminal is a high-level signal terminal. By connecting the virtual trace 130 to the power supply voltage signal terminal, the distance between the multiple virtual traces 130 is made to mimic the arrangement distance between the data trace 110 or the fan-out trace 120, so that the impedance of the multiple virtual traces 130 is approximately the impedance of the multiple data traces 110 or the data trace 120, thus avoiding the situation of impedance unevenness (RC Loading) in the data traces 110 or the fan-out trace 120. The virtual trace 130 in this application can compensate for the problem of uneven load in the fan-out trace clearance area 102, which is beneficial to further improve display uniformity, thereby improving display quality and display performance.

[0071] In some embodiments, such as Figure 3 As shown, the display area AA includes an adjacent fan-out routing area 101 and a fan-out routing clearance area 102. The fan-out routing area 101 includes a first routing area 1011 and a second routing area 1012. The first fan-out segment 121 is located within the first routing area 1011, the second fan-out segment 122 is located within the second routing area 1012, and the virtual routing 130 is located within the fan-out routing area 101 and / or the fan-out routing clearance area 102. That is, the virtual routing 130 may be located only within the fan-out routing area 101, only within the fan-out routing clearance area 102, or simultaneously within both the fan-out routing area 101 and the fan-out routing clearance area 102.

[0072] The fan-out cabling clearance area 102 includes a first clearance area 1021 and a second clearance area 1022. The second clearance area 1022 is adjacent to the first cabling area 1011 and the second cabling area 1012, respectively. The first clearance area 1021 is adjacent to the first cabling area 1011. The first clearance area 1021 is the area located above the display area AA, and the second clearance area 1022 is the area located at the lower corner of the display area AA.

[0073] In some embodiments, the virtual trace 130 includes multiple first virtual traces 131 and / or multiple second virtual traces 132.

[0074] In this embodiment, multiple first virtual traces 131 extend along a first direction Y, and adjacent first virtual traces 131 are spaced apart along a second direction X. The first virtual traces 131 and data traces 110 are spaced apart along the second direction X. For example, a fan-out trace 120 is provided between adjacent first virtual traces 131. It should be noted that this embodiment is not limited to this; multiple first virtual traces 131 can also be provided between adjacent fan-out traces 120.

[0075] When the first virtual trace 131 is located on the extension of the fan-out trace 120, the two endpoints of the first virtual trace 131 and the fan-out trace 120 that are close to each other can be set at intervals, that is, the first virtual trace 131 and the fan-out trace 120 are not connected to each other.

[0076] The first virtual trace 131 is arranged in the same direction and spaced apart from the data trace 110, and the first virtual trace 131 is also spaced apart from the fan-out trace 120. There are various ways to arrange the first virtual trace 131. For example, in multiple first virtual traces 131 and multiple data traces 110, the orthographic projection of each first virtual trace 131 on the substrate 10 and the orthographic projection of each data trace 110 on the substrate 10 can overlap each other. Alternatively, in multiple first virtual traces 131 and multiple data traces 110, the orthographic projection of each first virtual trace 131 on the substrate 10 and the orthographic projection of each data trace 110 on the substrate 10 can be alternately arranged adjacently or spaced apart.

[0077] The first virtual trace 131 includes at least two first sub-virtual segments 1311, with adjacent first sub-virtual segments 1311 spaced apart. The lengths of the multiple first sub-virtual segments 1311 can be the same or different. A second fan-out segment 122 can pass between adjacent first sub-virtual segments 1311, and a second virtual trace 132 can connect adjacent first sub-virtual segments 1311. Alternatively, the first sub-virtual segments 1311 can also be spaced apart from the first fan-out segment 121.

[0078] Multiple second virtual traces 132 extend along the second direction X, and adjacent second virtual traces 132 are spaced apart along the first direction Y. Specifically, the second virtual traces 132 and fan-out traces 120 are arranged side by side with intervals, so that the second metal layer 30 can form a uniform arrangement of traces within the fan-out trace clearance area 102, thereby better avoiding the problem of uneven display.

[0079] It should be noted that, in this embodiment of the application, when setting the virtual trace 130, only the first virtual trace 131 can be set, only the second virtual trace 132 can be set, or both the first virtual trace 131 and the second virtual trace 132 can be set simultaneously. For example, as shown... Figure 6 or Figure 7 As shown, the first virtual trace 131 and the second virtual trace 132 are set perpendicular to each other, and the first virtual trace 131 and the second virtual trace 132 are connected to each other.

[0080] Among them, such as Figure 4 As shown, the second virtual trace 132 includes at least two second sub-virtual segments 1321, with adjacent second sub-virtual segments 1321 spaced apart. The lengths of the multiple second sub-virtual segments 1321 can be the same or different. The second sub-virtual segments 1321 are located between adjacent fan-out traces 120, and the virtual traces 130 and fan-out traces 120 are not connected to each other. The number of first sub-virtual segments 1311 or second sub-virtual segments 1321 can be three, four, ..., N, etc. In this embodiment, the number of second sub-virtual segments 1321 increases sequentially from bottom to top in the first direction Y. The arrangement of the second sub-virtual segments 1321 prevents the virtual traces 130 in the second metal layer 30 from short-circuiting with the traces in the first metal layer 20, thereby helping to avoid the problem of short circuits.

[0081] In some embodiments, such as Figure 4 and Figure 6 As shown, a first fan-out segment 121 is provided within the first routing area 1011, and a second virtual trace 132 is located on the extension line of the second fan-out segment 122. A second sub-virtual segment 1321 is located between two adjacent first fan-out segments 121, and the second sub-virtual segment 1321 is connected to the first fan-out segment 121, and / or the second sub-virtual segment 1321 is spaced apart from the first fan-out segment 121.

[0082] In some embodiments, the second sub-virtual segment 1321 is spaced apart from the first fan-out segment 121, and the second sub-virtual segment 1321 is provided with a first via 1031, which is connected to a power supply voltage signal.

[0083] In some embodiments, such as Figure 5As shown, in the second routing area 1012, adjacent first sub-virtual segments 1311 are spaced apart, and each second sub-virtual segment 1321 is connected between two adjacent first sub-virtual segments 1311. Specifically, the first sub-virtual segments 1311 and the second sub-virtual segments 1321 form an H-shaped routing structure, and adjacent H-shaped routing structures are spaced apart. Each second sub-virtual segment 1321 is spaced apart in the second direction X.

[0084] In some embodiments, among the two first sub-virtual segments 1311 connected to the second sub-virtual segment 1321, one of the first sub-virtual segments 1311 is provided with a second via 1032, which is connected to a power supply voltage signal. Since the first sub-virtual segments 1311 and the second sub-virtual segments 1321 are interconnected to form an H-shaped trace structure, only one of the two first sub-virtual segments 1311 needs to have a second via 1032 to connect both first sub-virtual segments 1311 to the power supply voltage signal. This eliminates the need to drill holes in each first sub-virtual segment 1311, thereby simplifying the manufacturing process and reducing manufacturing costs.

[0085] In some embodiments, such as Figure 6 and Figure 7 As shown, within the fan-out trace clearance area 102, the first virtual trace 131 is located on the extension line of the first fan-out segment 121, that is, the first virtual trace 131 is flush with the first fan-out segment 121. The second virtual trace 132 is located on the extension line of the second fan-out segment 122, and the second virtual trace 132 is flush with the second fan-out segment 122. The first virtual trace 131 and the second virtual trace 132 are intersecting each other. By aligning the first virtual trace 131 and the second virtual trace 132 with the first fan-out segment 121 and the second fan-out segment 122 respectively, the arrangement of the second virtual trace 132 can be made as similar as possible to the arrangement structure of the fan-out trace 120, so that the second metal layer 30 forms a uniform trace arrangement structure, thereby better avoiding the problem of uneven display.

[0086] In some embodiments, at least one first virtual trace 131 is provided with a third via 1033, and the third via 1033 is connected to a power supply voltage signal. Specifically, each first sub-virtual segment 1311 is provided with a plurality of third vias 1033. In the first clearance area 1021 and the second clearance area 1022, since the first sub-virtual segment 1311 passes through multiple second fan-out segments 122 from top to bottom along the first direction Y, the first sub-virtual segment 1311 in the first clearance area 1021 and the second clearance area 1022 is longer than the first sub-virtual segment 1311 located in the interval between adjacent second fan-out segments 122. Therefore, by providing multiple third vias 1033 on each first sub-virtual segment 1311, and each third via 1033 being connected to a power supply voltage signal, the problem of impedance unevenness of the first sub-virtual segment 1311 in the first direction Y can be avoided, thereby improving the impedance uniformity of the first sub-virtual segment 1311 in the trace clearance area 102 and further improving the display uniformity.

[0087] In some embodiments, combined with Figures 8-10 As shown, the first metal layer 20 also includes a power supply voltage signal line VDD, which is located in the display area AA. The power supply voltage signal line VDD extends from the fan-out routing area 101 to the fan-out routing clearance area 102. The power supply voltage signal line VDD and the data routing line 110 are spaced apart. Both the power supply voltage signal line VDD and the data routing line 110 extend along the first direction Y.

[0088] Along the first direction Y, the orthographic projection of the power supply voltage signal line VDD on the substrate 10 coincides with the orthographic projection of the fan-out trace 120 on the substrate 10, and the orthographic projection of the data trace 110 on the substrate 10 coincides with the orthographic projection of the fan-out trace 120 on the substrate 10. Specifically, as... Figure 8 As shown, data trace 110 is data trace Data. The orthographic projection of virtual trace 130 on substrate 10 and the projection of data trace Data on substrate 10 coincide. A fourth connection hole 403 is provided on the first planarization layer 40 in the display substrate. Source and drain electrodes 143 are exposed in the fourth connection hole 403. Virtual trace 130 in the second metal layer 30 is connected to source and drain electrodes 143 through the fourth connection hole 403. Source and drain electrodes 143 are used to access high-level signals provided by power supply voltage signal terminals, so that virtual trace 130 can access high-level signals.

[0089] To better implement the display substrate of this application, this application embodiment also provides a display panel including the aforementioned display substrate. Since this display panel has the aforementioned display substrate, it has all the same beneficial effects, which will not be repeated here. The display panel of this application embodiment, by providing a first metal layer 20 and a second metal layer 30 mutually insulated on the substrate 10 of the display substrate, wherein the first metal layer 20 includes multiple data traces 110, and the second metal layer 30 includes fan-out traces 120 bent within a fan-out trace area 101, the data traces 110 and fan-out traces 120 are connected, and the data traces are formed using only the first metal layer 20 and the second metal layer 30 within the fan-out trace clearance area 102, thereby simplifying the film layer structure of the traces, simplifying the trace fabrication process, and thus reducing the manufacturing cost of the display substrate.

[0090] The display panel implemented in this application can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) or other active light-emitting display panel. This application does not specifically limit the applicability of the display panel; it can be used in handheld devices (smartphones, tablets, etc.), wearable devices (smart bracelets, wireless headphones, smartwatches, smart glasses, etc.), in-vehicle devices (navigation systems, reversing assistance systems, dashcams, car refrigerators, etc.), virtual reality devices, augmented reality devices, terminal devices, and other similar devices. No limitations are imposed here.

[0091] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not detailed in a particular embodiment, please refer to the relevant descriptions in other embodiments. In specific implementation, each of the above units or structures can be implemented as an independent entity, or can be arbitrarily combined to be implemented as the same or several entities. For specific implementations of the above units or structures, please refer to the preceding method embodiments, which will not be repeated here.

[0092] The above provides a detailed description of a display substrate and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the embodiments of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display substrate, characterized in that, include: Substrate, including the display area; A first metal layer is disposed on the substrate, and the first metal layer includes multiple data traces located within the display area; A second metal layer is disposed on the first metal layer. The first metal layer and the second metal layer are insulated from each other. The second metal layer includes multiple fan-out traces. The fan-out traces are bent within the display area. Part of the fan-out traces extend along a first direction and part of them extend along a second direction. The first direction and the second direction intersect. The second metal layer further includes at least one virtual trace, which is located on the extension line of the fan-out trace and is flush with the fan-out trace. Alternatively, the virtual trace and the fan-out trace are arranged in the same direction and spaced apart. The display substrate further includes a power supply voltage signal terminal, and the virtual trace is electrically connected to the power supply voltage signal terminal.

2. The display substrate according to claim 1, characterized in that, The fan-out trace includes a first fan-out section and a second fan-out section. The first fan-out section extends along the first direction, and the second fan-out section extends along the second direction. The second fan-out section is connected to the data trace.

3. The display substrate according to claim 2, characterized in that, The virtual trace includes a first virtual trace extending along the first direction, and the first virtual trace includes at least two first sub-virtual segments, with adjacent first sub-virtual segments spaced apart; and / or The virtual trace includes a second virtual trace, which extends along the second direction. The second virtual trace includes at least two second sub-virtual segments, with adjacent second sub-virtual segments spaced apart. The first virtual trace is located on the extension line of the first fan-out segment and is flush with the first fan-out segment, or is spaced apart from the first fan-out segment in the same direction. The second virtual trace is located on the extension line of the second fan-out segment and is flush with the second fan-out segment, or is spaced apart from the second fan-out segment in the same direction.

4. The display substrate according to claim 3, characterized in that, A second sub-virtual segment is connected between two adjacent first sub-virtual segments to form an "H"-shaped routing structure. At least one of the first sub-virtual segments in the "H"-shaped routing structure is located on the extension line of the first fan-out segment and is flush with the first fan-out segment.

5. The display substrate according to claim 4, characterized in that, The two first sub-virtual segments, which are flush with the two adjacent first fan-out segments, are located in the same "H"-shaped routing structure; Alternatively, the two first sub-virtual segments, which are flush with the two adjacent first fan-out segments, are respectively located in the two adjacent "H"-shaped trace structures along the second direction.

6. The display substrate according to claim 4, characterized in that, The distance between two first sub-virtual segments in the same "H"-shaped trace structure is less than the distance between two adjacent "H"-shaped trace structures along the second direction.

7. The display substrate according to any one of claims 3 to 6, characterized in that, The display area includes a fan-out cabling area and a fan-out cabling clearance area, wherein the fan-out cabling area includes a first cabling area and a second cabling area. The first fan-out section is located within the first routing area, the second fan-out section is located within the second routing area, and the virtual routing is located within the fan-out routing area and / or the fan-out routing clearance area.

8. The display substrate according to claim 7, characterized in that, Within the first routing area, the second virtual routing is located on the extension line of the second fan-out segment; The second sub-virtual segment is located between two adjacent first fan-out segments, the second sub-virtual segment is connected to the first fan-out segment, and / or the second sub-virtual segment is spaced apart from the first fan-out segment.

9. The display substrate according to claim 8, characterized in that, The second sub-virtual segment is spaced apart from the first fan-out segment. The second sub-virtual segment is provided with a first via, through which the second sub-virtual segment is connected to the power supply voltage signal.

10. The display substrate according to claim 7, characterized in that, Within the second routing area, adjacent first sub-virtual segments are spaced apart, and each second sub-virtual segment is connected between two adjacent first sub-virtual segments. Each second sub-virtual segment is spaced apart in the second direction.

11. The display substrate according to claim 10, characterized in that, Of the two first sub-virtual segments connected to the second sub-virtual segment, one of the first sub-virtual segments is provided with a second via, through which the first sub-virtual segment is connected to the power supply voltage signal.

12. The display substrate according to claim 7, characterized in that, Within the fan-out routing clearance area, the first virtual routing is located on the extension line of the first fan-out segment, and the second virtual routing is located on the extension line of the second fan-out segment. The first virtual routing and the second virtual routing are arranged to intersect each other.

13. The display substrate according to claim 12, characterized in that, At least one of the first virtual traces is provided with a third via, through which the first virtual trace is connected to the power supply voltage signal.

14. The display substrate according to any one of claims 1 to 6, characterized in that, The first metal layer further includes: A power supply voltage signal line is located within the display area. Both the power supply voltage signal line and the data trace extend along a first direction, and the power supply voltage signal line and the data trace are spaced apart. Along the first direction, the orthographic projection of the power supply voltage signal line on the substrate coincides with the orthographic projection of the fan-out trace on the substrate, and the orthographic projection of the data trace on the substrate coincides with the orthographic projection of the fan-out trace on the substrate.

15. The display substrate according to any one of claims 1 to 6, characterized in that, The virtual traces are spaced apart from the fan-out traces.

16. The display substrate according to any one of claims 1 to 6, characterized in that, The display substrate further includes: Thin-film transistors, at least disposed within the display area, the thin-film transistors comprising: An active pattern is disposed on the substrate; A gate is disposed on the active pattern; The source and drain electrodes are disposed on the gate and are located in the first metal layer.

17. The display substrate according to claim 16, characterized in that, The second metal layer further includes: a transition trace, wherein the transition trace is spaced apart from the fan-out trace; The display substrate further includes: an electrode layer disposed on the second metal layer, wherein the second metal layer and the electrode layer are insulated from each other, and one end of the adapter trace is connected to the electrode layer and the other end is connected to the source and drain electrodes.

18. A display panel, characterized in that, Includes the display substrate as described in any one of claims 1-17.

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