Method for testing microcosmic interface strength of BEOL layer of single chip based on high-precision precrack

Abstract

The invention discloses a method for testing the microcosmic interface strength of a BEOL layer of a single chip based on a high-precision precrack, and belongs to the technical field of integrated circuit manufacturing. The preparation method of the sample for measuring the microcosmic interface bonding strength of the BEOL layer of the single chip comprises the following steps: thinning and scribing a wafer subjected to a BEOL layer process to obtain a single bare chip; cutting the bare chip with the qualified BEOL layer without defects to obtain a bare chip test piece with a substrate silicon wafer and a BEOL layer; and adhering the BEOL layer of the bare chip test piece and the silicon wafer which is cut into the same size through a glue layer, and then prefabricating cracks on the bottom surface of the substrate silicon wafer to obtain a sample. The testing method comprises the following steps: performing a four-point bending test on a sample, and then calculating the adhesion energy of the layered interface according to a load displacement curve in the four-point bending test. According to the testing method, reliable and repeatable measurement of the BEOL layer interface bonding strength of the single chip can be realized.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit manufacturing, and in particular to a method for testing the microscopic interface bonding strength of a single chip BEOL layer based on high-precision prefabricated cracks. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, more than one billion transistors are integrated on a single integrated circuit (IC), which makes the interconnection within the chip face many challenges in electrical, thermal and mechanical aspects. At present, the back-end of the line (BEOL) of high-performance integrated circuits consists of copper wires and vias. In order to reduce interconnection delays, low-dielectric constant materials are sandwiched between these wires and vias to form BEOL stacking layers with thicknesses ranging from tens of nanometers to hundreds of nanometers. However, due to the high porosity and weak mechanical properties of low-dielectric materials, they are easily affected by chip-package interaction (CPI), resulting in reliability problems such as cracking and delamination in the BEOL layer. Therefore, it is particularly important to quantitatively characterize the stable interface bonding strength of the BEOL layer.

[0003] There are many methods to characterize the interface bonding strength, including double cantilever beam (DCB), three-point bending test (3PBT), four-point bending test (4PBT) and cross-sectional nanoindentation (CSN) test. Compared with other tests, four-point bending makes the stress in the middle area of ​​the sample more uniform, which helps to obtain stable fracture delamination data and improves the repeatability of the test.

[0004] Zhou Ming of Semiconductor Manufacturing International Corporation (Shanghai) disclosed the "Method for Detecting Interlayer Adhesion and Method for Making Test Pieces", patent publication number CN103185687A. This patent measures the adhesion performance between two layers of homogeneous dielectric films in a wafer based on the four-point bending method. Shi Gang and others of Shanghai Huali Microelectronics Co., Ltd. disclosed the "Characterization of Adhesion Performance between Multilayer Thin Films and Method for Preparing Samples", patent publication number CN103674832A. This patent uses the four-point bending method to measure the adhesion performance between multiple homogeneous thin film layers in a wafer. The above patents are all specific to four-point bending tests on non-patterned films on wafers. However, the BEOL layer structure in the chip is complex and patterned, so it cannot reflect the actual single-chip semiconductor process. Moreover, compared with wafers, single chips are smaller in size, making it more difficult to perform four-point bending tests and requiring higher dimensional accuracy.

[0005] When preparing four-point bending specimens, the quality and accuracy of the prefabricated cracks affect the accuracy of the actual measurement results. Mechanical cutting or wire cutting is generally used to prefabricate cracks. For thinned single chips, the thickness is usually between tens of microns and hundreds of microns, making it more challenging to create stable prefabricated cracks on their surfaces, because even small processing errors or external stresses can cause uncontrollable crack expansion. In addition, it is very difficult to control the depth of the crack, and even small deviations may affect the test results.

[0006] Therefore, it is urgent to find a high-precision pre-crack, accurate and repeatable test method to characterize the bonding strength of the micro-interface of the single-chip BEOL layer. Summary of the invention

[0007] The purpose of the present invention is to provide a method for testing the microscopic interface strength of a single chip BEOL layer based on high-precision pre-cracks, so as to solve the problems existing in the above-mentioned prior art.

[0008] To achieve the above object, the present invention provides the following solutions:

[0009] One of the technical solutions of the present invention: a sample for measuring the microscopic interface bonding strength of a single chip BEOL layer, comprising a substrate silicon wafer, a BEOL layer, a glue layer and a silicon wafer arranged from bottom to top;

[0010] Wherein, the bottom surface of the substrate silicon wafer has prefabricated cracks.

[0011] The second technical solution of the present invention is a method for preparing the above-mentioned sample, comprising the following steps:

[0012] The wafer that has completed the BEOL layer process is thinned and cut by a grinding wheel or laser scribing to obtain a single bare chip;

[0013] Cutting the bare chip with qualified process and no defect in BEOL layer to obtain bare chip test pieces with substrate silicon wafer and BEOL layer;

[0014] The BEOL layer of the bare chip test piece is adhered to a silicon wafer cut into the same size through a glue layer, and cracks are prefabricated on the bottom surface of the substrate silicon wafer after grinding and polishing to obtain the sample.

[0015] Furthermore, the material used for the glue layer includes epoxy resin glue;

[0016] The adhesion time is 8 to 12 hours.

[0017] The interfacial bonding strength between the glue layer and the silicon wafer is greater than that with the BEOL layer.

[0018] Furthermore, the thickness of the sample (ie, the thickness of the packaged chip) is 0.292-0.295 mm.

[0019] Furthermore, the cutting and pre-crack forming method includes femtosecond laser.

[0020] Furthermore, the process parameters of the femtosecond laser used in the cutting include: repetition frequency 100kHz, pulse width 268fs, power 6-8W, speed 1-2mm / s;

[0021] The process parameters of the femtosecond laser used for the prefabricated cracks include: a repetition frequency of 100 kHz, a pulse width of 268 fs, a power of 2.2 to 2.5 W, and a speed of 1 to 2 mm / s.

[0022] Traditionally, silicon wafers are cut using mechanical cutting methods, which will produce a large damaged area in the cross section cut by this method, and the cutting accuracy is not very precise. The present invention uses femtosecond laser equipment for cutting, which can achieve small-size high-precision cutting with a relatively smooth interface.

[0023] Grinding and polishing can remove the micro cracks caused by laser cutting and the glue remaining on the side wall, which can avoid premature cracking along the micro cracks on the side wall during the four-point bending test, significantly reducing the success rate of the four-point bending test.

[0024] By using femtosecond laser equipment to prefabricate cracks, cracks of a predetermined depth can be achieved by adjusting the laser parameters. Compared with mechanical cutting, the prefabricated crack interface has fewer microcracks and the crack shape is V-shaped. It is easier to crack and expand downward along the V-shaped crack during a four-point bending test.

[0025] Furthermore, before the BEOL layer of the bare chip test piece is adhered to the silicon wafer cut into the same size through the glue layer, the method further includes: roughening the silicon wafer with sandpaper.

[0026] Roughening the silicon wafer with sandpaper can enhance the interface bonding strength between the silicon wafer and the glue.

[0027] Furthermore, the depth of the prefabricated crack is 90-95% of the thickness of the substrate silicon wafer.

[0028] The third technical solution of the present invention is a method for testing the microscopic interface strength of a single chip BEOL layer based on high-precision prefabricated cracks, comprising the following steps:

[0029] A four-point bending test was performed on the above specimens, and then the adhesion energy of the delamination interface was calculated based on the load-displacement curve in the four-point bending test.

[0030] Furthermore, the loading rate of the four-point bending test is 1-3 μm / min.

[0031] The present invention discloses the following technical effects:

[0032] (1) The sample of the present invention can be used to test the inter-layer interface bonding strength of a single chip BEOL. The sample is prefabricated with a femtosecond laser, and the ablated crack wall produces fewer microcracks. The crack depth is controlled with high precision and will not crack prematurely, thereby improving the accuracy of the measurement result.

[0033] (2) The test method of the present invention can achieve reliable and repeatable measurement of the interface bonding strength of the complete BEOL layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 1 is a schematic diagram of a cross-sectional structure of a bare chip, wherein 1 is a bare chip, 101 is a substrate silicon wafer, and 102 is a BEOL layer;

[0036] Figure 2 The figure is a schematic diagram of cutting a bare chip into a plurality of small test pieces to be tested, wherein 1 is a bare chip and 2 is a small bare chip test piece;

[0037] Figure 3 Schematic diagram of the cross-sectional structure of a small sandwich test piece, wherein 3 is a small sandwich test piece, 101 is a substrate silicon wafer, 102 is a BEOL layer, 103 is a glue layer, and 104 is a small silicon wafer;

[0038] Figure 4 Schematic diagram of the cross-sectional structure of the measurement sample, wherein 4 is the measurement sample, 101 is the substrate silicon wafer, 102 is the BEOL layer, 103 is the glue layer, 104 is the small silicon wafer, and 105 is the prefabricated crack;

[0039] Figure 5 Schematic diagram of the preparation process of the measurement sample;

[0040] Figure 6 This is a BEOL weak interface delamination image taken with a SEM microscope;

[0041] Figure 7 It is the load-displacement curve during the four-point bending test;

[0042] Figure 8 Schematic diagram of the test process for the interface bonding strength between bare chip BEOL layers. DETAILED DESCRIPTION

[0043] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as limiting the present invention, but should be understood as a more detailed description of certain aspects, features, and embodiments of the present invention.

[0044] It should be understood that the terms described in the present invention are only for describing special embodiments and are not intended to limit the present invention. In addition, for the numerical range in the present invention, it should be understood that each intermediate value between the upper and lower limits of the scope is also specifically disclosed. Each smaller range between the intermediate value in any stated value or stated range and any other stated value or intermediate value in the described range is also included in the present invention. The upper and lower limits of these smaller ranges can be independently included or excluded in the scope.

[0045] Unless otherwise indicated, all technical and scientific terms used herein have the same meanings as those generally understood by those skilled in the art. Although the present invention describes only preferred methods and materials, any methods and materials similar or equivalent to those described herein may also be used in the implementation or testing of the present invention. All documents mentioned in this specification are incorporated by reference to disclose and describe the methods and / or materials associated with the documents. In the event of a conflict with any incorporated document, the content of this specification shall prevail.

[0046] It will be apparent to those skilled in the art that various modifications and variations may be made to the specific embodiments of the present invention description without departing from the scope or spirit of the present invention. Other embodiments derived from the present invention description will be apparent to those skilled in the art. The present invention description and examples are exemplary only.

[0047] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0048] Example 1

[0049] A test method for the microscopic interface strength of single chip BEOL layer based on high-precision pre-cracks:

[0050] (I) Preparation of measurement samples:

[0051] (1) Thinning the wafer that has completed the BEOL layer process and cutting it by grinding wheel or laser scribing to obtain a single bare chip;

[0052] (2) Prepare a bare chip 1 (length and width dimensions of approximately 5.9 mm×5.5 mm) and a silicon wafer with good process quality and no defects in the BEOL layer.

[0053] The cross-sectional structure diagram of a bare chip with a qualified BEOL layer and no defects is shown in Figure 1, Figure 1 1 is a bare chip, 101 is a substrate silicon wafer (with a height of about 140 μm), and 102 is a BEOL layer (with a height of about 10 μm).

[0054] (3) Then, a femtosecond laser device (with parameters set to a repetition rate of 100 kHz, a pulse width of 268 fs, a power of 6 W, and a speed of 1 mm / s) is used to cut the bare chip 1 into three parts of the same size along the length direction, and then the silicon wafer is cut into the same size to obtain a bare chip small test piece 2 and a small silicon wafer 104;

[0055] The schematic diagram of cutting a bare chip into multiple small test pieces is shown in Figure 2 , Figure 2 1 is a bare chip, and 2 is a bare chip test piece.

[0056] (4) The small silicon wafer 104 is roughened with sandpaper, and then the small silicon wafer 104 and the BEOL layer 102 of the bare chip small test piece 2 are glued together using epoxy resin glue, and left to stand at room temperature for 8 hours to allow the glue to completely cure, thereby obtaining a sandwich small test piece 3.

[0057] The cross-sectional structure diagram of the sandwich test piece is shown in Figure 3 , Figure 3 In the figure, 3 is a small sandwich test piece, 101 is a substrate silicon wafer, 102 is a BEOL layer, 103 is a glue layer (with a height of about 4 μm), and 104 is a small silicon wafer (with a height of about 140 μm).

[0058] (5) The side wall of the cut surface of the sandwich specimen 3 was polished (polishing was performed using a metallographic polishing machine. First, coarse grinding was performed using 2000-grit sandpaper and a rotation speed of about 150 r / min to prevent the sandwich specimen from cracking prematurely due to excessive vibration of the polishing machine. When no laser ablation cracks were observed under an optical microscope, fine grinding was performed using 5000-grit sandpaper and a rotation speed of about 100 r / min. When no obvious abrasive scratches were observed under an optical microscope, polishing was performed using 0.05 μm polishing liquid on a polishing cloth at a rotation speed of about 100 r / min. When no abrasive scratches were observed under an optical microscope, the specimen was ready). Then, a femtosecond laser device (parameters were set to a repetition rate of 100 kHz, a pulse width of 268 fs, a power of 2.4 W, and a speed of 1 mm / s) was used to preform cracks on the bottom surface of the substrate silicon wafer (the depth of the crack was close to 95% of the thickness of the substrate silicon wafer). The crack shape was V-shaped (the width of the opening was about 35 μm), and a measurement sample was obtained.

[0059] The schematic diagram of the cross-sectional structure of the measured sample is shown in Figure 4 , Figure 4 In the figure, 4 is a measurement sample, 101 is a substrate silicon wafer, 102 is a BEOL layer, 103 is a glue layer, 104 is a small silicon wafer, and 105 is a prefabricated crack.

[0060] The schematic diagram of the sample preparation process is shown in Figure 5 .

[0061] (II) Test of microscopic interface strength and bonding strength of bare chip BEOL layer:

[0062] (1) Four-point bending test: The test specimen was placed on a four-point bending support and loaded using an ultra-high precision tensile machine at a loading rate of 2 μm / min. The specimen was placed with the slotted surface facing upward and the prefabricated crack aligned with the center of the indenter. The load-displacement curve during the loading process was recorded using a force sensor and an extensometer.

[0063] (2) After the four-point bending test, the samples were placed under an optical microscope to observe the crack extension. Samples with obvious crack delamination in the bare chip and a stable load extension area in the load-displacement curve were selected, and SEM samples were prepared. Figure 6 ) to further observe the specific delamination interface area (cross-sectional delamination area).

[0064] Preparation of SEM samples: Select the cross section of the bare chip sample and place it vertically on the bottom of the small mold, and use epoxy resin to seal and cure the sample; use a metallographic grinder to grind and polish the cross section of the sample.

[0065] from Figure 6 It can be seen that because the sample size is small and the delamination area is short, the delamination area mainly occurs at the interface between the sixth interlayer dielectric layer and the sixth interlayer metal layer, indicating that the adhesion energy of this interface is the worst in the BEOL layer. This shows that the weakest layer in the BEOL layer is located at the interface between the sixth interlayer dielectric layer and the sixth interlayer metal layer. Therefore, in order to improve the adhesion energy of the BEOL layer, in the subsequent process, we can focus on improving the adhesion performance of the interface between the sixth interlayer dielectric layer and the sixth interlayer metal layer.

[0066] (3) According to the load displacement curve in the four-point bending test ( Figure 7 ), calculate the adhesion energy of the delamination interface, and the average adhesion energy is 3.5 J / m 2 , the test flow diagram is shown in Figure 8 .

[0067] The adhesion energy of the delamination interface is calculated by the following formula:

[0068]

[0069] Where P is the load that reaches steady-state crack growth; L is the distance between the inner and outer loading points; E is the Young's modulus of silicon; ν is the Poisson's ratio of silicon; B is the width of the specimen; and H is the thickness of the specimen.

[0070] Since bare chips are very small and thin, the use of traditional mechanical cutting methods will cause the bare chips to break irregularly during the cutting process and produce many cracks in the cutting section. Some cracks may extend in the BEOL layer, resulting in the performance of the four-point bending test being inaccurate and causing large errors.

[0071] When prefabricating cracks, when the power is less than 2W or the speed exceeds 3mm / min while other parameters of the femtosecond laser equipment remain unchanged, the depth of the crack cannot reach the preset depth within 90%, resulting in a significant decrease in the success rate of the test specimen during the four-point bending test.

[0072] When other types of glue are used, such as organic silicone, due to its relatively flexible mechanical properties, during the process of preparing the sidewall of the sample for grinding and polishing, some slight vibrations generated by the grinding and polishing machine will cause the glue layer in the test sample to drive the BEOL layer to slide, which will cause the BEOL layer to crack and delaminate prematurely. When the epoxy resin glue layer is too thin, it will lead to insufficient bonding. If the glue layer is too thick, the ductility of the glue itself will affect the rigidity of the overall structure, resulting in greater deformation and the measured adhesion energy will be too large.

[0073] When the sidewalls of the sandwich specimens are not ground and polished, the glue residue on the sidewalls and the cracks caused by laser ablation will result in no test results in the four-point bending test. When the sidewalls are simply ground and polished without polishing, the success rate of the four-point bending test will be significantly reduced due to some micro scratches on the sidewalls.

[0074] Comparative Example 1

[0075] When the other parameters of the femtosecond laser equipment remain unchanged during the prefabrication of cracks, the average adhesion energy is 3.6 J / m when the power is less than 2 W. 2 , the test success rate is 10%.

[0076] When the crack is prefabricated, when the other parameters of the femtosecond laser equipment remain unchanged, the average adhesion energy is 3.5 J / m when the power is 2.4 W. 2 , the test success rate is 80% (Example 1).

[0077] Comparative Example 2

[0078] When other parameters remain unchanged, the average adhesion energy is 3.5 J / m when epoxy resin glue is used. 2 , the test success rate is 80% (Example 1).

[0079] When other parameters remain unchanged, using other types of glue, such as silicone, will cause the BEOL layer to crack and delaminate prematurely, and the test success rate is 0%.

[0080] When other parameters remain unchanged, the average adhesion energy is 3.5 J / m when the loading rate is 2 μm / min using an ultra-high precision tensile machine. 2 , the test success rate is 80% (Example 1).

[0081] When other parameters remain unchanged, the average adhesion energy is 3.9 J / m when the loading rate exceeds 5 μm / min using an ultra-high precision tensile machine. 2 , the test success rate is 20%.

[0082] The embodiments described above are only descriptions of the preferred modes of the present invention, and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A sample for measuring the microscopic interface bonding strength of a single chip BEOL layer, characterized in that: It includes a substrate silicon wafer, a BEOL layer, a glue layer and a silicon wafer arranged from bottom to top; Wherein, the bottom surface of the substrate silicon wafer has prefabricated cracks.

2. A method for preparing a sample according to claim 1, characterized in that: The following steps are involved: The wafer that has completed the BEOL layer process is thinned and cut by a grinding wheel or laser scribing to obtain a single bare chip; Cutting the bare chip with qualified process and no defect in BEOL layer to obtain bare chip test pieces with substrate silicon wafer and BEOL layer; The BEOL layer of the bare chip test piece is adhered to a silicon wafer cut into the same size via a glue layer, and then a crack is prefabricated on the bottom surface of the substrate silicon wafer to obtain the sample.

3. The preparation method according to claim 2, characterized in that: The material used in the glue layer includes epoxy resin glue; And / or, the adhesion time is 8 to 12 hours.

4. The preparation method according to claim 2, characterized in that: The thickness of the sample is 0.292-0.295 mm.

5. The preparation method according to claim 2, characterized in that: The cutting and pre-crack methods include femtosecond lasers.

6. The preparation method according to claim 5, characterized in that: The process parameters of the femtosecond laser used in the cutting include: repetition frequency of 100kHz, pulse width of 268fs, power of 6-8W, and speed of 1-2mm / s; And / or, the process parameters of the femtosecond laser used for the prefabricated cracks include: repetition frequency of 100 kHz, pulse width of 268 fs, power of 2.2-2.5 W, and speed of 1-2 mm / s.

7. The preparation method according to claim 2, characterized in that: The depth of the prefabricated crack is 90-95% of the thickness of the substrate silicon wafer.

8. A method for testing the microscopic interface strength of a single chip BEOL layer based on high-precision prefabricated cracks, characterized in that: The following steps are involved: A four-point bending test is performed on the sample described in claim 1, and then the adhesion energy of the delamination interface is calculated according to the load-displacement curve in the four-point bending test.

9. The testing method according to claim 8, characterized in that: The loading rate of the four-point bending test is 1-3 μm / min.

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