WTA circuit based on dynamic competition feedback mechanism

Abstract

The invention relates to a WTA circuit based on a dynamic competition feedback mechanism, belongs to the technical field of WTA circuits, and solves the problems that in the prior art, a WTA circuit is high in delay, large in power consumption and large in area overhead, and the precision cannot meet the requirement. The WTA circuit comprises a plurality of WTA branches; each WTA branch comprises a first current mirror circuit and a competition circuit; the first current mirror circuit is used for receiving input current positive and current negative signals and outputting difference current of the current positive and current negative signals to the input end of the competition circuit; the competitive circuits compete based on the input difference current, the output of the competitive circuit with the maximum input difference current is a high level, and the output of other competitive circuits is a low level. The WTA circuit based on the dynamic competition feedback mechanism is small in delay, low in power consumption, small in circuit size and high in precision.

Description

Technical Field

[0001] The present invention relates to the technical field of WTA circuits, and in particular to a WTA circuit based on a dynamic competition feedback mechanism. Background Art

[0002] Winner-Take-All (WTA) circuits are used to determine the maximum value from multiple inputs and are widely used in image processing, artificial neural networks, neuromorphic computing, fuzzy systems, storage units, and nonlinear filters. WTA circuits can analyze multiple signals in parallel, thereby increasing processing speed.

[0003] At present, many different types of WTA circuits have been studied at home and abroad. WTA circuits can be classified from different perspectives, including input signal type (voltage or current), output signal type (winner signal or its index) and circuit architecture. Common WTA circuit structures include synchronous architecture and binary tree architecture. Predecessors have published a variety of patents: Patent application number CN201910291884.3, the invention name "A low-power current mode PUF based on WTA scheme" proposes a current mode PUF with a winner-takes-all (WTA) current measurement scheme to improve the reliability of PUF with low power consumption. However, its WTA circuit area overhead is large, the structure is complex, and it can only support 2 input currents, which limits its application. Patent application number CN202210583780.1, the invention name "A parallax processing circuit and parallax processing system and method thereof" provides a parallax processing circuit and a parallax processing system and method thereof, which are applied to the field of artificial intelligence technology. The parallax processing circuit includes a shift register matrix, a serial WTA circuit, a parallel WTA circuit, a row shift register group and a parallax selection circuit. However, the WTA circuit adopts a binary tree structure, which has high delay and large area.

[0004] As people's demand for equipment increases, the design requirements for WTA are also getting higher and higher. For real-time signal processing systems, the main challenges faced by WTA circuits are increased latency and reduced accuracy caused by increased input parallelism. Traditional WTA circuits have a serious drop in accuracy under the conditions of large current / voltage input and high parallel input, and are not suitable for high-precision, high-parallel image classification tasks. Traditional WTA circuits use a binary tree structure when processing multiple input signals, resulting in additional power consumption, area overhead and latency. Summary of the invention

[0005] In view of the above analysis, an embodiment of the present invention aims to provide a WTA circuit based on a dynamic competition feedback mechanism to solve the problems of high delay, high power consumption, large area overhead and insufficient accuracy of the existing WTA circuit.

[0006] An embodiment of the present invention provides a WTA circuit based on a dynamic competition feedback mechanism, the WTA circuit comprising: a plurality of WTA branches; each WTA branch comprising a first current mirror circuit and a competition circuit; the first current mirror circuit is used to receive input positive current and negative current signals and output a difference current between the positive current and negative current signals to an input end of the competition circuit; each competition circuit competes based on an input difference current, the output of the competition circuit with the largest input difference current is a high level, and the outputs of other competition circuits are low levels.

[0007] Furthermore, the WTA circuit further includes a first current source shared by each WTA branch;

[0008] Each competition circuit includes a current conduction circuit, a second current mirror circuit, a pre-charge circuit, a comparison circuit and a feedback circuit; the input end of the feedback circuit of each competition circuit is connected to the first current source to shunt the output current of the first current source, and the output end is connected to the first input end of the current conduction circuit; the feedback circuit control end is connected to the output end of the competition circuit, and is used to select whether to feed back the current divided from the first current source to the current conduction circuit according to the output end voltage of the competition circuit; the pre-charge circuit is used to pre-charge the output end voltage of the competition circuit to a high level; the second input end of the current conduction circuit is used to receive the difference current of the positive current and the negative current signal, the current conduction circuit generates a conduction current based on the difference current and the current divided from the first current source, and inputs the conduction current to the second current mirror circuit, the second current mirror circuit generates a mirror current of the conduction current and inputs it to the comparison circuit, the comparison circuit generates a comparison result output based on the mirror current and the preset current; the output end of the comparison circuit serves as the output end of the competition circuit.

[0009] Furthermore, the current conduction circuit includes a third NMOS tube and a fourth NMOS tube cascaded in sequence; the gate of the third NMOS tube is connected to the source of the fourth NMOS tube; the drain of the third NMOS tube is connected to the gate of the fourth NMOS tube; the source of the third NMOS tube is grounded; the gate of the third NMOS tube is connected to the output end of the feedback circuit as a first input end; and the gate of the fourth NMOS tube is used as a second input end of the current conduction circuit.

[0010] Furthermore, the feedback circuit includes a feedback switch; the feedback switch is an NMOS tube, the gate of the NMOS tube is connected to the output end of the competition circuit as a control end, the source of the NMOS tube is connected to the first current source as an input end; the drain of the NMOS tube is connected to the first input end of the current conduction circuit as an output end.

[0011] Furthermore, the pre-charging circuit includes a PMOS tube; the gate of the PMOS tube is used to receive the first pulse signal; the source of the PMOS tube is connected to the positive electrode of the power supply; and the drain of the PMOS tube is connected to the output end of the feedback circuit.

[0012] Furthermore, the comparison circuit includes a second current source and a seventh NMOS tube; the source of the seventh NMOS tube is connected to the second current source, and the drain of the seventh NMOS tube is connected to the output end of the second current mirror circuit; the gate of the seventh NMOS tube is used to receive the first pulse signal.

[0013] Furthermore, the first current mirror circuit includes a first NMOS tube and a second NMOS tube; the sources of the first NMOS tube and the second NMOS tube are both grounded; the gates of the first NMOS tube and the second NMOS tube are connected; the drain of the first NMOS tube is connected to the gate; the drains of the first NMOS tube and the second NMOS tube are respectively connected to the negative end and the positive end of the differential current; the drain of the second NMOS tube is connected to the second input end of the current conduction circuit.

[0014] Furthermore, the second current mirror circuit includes a fifth PMOS tube and a sixth PMOS tube; the sources of the fifth PMOS tube and the sixth PMOS tube are both connected to the positive pole of the power supply; the gates of the fifth PMOS tube and the sixth PMOS tube are connected; the drain of the fifth PMOS tube is connected to the gate; the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube; and the drain of the sixth PMOS tube is connected to the comparison circuit as the output end of the second current mirror circuit.

[0015] Furthermore, the current magnitude of the second current source is half of the current magnitude of the first current source.

[0016] Furthermore, the frequency of the first pulse signal is not higher than 84.75 MHz.

[0017] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0018] 1. In a WTA circuit based on a dynamic competition feedback mechanism of the present invention, the feedback switch is an NMOS tube, the gate of the NMOS tube is connected to the output end of the competition circuit as a control end, the source of the NMOS tube is connected to the first current source as an input end; the drain of the NMOS tube is connected to the first input end of the current conduction circuit as an output end. This design enables the feedback switch NMOS tube to be turned off for multiple branches whose final output of the competition circuit (i.e., the output of the second current mirror circuit) is low level, and the M3-M6 large area circuit is turned off at the same time, which greatly saves power consumption.

[0019] 2. In a WTA circuit based on a dynamic competition feedback mechanism of the present invention, a feedback circuit is used to accelerate the speed at which a branch at the output end of the competition circuit that should output a low level changes from a high level to a low level, thereby reducing circuit delay.

[0020] 3. In a WTA circuit based on a dynamic competition feedback mechanism of the present invention, the shared first current source of 15 loser signals is cut off by a feedback circuit, thereby suppressing the current interference of the 15 loser signals and improving the circuit accuracy.

[0021] 4. The 16-input WTA circuit based on a dynamic competition feedback mechanism of the present invention does not need to adopt a binary tree structure, thus saving circuit board area overhead and realizing a miniaturized design.

[0022] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings are only for the purpose of illustrating specific embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0024] Figure 1 A schematic diagram of a circuit principle of a WTA circuit based on a dynamic competition feedback mechanism;

[0025] Figure 2 A schematic diagram of a conventional synchronous architecture WTA circuit;

[0026] Figure 3 A schematic diagram of a traditional binary tree architecture WTA circuit;

[0027] Figure 4 A WTA function waveform diagram of a WTA circuit based on a dynamic competition feedback mechanism according to the present invention;

[0028] Figure 5 The invention discloses the influence of the presence or absence of feedback mechanism on the WTA delay of a WTA circuit based on a dynamic competition feedback mechanism;

[0029] Figure 6 The invention discloses the influence of the presence or absence of feedback mechanism on the minimum detectable difference of a WTA circuit based on a dynamic competitive feedback mechanism. DETAILED DESCRIPTION

[0030] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0031] A specific embodiment of the present invention discloses a WTA circuit based on a dynamic competition feedback mechanism, and the circuit principle schematic diagram is shown in FIG. Figure 1 shown.

[0032] The WTA circuit includes: multiple WTA branches; each WTA branch includes a first current mirror circuit and a competition circuit; the first current mirror circuit is used to receive input positive current and negative current signals and output the difference current between the positive current and negative current signals to the input end of the competition circuit; each competition circuit competes based on the input difference current, the output of the competition circuit with the largest input difference current is a high level, and the outputs of other competition circuits are low levels.

[0033] Specifically, the input current is the difference between the positive current signal and the negative current signal, and the minimum difference that can be distinguished for the input current by the WTA circuit based on the dynamic competitive feedback mechanism provided in this embodiment is less than 1.4 μA. The minimum difference that can be distinguished for the input current (i.e., the minimum detectable difference) is reduced to 1 / 4.33 of that of the WTA circuit without a feedback circuit.

[0034] The effect of the presence or absence of feedback mechanism on the minimum detectable difference Figure 6 shown.

[0035] The effect of the feedback mechanism on WTA delay is as follows: Figure 5 shown.

[0036] Specifically, WTA delay refers to the time delay between the moment when the second current mirror circuit outputs a low level and the moment when the input current enters the first current mirror circuit. The WTA circuit with feedback circuit provided in this embodiment has a greatly shortened WTA delay compared to the WTA circuit without feedback circuit.

[0037] The WTA function waveform of a WTA circuit based on a dynamic competition feedback mechanism of the present invention is as follows: Figure 4 shown.

[0038] YOUT[0:15] is the voltage output.

[0039] The WTA circuit also includes a first current source shared by each WTA branch;

[0040] Each competition circuit includes a current conduction circuit, a second current mirror circuit, a pre-charge circuit, a comparison circuit and a feedback circuit; the input end of the feedback circuit of each competition circuit is connected to the first current source to shunt the output current of the first current source, and the output end is connected to the first input end of the current conduction circuit; the feedback circuit control end is connected to the output end of the competition circuit, and is used to select whether to feed back the current divided from the first current source to the current conduction circuit according to the output end voltage of the competition circuit; the pre-charge circuit is used to pre-charge the output end voltage of the competition circuit to a high level; the second input end of the current conduction circuit is used to receive the difference current of the positive current and the negative current signal, the current conduction circuit generates a conduction current based on the difference current and the current divided from the first current source, and inputs the conduction current to the second current mirror circuit, the second current mirror circuit generates a mirror current of the conduction current and inputs it to the comparison circuit, the comparison circuit generates a comparison result output based on the mirror current and the preset current; the output end of the comparison circuit serves as the output end of the competition circuit.

[0041] A schematic diagram of a traditional synchronous architecture WTA circuit is shown in Figure 2 As shown;

[0042] A schematic diagram of a traditional binary tree structure WTA circuit is shown below: Figure 3 shown.

[0043] Specifically, in a synchronous architecture WTA circuit, the winner signal is determined by the competition of all input signals. As the number of inputs increases, the accuracy of such a WTA circuit will significantly decrease.

[0044] In the binary tree WTA circuit, input signals are applied to the comparators in the first layer in pairs, and one signal in each pair is considered to be the local winner binary tree that enters the next layer of competition. Although the accuracy of the WTA circuit does not decrease with the increase in the number of inputs, it has higher complexity, larger occupied area, longer winner determination delay and higher power consumption.

[0045] Compared with the existing binary tree structure, the present application has the advantages of low complexity, small occupied area, small WTA delay and low power consumption. The first current mirror circuit includes a first NMOS tube and a second NMOS tube; the sources of the first NMOS tube and the second NMOS tube are both grounded; the gates of the first NMOS tube and the second NMOS tube are connected; the drain of the first NMOS tube is connected to the gate; the drains of the first NMOS tube and the second NMOS tube are respectively connected to the negative end and the positive end of the differential current; the drain of the second NMOS tube is connected to the second input end of the current conduction circuit.

[0046] The 16-input WTA circuit provided in a specific embodiment of the present invention is composed of 16 identical sub-modules. At the input end, the current I p [0:15]And In [0:15] The first current mirror circuit M1 and M2 are used to copy the current mirrors and then perform subtraction. p [0:15] is the simulated positive current generated by the storage array; I n [0:15] is the simulated negative current generated by the storage array; the difference result current I ACT [0:15] is sent to the competition circuit for analog comparison. ACT [0:15] is the Relu activation signal; in order to avoid the increase in delay and reduction in resolution caused by the increase in input parallelism, this embodiment proposes a WTA circuit based on a dynamic competition feedback mechanism. The competition circuit output node (YOUT) is first precharged to VDD (when S1=1). Then S2 is activated to turn I WTA With the second current source (I B / 2) for comparison. The YOUT voltage of the lost WTA branch drops, and the feedback path controlled by S3 dynamically cuts off the feedback circuit to reduce the undesired leakage caused by the lost WTA branch.

[0047] The current conduction circuit includes a third NMOS tube and a fourth NMOS tube which are cascaded in sequence; the gate of the third NMOS tube is connected to the source of the fourth NMOS tube; the drain of the third NMOS tube is connected to the gate of the fourth NMOS tube; the source of the third NMOS tube is grounded; the gate of the third NMOS tube is connected to the output end of the feedback circuit as a first input end; and the gate of the fourth NMOS tube is used as a second input end of the current conduction circuit.

[0048] The feedback circuit includes a feedback switch; the feedback switch is an NMOS tube, the gate of the NMOS tube is connected to the output end of the competition circuit as a control end, the source of the NMOS tube is connected to the first current source as an input end; the drain of the NMOS tube is connected to the first input end of the current conduction circuit as an output end.

[0049] Specifically, the voltage drop of YOUT of the lost WTA branch causes the gate of the feedback switch S3 to drop, and the switch is disconnected. Therefore, the connection between the gate of M3 and the first current source is disconnected, and no current flows. Therefore, the lost WTA branch I WTA The current flowing through the source and drain of M4 is 0, and the drain current of M5 and M6 is 0. M5 and M6 are both turned off. M1 and M2 are still turned on and are not affected. After pre-charging, S3 is turned on, and the gates of 16 M3 are connected to I BIt is turned on, and the gates of 16 M3s are all connected together, and the gate voltages of M3s are the same. When an input current is extremely large (larger than the other 15), the gate voltage of M3 in this branch will increase rapidly. Therefore, the gates of all 16 M3s will increase rapidly. As a result, the gate voltages of M3s in 15 losing WTA branches are high, M4 is cut off (Vgs<Vth), while M4 in the winning branch conducts normally (the source voltage is high, but the gate voltage is also high). Therefore, there is a current I WTA flowing through the winning WTA branch, while the current of M4 in the losing WTA branch is I WTA very small, approaching 0. Therefore, for the WTA branch with a large input current, the I WTA distributed is large. So if one of the branches can get a current greater than I B / 2, it is the winning signal.

[0050] The pre-charge circuit includes a PMOS transistor; the gate of the PMOS transistor is used to receive the first pulse signal; the source of the PMOS transistor is connected to the positive power supply; the drain of the PMOS transistor is connected to the output end of the feedback circuit.

[0051] The comparison circuit includes a second current source and a seventh NMOS transistor; the source of the seventh NMOS transistor is connected to the second current source, the drain of the seventh NMOS transistor is connected to the output end of the second current mirror circuit; the gate of the seventh NMOS transistor is used to receive the first pulse signal.

[0052] Specifically, in the losing competing branches, the mirror current of the second current mirror is less than I B / 2, and YOUT gradually drops to the low level.

[0053] The frequency of the first pulse signal is not higher than 84.75 MHz.

[0054] Specifically, the first pulse signal is the CLK signal. When the low-level CLK = 0, it is the pre-charge stage, S1 is closed, S2 is open, and the power supply charges YOUT to 1 through S1. When CLK = 1, S1 is open, S2 is closed, and current competition is carried out.

[0055] The second current mirror circuit includes a fifth PMOS transistor and a sixth PMOS transistor; the sources of the fifth PMOS transistor and the sixth PMOS transistor are both connected to the positive power supply; the gates of the fifth PMOS transistor and the sixth PMOS transistor are connected; the drain and the gate of the fifth PMOS transistor are connected; the drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor; the drain of the sixth PMOS transistor is used as the output end of the second current mirror circuit and is connected to the comparison circuit.

[0056] The current magnitude of the second current source is one-half of the magnitude of the first current source.

[0057] Specifically, since the sum of the currents obtained by all WTA branches from the first current source is IB , it is impossible for the conduction currents of two branches to be greater than I simultaneously B / 2, so there is only one winning branch.

[0058] The 16-input WTA designed by the present invention works in two stages: a pre-charge stage and a current competition stage. When the first pulse signal is at a low level, it is the pre-charge stage. S1 is closed and S2 is open. The power supply VDD charges the output terminal YOUT of the second current mirror circuit to a high level through S1. When the first pulse signal is at a high level, since S1 is a PMOS and the first pulse signal is connected to the gate of S1, S1 is disconnected; since S2 is an NMOS and the first pulse signal is connected to the gate of S2, S2 is closed for current competition. The feedback switch S3 is an NMOS transistor, and the gate of the NMOS transistor is connected to the output terminal of the second current mirror circuit as a control terminal. Since the output terminal of the second current mirror circuit is charged to a high level at YOUT during the pre-charge stage, the feedback switch S3 is closed at the beginning of the current competition. The source of the feedback switch S3 is connected to the first current source as an input terminal, and the drain of the feedback switch S3 is connected to the first input terminal of the current conduction circuit (i.e., the gate of M3). The gates of 16 M3s are all connected to the first current source I B is applied, and the gates of 16 M3s are all connected together, and the gate voltages of M3 are the same. When the analog positive current and negative current generated by the memory and computing array, the resulting difference current I ACT is sent to the competition circuit for analog comparison. When one input current is particularly large (larger than the other 15), the gate voltage of the M3 in that branch will increase rapidly. Therefore, the gates of all 16 M3s will increase rapidly. As a result, the gate voltages of M3 in the 15 losing WTA branches are high, M4 is cut off (Vgs < Vth), and M5 and M6 will also be cut off. The output current of the second current mirror circuit is weak and close to 0, and the output terminal voltage of the second current mirror circuit gradually decreases to 0; while the winning branch M4 conducts normally (the source voltage is high, but the gate voltage is also high), and there is a current I WTA flowing through the winning branch M4. Since the current I WTA of the losing WTA branch M4 is very small and close to 0, for the WTA branch with a large input current, the I WTA it gets is large. If one of the branches can get a current greater than I B / 2, when compared by the comparison circuit, it will be greater than the second current source of the comparison circuit; the second current mirror circuit will output a high level as the winning signal, and the other branches will output a low level as the losing signal. The decrease in the YOUT voltage of the WTA branch where the losing signal is located causes the gate of the feedback switch S3 to decrease and the switch to disconnect. It stabilizes that the winning WTA branch obtains a current greater than I B / 2, and the second current mirror circuit will stably output a high level, and the other branches will output a low level.

[0059] Compared with the prior art, the feedback switch in the WTA circuit based on the dynamic competition feedback mechanism provided in this embodiment is an NMOS tube, the gate of the NMOS tube is connected to the output end of the competition circuit as the control end, the source of the NMOS tube is connected to the first current source as the input end; the drain of the NMOS tube is connected to the first input end of the current conduction circuit as the output end. This design makes the feedback switch NMOS tube turn off for multiple branches with low output levels, and at the same time turns off the M3-M6 large-area circuit, which greatly saves power consumption. In the WTA circuit based on the dynamic competition feedback mechanism provided in this embodiment, the feedback circuit accelerates the speed at which the branch at the output end of the competition circuit that should output a low level changes from a high level to a low level, thereby reducing circuit delay. In the WTA circuit based on the dynamic competition feedback mechanism provided in this embodiment, the feedback circuit cuts off the shared first current source of the 15 loser signals, suppresses the current interference of the 15 loser signals, and improves the circuit accuracy. The 16-input-WTA circuit based on the dynamic competition feedback mechanism provided in this embodiment does not need to adopt a binary tree structure, saves circuit board area overhead, and realizes a miniaturized design.

[0060] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0061] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A WTA circuit based on a dynamic competition feedback mechanism, characterized in that: The WTA circuit includes: multiple WTA branches; each WTA branch includes a first current mirror circuit and a competition circuit; the first current mirror circuit is used to receive input positive current and negative current signals and output the difference current between the positive current and negative current signals to the input end of the competition circuit; each competition circuit competes based on the input difference current, the output of the competition circuit with the largest input difference current is a high level, and the outputs of other competition circuits are low levels.

2. The WTA circuit according to claim 1, characterized in that: The WTA circuit also includes a first current source shared by each WTA branch; Each competition circuit includes a current conduction circuit, a second current mirror circuit, a precharge circuit, a comparison circuit and a feedback circuit; the input end of the feedback circuit of each competition circuit is connected to the first current source to shunt the output current of the first current source, and the output end is connected to the first input end of the current conduction circuit; The feedback circuit control terminal is connected to the competition circuit output terminal, and is used to select whether to feed back the current divided from the first current source to the current conduction circuit according to the competition circuit output terminal voltage; The pre-charging circuit is used to pre-charge the voltage at the output end of the competition circuit to a high level; The second input terminal of the current conduction circuit is used to receive the difference current of the positive current signal and the negative current signal. The current conduction circuit generates a conduction current based on the difference current and the current divided from the first current source, and inputs the conduction current to the second current mirror circuit. The second current mirror circuit generates a mirror current of the conduction current and inputs it to the comparison circuit. The comparison circuit generates a comparison result output based on the mirror current and a preset current. The output end of the comparison circuit serves as the output end of the competition circuit.

3. The WTA circuit according to claim 2, characterized in that: The current conduction circuit includes a third NMOS tube and a fourth NMOS tube which are cascaded in sequence; the gate of the third NMOS tube is connected to the source of the fourth NMOS tube; the drain of the third NMOS tube is connected to the gate of the fourth NMOS tube; the source of the third NMOS tube is grounded; the gate of the third NMOS tube is connected to the output end of the feedback circuit as a first input end; and the gate of the fourth NMOS tube is used as a second input end of the current conduction circuit.

4. The WTA circuit according to claim 2, characterized in that: The feedback circuit includes a feedback switch; the feedback switch is an NMOS tube, the gate of the NMOS tube is connected to the output end of the competition circuit as a control end, the source of the NMOS tube is connected to the first current source as an input end; the drain of the NMOS tube is connected to the first input end of the current conduction circuit as an output end.

5. The WTA circuit according to claim 2, characterized in that: The pre-charging circuit comprises a PMOS tube; the gate of the PMOS tube is used to receive a first pulse signal; the source of the PMOS tube is connected to the positive electrode of the power supply; and the drain of the PMOS tube is connected to the output end of the feedback circuit.

6. The WTA circuit according to claim 2, characterized in that: The comparison circuit includes a second current source and a seventh NMOS tube; the source of the seventh NMOS tube is connected to the second current source, and the drain of the seventh NMOS tube is connected to the output end of the second current mirror circuit; the gate of the seventh NMOS tube is used to receive the first pulse signal.

7. The WTA circuit according to claim 2, characterized in that: The first current mirror circuit includes a first NMOS tube and a second NMOS tube; the sources of the first NMOS tube and the second NMOS tube are both grounded; the gates of the first NMOS tube and the second NMOS tube are connected; the drain of the first NMOS tube is connected to the gate; the drains of the first NMOS tube and the second NMOS tube are respectively connected to the negative end and the positive end of the differential current; the drain of the second NMOS tube is connected to the second input end of the current conduction circuit.

8. The WTA circuit according to claim 2, characterized in that: The second current mirror circuit includes a fifth PMOS tube and a sixth PMOS tube; the sources of the fifth PMOS tube and the sixth PMOS tube are both connected to the positive electrode of the power supply; the gates of the fifth PMOS tube and the sixth PMOS tube are connected; the drain of the fifth PMOS tube is connected to the gate; the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube; and the drain of the sixth PMOS tube is connected to the comparison circuit as the output end of the second current mirror circuit.

9. The WTA circuit according to claim 2 or 6, characterized in that: The current magnitude of the second current source is half of the current magnitude of the first current source.

10. The WTA circuit according to claim 5 or 6, characterized in that: The frequency of the first pulse signal is no higher than 84.75 MHz.

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