A gate sidewall forming method and semiconductor product
By providing a resistive dielectric layer in the semiconductor structure, the side wall structure layer is etched and thinned separately, which solves the problem of difficulty in adjusting the gate side wall height in the prior art, and achieves the effect of reducing the gate side wall height without affecting other parameters.
Patent Information
- Application Number
- CN202411983484.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-04-04
AI Technical Summary
The prior art is difficult to adjust the height of the gate side wall individually without affecting other parameters, resulting in problems of uneven deposition and difficulty in planarization in subsequent processes.
By providing a etch-resisting dielectric layer on the upper surface of the substrate, the upper part of the side wall structure layer is etched separately and thinned, so as to ensure that the upper part of the side wall structure layer is more fully etched during subsequent full etching, and the height of the gate side wall is reduced.
Without extending the etching time, the height of the gate side wall is effectively reduced, while ensuring that the thickness of the third side wall dielectric layer of the gate side wall and the thickness of the second side wall dielectric layer of the upper surface of the substrate meets normal working needs.
Smart Images
Figure CN119764166A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor processing, and in particular, to a gate sidewall forming method and a semiconductor product. Background Art
[0002] The gate is an important electrode in the field effect transistor. Its main function is to control the conductive state of the field effect transistor, that is, to control the current flow between the source and the drain, so that the field effect transistor can realize multiple functions such as switching, signal amplification, power control, digital logic, etc. On both sides of the gate, gate sidewalls are usually provided to form an isolation layer to protect the gate from physical or chemical damage that may occur in subsequent process steps, and to prevent short circuits between the gate and the adjacent source / drain regions. In addition, the gate sidewalls also have multiple functions such as reducing parasitic capacitance, improving short channel effects, improving gate control capabilities, and reducing leakage current, which have an important impact on the performance and reliability of the field effect transistor.
[0003] Normally, the height of the gate sidewall needs to be higher than the top of the gate to ensure the electrical isolation effect of the gate, so the gate sidewall will inevitably form a protrusion similar to a "horn" on both sides of the top of the gate. If the height of the gate sidewall is too large, the size of the protrusion will be too large, which will have a negative impact on the subsequent process. For example, in the ILD0 silicon dioxide deposition process, the gate sidewall is too high, which may cause the silicon dioxide to be deposited unevenly around the gate, resulting in increased difficulty in the subsequent treatment of the silicon dioxide layer. In addition, the overly large protrusion is not conducive to the flattening process in the subsequent process. However, in the prior art, the gate height is usually a fixed value. When determining the sidewall deposition film thickness and etching process parameters, it is necessary to take into account the final sidewall width, sidewall height, substrate surface silicon dioxide thickness and other key parameters at the same time, and it is difficult to adjust any of the parameter results separately, and the adjustment range is also very limited. Compared with other result parameters, the gate sidewall height is more difficult to adjust independently, because the process adjustment that can affect the gate sidewall height usually has a greater impact on other result parameters, that is, adjusting the gate sidewall height can easily cause other result parameters to deviate from the normal range. Therefore, there is currently a lack of a method that can adjust the gate sidewall height without affecting other parameters as much as possible. Summary of the invention
[0004] The purpose of the embodiments of the present application is to provide a gate sidewall forming method and a semiconductor product. The gate sidewall forming method can first perform separate etching and thinning on the upper part of the sidewall structure layer, so that when the subsequent full etching is performed, it can ensure that the upper part of the sidewall structure layer is more fully etched without extending the etching time, thereby effectively reducing the height of the gate sidewall while ensuring the thickness of the gate sidewall and the thickness of the sidewall dielectric layer on the upper surface of the substrate.
[0005] In a first aspect, the present application provides a method for forming a gate spacer, comprising the following steps:
[0006] S1. Provide a semiconductor structure, including a substrate, a dummy gate structure and a sidewall structure layer, wherein the dummy gate structure is formed on the upper surface of the substrate, and the sidewall structure layer covers the upper surface, the sidewall of the dummy gate structure and the upper surface of the substrate;
[0007] S2, forming an etching-resistance dielectric layer covering the spacer structure layer; wherein each part of the upper surface of the etching-resistance dielectric layer is higher than the spacer structure layer covering the upper surface of the dummy gate structure layer;
[0008] S3, etching the resist dielectric layer to expose the sidewall structure layer covering the upper surface and part of the sidewall of the dummy gate structure;
[0009] S4, etching and thinning the exposed sidewall structure layer;
[0010] S5, removing the remaining resist dielectric layer;
[0011] S6. Etching the sidewall structure layer to form a gate sidewall, wherein the gate sidewall covers the lower side of the dummy gate structure and the upper surface of the substrate.
[0012] In an implementable solution, the dummy gate structure includes, from top to bottom, a first hard mask layer, a second hard mask layer, and a dummy gate dielectric layer.
[0013] In an implementable solution, the sidewall structure layer includes a first sidewall dielectric layer covering both sides of the dummy gate structure, and a second sidewall dielectric layer and a third sidewall dielectric layer sequentially covering the upper surface of the substrate, the upper surface of the dummy gate structure and the outside of the first sidewall dielectric layer.
[0014] In an implementable solution, the gate spacer includes a first spacer dielectric layer, a second spacer dielectric layer and a third spacer dielectric layer sequentially covering both sides of the dummy gate structure, wherein the second spacer dielectric layer also covers the upper surface of the substrate.
[0015] In an implementable solution, the material of the first hard mask layer is silicon dioxide, the material of the second hard mask layer is silicon nitride, and the material of the dummy gate dielectric layer is polysilicon or amorphous silicon.
[0016] In an implementable solution, the material of the first spacer dielectric layer is silicon carbon nitride, the material of the second spacer dielectric layer is silicon dioxide, and the material of the third spacer dielectric layer is silicon nitride.
[0017] In an implementable solution, the etching-resisting dielectric layer is a soft carbon-based film layer or an organic film layer.
[0018] In an implementable solution, after step S6 is completed, the bottom thickness of the third dielectric layer of the gate spacer is 13.3-24.7 nm.
[0019] In an practicable solution, after step S6 is completed, the thickness of the second sidewall dielectric layer covering the upper surface of the substrate is 1.5-4 nm.
[0020] In a second aspect, the present application further provides a semiconductor product, which is manufactured using the aforementioned gate sidewall formation method. The semiconductor product includes a substrate, a pseudo gate structure and a gate sidewall. The substrate includes an upper surface and a lower surface arranged opposite to each other. The pseudo gate structure is formed on the upper surface of the substrate. The gate sidewall covers the lower side of the pseudo gate structure and the upper surface of the substrate.
[0021] Compared with the prior art, the beneficial effects of this application include at least:
[0022] The present application provides a method for forming a gate sidewall. By setting an etching-resisting dielectric layer on the upper surface of a substrate to cover and protect the lower part of the sidewall structure layer, the upper part of the sidewall structure layer can be etched and thinned separately first. Therefore, when the sidewall structure layer is fully etched after removing the etching-resisting dielectric layer, it can be ensured that the upper part of the sidewall structure layer is more fully etched without extending the etching time, thereby reducing the height of the gate sidewall. At the same time, it can be ensured that the thickness of the third sidewall dielectric layer of the gate sidewall still meets the normal working requirements of the gate, and the upper surface of the substrate is still covered with a second sidewall dielectric layer of sufficient thickness.
[0023] Furthermore, since the degree of etching and thinning of the upper portion of the sidewall structure layer on both sides of the pseudo-gate structure will directly affect the height of the final gate sidewall 5, the degree of etching and thinning of the sidewall structure layer can be controlled by controlling process parameters (such as etching time), thereby accurately controlling the final gate sidewall height. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0025] Figure 1 It is a flow chart of a method for forming a gate spacer according to an embodiment of the present application;
[0026] Figure 2 A schematic diagram of providing a dummy gate structure and a sidewall dielectric layer on a substrate;
[0027] Figure 3is a schematic diagram of covering the third sidewall dielectric layer with an etching-resistance dielectric layer;
[0028] Figure 4 is a schematic diagram of etching back the resist dielectric layer;
[0029] Figure 5 is a schematic diagram of etching the upper portion of the third sidewall dielectric layer;
[0030] Figure 6 A schematic diagram for removing the resist dielectric layer;
[0031] Figure 7 A schematic diagram of forming a gate sidewall;
[0032] Figure 8 Schematic diagram of height and thickness of gate sidewall;
[0033] Fig. 9 for Figure 8 A partial enlarged schematic diagram of the dotted line frame in the middle;
[0034] Fig.10 A comparison diagram of gate sidewalls formed by the present application and the prior art.
[0035] In the figure: 1, substrate; 2, pseudo gate structure; 3, sidewall structure layer; 4, resist dielectric layer; 5, gate sidewall; 201, first hard mask layer; 202, second hard mask layer; 203, pseudo gate dielectric layer; 301, first sidewall dielectric layer; 302, second sidewall dielectric layer; 303, third sidewall dielectric layer. DETAILED DESCRIPTION
[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0037] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0038] like Figure 1 As shown, the present application provides a method for forming a gate sidewall, comprising the following steps:
[0039] S1, such as Figure 2As shown, a semiconductor structure is provided, including a substrate 1, a dummy gate structure 2 and a spacer structure layer 3, wherein the dummy gate structure 2 is formed on the upper surface of the substrate 1, and the spacer structure layer 3 covers the upper surface, the sidewall of the dummy gate structure 2 and the upper surface of the substrate 1. Specifically, the dummy gate structure 2 may include a first hard mask layer 201, a second hard mask layer 202 and a dummy gate dielectric layer 203 from top to bottom. The spacer structure layer 3 may include a first spacer dielectric layer 301 covering both sides of the dummy gate structure 2, and a second spacer dielectric layer 302 and a third spacer dielectric layer 303 sequentially covering the upper surface of the substrate 1, the upper surface of the dummy gate structure 2 and the outer side of the first spacer dielectric layer 301.
[0040] S2, such as Figure 3 As shown, an etching-resistance dielectric layer 4 is formed to cover the spacer structure layer 3. The upper surface of the etching-resistance dielectric layer 4 is higher than the spacer structure layer 3 covering the upper surface of the dummy gate structure 2 at all locations.
[0041] S3, such as Figure 4 As shown, the resist dielectric layer 4 is etched to expose the spacer structure layer 3 covering the upper surface and a portion of the sidewall of the dummy gate structure 2 .
[0042] S4, such as Figure 5 As shown, the exposed sidewall structure layer 3 is etched and thinned.
[0043] S5, such as Figure 6 As shown, the remaining etching-resisting dielectric layer 4 is removed to expose the entire sidewall structure layer 3 .
[0044] S6, such as Figure 7 As shown, the sidewall structure layer 3 is etched to form a gate sidewall 5. The gate sidewall 5 includes a first sidewall dielectric layer 301, a second sidewall dielectric layer 302 and a third sidewall dielectric layer 303 sequentially covering both sides of the dummy gate structure 2, wherein the second sidewall dielectric layer 302 also covers the entire upper surface of the substrate 1.
[0045] The material of the first hard mask layer 201 may be silicon dioxide (SiO2), the material of the second hard mask layer 202 may be silicon nitride (SiN), and the material of the pseudo gate dielectric layer 203 may be polysilicon or amorphous silicon. Specifically, the thickness of the first hard mask layer 201 may be 32-48 nm, the thickness of the second hard mask layer 202 may be 16-24 nm, and the thickness of the pseudo gate dielectric layer 203 may be 44-66 nm.
[0046] The material of the first spacer dielectric layer 301 may be silicon carbon nitride (SiCN), the material of the second spacer dielectric layer 302 may be silicon dioxide (SiO2), and the material of the third spacer dielectric layer 303 may be silicon nitride (SiN). Specifically, the thickness of the first spacer dielectric layer 301 may be 4-6 nm, the thickness of the second spacer dielectric layer 302 may be 3-5 nm, and the thickness of the third spacer dielectric layer 303 may be 16-24 nm.
[0047] It should be noted that the etching-resisting dielectric layer 4 can be a soft carbon-based film layer or an organic film layer, which has good filling properties and can meet the requirements of this application. Preferably, a SOC (Spin-On Carbon, spin-coated carbon) film layer or a BARC film layer (bottom anti-reflective layer) can be used as the etching-resisting dielectric layer 4, and the specific material is not too limited here. Specifically, in step S3, the thickness of the etching-resisting dielectric layer 4 after etching can be 20-120nm.
[0048] In addition, a titanium nitride (TiN) layer and a hafnium dioxide (HfO2) layer (not shown in the figure) with a total thickness of 3.5-6.5 nm can be arranged in sequence from top to bottom between the upper surface of the substrate 1 and the pseudo gate dielectric layer 203. Among them, the hafnium dioxide layer has a high dielectric constant and good electrical stability and can be used as an insulating layer; the titanium nitride layer has good chemical stability and mechanical properties, can be used as an isolation layer in subsequent processes, and helps to ensure the normal formation of the work function.
[0049] Since the sidewall structure layer 3 and the etching-resisting dielectric layer 4 are made of different materials, in step S3, by selecting appropriate etching process and etching parameters, the etching-resisting dielectric layer 4 can be etched separately, while the sidewall structure layer 3 has little or no effect. Specifically, in step S3, oxygen-based gases such as O2 can be used as etching gases to dry-etch the etching-resisting dielectric layer 4, while other structures are basically not affected. Since the remaining thickness of the etching-resisting dielectric layer 4 in step S3 directly affects how much of the sidewall structure layer 3 is not etched in step S4, and further affects the thickness of the final third sidewall dielectric layer 303 and the thickness of the second sidewall dielectric layer 302 on the upper surface of the substrate 1, the etching process parameters (such as etching time) of step S3 can be controlled to ensure that the working effect of the final gate sidewall 5 meets the requirements.
[0050] Similarly, in step S4, HBr, C x F y H z (where x, y, and z are the number of atoms, and there are multiple combinations of values, such as CF4, CHF3, etc.), He and other gases are used as etching gases to dry-etch the exposed sidewall structure layer 3. Figure 5and Figure 6 As shown, only the exposed sidewall structure layer 3 is etched and thinned, while the portion of the sidewall structure layer 3 covered by the etching-resisting dielectric layer 4 is not affected, so that in step S6, the upper portion of the sidewall structure layer 3 located on both sides of the pseudo gate structure 2 will be etched before the lower portion. This etching method can achieve an etching selectivity ratio of 2:1-1:2 for the sidewall structure layer 3 and the etching-resisting dielectric layer 4. Therefore, at the end of step S4, on the one hand, the etching of the sidewall structure layer 3 can be completed, and on the other hand, it can be ensured that a sufficient thickness of the etching-resisting dielectric layer 4 is still retained on the upper surface of the substrate 1 for covering and protecting part of the sidewall structure layer 3. Generally, at least 10nm of the etching-resisting dielectric layer 4 is retained on the upper surface of the substrate 1.
[0051] In step S5, O2 can be used as an etching gas to etch and remove the resistive dielectric layer 4. Compared with step S3, the main difference between step S5 and step S3 is that step S5 can remove the resistive dielectric layer 4 at a faster speed and has little effect on other structures. Step S5 can also be divided into step S51 and step S52. In step S51, the etching method used is the same as that in step S4; in step S52, C x F y H z (Compared with step S4, the proportion of H is increased), He, O2 and other gases are used as etching gases to dry-etch the sidewall structure layer 3, the purpose of which is to minimize the consumption of the second sidewall dielectric layer 302 while ensuring that the etching morphology of the third sidewall dielectric layer 303 meets the requirements. The etching method used in step S52 can achieve a selectivity of 10:1-20:1 for the third sidewall dielectric layer 303 and the second sidewall dielectric layer 302.
[0052] When using the prior art, if the height of the gate sidewall 5 needs to be reduced, the etching time needs to be extended so as to more fully etch the upper part of the sidewall structure layer 3 located on both sides of the dummy gate structure 2. However, if the etching time is extended, the thickness of the third sidewall dielectric layer 303 of the gate sidewall 5 will be too low to meet the normal working requirements of the gate. In addition, the thickness of the second sidewall dielectric layer 302 covering the upper surface of the substrate 1 may be insufficient or even completely etched away, resulting in the substrate 1 being in an unprotected exposed state, which may damage the substrate 1 in subsequent steps. In contrast, Figure 8 and Fig.10As shown, by adopting the gate sidewall formation method provided in the present application, since the upper part of the sidewall structure layer 3 located on both sides of the dummy gate structure 2 has been etched and thinned in advance, it can ensure that the upper part is more fully etched without extending the etching time, thereby reducing the final height h of the gate sidewall 5, and at the same time ensure that the bottom thickness d1 of the third sidewall dielectric layer 303 of the gate sidewall 5 still meets the normal working requirements of the gate, and the upper surface of the substrate 1 is still covered with the second sidewall dielectric layer 302 of sufficient thickness.
[0053] According to the above description, in step S4, the degree of etching and thinning of the upper part of the sidewall structure layer 3 on both sides of the pseudo gate structure 2 will directly affect the height of the gate sidewall 5 in step S6. Therefore, the degree of etching and thinning of the sidewall structure layer 3 can be controlled by controlling the process parameters (such as etching time) in step S4, so as to accurately control the final height of the gate sidewall 5. For example, the etching time in step S4 can be recorded as t, and the initial height of the pseudo gate structure 2 is H. When other etching process parameters are constant, it can be generally considered that the height h of the final gate sidewall 5 is approximately linearly related to t, that is, h=Hk·t. Wherein, k is the etching coefficient.
[0054] Specifically, Fig.10 As shown, compared with the prior art, the height h of the gate sidewall 5 can be reduced by 0-40nm using the solution of the present application, and the specific reduction amount can be precisely controlled according to the requirements of the subsequent process. On the one hand, such a gate sidewall 5 can provide sufficient protection for the metal gate formed subsequently to ensure the normal working effect of the gate, and on the other hand, it can also effectively limit the size of the protrusion, thereby reducing the negative impact on the subsequent process and improving production efficiency and quality. In addition, as Figure 8 As shown, the preferred range of the bottom thickness d1 of the third dielectric layer 303 of the gate spacer 5 is 13.3-24.7 nm. Fig. 9 As shown, the thickness of the second sidewall dielectric layer 302 covering the upper surface of the substrate 1 is d2, and preferably d2 may be in the range of 1.5-4 nm.
[0055] The present application also provides a semiconductor product, which is manufactured using the above-mentioned gate sidewall forming method. Figure 7 As shown, the semiconductor product includes a substrate 1, a dummy gate structure 2 and a gate spacer 5. The substrate 1 includes an upper surface and a lower surface arranged opposite to each other, the dummy gate structure 2 is formed on the upper surface of the substrate 1, and the gate spacer 5 covers the lower side of the dummy gate structure 2 and the upper surface of the substrate 1.
[0056] In one embodiment, if Figure 7As shown, the pseudo gate structure 2 includes a first hard mask layer 201, a second hard mask layer 202 and a pseudo gate dielectric layer 203 from top to bottom. The material of the first hard mask layer 201 may be silicon dioxide (SiO2), the material of the second hard mask layer 202 may be silicon nitride (SiN), and the material of the pseudo gate dielectric layer 203 may be polysilicon or amorphous silicon. Specifically, the thickness of the first hard mask layer 201 may be 32-48 nm, the thickness of the second hard mask layer 202 may be 16-24 nm, and the thickness of the pseudo gate dielectric layer 203 may be 44-66 nm.
[0057] In one embodiment, if Figure 7 As shown, the gate spacer 5 may include a first spacer dielectric layer 301, a second spacer dielectric layer 302 and a third spacer dielectric layer 303 sequentially covering both sides of the pseudo gate structure 2, wherein the second spacer dielectric layer 302 also covers the entire upper surface of the substrate 1. The material of the first spacer dielectric layer 301 may be silicon carbon nitride (SiCN), the material of the second spacer dielectric layer 302 may be silicon dioxide (SiO2), and the material of the third spacer dielectric layer 303 may be silicon nitride (SiN). Specifically, the thickness of the first spacer dielectric layer 301 may be 4-6nm, and the thickness of the second spacer dielectric layer 302 covering the first spacer dielectric layer 301 may be 3-5nm. Figure 8 As shown, the bottom thickness d1 of the third dielectric layer 303 of the gate spacer 5 is preferably in the range of 13.3-24.7 nm. Fig. 9 As shown, the thickness d2 of the second spacer dielectric layer 302 covering the upper surface of the substrate 1 is preferably in the range of 1.5-4 nm.
[0058] In one embodiment, if Fig.10 As shown, compared with the prior art, the height h of the gate sidewall 5 can be reduced by 0-40nm using the solution of the present application, and the specific reduction amount can be accurately controlled according to the requirements of the subsequent process. On the one hand, such a gate sidewall 5 can provide sufficient protection for the metal gate formed subsequently to ensure the normal working effect of the gate, and on the other hand, it can also effectively limit the size of the protrusion, thereby reducing the negative impact on the subsequent process and improving production efficiency and quality.
[0059] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for forming a gate sidewall, characterized in that: include: S1. Provide a semiconductor structure, including a substrate, a dummy gate structure and a sidewall structure layer, wherein the dummy gate structure is formed on the upper surface of the substrate, and the sidewall structure layer covers the upper surface, the sidewall of the dummy gate structure and the upper surface of the substrate; S2, forming an etching-resistance dielectric layer covering the spacer structure layer; wherein each part of the upper surface of the etching-resistance dielectric layer is higher than the spacer structure layer covering the upper surface of the dummy gate structure layer; S3, etching the resist dielectric layer to expose the sidewall structure layer covering the upper surface and part of the sidewall of the dummy gate structure; S4, etching and thinning the exposed sidewall structure layer; S5, removing the remaining resist dielectric layer; S6. Etching the sidewall structure layer to form a gate sidewall, wherein the gate sidewall covers the lower side of the dummy gate structure and the upper surface of the substrate.
2. The method for forming a gate spacer according to claim 1, characterized in that: The dummy gate structure includes, from top to bottom, a first hard mask layer, a second hard mask layer and a dummy gate dielectric layer.
3. The method for forming a gate spacer according to claim 1, wherein: The spacer structure layer includes a first spacer dielectric layer covering both sides of the dummy gate structure, and a second spacer dielectric layer and a third spacer dielectric layer sequentially covering the upper surface of the substrate, the upper surface of the dummy gate structure and the outer side of the first spacer dielectric layer.
4. The method for forming a gate spacer according to claim 1, wherein: The gate spacer comprises a first spacer dielectric layer, a second spacer dielectric layer and a third spacer dielectric layer which sequentially cover both sides of the dummy gate structure, wherein the second spacer dielectric layer also covers the upper surface of the substrate.
5. The method for forming a gate spacer according to claim 2, wherein: The material of the first hard mask layer is silicon dioxide, the material of the second hard mask layer is silicon nitride, and the material of the pseudo gate dielectric layer is polysilicon or amorphous silicon.
6. The method for forming a gate spacer according to claim 3, characterized in that: The material of the first spacer dielectric layer is silicon carbon nitride, the material of the second spacer dielectric layer is silicon dioxide, and the material of the third spacer dielectric layer is silicon nitride.
7. The method for forming a gate spacer according to claim 1, wherein: The etching-resisting dielectric layer is a soft carbon-based film layer or an organic film layer.
8. The method for forming a gate spacer according to claim 4, wherein: After step S6 is completed, the bottom thickness of the third dielectric layer of the gate spacer is 13.3-24.7 nm.
9. The method for forming a gate spacer according to claim 4, wherein: After step S6 is completed, the thickness of the second sidewall dielectric layer covering the upper surface of the substrate is 1.5-4 nm.
10. A semiconductor product, characterized in that: The semiconductor product is manufactured by the gate sidewall forming method according to any one of claims 1 to 9; the semiconductor product comprises: A substrate (1) comprising an upper surface and a lower surface arranged opposite to each other; A dummy gate structure (2) formed on the upper surface of the substrate (1); A gate sidewall (5), the gate sidewall (5) covering the lower side of the dummy gate structure (2) and the upper surface of the substrate (1).