Double pattern gate and manufacturing method thereof

Abstract

The present invention provides a double pattern gate and a manufacturing method thereof, the manufacturing method comprising: forming a gate dielectric layer and a gate polysilicon layer on a substrate; forming a first hard mask layer and a first photoresist pattern, the first photoresist pattern being used to define a gate portion extending along a first direction; etching to form a first hard mask pattern, etching and removing the exposed portion of the gate polysilicon layer to form a polysilicon protrusion under the first hard mask pattern; removing the natural oxide layer and forming a protective oxide layer; forming a second hard mask layer and a second photoresist pattern on the surface of the substrate, the second photoresist pattern being used to define a truncation region of the gate portion; etching to form a second hard mask pattern; etching the first hard mask pattern to form a gate mask pattern, etching to form a polysilicon recess at the truncation region; removing the protective oxide layer; etching the gate polysilicon layer and the gate dielectric layer to form a gate structure. The present invention can ensure that the gate polysilicon layer will not be repeatedly etched, and ensure the morphological integrity of the gate structure.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a double pattern gate and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor manufacturing technology, line width dimensions are gradually approaching physical limits. In 28nm and below processes, traditional single-shot photolithography and single-shot dry etching methods can no longer effectively control critical line widths. Therefore, the industry generally adopts a two-shot etching method, first performing the first etching, that is, defining the polysilicon line width in the X direction through polysilicon hard mask etching, and then performing the second etching, that is, etching the polysilicon by cutting the polysilicon gate line tail in the Y direction, and finally forming multiple independent polysilicon gates. However, while this etching method controls the critical line width, it also increases the incidence of particle defects. The existing method of forming a polysilicon gate by two etchings has the following problems:

[0003] 1) The hard mask used for etching usually contains a stack of silicon oxide and silicon nitride. However, due to the limitations of the dry etching characteristics during the two etching processes, the selectivity between the silicon nitride layer under the hard mask and the polysilicon layer to be etched is not good, resulting in difficulty in controlling the XY direction morphology.

[0004] 2) During the first etching process, after the silicon nitride hard mask etching is completed, the photoresist stripping process will be carried out. During this process, a natural oxide layer will be formed on the surface of the polysilicon, affecting the subsequent etching process.

[0005] 3) During the second etching process, during the removal of the silicon nitride hard mask, the part of the polysilicon layer exposed by the first etching will be removed, which will eventually cause some areas of the polysilicon layer to be repeatedly etched twice and cause defects, which will greatly increase the complexity of the process and the instability of the product.

[0006] In summary, the improvement of polysilicon gate technology currently faces multiple challenges, such as lithography capability limitation, dry etching characteristic limitation, polysilicon layer oxidation problem and defect control, etc. These problems not only affect the quality and performance of the product, but also increase the production cost and process complexity.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a double pattern gate and a manufacturing method thereof, so as to solve the problem that when the gate is formed by etching twice in the prior art, the gate morphology is easily poor or defective.

[0009] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for manufacturing a double-patterned gate, the manufacturing method comprising: providing a substrate, forming a gate dielectric layer and a gate polysilicon layer on the substrate; forming a first hard mask layer on the gate polysilicon layer; forming a first photoresist layer on the first hard mask layer, forming a first photoresist pattern based on the first photoresist layer, the first photoresist pattern being used to define a gate portion extending along a first direction; etching the first hard mask layer based on the first photoresist pattern to form a first hard mask pattern, etching and removing the exposed portion of the gate polysilicon layer to form a polysilicon protrusion under the first hard mask pattern, removing the first photoresist pattern, and retaining the first hard mask pattern; removing the natural The present invention relates to a method for forming a gate structure, comprising: forming an oxide layer, and forming a protective oxide layer on the exposed surface of the gate polysilicon layer and the side of the polysilicon protrusion; forming a second hard mask layer and a second photoresist layer on the surface of the substrate, and forming a second photoresist pattern based on the second photoresist layer, wherein the second photoresist pattern has an etching window extending along a second direction and is used to define a truncation area of ​​the gate portion; etching the second hard mask layer based on the second photoresist pattern to form a second hard mask pattern; etching the first hard mask pattern based on the second hard mask pattern to form a gate mask pattern, etching and removing a portion of the gate polysilicon layer exposed in the truncation area to form a polysilicon recess at the truncation area, and retaining the gate mask pattern; removing the protective oxide layer; etching the gate polysilicon layer and the gate dielectric layer based on the gate mask pattern to form a gate structure.

[0010] Optionally, the first hard mask layer includes a stack of a silicon nitride layer and a silicon oxide layer.

[0011] Optionally, when etching the first hard mask layer based on the first photoresist pattern, after removing the silicon oxide layer and the silicon nitride layer, a portion of the gate polysilicon layer exposed is removed based on an overload effect to form a polysilicon protrusion under the first hard mask pattern.

[0012] Optionally, the truncation area includes a continuous first area and a second area, the first area is located on the first mask pattern, and the second area is located outside the first mask pattern and connected between two adjacent first areas. When the first hard mask pattern is etched based on the second hard mask pattern, after removing the silicon oxide layer and the silicon nitride layer in the first area, the exposed portion of the gate polysilicon layer is removed based on the overload effect to form a polysilicon recess in the first area. Based on the etching selectivity ratio of the protective oxide layer to the silicon nitride layer, the etching of the second area stays on the protective oxide layer.

[0013] Optionally, the first photoresist layer includes an APF layer, a nitrogen-free anti-reflective coating layer, a bottom anti-reflective layer and a photoresist layer stacked in sequence.

[0014] Optionally, the second hard mask layer includes one or a stack of two or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and an amorphous carbon layer, and the second photoresist layer includes a bottom anti-reflection layer and a photoresist layer.

[0015] Optionally, a protective oxide layer is formed on the exposed surface of the gate polysilicon layer and the side surfaces of the polysilicon protrusions by an in-situ water vapor growth process, and the thickness of the protective oxide layer is 100 angstroms to 150 angstroms.

[0016] Optionally, the reaction gas of the in-situ water vapor growth process is hydrogen and oxygen, and the temperature is 900° C. to 1200° C. At this temperature, hydrogen and oxygen chemically react to generate atomic oxygen, and the atomic oxygen reacts with the gate polysilicon layer to generate an oxide layer.

[0017] Optionally, the gate dielectric layer includes a high-k dielectric layer, and a metal gate layer is provided between the gate polysilicon layer and the gate dielectric layer, the metal gate layer includes one of TiN, TaN, MoN and WN, and the high-k dielectric layer includes one of ZrO2, ZrON, ZrSiON, HfZrO, HfZrON, HfON, HfO2, HfAlO, HfAlON, HfSiO, HfSiON, HfLaO and HfLaON.

[0018] Optionally, the substrate includes multiple well regions, and a first shallow trench isolation structure extending along a first direction and a second shallow trench isolation structure extending along a second direction are provided between two adjacent well regions. The first shallow trench isolation structure and the second shallow trench structure are cross-arranged, and the truncation area is located above the second shallow trench isolation structure.

[0019] The present invention also provides a double pattern gate, which is prepared by the double pattern gate manufacturing method of any one of the above schemes.

[0020] As described above, the dual pattern gate and the manufacturing method thereof of the present invention have the following beneficial effects:

[0021] The present invention forms a protective oxide layer on the surface of the gate polysilicon layer and the side of the polysilicon protrusion exposed by the first etching, so that the surface of the gate polysilicon layer and the side of the polysilicon protrusion are effectively protected. During the second etching, due to the high etching selectivity between silicon nitride and the protective oxide layer, the surface of the gate polysilicon layer and the side of the polysilicon protrusion will not be repeatedly etched, thereby ensuring the morphological integrity of the surface of the gate polysilicon layer and the side of the polysilicon protrusion.

[0022] After removing the natural oxide layer on the exposed polysilicon surface, the present invention uses an in-situ water vapor growth process to generate a protective oxide layer, which is thin and has a high density. It can effectively protect the polysilicon layer while reducing the oxidation consumption of the polysilicon layer, and ensure the subsequent removal speed of the protective oxide layer, thereby improving process efficiency.

[0023] The present invention can use the protective oxide layer as an etching stop layer for the silicon nitride layer during the second etching, so that the etching depths of the gate polysilicon layer are kept consistent during the two etchings, thereby avoiding the problem of large height differences between polysilicon layers in different directions caused by the second etching process, and ultimately ensuring the gate morphology. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0025] Figures 1 to 11 It is a schematic diagram showing the structure of each step of the method for manufacturing a double pattern gate according to an embodiment of the present invention, wherein: Fig.11 The structure diagram of the double pattern gate of an embodiment of the present invention is shown, wherein: Figure 1-2 , Figures 4 to 6 and Figure 8 to Figure 10 It includes a schematic diagram of the structure in the X direction (left figure) and a schematic diagram of the structure in the Y direction (right figure).

[0026] Component number description

[0027] 101 Base

[0028] 102 N-type well region

[0029] 103 P-type well region

[0030] 1041 First Shallow Trench Isolation Structure

[0031] 1042 Second shallow trench isolation structure

[0032] 105Silicon dioxide layer

[0033] 106 gate dielectric layer

[0034] 107 metal gate layer

[0035] 108 gate polysilicon layer

[0036] 109 Silicon nitride layer

[0037] 110 silicon oxide layer

[0038] 111 APF layer

[0039] 112 Nitrogen-free anti-reflective coating

[0040] 113 bottom anti-reflection layer

[0041] 114 Oxide capping layer

[0042] 115 photoresist layer

[0043] 116 first hard mask pattern

[0044] 117 Polysilicon Bump

[0045] 118 Protective oxide layer

[0046] 119 second hard mask layer

[0047] 120 bottom anti-reflective layer

[0048] 121 photoresist layer

[0049] 122 truncation area

[0050] 1221 First Area

[0051] 1222 Second Area

[0052] 123 Polysilicon Depression

[0053] 124 Gate structure DETAILED DESCRIPTION

[0054] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0056] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0057] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0058] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0059] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0060] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0061] like Figures 1 to 11 As shown, this embodiment provides a method for manufacturing a double pattern gate, the manufacturing method comprising:

[0062] like Figure 1 As shown, step 1) is first performed to provide a substrate 101 , and to form a gate dielectric layer 106 and a gate polysilicon layer 108 on the substrate 101 .

[0063] In some embodiments, the substrate 101 may be a silicon substrate, a germanium substrate, a germanium silicon substrate, a silicon carbide substrate, a III-V compound substrate, etc. The substrate 101 may be doped or undoped. For example, well regions with various doping concentrations or different electrical properties may be formed in the substrate 101 by doping. Various isolation structures may also be formed in the substrate 101, such as a shallow trench isolation structure or a voltage-resistant ring.

[0064] In one embodiment, the substrate 101 is a silicon substrate, and the substrate 101 includes multiple well regions, for example, multiple P-type well regions 103 and multiple N-type well regions 102. A first shallow trench isolation structure 1041 extending along a first direction and a second shallow trench isolation structure 1042 extending along a second direction are provided between two adjacent well regions. The first shallow trench isolation structure 1041 and the second shallow trench structure are arranged crosswise. In one embodiment, the first direction can be set as the X direction, and the second direction can be set as the Y direction, and the X direction is perpendicular to the Y direction.

[0065] In one embodiment, a silicon dioxide layer 105 is formed on the surface of the substrate 101 .

[0066] In one embodiment, the gate dielectric layer 106 includes a high-k dielectric layer, and a metal gate layer 107 is further provided between the gate polysilicon layer 108 and the gate dielectric layer 106. The metal gate layer 107 may be TiN, TaN, MoN, WN, etc. The high-k dielectric layer is a dielectric material having a dielectric constant greater than SiO2, such as ZrO2, ZrON, ZrSiON, HfZrO, HfZrON, HfON, HfO2, HfAlO, HfAlON, HfSiO, HfSiON, HfLaO, HfLaON, etc. For example, a deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), sputtering, etc. The high-k dielectric layer may be, for example, a HfO2 layer having a thickness of 1.5 nanometers to 5 nanometers, and the metal gate layer 107 may be, for example, a TiN layer having a thickness of 2 nanometers to 30 nanometers.

[0067] After forming the high-K dielectric layer, a step of annealing the high-K dielectric layer may be included to improve the quality of the high-K dielectric layer so as to facilitate the subsequent formation of a uniform thickness of the metal gate layer 107. In one example, the annealing temperature may be 500° C. to 1000° C., and the annealing time may be 5s to 100s.

[0068] like Figure 1 As shown, step 2) is then performed to form a first hard mask layer on the gate polysilicon layer 108 .

[0069] In one embodiment, the first hard mask layer includes a stack of a silicon nitride layer 109 and a silicon oxide layer 110, wherein the silicon nitride layer 109 is a lower layer located on the gate polysilicon layer 108, and the silicon oxide layer 110 is an upper layer located on the silicon nitride layer 109. The silicon nitride layer 109 and the silicon oxide layer 110 may be sequentially formed by a deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and the like.

[0070] like Figure 1As shown, step 3) is then performed to form a first photoresist layer on the first hard mask layer, and a first photoresist pattern is formed based on the first photoresist layer. The first photoresist pattern is used to define a gate portion extending along a first direction, and the width of the gate portion is smaller than the spacing between two adjacent first shallow trench isolation structures 1041.

[0071] In one embodiment, the first photoresist layer includes an APF layer 111 , a nitrogen-free anti-reflection coating layer 112 , a bottom anti-reflection layer 113 , an oxide capping layer 114 , and a photoresist layer 115 which are sequentially stacked.

[0072] The APF layer 111 is an advanced pattern film. The nitrogen-free anti-reflective coating (NFDARC) does not contain nitrogen and nitrogen-containing amino groups (NH2), so it does not cause the poisoning phenomenon of the photoresist, and can effectively avoid the deformation of the photoresist pattern or the residue of the photoresist layer on the surface of the substrate 101. The bottom anti-reflective layer (BARC) can reduce the reflection of light, improve the resolution and accuracy of photolithography, and improve the performance of the photoresist. Specifically, the bottom anti-reflective layer (BARC) can absorb or reduce the reflected light, so that the incident light can be better focused on the photoresist layer 115, reducing the change in photoresist thickness and pattern deformation caused by reflection.

[0073] like Figure 2-3 As shown, step 4 is then performed, the first hard mask layer is etched based on the first photoresist pattern to form a first hard mask pattern 116, and the exposed portion of the gate polysilicon layer 108 is etched away to form a polysilicon protrusion 117 under the first hard mask pattern 116, the first photoresist pattern is removed, and the first hard mask pattern 116 is retained.

[0074] In one embodiment, when etching the first hard mask layer based on the first photoresist pattern, after removing the silicon oxide layer 110 and the silicon nitride layer 109 , the exposed portion of the gate polysilicon layer 108 is removed based on the overload effect to form a polysilicon protrusion 117 under the first hard mask pattern 116 .

[0075] like Figure 4 As shown, step 5) is then performed to remove the natural oxide layer on the exposed surface of the gate polysilicon layer 108 and the side of the polysilicon protrusion 117, and to form a protective oxide layer 118 on the exposed surface of the gate polysilicon layer 108 and the side of the polysilicon protrusion 117.

[0076] In one embodiment, the native oxide layer on the exposed surface of the gate polysilicon layer 108 and the side surface of the polysilicon protrusion 117 is removed by a wet cleaning process.

[0077] In one embodiment, a protective oxide layer 118 is formed on the exposed surface of the gate polysilicon layer 108 and the side of the polysilicon protrusion 117 by an in-situ water vapor growth process. The thickness of the protective oxide layer 118 is 100 angstroms to 150 angstroms. For example, the thickness of the protective oxide layer 118 can be 110 angstroms, 120 angstroms, 130 angstroms, 140 angstroms, etc.

[0078] In one embodiment, the reaction gas of the in-situ water vapor growth process is hydrogen and oxygen, the ratio of hydrogen to oxygen is in the range of 0.1% to 99%, the flow rate of the total input gas is in the range of 1slm / s to 100slm / s, the pressure is carried out under a low pressure environment, the pressure range is 5.5torr to 8torr, the temperature is 900°C to 1200°C, at which temperature hydrogen and oxygen react chemically to generate atomic oxygen, and the atomic oxygen reacts with the gate polysilicon layer 108 to generate an oxide layer, and the reaction time can be 10 seconds to 240 seconds. Due to the strong oxidizing effect of atomic oxygen, the oxide film finally obtained has few defects in the body, low interface state density, and high oxide film quality and good flatness. After removing the natural oxide layer of poor quality, the present invention uses the in-situ water vapor growth process to generate a protective oxide layer 118, which is thin and has a high density, and can effectively protect the polysilicon layer while reducing the oxidation consumption of the polysilicon layer, and ensure the removal speed of the subsequent protective oxide layer 118, thereby improving the process efficiency.

[0079] like Figure 5 As shown, step 6 is then performed to form a second hard mask layer 119 and a second photoresist layer on the surface of the substrate 101, and a second photoresist pattern is formed based on the second photoresist layer. The second photoresist pattern has an etching window extending along the second direction for defining a truncation region 122 of the gate portion.

[0080] In one embodiment, the second direction is perpendicular to the first direction.

[0081] In one embodiment, the truncation region 122 is located above the second shallow trench isolation structure 1042 .

[0082] In one embodiment, the second hard mask layer 119 includes one or a stack of two or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and an amorphous carbon layer, and the second photoresist layer includes a bottom anti-reflective layer 120 and a photoresist layer 121 .

[0083] like Figure 6 to Figure 8 As shown, step 7 is then performed to etch the second hard mask layer 119 based on the second photoresist pattern to form a second hard mask pattern, and the first hard mask pattern 116 is etched based on the second hard mask pattern to form a gate mask pattern, and the portion of the gate polysilicon layer 108 exposed in the truncation area 122 is etched away to form a polysilicon recess 123 at the truncation area 122, and the gate mask pattern is retained.

[0084] In one embodiment, the truncation region 122 includes a continuous first region 1221 and a second region 1222, the first region 1221 is located on the first mask pattern, and the second region 1222 is located outside the first mask pattern and is connected between two adjacent first regions 1221. When the first hard mask pattern 116 is etched based on the second hard mask pattern, after removing the silicon oxide layer 110 and the silicon nitride layer 109 of the first region 1221, the exposed portion of the gate polysilicon layer 108 is removed based on the overload effect to form a polysilicon recess 123 at the first region 1221. Based on the etching selectivity of the protective oxide layer 118 and the silicon nitride layer 109, the etching of the second region 1222 stays on the protective oxide layer 118. Specifically, when removing the silicon oxide layer 110 and the silicon nitride layer 109 in the first area 1221, due to the inconsistent etching rates between the first hard mask layer (silicon oxide layer 110 and silicon nitride layer 109) and the second hard mask layer 119, the gate polysilicon layer 108 and the side walls of the polysilicon protrusion 117 in the second area 1222 may be exposed in advance. Since a protective oxide layer 118 is formed on the surface of the polysilicon exposed in the above-mentioned area, even if the gate polysilicon layer 108 and the side walls of the polysilicon protrusion 117 in the second area 1222 are exposed in advance, the protective oxide layer 118 on their surface can prevent further etching, thereby ensuring that the polysilicon in the above-mentioned area will not be repeatedly etched, and ultimately ensuring that the etching depths of the gate polysilicon layer 108 etched in the first direction and the polysilicon layer etched in the second direction remain consistent, so that the final etching of the polysilicon layer has a good morphology.

[0085] like Fig. 9 As shown, step 8) is then performed to remove the protective oxide layer 118.

[0086] For example, the protective oxide layer 118 may be removed by a dry etching process or a wet etching process with no etching selectivity.

[0087] like Figure 10-11 As shown, step 9) is finally performed to etch the gate polysilicon layer 108 and the gate dielectric layer 106 based on the gate mask pattern to form a gate structure 124.

[0088] like Fig.11 As shown, this embodiment further provides a double pattern gate, and the double pattern gate is prepared by the manufacturing method of the double pattern gate in the above embodiment.

[0089] As described above, the dual pattern gate and the manufacturing method thereof of the present invention have the following beneficial effects:

[0090] The present invention forms a protective oxide layer 118 on the surface of the gate polysilicon layer 108 and the side of the polysilicon protrusion 117 exposed by the first etching, so that the surface of the gate polysilicon layer 108 and the side of the polysilicon protrusion 117 can be effectively protected. During the second etching, due to the high etching selectivity between silicon nitride and the protective oxide layer 118, the surface of the gate polysilicon layer 108 and the side of the polysilicon protrusion 117 will not be repeatedly etched, thereby ensuring the morphological integrity of the surface of the gate polysilicon layer 108 and the side of the polysilicon protrusion 117.

[0091] After removing the natural oxide layer on the exposed polysilicon surface, the present invention uses an in-situ water vapor growth process to generate a protective oxide layer 118, which is thin and has a high density. It can effectively protect the polysilicon layer while reducing the oxidation consumption of the polysilicon layer, and ensure the subsequent removal speed of the protective oxide layer 118, thereby improving process efficiency.

[0092] The present invention can use the protective oxide layer 118 as the etching stop layer of the silicon nitride layer 109 during the second etching, so that the etching depth of the gate polysilicon layer 108 remains consistent during the two etchings, thereby avoiding the problem of large height differences between polysilicon layers in different directions caused by the second etching process, and ultimately ensuring the gate morphology.

[0093] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0094] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a double pattern gate, characterized in that: The production method comprises: Providing a substrate, and forming a gate dielectric layer and a gate polysilicon layer on the substrate; forming a first hard mask layer on the gate polysilicon layer; forming a first photoresist layer on the first hard mask layer, and forming a first photoresist pattern based on the first photoresist layer, wherein the first photoresist pattern is used to define a gate portion extending along a first direction; Etching the first hard mask layer based on the first photoresist pattern to form a first hard mask pattern, wherein the etching removes the exposed portion of the gate polysilicon layer to form a polysilicon protrusion under the first hard mask pattern, removes the first photoresist pattern, and retains the first hard mask pattern; Removing the natural oxide layer on the exposed surface of the gate polysilicon layer and the side of the polysilicon protrusion, and forming a protective oxide layer on the exposed surface of the gate polysilicon layer and the side of the polysilicon protrusion; Forming a second hard mask layer and a second photoresist layer on the surface of the substrate, and forming a second photoresist pattern based on the second photoresist layer, wherein the second photoresist pattern has an etching window extending along a second direction and is used to define a truncation region of the gate portion; etching the second hard mask layer based on the second photoresist pattern to form a second hard mask pattern; Etching the first hard mask pattern based on the second hard mask pattern to form a gate mask pattern, wherein the etching removes a portion of the gate polysilicon layer exposed in the cutoff region to form a polysilicon recess in the cutoff region, and retains the gate mask pattern; removing the protective oxide layer; The gate polysilicon layer and the gate dielectric layer are etched based on the gate mask pattern to form a gate structure.

2. The method for manufacturing a double pattern gate according to claim 1, characterized in that: The first hard mask layer includes a stack of a silicon nitride layer and a silicon oxide layer.

3. The method for manufacturing a double pattern gate according to claim 2, characterized in that: When etching the first hard mask layer based on the first photoresist pattern, after removing the silicon oxide layer and the silicon nitride layer, the exposed portion of the gate polysilicon layer is removed based on the overload effect to form a polysilicon protrusion under the first hard mask pattern.

4. The method for manufacturing a double pattern gate according to claim 2, characterized in that: The truncation area includes a continuous first area and a second area, the first area is located on the first mask pattern, and the second area is located outside the first mask pattern and connected between two adjacent first areas. When the first hard mask pattern is etched based on the second hard mask pattern, after removing the silicon oxide layer and the silicon nitride layer in the first area, the exposed part of the gate polysilicon layer is removed based on the overload effect to form a polysilicon recess in the first area. Based on the etching selectivity ratio of the protective oxide layer to the silicon nitride layer, the etching of the second area stays on the protective oxide layer.

5. The method for manufacturing a double pattern gate according to claim 1, characterized in that: The first photoresist layer includes an APF layer, a nitrogen-free anti-reflection coating, a bottom anti-reflection layer and a photoresist layer stacked in sequence.

6. The method for manufacturing a double pattern gate according to claim 1, characterized in that: The second hard mask layer includes one or a stack of two or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and an amorphous carbon layer, and the second photoresist layer includes a bottom anti-reflection layer and a photoresist layer.

7. The method for manufacturing a double pattern gate according to claim 1, characterized in that: A protective oxide layer is formed on the exposed surface of the gate polysilicon layer and the side of the polysilicon protrusion through an in-situ water vapor growth process, and the thickness of the protective oxide layer is 100 angstroms to 150 angstroms.

8. The method for manufacturing a double pattern gate according to claim 7, characterized in that: The reaction gas of the in-situ water vapor growth process is hydrogen and oxygen, and the temperature is 900° C. to 1200° C. At this temperature, hydrogen and oxygen undergo a chemical reaction to generate atomic oxygen, which reacts with the gate polysilicon layer to generate an oxide layer.

9. The method for manufacturing a double pattern gate according to claim 1, characterized in that: The gate dielectric layer includes a high-k dielectric layer, and a metal gate layer is provided between the gate polysilicon layer and the gate dielectric layer, the metal gate layer includes one of TiN, TaN, MoN and WN, and the high-k dielectric layer includes one of ZrO2, ZrON, ZrSiON, HfZrO, HfZrON, HfON, HfO2, HfAlO, HfAlON, HfSiO, HfSiON, HfLaO and HfLaON.

10. The method for manufacturing a double pattern gate according to claim 1, characterized in that: The substrate includes multiple well regions, and a first shallow trench isolation structure extending along a first direction and a second shallow trench isolation structure extending along a second direction are provided between two adjacent well regions. The first shallow trench isolation structure and the second shallow trench structure are cross-arranged, and the truncation area is located above the second shallow trench isolation structure.

11. A double pattern gate, characterized in that: The double pattern gate is prepared by the double pattern gate manufacturing method described in any one of items 1 to 10 above.

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