A high-performance chip and its manufacturing method

Abstract

A high-performance chip and its manufacturing method disclosed by the present invention include a chip body, which comprises a substrate, a device layer, a bridging part and an I / O port layer that are sequentially added in the direction away from the substrate; a main device area and an auxiliary device area are added on the device layer; the I / O port layer includes a heat dissipation area and a port area, the heat dissipation area is located at the middle position of the I / O port layer, the port area is in a ring structure and surrounds the outer peripheral side of the heat dissipation area, and I / O ports are arranged in an array at the port area; the bridging part includes a plurality of stacked bridging circuit layers, and bridging tracks for connecting the main device and the auxiliary device into a circuit and leads for connecting the I / O ports are added in the bridging circuit layers, and each bridging track is covered with an insulating layer, so that the chip has more transistors, less heat generation and stronger heat dissipation capacity.

Description

Technical Field

[0001] The present invention relates to the technical field of chip manufacturing, and particularly to a high-performance chip and a manufacturing method thereof. Background Art

[0002] High-end general-purpose chips have always been the commanding heights contested by various countries in the forefront fields, and their manufacturing technologies represent the highest level of world ultra-precision manufacturing. In the process of digital transformation, for high-performance computing, 5G communication, artificial intelligence, big data, etc., as a carrier, the importance of high-performance chips is self-evident.

[0003] In terms of high-performance chips themselves, they mainly depend on the operating frequency and transistor density.

[0004] By increasing the operating frequency to obtain higher performance, Intel spent more than a decade in research and development, but finally ended in failure due to serious heat generation problems. Chip heat generation and heat dissipation have been problems plaguing the industry for many years. Without solving heat dissipation and finding the mechanism of heat generation, it is impossible to obtain higher performance by increasing the operating frequency. Summary of the Invention

[0005] The purpose of the present invention is to provide a high-performance chip and a manufacturing method thereof to solve the problems existing in the above-mentioned prior art, so that the chip has more transistors, less heat generation, and stronger heat dissipation ability.

[0006] To achieve the above object, the present invention provides the following solution: The present invention provides a high-performance chip, which is characterized in that it includes a chip body, and the chip body includes a substrate and a device layer, a bridging part, and an I / O port layer sequentially added in a direction away from the substrate;

[0007] A main device area and an auxiliary device area are added on the device layer;

[0008] The I / O port layer includes a heat dissipation area and a port area. The heat dissipation area is located at the middle position of the I / O port layer. The port area is in a ring structure and surrounds the outer periphery of the heat dissipation area, and I / O ports are arranged in an array at the port area;

[0009] The bridging part includes a plurality of stacked bridging circuit layers. The bridging circuit layer is provided with bridging tracks for connecting the main device and the auxiliary device into a circuit and leads for connecting the I / O ports, and each bridging track is covered with an insulating layer.

[0010] Preferably, the device layer includes a main device area and an auxiliary device area that are respectively distributed corresponding to the heat dissipation area and the port area. The main device area is located at the middle position of the device layer, and the main device is additionally provided. The auxiliary device area is in a ring structure and surrounds the outer peripheral side of the main device area, and the auxiliary device is additionally provided.

[0011] Preferably, the auxiliary devices include, but are not limited to, capacitors, inductors, resistors, and diodes.

[0012] Preferably, the I / O port near the outer peripheral edge position of the port area serves as a power port and is connected to a power lead;

[0013] The I / O port located on the inner peripheral side of the power port and near the power port serves as a ground port and is connected to a ground lead.

[0014] Preferably, the I / O port located on the inner peripheral side of the ground port serves as a signal port and is connected by nearby wiring to the connection circuits of the corresponding main device and the auxiliary device.

[0015] Preferably, a heat sink is installed on the chip body. Grooves are provided on the inner walls of the heat sink that are respectively connected to the front and back sides of the chip body, and heat-conducting glue is filled in the grooves.

[0016] Preferably, the heat sink is a copper-aluminum alloy heat sink.

[0017] A method for a high-performance chip is also provided, including the following steps:

[0018] S1. Prepare the chip body, and sequentially add a device layer, a bridging part, and an I / O port layer on the substrate. Add a heat dissipation area and a port area surrounding the outer peripheral side of the heat dissipation area on the I / O port layer. The heat dissipation area corresponds to the main device area on the device layer, the port area corresponds to the auxiliary device area on the device layer, I / O ports are arrayed and added in the port area, and the bridging part includes multiple stacked bridging circuit layers;

[0019] The I / O port near the outer peripheral edge position of the port area serves as a power port and is connected to a power lead; the I / O port located on the inner peripheral side of the power port and near the power port serves as a ground port and is connected to a ground lead, and the I / O port located on the inner peripheral side of the ground port serves as a signal port and is distributed nearby corresponding to the main device and the auxiliary device;

[0020] Starting from the device layer to the bridging circuit layer adjacent to the I / O port layer, for adjacent contacts at the same circuit node, after connection, lead wires are drawn out to the periphery nearby to the signal port until all circuit connections are completed;

[0021] S2. Add the main device to the main device area, and add some auxiliary devices to the auxiliary device area. The auxiliary devices in the auxiliary device area surround the outer peripheral side of the main device.

[0022] S3. When packaging the chip body, install a corresponding heat sink according to the product positioning.

[0023] Preferably, in step S3, before installing the heat sink, grooved channels are respectively opened on the inner walls of the heat sink that are connected to the front and back sides of the chip body, and heat-conducting glue is filled in the grooved channels.

[0024] Preferably, the heat-conducting glue is made of resin doped with copper powder.

[0025] The present invention has achieved the following technical effects compared with the prior art:

[0026] The present invention adds an edge area for I / O port layout around the main device area, liberates the front and back ends of the chip body, incorporates the double sides of the chip body into the device manufacturing area, and significantly increases the number of transistors; by using this method, a single side can be made into a dual-core or multi-core chip with stronger computing power after re-integration; different functional chips can also be re-integrated on the front and back sides, such as SoC; and heat can be dissipated to the front and back sides of the chip body synchronously, greatly increasing the heat dissipation area without leaving heat dissipation dead corners; the distance of heat conduction to the outside is shorter compared with single-sided heat conduction; and the freedom of releasing leads to the surrounding is increased, the connection is more efficient and convenient, the flat bridge circuit structure shortens the connection distance, and at the same time reduces the number of manufacturing layers of the bridge layer, making the chip thinner. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 It is the I / O port layout diagram at the port area of the present invention;

[0029] Figure 2 It is the side view of the chip body of the present invention;

[0030] Figure 3 It is the internal node connection model diagram of the bridge circuit layer of the present invention;

[0031] Figure 4 It is the schematic diagram of the internal device distribution of the chip body of the present invention;

[0032] Figure 5 This is the structure of the joint part between the chip body and the heat sink of the present invention;

[0033] Figure 6 It is Figure 5 The enlarged view of the joint between the chip body and the heat sink in the middle;

[0034] Figure 7 It is the internal heat flow pattern of the chip body in the prior art;

[0035] Figure 8 It is the internal heat flow pattern of the chip body of the present invention;

[0036] Figure 9 It is the temperature distribution diagram of the chip body of the present invention in the thickness direction;

[0037] Figure 10 It is the structural schematic diagram of the chip body of the present invention after installing the heat sink;

[0038] Figure 11 It is the structural schematic diagram of the first sub - cover and the second sub - cover of the present invention;

[0039] Figure 12 It is the structural schematic diagram of the chip body of the present invention combined with the PCB board;

[0040] Among them, 1 - signal port, 2 - heat dissipation area, 3 - power supply port, 4 - I / O interface, 5 - port area, 6 - insulation layer, 7 - bridging circuit layer, 8 - lead, 9 - auxiliary device area, 10 - substrate, 11 - main device area, 12 - heat sink, 13 - chip body, 14 - thermal conductive adhesive, 15 - grooving, 16 - second tooth - shaped structure, 17 - first sub - cover, 18 - second sub - cover, 19 - boss structure, 20 - first tooth - shaped structure, 21 - locking screw hole, 22 - PCB board. Specific embodiments

[0041] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0042] The purpose of the present invention is to provide a high - performance chip and its manufacturing method to solve the problems existing in the above - mentioned prior art, so that the chip has more transistors, less heat generation and stronger heat dissipation ability.

[0043] To make the above - mentioned objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0044] like Figures 1 to 12 As shown, this embodiment provides a high-performance chip, including a chip body 13, the chip body 13 includes a substrate 10 and a device layer, a bridge part and an I / O port layer added in sequence along a direction away from the substrate 10; main devices and auxiliary devices are added on the device layer, preferably, the main devices include but are not limited to transistors, and the auxiliary devices include but are not limited to capacitors, inductors, resistors and diodes; the I / O port layer includes a heat dissipation area 2 and a port area 5, the heat dissipation area 2 is located in the middle position of the I / O port layer, the port area 5 is a ring structure and surrounds the outer peripheral side of the heat dissipation area 2, and the port area 5 is arrayed with I / O ports to realize the addition of I / O ports to the periphery of the main device; the bridge part includes a plurality of bridge circuit layers 7 stacked together, and the bridge circuit layer 7 is provided with a bridge track for connecting the main device and the auxiliary device into a circuit and a lead 8 connecting the I / O port, each bridge track is covered with an insulating layer 6, and the lead 8 added in the bridge circuit layer 7 is preferably a copper lead 8. The present invention liberates the front and back end surfaces of the chip body 13 by adding an edge area for I / O terminal layout outside the main device area 11, incorporates both sides of the chip body 13 into the device manufacturing area, and greatly increases the number of transistors; this method is used to make a single side into a dual-core or multi-core chip with stronger computing power after reintegration; chips with different functions can also be reintegrated on the front and back sides, such as SoC; and heat can be dissipated to the front and back sides of the chip body 13 simultaneously, the heat dissipation area is greatly increased while leaving no heat dissipation dead corners; the distance of heat conduction outward is shorter than that of a single side; and 8 degrees of freedom of the leads are released to the surrounding areas, making the connection more efficient and convenient, and the flattened bridge circuit structure shortens the connection distance, while reducing the number of manufacturing layers of the bridge layer, making the chip thinner.

[0045] In this specific embodiment, the device layer includes a main device area 11 and an auxiliary device area 9 respectively distributed corresponding to the heat dissipation area 2 and the port area 5. The main device area 11 is located in the middle of the device layer and is additionally provided with a main device. The auxiliary device area 9 is an annular structure and surrounds the outer peripheral side of the main device area 11, and is additionally provided with an auxiliary device. The lead 8 added in the bridge circuit layer 7 transfers part of the heat energy out of the main device area 11, which is equivalent to opening up a fast channel for heat dissipation from the main device area 11 to the surroundings; while greatly shortening the connection distance, more leads 8 and nodes are moved out of the main device area 11, the purpose of which is to eliminate the environment for the generation of electromagnetic heating as much as possible, and to move the electromagnetic heating of part of the leads 8 out of the main device area 11.

[0046] It should be further noted that: From the perspective of current desktop computer CPUs, the pursuit of a higher chip yield, manufacturing more transistors in the limited space on the wafer to maximize profits is the foundation for the survival of enterprises. The result of this is that heat dissipation considerations are subordinated to the number of transistors: the front side of the chip is used as the I / O interface 4, and the back side is used for heat dissipation. In the dense bridging circuits on one side of the front, its physical properties tend to be metallized. The dense wires interact with each other, and the electromagnetic heat generation of each other and themselves creates the largest heat source; the heat energy is preferentially transmitted to the front through the copper leads 8 with strong thermal conductivity, and the heat dissipation capacity of the front is insufficient, resulting in the accumulation of heat energy. Therefore, in the middle area of this region, the highest temperature inside the chip is formed. The existence of the temperature gradient causes some heat energy to return to the back side and be dissipated out of the chip. Therefore, the increasing number of pins in high-performance chips, in addition to shunting the current to less than 1A and borrowing the dense pins to conduct a large amount of heat energy accumulated on the front, are all important factors; therefore, the front has a more urgent and practical need for a heat dissipation layout compared to the back side.

[0047] Taking all factors into consideration, the present invention places the I / O ports at the four peripheral edges, enabling the double-sided incorporation of the chip body 13 into device manufacturing, greatly increasing the number of transistors, and allowing both the front and back sides to be used for heat dissipation; releasing the freedom of the leads 8 to the outside of the main device area 11, greatly shortening the long connection wires and reducing the number of manufacturing layers; radiating the wiring to the surroundings, and preferably using copper leads 8, and also taking advantage of the characteristics of the large heat capacity and fast heat conduction of the copper leads 8 to open up a fast heat dissipation channel from the main device area 11 to the surroundings; especially for products with double-sided manufacturing (or single-sided manufacturing, pseudo double-sided after grinding and thinning and then bonding a heat dissipation layer such as graphene and then encapsulating).

[0048] In a specific embodiment, the I / O port at the outer peripheral edge position near the port area 5 is used as the power port 3 and is connected to a power lead 8; the I / O port located on the inner peripheral side of the power port 3 and close to the power port 3 is used as the ground port and is connected to a ground lead 8, so that the four peripheral edges of the chip body 13 are powered first and then grounded.

[0049] In a specific embodiment, the I / O port located on the inner peripheral side of the ground port is used as the signal port 1, so that the signal port 1, the ground port, and the power port 3 are arranged in sequence along the direction away from the main device area 11, and are connected to the connection circuits of the corresponding main devices and auxiliary devices by the nearest leads 8. Specifically, each auxiliary device is distributed corresponding to the arrangement position of each I / O port, so that when the I / O ports lead the wires 8 to the periphery, they are connected to the auxiliary devices located below, and the path is more reasonable.

[0050] In a specific embodiment, the chip body 13 is additionally provided with a heat dissipation cover 12. Preferably, the heat dissipation cover 12 is made of a copper-aluminum alloy cover. The inner walls of the heat dissipation cover 12 respectively connected to the front and back sides of the chip body 13 are provided with grooves 15, and the grooves 15 are filled with thermal conductive adhesive 14. The heat dissipation cover 12 is provided to ensure the heat dissipation of the chip and improve its ability to work efficiently and stably.

[0051] Specifically, it should be noted that: by adding a heat dissipation cover 12, the heat dissipation path of the chip is simplified. The chip fits tightly with the heat dissipation cover 12 of the first heated environment. When the heat capacity is large enough, even the disturbance of the heat source and the second heated environment can be ignored. Moreover, it has the effect of indirectly smoothing the maximum temperature fluctuation inside the chip; in the prior art, T3 has a strong heat conduction capacity due to the dense bridge circuit on the front side, but the existence of the I / O port on the front side does not have the conditions for active heat dissipation, so it will accumulate a lot of heat energy, causing the temperature to rise; the highest temperature inside the chip appears on this side, which is the biggest problem for chip heat dissipation; in the present invention, Ta and Tc connected to the heat dissipation cover 12 are basically the same, and heat is dissipated to both sides, with a short distance, small thermal resistance, and strong heat-bearing capacity, so Ta <T1、Tb<T2、Tc<T3,且稳定得多;进一步的,为芯片不同的散热需求提供方便、高效的接口基础。具体举例说明:第一类为桌面型CPU,其配备十倍于芯片的热容量散热罩12,经表面积更大的齿形接合面外接散热器,热容量可达百倍,相当于为芯片配备了温度相对稳定的蓄热池(受热环境);利用铜合金更强大的比热容和热导率,快速吸纳芯片热能时,又有很强的散热能力,本身温度变化更平稳。芯片在不同负载的工作条件(如工作频率、电压等),有着不同的温度梯度,这样间接保证了芯片内的最高温度的稳定。第二类为服务器,其配备高性能的再集成芯片,并提供高效、紧凑、整体、易于实现的散热接口;通过散热罩12预埋管,与配备的制冷系统相连,进行强制制冷,以配合更高性能的散热需求。此外,通过采用合金罩作为散热罩12为芯片提供了抗电磁辐射功能,为特殊环境提供防电磁辐射的芯片,如太空、核电站、战场等环境。

[0052] In a specific embodiment, the heat sink 12 includes a first sub-cover 17 and a second sub-cover 18 respectively installed on the front and back surfaces of the chip body 13. Grooves 15 are provided on the surfaces of the first sub-cover 17 and the second sub-cover 18 that are respectively combined with the chip body 13. The joint surfaces for connecting the two are provided on both the first sub-cover 17 and the second sub-cover 18, and the joint surfaces are located outside the chip body 13. First tooth-shaped structures 20 are arrayed on the joint surfaces of the first sub-cover 17 and the second sub-cover 18 to ensure the bonding strength between the two. Second tooth-shaped structures 16 are arrayed on the surfaces of the first sub-cover 17 and the second sub-cover 18 that are away from the chip body 13. Locking screw holes 21 are opened on the joint surfaces of the first sub-cover 17 and the second sub-cover 18, and bolts are used to connect the two locking screw holes 21, thereby realizing the connection between the first sub-cover 17 and the second sub-cover 18, and making the chip body 13 fit between the first sub-cover 17 and the second sub-cover 18. Preferably, boss structures 19 are provided at the positions where the first sub-cover 17 and the second sub-cover 18 are respectively combined with the chip body 13. The chip body 13 is fitted between the two boss structures 19, and the grooves 15 are correspondingly opened on the surfaces of the boss structures 19 close to the chip body 13. After the heat sink 12 is installed on the chip body 13, it is installed on the PCB board 22.

[0053] Furthermore, a method for a high-performance chip is also provided, including the following steps:

[0054] S1. Prepare the chip body 13. A device layer, a bridging part, and an I / O port layer are sequentially added on the substrate 10. A heat dissipation area 2 and a port area 5 surrounding the outer periphery of the heat dissipation area 2 are added on the I / O port layer. The heat dissipation area 2 corresponds to the main device area 11 on the device layer, and the port area 5 corresponds to the auxiliary device area 9 on the device layer. I / O ports are arrayed and added in the port area 5. According to the principle of topology, the degrees of freedom of the leads 8 are released to the surroundings, and the node connection can be completed efficiently and conveniently with shorter connections and fewer bridging layers; the bridging part includes a plurality of stacked bridging circuit layers 7;

[0055] The I / O ports at the position near the outer periphery of the port area 5 are used as power ports 3 and are connected with power leads 8; the I / O ports located on the inner periphery of the power ports 3 and close to the power ports 3 are used as ground ports and are connected with ground leads 8, so that the four edges of the chip body 13 are powered first and then grounded. The I / O ports located on the inner periphery of the ground ports are used as signal ports 1 and are distributed in the vicinity of the corresponding main devices and auxiliary devices, so that when the I / O ports lead the leads 8 to the periphery, they are connected to the auxiliary devices located below, and the path is more reasonable;

[0056] Starting from the device layer to the bridging circuit layer 7 adjacent to the I / O port layer, the adjacent contacts at the same circuit node are connected and then lead the leads to the periphery to the signal ports 1 nearby until all the circuit connections are completed; as Figure 3It is a node connection model diagram after I / O port expansion, where A, B, and C are the same node positions within the bridging circuit layer, and F is the peripheral auxiliary device;

[0057] S2. Add the main device to the main device area 11, add some auxiliary devices to the auxiliary device area 9, and the auxiliary devices in the auxiliary device area 9 surround the outer periphery of the main device; manufacture some auxiliary devices supporting the main device area 11 on the outer periphery of the main device area 11, separate the auxiliary devices from the main device area 11 to the periphery, generally maintaining the manufacturing area of the device while increasing the density of the transistors in the main device area 11, and incidentally moving the connection wires and auxiliary devices out of the main device area 11, that is, reducing the electromagnetic heating environment;

[0058] S3. When the chip body 13 is encapsulated, install the corresponding heat sink 12 according to the product positioning. Preferably, in step S3, before installing the heat sink 12, open grooved channels 15 on the inner walls of the heat sink 12 that are respectively connected to the front and back of the chip body 13, fill the grooved channels 15 with thermal conductive adhesive 14, and the thermal conductive adhesive 14 is made of resin doped with copper powder. By setting the heat sink 12, the heat dissipation of the chip is ensured, and its ability to work efficiently and stably is improved.

[0059] Adaptations made according to actual needs are all within the protection scope of the present invention.

[0060] It should be noted that for those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, in any regard, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be encompassed by the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0061] Specific examples are used in the present invention to elaborate on the principles and implementation manners of the present invention. The descriptions of the above embodiments are only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, there will be changes in the specific implementation manners and application scopes according to the idea of the present invention. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A high-performance chip, characterized in that: The chip body includes a substrate and a device layer, a bridge portion and an I / O port layer which are sequentially added in a direction away from the substrate; A main device area and an auxiliary device area are added to the device layer; The I / O port layer includes a heat dissipation area and a port area, wherein the heat dissipation area is located in the middle of the I / O port layer, the port area is in a ring structure and surrounds the outer periphery of the heat dissipation area, and the port area is arrayed with I / O ports; The bridge portion includes a plurality of bridge circuit layers stacked together, wherein the bridge circuit layer is provided with a bridge track for connecting the main device and the auxiliary device into a circuit and a lead wire connected to the I / O port, and each of the bridge tracks is covered with an insulating layer; The I / O port near the outer edge of the port area is used as a power port and is connected to a power lead; The I / O port located on the inner circumference side of the power port and close to the power port serves as a ground port and is connected to a ground lead.

2. The high-performance chip according to claim 1, characterized in that: The device layer includes a main device area and an auxiliary device area respectively distributed corresponding to the heat dissipation area and the port area. The main device area is located in the middle position of the device layer and is additionally provided with the main device. The auxiliary device area is an annular structure and surrounds the outer periphery of the main device area and is additionally provided with the auxiliary device.

3. The high-performance chip according to claim 2, characterized in that: The auxiliary devices include but are not limited to capacitors, inductors, resistors and diodes.

4. The high-performance chip according to claim 3, characterized in that: The I / O port located on the inner peripheral side of the ground port is used as a signal port and is connected to the corresponding connection circuit node positions of the main device and the auxiliary device by wires.

5. The high-performance chip according to claim 4, characterized in that: The chip body is additionally provided with a heat dissipation cover, and inner walls of the heat dissipation cover respectively connected to the front and back surfaces of the chip body are provided with grooves, and the grooves are filled with heat-conducting glue.

6. The high-performance chip according to claim 5, characterized in that: The heat dissipation cover is made of copper-aluminum alloy.

7. A method for manufacturing a high-performance chip according to any one of claims 1 to 6, characterized in that: The steps include: S1. Prepare a chip body, add a device layer, a bridge portion and an I / O port layer on the substrate in sequence, add a heat dissipation area and a port area surrounding the outer periphery of the heat dissipation area on the I / O port layer, the heat dissipation area corresponds to the main device area on the device layer, the port area corresponds to the auxiliary device area on the device layer, the port area array adds I / O ports, and the bridge portion includes a plurality of bridge circuit layers stacked together; The I / O port near the outer edge of the port area is used as a power port and is connected to a power lead; the I / O port located on the inner side of the power port and close to the power port is used as a ground port and is connected to a ground lead; the I / O port located on the inner side of the ground port is used as a signal port and is distributed close to the corresponding main device and the auxiliary device; Starting from the device layer to the bridge circuit layer adjacent to the I / O port layer, adjacent contacts at the same node of the circuit are connected and then wired to the signal port nearby until all circuit connections are completed; S2, adding the main device to the main device area, adding some auxiliary devices to the auxiliary device area, and the auxiliary device area surrounds the outer periphery of the main device area; S3. When the chip body is packaged, a corresponding heat dissipation cover is installed according to product positioning.

8. The method for manufacturing a high-performance chip according to claim 7, characterized in that: In step S3, before installing the heat dissipation cover, grooves are formed on the inner walls of the heat dissipation cover respectively connected to the front and back surfaces of the chip body, and the grooves are filled with thermal conductive glue.

9. The method for manufacturing a high-performance chip according to claim 8, characterized in that: The thermal conductive adhesive is made of resin mixed with copper powder.

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