Bus voltage adaptive short circuit protection circuit and high voltage integrated circuit thereof

Abstract

The application relates to the field of power electronics, in particular to a short-circuit protection circuit suitable for adapting bus voltage and a high-voltage integrated circuit thereof. The short-circuit protection circuit comprises a detection time adaptation unit, a detection time reference unit and a trigger unit. The detection time reference unit is used for generating a reference voltage. The detection time adaptation unit is used for receiving a short-circuit signal and the reference voltage, generating a trigger signal after a delay, and the delay time is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage. The trigger unit is used for generating a short-circuit protection signal when the trigger signal is received. The high-voltage integrated circuit comprises a fault logic control unit, at least one fault detection unit and the short-circuit protection circuit. The fault logic control unit is used for shutting down the high-voltage integrated circuit when a feedback protection signal of any one unit is received. Therefore, the detection time can be automatically adjusted according to different bus voltages, and the bus voltage sensitive device or circuit can realize short-circuit protection quickly under the premise of maintaining the anti-mis-triggering capability.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, in particular to a short-circuit protection circuit adapted to bus voltage and a high-voltage integrated circuit thereof. Background Art

[0002] High-voltage integrated circuit, or HVIC, integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low-voltage level, high-voltage level, pulse generation circuit, delay circuit, filter circuit, over-current and over-temperature protection circuit, under-voltage protection circuit, bootstrap circuit and other circuits. It is an integrated circuit product that converts MCU signals into driving IGBT or MOS signals. It does not have short-circuit detection and protection circuits for switching devices such as IGBT and SiC-MOSFET.

[0003] Existing high-voltage integrated circuits perform short-circuit detection on switching devices such as IGBTs and SiC-MOSFETs within power modules through peripheral circuits, and feed the detection results together with other short-circuit signals and other fault detection signals in the peripheral circuits back to the high-voltage integrated circuit for overall short-circuit fault detection and protection. That is, after comprehensively judging all fault conditions, the high-voltage integrated circuit executes protection actions (usually, short-circuit protection is executed as soon as a fault signal is detected).

[0004] However, since multiple short-circuit signals are sampled by peripheral circuits and then transmitted to the high-voltage integrated circuit inside the power module for processing, the short-circuit detection time is basically fixed, and the ability to prevent false triggering of narrow pulse widths is fixed. It can only be applied to limited short-circuit situations and has low adaptability. In particular, when a short-circuit fault occurs in the SiC-MOSFET switching device, due to the characteristics of the SiC-MOSFET, the higher the bus voltage of the SiC-MOSFET, the shorter the short-circuit tolerance time. Therefore, the fixed detection time is not suitable for such devices or circuits that are sensitive to the bus voltage. A short-circuit protection circuit that can automatically adjust the detection time according to different bus voltages is needed. It can detect short-circuit faults and provide protection more quickly, while maintaining the ability to prevent false triggering of short-circuit protection by narrow pulses of different pulse widths under different bus voltages. Summary of the Invention

[0005] In response to the above-mentioned defects, the purpose of the present invention is to propose a short-circuit protection circuit and a high-voltage integrated circuit that are adapted to the bus voltage, which can automatically adjust the detection time according to different bus voltages and quickly implement short-circuit protection for bus voltage-sensitive devices or circuits while maintaining the ability to prevent false triggering.

[0006] To achieve this object, the present invention adopts the following technical solutions:

[0007] A short-circuit protection circuit adapted to bus voltage, comprising a detection time adaptation unit, a detection time reference unit, and a trigger unit; the input end of the detection time adaptation unit serves as the input end of the short-circuit protection circuit, and the output end of the trigger unit serves as the output end of the short-circuit protection circuit;

[0008] The reference end of the detection time adaptation unit is electrically connected to the output end of the detection time reference unit, the output end of the detection time adaptation unit is electrically connected to the input end of the trigger unit, the VCC ends of the detection time adaptation unit, the detection time reference unit, and the trigger unit are all connected to a power supply VCC, and the VSS ends of the detection time adaptation unit, the detection time reference unit, and the trigger unit are all connected to a power supply VSS;

[0009] The detection time reference unit is used to generate a reference voltage;

[0010] The detection time adaptation unit is used to receive the short-circuit signal and the reference voltage, and generate a trigger signal with a delay, wherein the delay time is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage;

[0011] The trigger unit is configured to generate a short-circuit protection signal when receiving the trigger signal.

[0012] Furthermore, the short-circuit signal is a step signal, and the detection time adaptation unit is used to receive the short-circuit signal and the reference voltage, and convert the step signal into a ramp signal, wherein the slope of the ramp signal is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage;

[0013] When the ramp signal ramps down or ramps up to a threshold of the trigger unit, the trigger unit generates the short-circuit protection signal.

[0014] Furthermore, the detection time adaptation unit includes a current mirror circuit and an integration circuit; the input end of the integration circuit serves as the input end of the detection time adaptation unit, the output end of the integration circuit serves as the output end of the detection time adaptation unit, the reference end of the integration circuit serves as the reference end of the detection time adaptation unit, the VCC ends of the current mirror circuit and the integration circuit serve as the VCC end of the detection time adaptation unit, and the VSS ends of the current mirror circuit and the integration circuit serve as the VSS end of the detection time adaptation unit;

[0015] The output end of the current mirror circuit is electrically connected to the control end of the integration circuit;

[0016] The current mirror circuit is used to keep the constant current source of the integration circuit turned on;

[0017] The integration circuit is used to receive the short-circuit signal and the reference voltage, and convert the step signal into a ramp signal, wherein the slope of the ramp signal is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage.

[0018] Furthermore, the integration circuit includes a resistor R1, a capacitor C1, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, and a MOS transistor M7; one end of the resistor R1 serves as an input end of the integration circuit, the drain of the MOS transistor M5 serves as an output end of the integration circuit, the gate of the MOS transistor M5 serves as a reference end of the integration circuit, the gate of the MOS transistor M3 serves as a control end of the integration circuit, the sources of the MOS transistors M6 and M7 serve as VCC ends of the integration circuit, and the source of the MOS transistor M3 serves as VSS ends of the integration circuit;

[0019] The other end of the resistor R1 and one end of the capacitor C1 are electrically connected to the gate of the MOS transistor M4. The drain of the MOS transistor M4, the drain of the MOS transistor M6, and the gate of the MOS transistor M6 are electrically connected to the gate of the MOS transistor M7. The drain of the MOS transistor M7 and the other end of the capacitor C1 are electrically connected to the drain of the MOS transistor M5. The source of the MOS transistor M5 and the drain of the MOS transistor M3 are electrically connected to the source of the MOS transistor M4.

[0020] Furthermore, the MOS transistor M4 and the MOS transistor M5 are identical MOS transistors, and the MOS transistor M6 and the MOS transistor M7 are identical MOS transistors.

[0021] Furthermore, the current mirror circuit includes a MOS transistor M1 and a MOS transistor M2; the gate of the MOS transistor M1 serves as the output end of the current mirror circuit, the source of the MOS transistor M1 and the gate of the MOS transistor M2 serve as the VSS end of the current mirror circuit, and the source of the MOS transistor M2 serves as the VCC end of the current mirror circuit;

[0022] The drain of the MOS transistor M1 and the gate of the MOS transistor M1 are electrically connected to the drain of the MOS transistor M2.

[0023] Furthermore, the detection time reference unit includes a resistor R2 and a resistor R3; one end of the resistor R2 is used as the output end of the detection time reference unit, the other end of the resistor R2 is used as the VCC end of the detection time reference unit, and one end of the resistor R3 is used as the VSS end of the detection time reference unit;

[0024] The other end of the resistor R2 is electrically connected to the other end of the resistor R3.

[0025] Furthermore, the trigger unit includes a MOS transistor M8 and a MOS transistor M9; the gate of the MOS transistor M8 is used as the input end of the trigger unit, the drain of the MOS transistor M8 is used as the output end of the trigger unit, the source of the MOS transistor M8 is used as the VSS end of the trigger unit, and the source of the MOS transistor M9 is used as the VCC end of the trigger unit;

[0026] The gate of the MOS transistor M9 is electrically connected to the gate of the MOS transistor M8 , and the drain of the MOS transistor M9 is electrically connected to the drain of the MOS transistor M8 .

[0027] A high-voltage integrated circuit, comprising at least one of the above-mentioned short-circuit protection circuits adapted to bus voltage; further comprising a fault logic control unit and at least one fault detection unit; the input end of the short-circuit protection circuit and the input end of the fault detection unit both serving as feedback ports of the high-voltage integrated circuit, and the output end of the short-circuit protection circuit and the output end of the fault detection unit being electrically connected to the input end of the fault logic control unit respectively;

[0028] The fault logic control unit is used to shut down the high-voltage integrated circuit when any one of the short-circuit protection circuit and the fault detection unit feeds back a protection signal.

[0029] The technical solution provided by the present invention may include the following beneficial effects: taking the intelligent power module as an example, when the peripheral circuit of the high-voltage integrated circuit (HVIC) detects that the SiC-MOSFET in the intelligent power module has a short-circuit fault, it will feed back a short-circuit signal to the high-voltage integrated circuit, and the high-voltage integrated circuit can use the detection time adaptation unit to receive the short-circuit signal, and start delaying at the same time. After the delay ends, a trigger signal is generated for the trigger unit to generate a short-circuit protection signal, so that the high-voltage integrated circuit can implement short-circuit protection action, thereby avoiding temporary short-circuit faults (such as narrow pulse disturbances with different pulse widths) from falsely triggering the short-circuit protection; and because the voltage of the short-circuit signal represents the voltage caused by the busbar connected to the SiC-MOSFET The short-circuit voltage is the short-circuit signal, so the greater the voltage of the short-circuit signal (that is, the greater the connected bus voltage), the shorter the tolerance time of the SiC-MOSFET, and the shorter the anti-false triggering detection time (that is, the delay time). Therefore, the detection time reference unit is used to generate a reference voltage as a reference to judge the size of the connected bus voltage, so that the delay time is set in inverse proportion to the difference between the voltage of the short-circuit signal and the reference voltage, thereby automatically adjusting the short-circuit detection time (that is, the delay time) according to different bus voltages, which can detect short-circuit faults and perform protection more quickly, while maintaining the ability to prevent narrow pulses of different pulse widths from falsely triggering short-circuit protection under different bus voltages. It is particularly suitable for devices or circuits that are sensitive to bus voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a circuit schematic diagram of a short-circuit protection circuit adapted to bus voltage according to one embodiment of the present invention.

[0031] Figure 2 Yes Figure 1 The waveform comparison diagram of a short-circuit protection circuit adapted to bus voltage is shown.

[0032] Figure 3 This is a partial schematic diagram of a high-voltage integrated circuit according to one embodiment of the present invention.

[0033] Among them: detection time adaptation unit 1, detection time reference unit 2, trigger unit 3, current mirror circuit 11, integration circuit 12, resistor R1, capacitor C1, MOS transistor M3, MOS transistor M4, MOS transistor M5, MOS transistor M6, MOS transistor M7, MOS transistor M1, MOS transistor M2, resistor R2, resistor R3, MOS transistor M8, MOS transistor M9, short-circuit protection circuit 4, fault logic control unit 5, fault detection unit 6. DETAILED DESCRIPTION

[0034] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0035] In the description of the embodiments of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of the embodiments of the present invention, "plurality" means two or more, unless otherwise specifically specified.

[0036] In the description of the embodiments of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to direct connections or indirect connections through an intermediate medium; they may refer to internal communication between two components or an interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the embodiments of the present invention based on specific circumstances.

[0037] The following combination Figures 1 to 3 , describing a short-circuit protection circuit adapted to bus voltage and a high-voltage integrated circuit thereof according to an embodiment of the present invention.

[0038] Example 1

[0039] A short-circuit protection circuit adapted to bus voltage, comprising a detection time adaptation unit 1, a detection time reference unit 2, and a trigger unit 3; the input end of the detection time adaptation unit 1 serves as the input end of the short-circuit protection circuit, and the output end of the trigger unit 3 serves as the output end of the short-circuit protection circuit;

[0040] The reference end of the detection time adaptation unit 1 is electrically connected to the output end of the detection time reference unit 2, the output end of the detection time adaptation unit 1 is electrically connected to the input end of the trigger unit 3, the VCC ends of the detection time adaptation unit 1, the detection time reference unit 2, and the trigger unit 3 are all connected to the power supply VCC, and the VSS ends of the detection time adaptation unit 1, the detection time reference unit 2, and the trigger unit 3 are all connected to the power supply VSS;

[0041] The detection time reference unit 2 is used to generate a reference voltage;

[0042] The detection time adaptation unit 1 is used to receive the short-circuit signal and the reference voltage, and generate a trigger signal with a delay, wherein the delay time is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage;

[0043] The trigger unit 3 is configured to generate a short-circuit protection signal when receiving a trigger signal.

[0044] The present invention proposes a short-circuit protection circuit adapted to bus voltage and a preferred embodiment of a high-voltage integrated circuit thereof, as shown in FIG. Figure 1 As shown, taking the intelligent power module as an example, when the peripheral circuit of the high-voltage integrated circuit (HVIC) detects that the SiC-MOSFET in the intelligent power module has a short-circuit fault, it will feed back a short-circuit signal to the high-voltage integrated circuit. The high-voltage integrated circuit can use the detection time adaptation unit 1 to receive the short-circuit signal, and start delaying at the same time. After the delay ends, a trigger signal is generated for the trigger unit 3 to generate a short-circuit protection signal, so that the high-voltage integrated circuit can implement short-circuit protection action, thereby avoiding temporary short-circuit faults (such as narrow pulse disturbances with different pulse widths) from falsely triggering the short-circuit protection; and because the voltage of the short-circuit signal represents the short-circuit voltage caused by the busbar connected to the SiC-MOSFET, The greater the voltage of the short-circuit signal (i.e., the greater the connected bus voltage), the shorter the tolerance time of the SiC-MOSFET, and the shorter the anti-false triggering detection time (i.e., the delay time). Therefore, the detection time reference unit 2 is used to generate a reference voltage as a reference to judge the size of the connected bus voltage, so that the delay time is set inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage. In this way, the short-circuit detection time (i.e., the delay time) is automatically adjusted according to different bus voltages, which can detect short-circuit faults and provide protection more quickly, while maintaining the ability to prevent narrow pulses of different pulse widths from falsely triggering short-circuit protection under different bus voltages. This is particularly suitable for devices or circuits that are sensitive to bus voltage.

[0045] Furthermore, the short-circuit signal is a step signal, and the detection time adaptation unit 1 is used to receive the short-circuit signal and the reference voltage, and convert the step signal into a ramp signal, wherein the slope of the ramp signal is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage;

[0046] When the ramp signal ramps down or ramps up to the threshold of the trigger unit 3 , the trigger unit 3 generates a short-circuit protection signal.

[0047] In this embodiment, the short-circuit signal is usually a step signal. For example, it is a low level in the normal state, and when a short-circuit fault occurs, it will step to a high level. In order to enable the detection time adaptation unit 1 to delay the generation of the trigger signal, the delay time is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage. The detection time adaptation unit 1 preferably converts the step signal into a ramp signal, and makes the slope of the ramp signal inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage, thereby obtaining the following: Figure 2 The waveform diagram shown is only a waveform diagram of one embodiment, in which Vin is the voltage of the short-circuit signal, and Va is Figure 1 The voltage at point a in the figure (shows a ramp-down change, i.e., a ramp-changing signal), Vout in the figure represents the output signal change of the trigger unit 3, and Vth8 in the figure is the threshold of the trigger unit 3 (equivalent to the trigger signal). When the ramp-changing signal ramps down to the threshold of the trigger unit 3, the trigger unit 3 generates a short-circuit protection signal (for example, Vout is a high level), and then the short-circuit protection signal is generated by Figure 2 It can be seen that the function to be implemented by the detection time adaptation unit 1 is realized.

[0048] Furthermore, the detection time adaptation unit 1 includes a current mirror circuit 11 and an integration circuit 12; the input end of the integration circuit 12 serves as the input end of the detection time adaptation unit 1, the output end of the integration circuit 12 serves as the output end of the detection time adaptation unit 1, the reference end of the integration circuit 12 serves as the reference end of the detection time adaptation unit 1, the VCC ends of the current mirror circuit 11 and the integration circuit 12 serve as the VCC ends of the detection time adaptation unit 1, and the VSS ends of the current mirror circuit 11 and the integration circuit 12 serve as the VSS ends of the detection time adaptation unit 1;

[0049] The output terminal of the current mirror circuit 11 is electrically connected to the control terminal of the integration circuit 12;

[0050] The current mirror circuit 11 is used to keep the constant current source of the integration circuit 12 turned on;

[0051] The integration circuit 12 is used to receive the short-circuit signal and the reference voltage, and convert the step signal into a ramp signal. The slope of the ramp signal is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage.

[0052] In this embodiment, the detection time adaptation unit 1 receives the short-circuit signal via the integration circuit 12 and integrates it to form a linear ramp signal based on the characteristics of the integration circuit. Simultaneously, the current mirror circuit 11 is used to keep the constant current source of the integration circuit 12 conductive, thereby improving the stability of the integration circuit 12 and making the ramp signal more linear. This is because the current mirror circuit 11 can accurately replicate the current and is not affected by process and temperature.

[0053] Furthermore, the integration circuit 12 includes a resistor R1, a capacitor C1, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, and a MOS transistor M7; one end of the resistor R1 serves as an input end of the integration circuit 12, the drain of the MOS transistor M5 serves as an output end of the integration circuit 12, the gate of the MOS transistor M5 serves as a reference end of the integration circuit 12, the gate of the MOS transistor M3 serves as a control end of the integration circuit 12, the sources of the MOS transistors M6 and M7 serve as VCC ends of the integration circuit 12, and the source of the MOS transistor M3 serves as VSS ends of the integration circuit 12;

[0054] The other end of the resistor R1 and one end of the capacitor C1 are electrically connected to the gate of the MOS transistor M4. The drain of the MOS transistor M4, the drain of the MOS transistor M6, and the gate of the MOS transistor M6 are electrically connected to the gate of the MOS transistor M7. The drain of the MOS transistor M7 and the other end of the capacitor C1 are electrically connected to the drain of the MOS transistor M5. The source of the MOS transistor M5 and the drain of the MOS transistor M3 are electrically connected to the source of the MOS transistor M4.

[0055] In this embodiment, the resistor R1 and the capacitor C1 form a charge-discharge circuit, and the MOS transistor M3 (equivalent to a constant current source), the MOS transistor M4, the MOS transistor M5, the MOS transistor M6, and the MOS transistor M7 form an amplifier. The charge-discharge circuit and the amplifier form an integration circuit 12. Taking the ramp signal as a ramp-down signal as an example, the step signal transmitted by Vin is converted into a ramp-down signal:

[0056] According to the formula of the integration circuit, we know

[0057] Where Va is Figure 1 The voltage at point a, R1 is the resistance of resistor R1, C1 is the capacitance of capacitor C1, Vin is the voltage of the short-circuit signal, and Vb is the reference voltage;

[0058] like Figure 1As shown in FIG5 , when the input terminal IN is at a low level, the MOS transistor M4 is not turned on, the MOS transistors M3, M5, M6 and M7 are all turned on, and the voltage at point a is a high level; when the voltage at the input terminal IN jumps to a high level, the MOS transistors M3, M4, M5, M6 and M7 are all turned on, and the voltage at point a becomes a low level. Due to the existence of the charge and discharge circuit of the resistor R1 and the capacitor C1, the voltage at point a will not suddenly change to a low level, but will decrease to a low level, as shown in FIG5 . Figure 2 As shown in the Va-t waveform diagram.

[0059] The trigger unit 3 is equivalent to an inverter, which is used to invert the output voltage at point a and shape it into a square wave (such as Figure 2 When the voltage at point a is high, the output voltage at the OUT terminal is low. When the voltage at point a drops below the threshold Vth8 of the trigger unit 3, the OUT terminal outputs a high level (i.e., a short-circuit protection signal).

[0060] Therefore, when the input terminal IN is low, the OUT terminal outputs a low level. When the input terminal IN jumps to a high level, the OUT terminal also jumps to output a high level. The delay time is t2-t1 (e.g. Figure 2 shown).

[0061] According to formula (1), the short-circuit detection time T = t2-t1 = R1*C1*Vth8 / (Vin-Vb)……(2);

[0062] As can be seen from formula (2), the larger the input voltage Vin, the larger the Vin-Vb difference, the larger the gate voltage difference between MOS tube M4 and MOS tube M5, the smaller the short-circuit detection time T, and the smaller the ability to prevent narrow pulse false triggering; the smaller the input voltage Vin, the smaller the Vin-Vb difference, the smaller the gate voltage difference between M4 and M5, and the longer the short-circuit detection time T (i.e., delay time); therefore, the circuit can automatically adjust the short-circuit detection time according to different bus voltages, can detect short-circuit faults more quickly and provide protection, while maintaining the ability to prevent narrow pulses of different pulse widths from falsely triggering short-circuit protection under different bus voltages. More importantly, as can be seen from formula (2), the integration circuit 12 composed of resistor R1, capacitor C1, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, and MOS tube M7 has better linearity.

[0063] Furthermore, the MOS transistor M4 and the MOS transistor M5 are identical MOS transistors, and the MOS transistor M6 and the MOS transistor M7 are identical MOS transistors.

[0064] In this embodiment, in order to reduce the noise of the integration circuit 12 and improve stability and linearity, the integration circuit 12 is arranged as symmetrically as possible to reduce the influence of input signal noise. The MOS transistors M4 and M5 are exactly the same MOS transistors, so that the width-to-length ratio parameters of the MOS transistors M4 and M5 are consistent; the MOS transistors M6 and M7 are exactly the same MOS transistors, so that the width-to-length ratio parameters of the MOS transistors M6 and M7 are consistent.

[0065] Furthermore, the current mirror circuit 11 includes a MOS transistor M1 and a MOS transistor M2; the gate of the MOS transistor M1 serves as the output terminal of the current mirror circuit 11, the source of the MOS transistor M1 and the gate of the MOS transistor M2 serve as the VSS terminal of the current mirror circuit 11, and the source of the MOS transistor M2 serves as the VCC terminal of the current mirror circuit 11;

[0066] The drain of the MOS transistor M1 and the gate of the MOS transistor M1 are electrically connected to the drain of the MOS transistor M2.

[0067] In this embodiment, the current mirror circuit 11 composed of MOS transistors shows significant advantages in accuracy, stability, power consumption, input impedance and voltage range, making it more stable when the MOS transistor M3 equivalent to the constant current source in the control integration circuit 12 remains turned on.

[0068] Furthermore, the detection time reference unit 2 includes a resistor R2 and a resistor R3; one end of the resistor R2 is used as the output end of the detection time reference unit 2, the other end of the resistor R2 is used as the VCC end of the detection time reference unit 2, and one end of the resistor R3 is used as the VSS end of the detection time reference unit 2;

[0069] The other end of the resistor R2 and the other end of the resistor R3 are electrically connected.

[0070] In this embodiment, the detection time reference unit 2 uses a resistor R2 and a resistor R3 to form a voltage divider circuit to provide a reference voltage Vb for the detection time adaptation unit 1, while keeping the MOS transistor M5 turned on.

[0071] Furthermore, the trigger unit 3 includes a MOS transistor M8 and a MOS transistor M9; the gate of the MOS transistor M8 is used as the input end of the trigger unit 3, the drain of the MOS transistor M8 is used as the output end of the trigger unit 3, the source of the MOS transistor M8 is used as the VSS end of the trigger unit 3, and the source of the MOS transistor M9 is used as the VCC end of the trigger unit 3;

[0072] The gate of the MOS transistor M9 is electrically connected to the gate of the MOS transistor M8 , and the drain of the MOS transistor M9 is electrically connected to the drain of the MOS transistor M8 .

[0073] In this embodiment, the trigger unit 3 is composed of a MOS transistor M8 and a MOS transistor M9 forming an inverter, which realizes the requirement of inverting the output voltage at point a and shaping it into a square wave. Specifically, when the voltage at point a is at a high level, the MOS transistor M8 is turned on, the MOS transistor M9 is turned off, and the output voltage at the OUT terminal is a low level. When the voltage at point a drops below the threshold voltage Vth8 of the MOS transistor M8, the MOS transistor M8 is turned off, the MOS transistor M9 is turned on, and the OUT terminal outputs a high level.

[0074] Example 2

[0075] A high-voltage integrated circuit, comprising at least one of the above-mentioned short-circuit protection circuits 4 adapted to bus voltage; further comprising a fault logic control unit 5 and at least one fault detection unit 6; the input end of the short-circuit protection circuit 4 and the input end of the fault detection unit 6 both serving as feedback ports of the high-voltage integrated circuit, and the output end of the short-circuit protection circuit 4 and the output end of the fault detection unit 6 being electrically connected to the input end of the fault logic control unit 5, respectively;

[0076] The fault logic control unit 5 is used to shut down the high-voltage integrated circuit when any one of the short-circuit protection circuit 4 and the fault detection unit 6 feeds back a protection signal.

[0077] The present invention also proposes a preferred embodiment of a high voltage integrated circuit, such as Figure 3 As shown, the above-mentioned short-circuit protection circuit 4 adapted to the bus voltage can be integrated into a high-voltage integrated circuit. Devices or circuits that are insensitive to the bus voltage are detected by connecting the input end of the fault detection unit 6, and devices or circuits that are sensitive to the bus voltage are detected by connecting the input end of the short-circuit protection circuit 4. Then, the fault logic control unit 5 is used to comprehensively judge all fault conditions of the short-circuit protection circuit 4 and the fault detection unit 6. As long as there is a trigger feedback protection signal, the protection action is executed and the high-voltage integrated circuit is shut down; thereby, the high-voltage integrated circuit has two protection detection modes: fixed detection time and automatic adjustment of detection time according to different bus voltages, and is adapted to the application environment of more power modules.

[0078] Other structures and operations of a short-circuit protection circuit adapted to bus voltage and a high-voltage integrated circuit thereof according to an embodiment of the present invention are well known to those skilled in the art and will not be described in detail here.

[0079] Throughout this specification, reference to terms such as "embodiment" or "example" indicates that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0080] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

Claims

1. A short-circuit protection circuit adapted to bus voltage, characterized in that: It includes a detection time adaptation unit, a detection time reference unit and a trigger unit; the input end of the detection time adaptation unit is used as the input end of the short-circuit protection circuit, and the output end of the trigger unit is used as the output end of the short-circuit protection circuit; The reference end of the detection time adaptation unit is electrically connected to the output end of the detection time reference unit, the output end of the detection time adaptation unit is electrically connected to the input end of the trigger unit, the VCC ends of the detection time adaptation unit, the detection time reference unit, and the trigger unit are all connected to a power supply VCC, and the VSS ends of the detection time adaptation unit, the detection time reference unit, and the trigger unit are all connected to a power supply VSS; The detection time reference unit is used to generate a reference voltage; The detection time adaptation unit is used to receive the short-circuit signal and the reference voltage, and generate a trigger signal with a delay, wherein the delay time is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage; The trigger unit is configured to generate a short-circuit protection signal when receiving the trigger signal; The short-circuit signal is a step signal, and the detection time adaptation unit is used to receive the short-circuit signal and the reference voltage, and convert the step signal into a ramp signal, wherein the slope of the ramp signal is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage; When the ramp signal ramps down or ramps up to a threshold of the trigger unit, the trigger unit generates the short-circuit protection signal.

2. A short-circuit protection circuit adapted to bus voltage according to claim 1, characterized in that: The detection time adaptation unit includes a current mirror circuit and an integration circuit; the input end of the integration circuit serves as the input end of the detection time adaptation unit, the output end of the integration circuit serves as the output end of the detection time adaptation unit, the reference end of the integration circuit serves as the reference end of the detection time adaptation unit, the VCC ends of the current mirror circuit and the integration circuit serve as the VCC end of the detection time adaptation unit, and the VSS ends of the current mirror circuit and the integration circuit serve as the VSS end of the detection time adaptation unit; The output end of the current mirror circuit is electrically connected to the control end of the integration circuit; The current mirror circuit is used to keep the constant current source of the integration circuit turned on; The integration circuit is used to receive the short-circuit signal and the reference voltage, and convert the step signal into a ramp signal, wherein the slope of the ramp signal is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage.

3. The short-circuit protection circuit adapted to bus voltage according to claim 2, characterized in that: The integration circuit includes a resistor R1, a capacitor C1, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, and a MOS transistor M7; one end of the resistor R1 serves as the input end of the integration circuit, the drain of the MOS transistor M5 serves as the output end of the integration circuit, the gate of the MOS transistor M5 serves as the reference end of the integration circuit, the gate of the MOS transistor M3 serves as the control end of the integration circuit, the sources of the MOS transistors M6 and M7 serve as the VCC end of the integration circuit, and the source of the MOS transistor M3 serves as the VSS end of the integration circuit; The other end of the resistor R1 and one end of the capacitor C1 are electrically connected to the gate of the MOS transistor M4. The drain of the MOS transistor M4, the drain of the MOS transistor M6, and the gate of the MOS transistor M6 are electrically connected to the gate of the MOS transistor M7. The drain of the MOS transistor M7 and the other end of the capacitor C1 are electrically connected to the drain of the MOS transistor M5. The source of the MOS transistor M5 and the drain of the MOS transistor M3 are electrically connected to the source of the MOS transistor M4.

4. A short-circuit protection circuit adapted to bus voltage according to claim 3, characterized in that: The MOS transistor M4 and the MOS transistor M5 are identical MOS transistors, and the MOS transistor M6 and the MOS transistor M7 are identical MOS transistors.

5. The short-circuit protection circuit adapted to bus voltage according to claim 2, characterized in that: The current mirror circuit includes a MOS transistor M1 and a MOS transistor M2; the gate of the MOS transistor M1 serves as the output terminal of the current mirror circuit, the source of the MOS transistor M1 and the gate of the MOS transistor M2 serve as the VSS terminal of the current mirror circuit, and the source of the MOS transistor M2 serves as the VCC terminal of the current mirror circuit; The drain of the MOS transistor M1 and the gate of the MOS transistor M1 are electrically connected to the drain of the MOS transistor M2.

6. The short-circuit protection circuit adapted to bus voltage according to claim 1, characterized in that: The detection time reference unit includes a resistor R2 and a resistor R3; one end of the resistor R2 is used as the output end of the detection time reference unit, the other end of the resistor R2 is used as the VCC end of the detection time reference unit, and one end of the resistor R3 is used as the VSS end of the detection time reference unit; The other end of the resistor R2 is electrically connected to the other end of the resistor R3.

7. The short-circuit protection circuit adapted to bus voltage according to claim 1, characterized in that: The trigger unit includes a MOS transistor M8 and a MOS transistor M9; the gate of the MOS transistor M8 is used as the input end of the trigger unit, the drain of the MOS transistor M8 is used as the output end of the trigger unit, the source of the MOS transistor M8 is used as the VSS end of the trigger unit, and the source of the MOS transistor M9 is used as the VCC end of the trigger unit; The gate of the MOS transistor M9 is electrically connected to the gate of the MOS transistor M8 , and the drain of the MOS transistor M9 is electrically connected to the drain of the MOS transistor M8 .

8. A high-voltage integrated circuit, characterized in that: The device comprises at least one short-circuit protection circuit for adapting bus voltage according to any one of claims 1 to 7; further comprising a fault logic control unit and at least one fault detection unit; the input end of the short-circuit protection circuit and the input end of the fault detection unit are both used as feedback ports of the high-voltage integrated circuit, and the output end of the short-circuit protection circuit and the output end of the fault detection unit are respectively electrically connected to the input end of the fault logic control unit; The fault logic control unit is used to shut down the high-voltage integrated circuit when any one of the short-circuit protection circuit and the fault detection unit feeds back a protection signal.

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