A MOSFET gate-level drive circuit with interlocking function

Abstract

The present invention relates to a MOSFET gate-level driving circuit with an interlocking function, wherein the driving circuit is designed with a power bridge upper and lower bridge arm control signal interlocking function and has a dead zone function, and comprises an optocoupler circuit, a switch circuit, and a driving circuit, wherein the optocoupler circuit outputs two-way signals PWM1‑OUT and PWM2‑OUT after performing optocoupler isolation on an input signal, wherein an input end of the switch circuit receives the output signal of the optocoupler circuit, and the switch circuit performs interlocking processing on the input two-way signals, and outputs four-way signals PWM1‑OUT, PWM2‑OUT and PWM1‑EN, PWM2‑EN. The MOSFET gate-level driving circuit of the present invention has strong anti-interference performance, and when the control signal is strongly interfered, the upper and lower bridge arms of the power bridge will not be opened at the same time, thereby ensuring the reliable operation of the power circuit when the control circuit operates abnormally.

Description

Technical Field

[0001] The invention relates to the technical field of general circuit signal amplification, and in particular to a MOSFET gate-level driving circuit with an interlocking function. Background Art

[0002] Under traditional technology, the full-bridge application of MOSFET (metal oxide semiconductor field effect transistor) is an important application in the field of power electronics. The following is the basic situation of the traditional technology of MOSFET full-bridge application:

[0003] (1) Full-bridge circuit structure: The full-bridge circuit consists of four MOSFETs divided into two half-bridges, each half-bridge contains a high-side switch and a low-side switch. This structure allows current to flow in both directions, thereby achieving bidirectional control of the load.

[0004] (2) DC motor drive: Full-bridge circuits are often used to drive DC motors. By controlling the switching state of the MOSFET, the direction and speed of the motor can be changed. This application is widely used in industrial automation and robotics.

[0005] (3) Frequency converter application: In the frequency converter, the full-bridge circuit is used to adjust the frequency and voltage of the AC power supply. By adjusting the conduction mode of the switch, the AC power supply can be adjusted over a wide range to meet the needs of different loads.

[0006] (4) Inverter application: An inverter is a device that converts direct current into alternating current. The full-bridge circuit plays a core role in the inverter. By controlling the switching of MOSFET, the DC power supply can be converted into AC power supply. It is widely used in solar power generation systems and uninterruptible power supplies (UPS).

[0007] (5) Power management: In power management applications, full-bridge circuits are used to switch the positive and negative polarity of power and adjust the voltage and current. This circuit is very critical in communication equipment, industrial equipment, and medical equipment.

[0008] These traditional applications demonstrate the diversity and importance of MOSFET full-bridge circuits in the field of power electronics. Through continuous technological innovation, MOSFET full-bridge circuits continue to improve efficiency, reduce size and enhance reliability, meeting the needs of modern electronic devices for high-performance power management systems.

[0009] In the full-bridge circuit, MOSFET will generate losses during the switching process, including turn-on loss and turn-off loss. These losses are particularly significant in high-frequency switching applications, which may lead to reduced efficiency and device overheating.

[0010] In high voltage and high current applications, the reliability and life of MOSFETs may be challenged. For example, overvoltage, overcurrent and overheating may cause device damage;

[0011] The control strategy of the full-bridge circuit is relatively complex and requires precise PWM signal synchronization and dead time control to prevent shoot-through short circuits and other faults.

[0012] Therefore, there is an urgent need for a circuit structure that provides an interlocking function for the control signals of the upper and lower arms of the power bridge to solve the problems of loss and heat generation and direct short circuit, and ensure that the circuit can work normally. Summary of the invention

[0013] In order to solve the above technical problems, the present invention provides a MOSFET gate-level drive circuit with an interlocking function. The drive circuit is designed with a power bridge upper and lower bridge arm control signal interlocking function and has a dead zone function, including an optocoupler circuit, a switch circuit, and a drive circuit. After the optocoupler circuit performs optocoupler isolation on the input signal, the optocoupler circuit outputs two signals PWM1-OUT and PWM2-OUT, wherein the input end of the switch circuit receives the output signal of the optocoupler circuit, and the switch circuit performs interlocking processing on the two input signals, and outputs four signals PWM1-OUT, PWM2-OUT and PWM1-EN, PWM2-EN;

[0014] The switching circuit includes two groups of branch circuits, which have the same structure and only different input and output ends. In one group of branch circuits, the base of the transistor is connected to the PWM1-OUT signal, and the collector end outputs the PWM2-EN signal; in the other group of branch circuits, the base of the transistor is connected to the PWM2-OUT signal, and the collector end outputs the PWM1-EN signal.

[0015] In one embodiment of the present invention, the input signal of the optocoupler circuit is two complementary control signals PWM1-IN and PWM2-IN input from the outside.

[0016] In one embodiment of the present invention, the optocoupler circuit includes an optocoupler chip and a peripheral circuit, wherein the peripheral circuit includes a plurality of resistors and capacitors, and two 1KΩ resistors R1 and R2 are provided, which are respectively arranged between the external input and the input pin of the optocoupler circuit; at the same time, R3 and R4 are provided as pull-down resistors, which are connected between the PWM1-OUT and PWM2-OUT output signals and the ground terminal.

[0017] In one embodiment of the present invention, a capacitor is disposed between the ground pin of the optocoupler chip and the ground as a filter capacitor to filter out high-frequency noise in the power supply.

[0018] In one embodiment of the present invention, the input end of the driving circuit receives the output signal of the switch circuit, and the driving circuit of the MOSFET outputs two signals PWM1 and PWM2 that are not high at the same time.

[0019] In one embodiment of the present invention, the driving circuit adopts a SL27523 driver, and its two independent enable control pins are respectively connected to PWM1-EN and PWM2-EN output by the switch circuit.

[0020] The above technical solution of the present invention has the following advantages over the prior art: the MOSFET gate-level drive circuit of the present invention has a control signal interlocking function of the upper and lower bridge arms of the power bridge, and a dead zone function, and has strong anti-interference performance. When the control signal is strongly interfered, the upper and lower bridge arms of the power bridge will not be opened at the same time, thereby ensuring the reliable operation of the power circuit when the control circuit operates abnormally. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0022] Figure 1 It is a principle block diagram of a MOSFET gate-level driving circuit with an interlocking function of the present invention;

[0023] Figure 2 is a circuit diagram of the optocoupler isolation circuit of the present invention;

[0024] Figure 3 is a circuit diagram of the driving circuit of the present invention;

[0025] Figure 4 Schematic diagram of the switch circuit of the present invention. DETAILED DESCRIPTION

[0026] like Figure 1 As shown, this embodiment provides a MOSFET gate-level drive circuit with an interlocking function, the drive circuit is designed with a power bridge upper and lower bridge arm control signal interlocking function, and has a dead zone function, including an optocoupler circuit, a switch circuit, and a drive circuit. After the optocoupler circuit performs optocoupler isolation on the input signal, it outputs two signals PWM1-OUT and PWM2-OUT, wherein the input end of the switch circuit receives the output signal of the optocoupler circuit, and the switch circuit performs interlocking processing on the two input signals, and outputs four signals PWM1-OUT, PWM2-OUT and PWM1-EN, PWM2-EN;

[0027] The input end of the driving circuit receives the output signal of the switching circuit, and the driving circuit of the MOSFET outputs two signals PWM1 and PWM2 which are high level at different times.

[0028] Specifically, in this embodiment, a MOSFET gate-level drive circuit with an interlocking function is constructed by an optocoupler circuit, a switch circuit and a drive circuit, wherein the switch circuit and the drive circuit constitute a control signal interlocking function. In the figure, the PWM1-IN and PWM2-IN control circuits output complementary PWM signals, and PWM1 and PWM2 are power bridge drive signals.

[0029] like Figure 2 As shown, the optocoupler circuit includes an optocoupler chip and a peripheral circuit. The optocoupler chip is ACPL-064L-000E, but this circuit is not limited to this chip. The function of the optocoupler circuit is to use optical signals to transmit electrical signals to achieve electrical isolation between input and output, thereby protecting the circuit from high voltage or noise interference. In the peripheral circuit, two 1KΩ resistors R1 and R2 are used to limit the current and protect the input of the optocoupler chip; R3 and R4 are used as pull-down resistors to keep the PWM1-OUT and PWM2-OUT output signals at a low level; the C1 capacitor is used as a filter capacitor to filter out high-frequency noise in the power supply and reduce interference with the output signal.

[0030] like Figure 3 As shown, the drive circuit adopts SL27523 driver, and its two independent enable control pins are respectively connected to PWM1-EN and PWM2-EN output by the switch circuit; since the selected chip has two independent enable control pins, only when the enable pin is at a high level, the output of the corresponding channel will change with the change of the input, so when one enable is high and the other enable is low, only one signal will be output. By using this principle, the two PWM control signals can be interlocked.

[0031] PWM1-OUT is converted to PWM1. As long as the VDD pin is powered, such as 15V, then when PWM1-OUT and ENA input are valid, the output level is 15V. Similarly, PWM2-OUT is converted to PWM2, and the principle is the same.

[0032] At the same time Figure 3 , 4 As shown, the switch circuit and the drive circuit constitute the interlocking circuit of the upper and lower tube control signals, forming a NOT gate logic structure. When PWM1-OUT is high and PWM2-EN is low, then no matter what state PWM2-OUT is in, the corresponding PWM2 is invalid (low level). Only when PWM1-IN is low, the PWM2 corresponding to the output of PWM2-IN is valid, which realizes the complete control of the upper and lower tubes. The principle of the second signal is the same.

[0033] In summary, the MOSFET gate-level drive circuit described in this embodiment is designed with a signal interlocking circuit structure to ensure that when the signal is subject to unpredictable power electrical interference or the control circuit is out of control, the upper and lower bridge arms of the power tube can still be effectively prevented from being directly connected, thereby ensuring the working reliability of the power bridge.

[0034] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A MOSFET gate-level drive circuit with an interlocking function, wherein the drive circuit is designed with a power bridge upper and lower bridge arm control signal interlocking function and has a dead zone function, characterized in that: It includes an optocoupler circuit, a switch circuit, and a drive circuit. After the optocoupler circuit performs optocoupler isolation on the input signal, it outputs two signals PWM1-OUT and PWM2-OUT. The input end of the switch circuit receives the output signal of the optocoupler circuit. The switch circuit performs interlocking processing on the two input signals and outputs four signals PWM1-OUT, PWM2-OUT and PWM1-EN, PWM2-EN. The switching circuit includes two groups of branch circuits, which have the same structure and only different input and output ends. In one group of branch circuits, the base of the transistor is connected to the PWM1-OUT signal, and the collector end outputs the PWM2-EN signal; in the other group of branch circuits, the base of the transistor is connected to the PWM2-OUT signal, and the collector end outputs the PWM1-EN signal.

2. The MOSFET gate-level driving circuit according to claim 1, characterized in that: The input signals of the optocoupler circuit are two complementary control signals PWM1-IN and PWM2-IN input from the outside.

3. The MOSFET gate-level driving circuit according to claim 2, characterized in that: The optocoupler circuit includes an optocoupler chip and a peripheral circuit, wherein the peripheral circuit includes a plurality of resistors and capacitors. Two 1KΩ resistors R1 and R2 are provided, which are respectively provided between the external input and the input pin of the optocoupler circuit; R3 and R4 are provided as pull-down resistors, which are connected between the PWM1-OUT and PWM2-OUT output signals and the ground terminal.

4. The MOSFET gate-level driving circuit according to claim 3, characterized in that: The capacitor is arranged between the ground pin of the optocoupler chip and the ground as a filter capacitor to filter out high-frequency noise in the power supply.

5. The MOSFET gate-level driving circuit according to claim 1, characterized in that: The input end of the driving circuit receives the output signal of the switching circuit, and the driving circuit of the MOSFET outputs two signals PWM1 and PWM2 which are high level at different times.

6. The MOSFET gate-level driving circuit according to claim 5, characterized in that: The driving circuit adopts a SL27523 driver, and its two independent enable control pins are respectively connected to PWM1-EN and PWM2-EN output by the switch circuit.

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