Packaging substrate and manufacturing method thereof, electric driving system and vehicle

Abstract

The invention provides a packaging substrate and a manufacturing method thereof, an electric driving system and a vehicle. The packaging substrate comprises a transmission layer group, a power chip embedded in the transmission layer group, a first circuit layer, a second circuit layer, a top layer and a power supply negative electrode layer, the transmission layer group is provided with a first surface and a second surface which are oppositely arranged along the stacking direction of the packaging substrate, the first circuit layer is stacked on the first surface, and the second circuit layer is stacked on the second surface; a first potential transmission part and a negative potential part are arranged on the first circuit layer, and a second potential transmission part and a positive potential part are arranged on the second circuit layer; the power supply cathode layer is laminated on one side of the first circuit layer away from the first surface and is connected to the cathode potential part. The top layer is laminated on the power supply cathode layer.

Description

Technical Field

[0001] The present application belongs to the field of electric drive control technology, and more specifically, relates to a packaging substrate and a manufacturing method thereof, an electric drive system and a vehicle. Background Art

[0002] Generally, in the driving system of electric vehicles, the main driving circuit board based on the embedded system adopts a symmetrical board structure with an even number of layers, such as 6 or 8 layers. The manufacturing process of the even-numbered symmetrical board structure is simple and the board surface warping is small. In practical applications, it is difficult to layout various components in the 6-layer board structure, and it is impossible to achieve the design requirements of low parasitic inductance. The 8-layer board structure has a large heat dissipation requirement due to the large number of layers, and the heat dissipation design requirements of the circuit board are high.

[0003] like Figure 1 As shown, taking a 6-layer board structure as an example, from top to bottom, the first layer 10 is used to arrange devices, the second layer 20 is provided with a first control circuit and a first power circuit arranged in sequence in the horizontal direction, the third layer 30 and the fourth layer 40 are used to embed the power chip 70, and the fifth layer 50 is provided with a second power circuit and a second control circuit arranged in sequence in the horizontal direction. As can be seen from the figure, the second layer 20 and the fifth layer 50 are respectively partitioned to contain different circuits arranged in the horizontal direction, resulting in a small stacking of the first power circuit and the first control circuit, and the first control circuit and the second power circuit, and the parasitic inductance of the loop is relatively large, and the design requirement of low parasitic inductance cannot be achieved. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a packaging substrate and a method for manufacturing the same, an electric drive system and a vehicle, so as to solve the technical problem that the existing even-layer board structure cannot achieve low parasitic inductance and has high heat dissipation requirements.

[0005] To achieve the above purpose, the technical solution adopted in this application is:

[0006] Provided is a packaging substrate, comprising a transmission layer group and a power chip embedded in the transmission layer group, as well as a first circuit layer, a second circuit layer, a top layer and a power supply cathode layer;

[0007] The transmission layer group has a first surface and a second surface which are arranged in opposition to each other along the stacking direction of the package substrate, the first circuit layer is stacked on the first surface, and the second circuit layer is stacked on the second surface; a first potential transmission portion and a negative potential portion spaced apart from the first potential transmission portion are provided on the first circuit layer, and a second potential transmission portion and a positive potential portion spaced apart from the second potential transmission portion are provided on the second circuit layer; the first potential transmission portion and the positive potential portion are arranged opposite to each other along the stacking direction, and the second potential transmission portion and the negative potential portion are arranged opposite to each other along the stacking direction;

[0008] Furthermore, the negative power layer is stacked on a side of the first circuit layer away from the first surface and connected to the negative potential portion, and the top layer is stacked on the negative power layer.

[0009] In some embodiments, the packaging substrate further includes a metal weight layer and a weight insulation layer;

[0010] The counterweight insulating layer is stacked on the side of the second circuit layer away from the second surface, the metal counterweight layer is stacked on the side of the counterweight insulating layer away from the second surface, and the weight of the metal counterweight layer is equal to the sum of the weights of the negative power layer and the top layer.

[0011] In some embodiments, the thickness of the metal weight layer along the stacking direction is equal to the sum of the thicknesses of the negative power supply layer and the top layer along the stacking direction.

[0012] In some embodiments, the packaging substrate further includes a metal weight layer and a weight insulation layer;

[0013] The counterweight insulating layer is stacked on the side of the second circuit layer away from the second surface, the metal counterweight layer is stacked on the side of the counterweight insulating layer away from the second surface, and the sum of the weights of the metal counterweight layer and the counterweight insulating layer is equal to the sum of the weights of the negative power supply layer and the top layer.

[0014] In some embodiments, the thickness of the metal counterweight layer along the stacking direction is smaller than the sum of the thickness of the negative power supply layer and the top layer along the stacking direction, and the thickness of the counterweight insulation layer along the stacking direction is larger than the sum of the thickness of the negative power supply layer and the top layer along the stacking direction.

[0015] In some embodiments, the metal weight layer, the negative power layer, and the top layer are made of the same material.

[0016] In some embodiments, the power chip is embedded in the transmission layer group located between the positive potential portion and the first potential transmission portion along the stacking direction, and the power chip is embedded in the transmission layer group located between the second potential transmission portion and the negative potential portion along the stacking direction.

[0017] The packaging substrate provided by the present application has the following beneficial effects:

[0018] The packaging substrate provided in the present application adds a negative power electrode layer, which is stacked on the side of the first circuit layer away from the first surface. Along the stacking direction of the packaging substrate, the positive potential part and the first potential transmission part, as well as the first potential transmission part and the negative power electrode layer are stacked, thereby meeting the design requirements of low parasitic loop inductance.

[0019] For example, compared with the existing 6-layer board structure, a negative power layer is added, and the negative power layer is stacked on the side of the first circuit layer away from the first surface, realizing the stacking of the positive potential part and the first potential transmission part and the first potential transmission part and the negative power layer, thereby meeting the design requirements of low parasitic loop inductance.

[0020] For example, compared with the existing 8-layer board structure, the packaging substrate provided in the present application adds a negative power layer, so that an odd-numbered layer design can be achieved. Compared with 8 layers, the design requirements for heat dissipation can be reduced, thereby reducing the design cost compared with 8 layers.

[0021] Another object of the present application is to provide an electric drive system, which includes the packaging substrate as described above.

[0022] The beneficial effects of the electric drive system provided in the present application compared to the prior art are consistent with the beneficial effects of the packaging substrate provided in the present application compared to the prior art, and will not be repeated here.

[0023] Another object of the present application is to provide a vehicle, the vehicle comprising the packaging substrate as described above; or the vehicle comprising the electric drive system as described above.

[0024] The beneficial effects of the vehicle provided in the present application compared to the prior art are consistent with the beneficial effects of the packaging substrate or electric drive system provided in the present application compared to the prior art, and will not be repeated here.

[0025] Another object of the present application is to provide a method for manufacturing a packaging substrate, the manufacturing method comprising:

[0026] A first prefabricated layer group is provided, comprising a transmission layer group having a first surface and a second surface, a power chip embedded in the transmission layer group, and a first circuit layer stacked on the first surface and a second circuit layer stacked on the second surface; wherein a first potential transmission portion and a negative electrode potential portion spaced apart from the first potential transmission portion are provided on the first circuit layer, and a second potential transmission portion and a positive electrode potential portion spaced apart from the second potential transmission portion are provided on the second circuit layer; the first potential transmission portion and the positive electrode potential portion are arranged opposite to each other along the stacking direction, and the second potential transmission portion and the negative electrode potential portion are arranged opposite to each other along the stacking direction;

[0027] A second prefabricated layer group is provided, including a negative power layer and a top layer stacked on the negative power layer. The second prefabricated layer group is stacked on the first prefabricated layer group, and the negative power layer is stacked on the side of the first circuit layer away from the first surface.

[0028] In some embodiments, before or after laminating the second prefabricated layer group on the first prefabricated layer group, the manufacturing method further includes:

[0029] A third prefabricated layer group is provided, comprising a metal weight layer and a weight insulation layer stacked on the metal weight layer; the third prefabricated layer group is stacked on the first prefabricated layer group, and the weight insulation layer is stacked on a side of the second circuit layer away from the second surface.

[0030] Another object of the present application is to provide a method for manufacturing a packaging substrate, the manufacturing method comprising:

[0031] A prefabricated layer group is provided, comprising a transmission layer group having a first surface and a second surface, a power chip embedded in the transmission layer group, and a first circuit layer stacked on the first surface, a second circuit layer stacked on the second surface, and a weighted insulating layer stacked on the second circuit layer; wherein a first potential transmission portion and a negative electrode potential portion spaced apart from the first potential transmission portion are provided on the first circuit layer, and a second potential transmission portion and a positive electrode potential portion spaced apart from the second potential transmission portion are provided on the second circuit layer; the first potential transmission portion and the positive electrode potential portion are arranged opposite to each other along the stacking direction, and the second potential transmission portion and the negative electrode potential portion are arranged opposite to each other along the stacking direction;

[0032] stacking a negative power supply layer on a side of the first circuit layer away from the first surface;

[0033] laminating a metal weight layer on a side of the weight insulation layer facing away from the second surface;

[0034] The top layer is stacked on the side of the negative power supply layer facing away from the first surface.

[0035] Another object of the present application is to provide a method for manufacturing a packaging substrate, the manufacturing method comprising:

[0036] A prefabricated layer group is provided, comprising a transmission layer group having a first surface and a second surface, a power chip embedded in the transmission layer group, and a first circuit layer stacked on the first surface, a second circuit layer stacked on the second surface, and a weighted insulating layer stacked on the second circuit layer; wherein a first potential transmission portion and a negative electrode potential portion spaced apart from the first potential transmission portion are provided on the first circuit layer, and a second potential transmission portion and a positive electrode potential portion spaced apart from the second potential transmission portion are provided on the second circuit layer; the first potential transmission portion and the positive electrode potential portion are arranged opposite to each other along the stacking direction, and the second potential transmission portion and the negative electrode potential portion are arranged opposite to each other along the stacking direction;

[0037] stacking a negative power supply layer on a side of the first circuit layer away from the first surface;

[0038] stacking a portion of the thickness of the metal weight layer along the stacking direction on a side of the weight insulation layer away from the second surface;

[0039] stacking a top layer on a side of the negative power supply layer facing away from the first surface;

[0040] Another portion of the thickness of the metal weight layer along the stacking direction is stacked on a side of the portion of the thickness away from the second surface.

[0041] The packaging substrate provided by the present application has the following beneficial effects:

[0042] The packaging substrate provided in the present application provides and adds a negative power electrode layer during the manufacturing process, and the negative power electrode layer is stacked on the side of the first potential transmission part and the negative potential part away from the first surface. Along the stacking direction of the packaging substrate, the stacking of the positive potential part and the first potential transmission part as well as the first potential transmission part and the negative power electrode layer is achieved, thereby meeting the design requirements of low parasitic loop inductance.

[0043] For example, through the manufacturing method of the packaging substrate provided by the present application, a negative power layer is added on the basis of the existing 6-layer board structure, so that the manufacturing of odd layers can be realized. Compared with 8 layers, the manufacturing requirements of the packaging substrate for heat dissipation can be reduced, thereby reducing the manufacturing cost compared with 8 layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0045] Figure 1 It is a schematic diagram of a plate structure with 6 metal layers;

[0046] Figure 2 A packaging substrate with 7 metal layers provided in one embodiment of the present application;

[0047] Figure 3 A flowchart of a method for manufacturing a packaging substrate provided in one embodiment of the present application;

[0048] Figure 4 A flowchart of a method for manufacturing a packaging substrate provided in another embodiment of the present application;

[0049] Figure 5A flowchart of a method for manufacturing a packaging substrate provided in yet another embodiment of the present application;

[0050] Figure 6 A flowchart of a method for manufacturing a packaging substrate provided in yet another embodiment of the present application.

[0051] Among them, the reference numerals in the figure are:

[0052] 100, top layer; 201, negative potential part; 202, negative power supply layer; 300, metal hole; 301, first potential transmission part; 302, second potential transmission part; 400, positive potential part; 500, transmission layer group; 501, first signal transmission layer; 502, second signal transmission layer; 600, power chip; 700, counterweight insulation layer; 800, metal counterweight layer. DETAILED DESCRIPTION

[0053] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0054] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0055] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0056] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0057] The packaging substrate and its manufacturing method, the electric drive system and the vehicle provided in the embodiments of the present application are now described.

[0058] See also Figure 2 The packaging substrate provided in the embodiment of the present application includes a transmission layer group 500 and a power chip 600 embedded in the transmission layer group 500 , as well as a first circuit layer, a second circuit layer, a top layer 100 and a negative power layer 202 .

[0059] The transmission layer group 500 has a first surface and a second surface which are arranged in opposite directions along the stacking direction of the packaging substrate, the first circuit layer is stacked on the first surface, and the second circuit layer is stacked on the second surface; the first circuit layer is provided with a first potential transmission part 301 and a negative potential part 201 separated from the first potential transmission part 301, and the second circuit layer is provided with a second potential transmission part 302 and a positive potential part 400 separated from the second potential transmission part 302; the first potential transmission part 301 and the positive potential part 400 are arranged opposite to each other along the stacking direction, and the second potential transmission part 302 and the negative potential part 201 are arranged opposite to each other along the stacking direction.

[0060] Moreover, the negative power layer 202 is stacked on the side of the first circuit layer away from the first surface and connected to the negative potential portion 201 , and the top layer 100 is stacked on the negative power layer 202 .

[0061] Among them, the packaging substrate refers to a structure in which multiple layers are stacked in sequence along the stacking direction and a variety of different functional devices are integrated on its surface and inside. These layers include but are not limited to metal layers, protective layers, dielectric layers, insulating layers, etc. Multiple layers constitute the main part of the packaging substrate, which plays a supporting and conductive role, and each functional device is arranged on the surface or inside of multiple layers. The multiple layers and functions of each layer of the packaging substrate are well-known technologies for those in the field, and the embodiments of the present application do not make a detailed description of this. Among them, the power chip 600 is embedded in the transmission layer group 500, and the embedding method of the power chip 600 and the connection relationship between the different ends of the power chip 600 and each layer are well-known technologies for those in the field, and the embodiments of the present application do not make a detailed description of this. Generally, the packaging substrate can be a PCB (Printed Circuit Board), also known as a printed circuit board.

[0062] Generally, the power chip is embedded in the transmission layer group 500, and the first circuit layer and the second circuit layer refer to two metal layer structures located outside the transmission layer group 500. The first circuit layer and the second circuit layer have electrical and / or signal interconnection functions, and play the role of connecting the substrate to the external circuit. The thickness of the first circuit layer and the second circuit layer is customized according to different needs, and the material can be one of the metals or metal alloys such as copper, aluminum, copper-aluminum alloy, etc.

[0063] In an actual packaging substrate, insulating layers may be optionally provided between the layer structures inside the transmission layer group 500, between the transmission layer group 500 and the first circuit layer and the second circuit layer, and between the first circuit layer and the second circuit layer and the layer structures located outside thereof. These insulating layers and other metal layers are not described in detail in this embodiment.

[0064] Generally, the negative electrode layer 202, the negative electrode potential portion 201 and the positive electrode potential portion 400 of the power supply refer to interconnection functions with electricity and / or signals, and play the role of connecting the substrate to an external circuit. Among them, the thickness size of the negative electrode layer 202 of the power supply is specifically customized according to different needs, and the material of the negative electrode layer 202 of the power supply can be one of metals or metal alloys such as copper, aluminum, copper-aluminum alloy, etc. In some embodiments, the negative electrode layer 202 of the power supply can be a copper foil. Among them, the positive electrode potential portion 400 can be referred to as DC+, and the negative electrode layer of the power supply can also be referred to as DC-. The functions of the negative electrode layer 202, the negative electrode potential portion 201 and the positive electrode potential portion 400 in the package substrate and the stacking relationship with other layer structures, as well as the connection relationship with each functional device are well-known technologies for those skilled in the art, and the embodiments of the present application will not be described in detail.

[0065] Generally, the first potential transmission part 301 and the second potential transmission part 302 have the function of interconnecting electricity and / or signals, and the power chip 600 can be connected to electricity or input / output signals through the potential transmission part and / or the signal transmission layer. The first potential transmission part 301 and the second potential transmission part 302 can be called two electrodes of AC. The function of the potential transmission part and the stacking relationship with other layer structures, as well as the connection relationship with each functional device are well-known technologies in the art, and the embodiments of the present application do not make a detailed description of this.

[0066] Generally, the first potential transmission part 301 and the second potential transmission part 302 are connected through a metal hole 300. The metal hole 300 refers to a hole opened on the package substrate between the two first circuit layers and the second circuit layer, and metal is plated on the hole wall to electrically connect the first potential transmission part 301 and the second potential transmission part 302. The aperture and number of the metal hole 300 are specifically customized according to different needs. The material, function and connection relationship of the metal hole 300 with each layer structure are well-known technologies to those skilled in the art, and are not described in detail in the embodiments of the present application.

[0067] The packaging substrate provided in the embodiment of the present application is additionally provided with a negative power supply layer 202, and the negative power supply layer 202 is stacked on the side of the first potential transmission part 301 and the negative potential part 201 away from the first surface. Along the stacking direction of the packaging substrate, the stacking of the positive potential part 400 and the first potential transmission part 301 and the first potential transmission part 301 and the negative power supply layer 202 is realized, thereby meeting the design requirement of low parasitic loop inductance.

[0068] For example, compared with the existing Figure 1 Compared with the 6-layer board structure shown in the figure, a negative power layer 202 is added. The negative power layer 202 is stacked on the side of the first potential transmission part 301 and the negative potential part 201 away from the first surface. Along the stacking direction of the packaging substrate, the positive potential part 400 and the first potential transmission part 301 as well as the first potential transmission part 301 and the negative power layer 202 are stacked, thereby meeting the design requirement of low parasitic loop inductance.

[0069] For example, compared with the existing 8-layer board structure, the packaging substrate provided in the embodiment of the present application adds a negative power layer 202, so that an odd-numbered layer design can be achieved, which can reduce the design requirements for heat dissipation compared to 8 layers, thereby reducing the design cost compared to 8 layers.

[0070] It should be noted that the 6 layers and 8 layers of the existing plate structure mentioned in the embodiments of the present application refer to the number of metal layers of the plate structure, and the number of odd layers of the packaging substrate mentioned in the embodiments of the present application refers to the number of metal layers of the packaging substrate. For example, the packaging substrate provided in the embodiments of the present application may be a 7-layer metal layer. The packaging substrate mentioned in the embodiments of the present application does not only include metal layers, but may include layers of other materials, such as non-metallic insulating layers, such as dielectric layers or protective layers of other materials, and these layers can be arranged between any two adjacent layers of the multiple layers of the packaging substrate according to actual needs, or on any outer surface of the packaging substrate. The arrangement and function of these layers are selected according to needs, which is a well-known technology for those skilled in the art, and this application does not impose specific restrictions on this.

[0071] like Figure 2 As shown, the transmission layer group 500 may include two signal transmission layers, namely a first signal transmission layer 501 and a second signal transmission layer 502, and an insulating layer may be provided between the two signal transmission layers. Generally, the signal transmission layer refers to a layer structure located inside the first circuit layer and the second circuit layer, which has the function of interconnecting electricity and / or signals, and the number of layers and thickness of the signal transmission layer are specifically customized according to different requirements. The material, function and stacking relationship of the signal transmission layer with other layer structures, as well as the connection relationship with each functional device are well known to those skilled in the art, and the embodiments of the present application will not be described in detail.

[0072] It should be noted that the metal weight layer 800 and the weight insulation layer 700 mentioned in the embodiment of the present application can be provided for the purpose of weighting, but are not limited to providing weighting functions. For example, the metal weight layer 800 can be optionally connected to various functional devices or layer structures in the packaging substrate according to specific needs to play a role other than weighting. In an actual packaging substrate, a cooling channel can be provided on the side of the metal weight layer 800 facing away from the top layer 100 to provide cooling for the packaging substrate.

[0073] In some embodiments, the packaging substrate further includes a metal weight layer 800 and a weight insulation layer 700, the weight insulation layer 700 is stacked on the side of the second circuit layer away from the second surface, the metal weight layer 800 is stacked on the side of the weight insulation layer 700 away from the second surface, and the weight of the metal weight layer 800 is equal to the sum of the weights of the negative power layer 202 and the top layer 100.

[0074] As an example, Figure 2 As shown, along the stacking direction of the package substrate, the top layer 100, the negative power layer 202, the first potential transmission part 301, the first signal transmission layer 501, the second signal transmission layer 502, the positive potential part 400, and the metal weight layer 800 constitute an odd number of metal layers, which may be 7 layers. Figure 1 Compared with the 6-layer board structure shown in the figure, along the stacking direction of the package substrate, the substrate with 7 metal layers realizes the stacking of the positive potential part 400 and the first potential transmission part 301 and the first potential transmission part 301 and the power supply negative electrode layer 202, thereby meeting the design requirements of low parasitic loop inductance. Compared with the 8-layer board structure, the design requirements for heat dissipation can be reduced, thereby reducing the design cost compared with 8 layers.

[0075] As an example, for the substrate having 7 metal layers, considering that the manufacturing process of the 7-layer substrate may cause a large warp, a metal weight layer 800 is added and separated by the weight insulation layer 700. Since the weight insulation layer 700 has a negligible weight when the thickness is small, or it can be equal to the weight of the insulation layer between the negative power layer 202 and the first circuit layer, the weight of the metal weight layer 800 is equal to the sum of the weights of the negative power layer 202 and the top layer 100, so as to achieve a small warp without substantially changing the heat dissipation effect.

[0076] In some embodiments, the weight of the metal weight layer 800 is made equal to the sum of the weights of the negative power layer 202 and the top layer 100 by making the thickness of the metal weight layer 800 along the stacking direction equal to the sum of the thicknesses of the negative power layer 202 and the top layer 100 along the stacking direction.

[0077] In some embodiments, the packaging substrate further includes a metal weight layer 800 and a weight insulation layer 700; the weight insulation layer 700 is stacked on the side of the second circuit board away from the second surface, and the metal weight layer 800 is stacked on the side of the weight insulation layer 700 away from the second surface, and the sum of the weights of the metal weight layer 800 and the weight insulation layer 700 is equal to the sum of the weights of the negative power supply layer 202 and the top layer 100.

[0078] Specifically, the thickness of the metal weight layer 800 along the stacking direction is less than the sum of the thickness of the negative power layer 202 and the top layer 100 along the stacking direction, and the thickness of the weight insulation layer 700 along the stacking direction is greater than the sum of the thickness of the negative power layer 202 and the top layer 100 along the stacking direction. In this way, by making the thickness of the weight insulation layer 700 along the stacking direction much greater than the sum of the thickness of the negative power layer 202 and the top layer 100 along the stacking direction, for example, greater than twice the sum of the thickness of the negative power layer 202 and the top layer 100 along the stacking direction, a smaller warping is achieved without substantially changing the heat dissipation effect. In some embodiments, the metal weight layer 800, the negative power layer 202, and the top layer 100 are made of the same material, for example, all three can be made of copper.

[0079] In some embodiments, a power chip 600 is embedded in the transmission layer group 500 located between the positive potential portion 400 and the first potential transmission portion 301 along the stacking direction, and a power chip 600 is embedded in the transmission layer group 500 located between the second potential transmission portion 302 and the negative potential portion 201 along the stacking direction.

[0080] Another purpose of the embodiment of the present application is to provide an electric drive system, the electric drive system comprising the above packaging substrate. The beneficial effects of the electric drive system provided by the embodiment of the present application compared with the prior art are consistent with the beneficial effects of the packaging substrate provided by the embodiment of the present application compared with the prior art, and will not be repeated here.

[0081] Another object of the embodiments of the present application is to provide a vehicle, the vehicle includes the above packaging substrate; or the vehicle includes the above electric drive system. The beneficial effects of the vehicle provided by the embodiments of the present application compared with the prior art are consistent with the beneficial effects of the packaging substrate or the electric drive system provided by the embodiments of the present application compared with the prior art, and will not be repeated here.

[0082] like Figure 3 and Figure 4 As shown, another object of the embodiment of the present application is to provide a method for manufacturing a packaging substrate, the manufacturing method comprising:

[0083] 1001. Provide a first prefabricated layer group, including a transmission layer group 500 having a first surface and a second surface, a power chip 600 embedded in the transmission layer group 500, and a first circuit layer stacked on the first surface and a second circuit layer stacked on the second surface; wherein the first circuit layer is provided with a first potential transmission portion 301 and a negative electrode potential portion 201 spaced apart from the first potential transmission portion 301, and the second circuit layer is provided with a second potential transmission portion 302 and a positive electrode potential portion 400 spaced apart from the second potential transmission portion 302; the first potential transmission portion 301 and the positive electrode potential portion 400 are arranged opposite to each other along the stacking direction, and the second potential transmission portion 302 and the negative electrode potential portion 201 are arranged opposite to each other along the stacking direction;

[0084] 1002. Provide a second prefabricated layer group, including a negative power layer 202 and a top layer 100 stacked on the negative power layer 202, stack the second prefabricated layer group on the first prefabricated layer group, and stack the negative power layer 202 on the side of the first circuit layer away from the first surface.

[0085] In some embodiments, in the above-mentioned providing of the second prefabricated layer group, including the negative power electrode layer 202 and the top layer 100 stacked on the negative power electrode layer 202, the second prefabricated layer group is stacked on the first prefabricated layer group, and the negative power electrode layer 202 is stacked before or after the first potential transmission portion 301 and the negative electrode potential portion 201 are stacked away from the first surface, the manufacturing method further includes:

[0086] 1003. Provide a third prefabricated layer group, including a metal weight layer 800 and a weight insulation layer 700 stacked on the metal weight layer 800, stack the third prefabricated layer group on the first prefabricated layer group, and stack the weight insulation layer 700 on the side of the second circuit layer away from the second surface.

[0087] like Figure 3 and Figure 4 As shown, steps 1012 and 1013 can be performed simultaneously, or one can be performed first and the other can be performed later.

[0088] like Figure 5 As shown, another object of the embodiment of the present application is to provide a method for manufacturing a packaging substrate, the manufacturing method comprising:

[0089] 1011. Provide a prefabricated layer group, including a transmission layer group 500 having a first surface and a second surface, a power chip 600 embedded in the transmission layer group 500, and a first circuit layer stacked on the first surface, a second circuit layer stacked on the second surface, and a weighted insulating layer 700 stacked on the second circuit layer; wherein the first circuit layer is provided with a first potential transmission portion 301 and a negative electrode potential portion 201 spaced apart from the first potential transmission portion 301, and the second circuit layer is provided with a second potential transmission portion 302 and a positive electrode potential portion 400 spaced apart from the second potential transmission portion 302; the first potential transmission portion 301 and the positive electrode potential portion 400 are arranged opposite to each other along the stacking direction, and the second potential transmission portion 302 and the negative electrode potential portion 201 are arranged opposite to each other along the stacking direction;

[0090] 1012. Stack the negative power layer 202 on a side of the first circuit layer away from the first surface;

[0091] 1013. Stacking the metal weight layer 800 on the side of the weight insulation layer 700 facing away from the second surface;

[0092] 1014. Stack the top layer 100 on the side of the negative power layer 202 facing away from the first surface.

[0093] like Figure 6 As shown, another object of the embodiment of the present application is to provide a method for manufacturing a packaging substrate, the manufacturing method comprising:

[0094] 1111. Provide a prefabricated layer group, including a transmission layer group 500 having a first surface and a second surface, a power chip 600 embedded in the transmission layer group 500, and a first circuit layer stacked on the first surface, a second circuit layer stacked on the second surface, and a weighted insulating layer 700 stacked on the second circuit layer; wherein the first circuit layer is provided with a first potential transmission portion 301 and a negative electrode potential portion 201 spaced apart from the first potential transmission portion 301, and the second circuit layer is provided with a second potential transmission portion 302 and a positive electrode potential portion 400 spaced apart from the second potential transmission portion 302; the first potential transmission portion 301 and the positive electrode potential portion 400 are arranged opposite to each other along the stacking direction, and the second potential transmission portion 302 and the negative electrode potential portion 201 are arranged opposite to each other along the stacking direction;

[0095] 1112. Stack the negative power layer 202 on a side of the first circuit layer away from the first surface;

[0096] 1113. Stack a portion of the thickness of the metal weight layer 800 along the stacking direction on a side of the weight insulation layer 700 away from the second surface;

[0097] 1114. Stack the top layer 100 on the side of the negative power layer 202 facing away from the first surface;

[0098] 1115. Stack another portion of the thickness of the metal weight layer 800 along the stacking direction on a side of the portion of the thickness facing away from the second surface.

[0099] The packaging substrate provided in the embodiment of the present application provides and adds a negative power electrode layer 202 during the manufacturing process, and the negative power electrode layer 202 is stacked on the side of the first potential transmission part 301 and the negative potential part 201 away from the first surface. Along the stacking direction of the packaging substrate, the positive potential part 400 and the first potential transmission part 301 and the first potential transmission part 301 and the negative power electrode layer 202 are stacked, thereby meeting the design requirements of low parasitic loop inductance.

[0100] For example, through the manufacturing method of the packaging substrate provided in the embodiment of the present application, a negative power supply layer 202 is added on the basis of the existing 6-layer board structure, so that the manufacturing of odd layers can be realized. Compared with 8 layers, the manufacturing requirements of the packaging substrate for heat dissipation can be reduced, thereby reducing the manufacturing cost compared with 8 layers.

[0101] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A packaging substrate, characterized in that: It comprises a transmission layer group (500), a power chip (600) embedded in the transmission layer group (500), a first circuit layer, a second circuit layer, a top layer (100) and a power supply negative electrode layer (202); The transmission layer group (500) comprises a first surface and a second surface which are arranged in opposition to each other along the stacking direction of the packaging substrate, the first circuit layer is stacked on the first surface, and the second circuit layer is stacked on the second surface; the first circuit layer is provided with a first potential transmission portion (301) and a negative potential portion (201) spaced apart from the first potential transmission portion (301), and the second circuit layer is provided with a second potential transmission portion (302) and a positive potential portion (400) spaced apart from the second potential transmission portion (302); the first potential transmission portion (301) and the positive potential portion (400) are arranged opposite to each other along the stacking direction, and the second potential transmission portion (302) and the negative potential portion (201) are arranged opposite to each other along the stacking direction; Furthermore, the power supply negative electrode layer (202) is stacked on the side of the first circuit layer away from the first surface and connected to the negative electrode potential portion (201), and the top layer (100) is stacked on the power supply negative electrode layer (202).

2. The packaging substrate according to claim 1, wherein: The packaging substrate further comprises a metal weight layer (800) and a weight insulation layer (700); The counterweight insulating layer (700) is stacked on the side of the second circuit layer away from the second surface, the metal counterweight layer (800) is stacked on the side of the counterweight insulating layer (700) away from the second surface, and the weight of the metal counterweight layer (800) is equal to the sum of the weights of the negative power supply layer (202) and the top layer (100).

3. The packaging substrate according to claim 2, wherein: The thickness of the metal weight layer (800) along the stacking direction is equal to the sum of the thicknesses of the negative power supply layer (202) and the top layer (100) along the stacking direction.

4. The packaging substrate according to claim 1, wherein: The packaging substrate further comprises a metal weight layer (800) and a weight insulation layer (700); The counterweight insulating layer (700) is stacked on a side of the second circuit layer away from the second surface, the metal counterweight layer (800) is stacked on a side of the counterweight insulating layer (700) away from the second surface, and the sum of the weights of the metal counterweight layer (800) and the counterweight insulating layer (700) is equal to the sum of the weights of the negative power supply layer (202) and the top layer (100).

5. The packaging substrate according to claim 4, wherein: The thickness dimension of the metal counterweight layer (800) along the stacking direction is smaller than the sum of the thickness dimensions of the negative power supply layer (202) and the top layer (100) along the stacking direction, and the thickness dimension of the counterweight insulation layer (700) along the stacking direction is larger than the sum of the thickness dimensions of the negative power supply layer (202) and the top layer (100) along the stacking direction.

6. The packaging substrate according to any one of claims 2 to 5, characterized in that: The metal weight layer (800), the power supply negative electrode layer (202), and the top layer (100) are made of the same material.

7. The packaging substrate according to any one of claims 1 to 5, characterized in that: The power chip (600) is embedded in the transmission layer group (500) located between the positive potential part (400) and the first potential transmission part (301) along the stacking direction, and the power chip (600) is embedded in the transmission layer group (500) located between the second potential transmission part (302) and the negative potential part (201) along the stacking direction.

8. An electric drive system, characterized in that: The electric drive system comprises a packaging substrate as claimed in any one of claims 1 to 7.

9. A vehicle, characterized in that: The vehicle comprises a packaging substrate as claimed in any one of claims 1 to 7; Or, the vehicle includes the electric drive system as claimed in claim 8.

10. A method for manufacturing a packaging substrate, characterized in that: The production method comprises: A first prefabricated layer group is provided, comprising a transmission layer group (500) having a first surface and a second surface, a power chip (600) embedded in the transmission layer group (500), and a first circuit layer stacked on the first surface and a second circuit layer stacked on the second surface; wherein the first circuit layer is provided with a first potential transmission portion (301) and a negative potential portion (201) spaced apart from the first potential transmission portion (301), and the second circuit layer is provided with a second potential transmission portion (302) and a positive potential portion (400) spaced apart from the second potential transmission portion (302); the first potential transmission portion (301) and the positive potential portion (400) are arranged relative to each other along the stacking direction, and the second potential transmission portion (302) and the negative potential portion (201) are arranged relative to each other along the stacking direction; A second prefabricated layer group is provided, comprising a negative power layer (202) and a top layer (100) stacked on the negative power layer (202); the second prefabricated layer group is stacked on the first prefabricated layer group, and the negative power layer (202) is stacked on a side of the first circuit layer away from the first surface.

11. The method for manufacturing a packaging substrate according to claim 10, wherein: Before or after laminating the second prefabricated layer group on the first prefabricated layer group, the manufacturing method further comprises: A third prefabricated layer group is provided, comprising a metal counterweight layer (800) and a counterweight insulation layer (700) stacked on the metal counterweight layer (800); the third prefabricated layer group is stacked on the first prefabricated layer group, and the counterweight insulation layer (700) is stacked on a side of the second circuit layer away from the second surface.

12. A method for manufacturing a packaging substrate, characterized in that: The production method comprises: A prefabricated layer group is provided, comprising a transmission layer group (500) having a first surface and a second surface, a power chip (600) embedded in the transmission layer group (500), and a first circuit layer stacked on the first surface, a second circuit layer stacked on the second surface, and a weighted insulating layer (700) stacked on the second circuit layer; wherein the first circuit layer is provided with a first potential transmission portion (301) and a negative potential portion (201) spaced apart from the first potential transmission portion (301), and the second circuit layer is provided with a second potential transmission portion (302) and a positive potential portion (400) spaced apart from the second potential transmission portion (302); the first potential transmission portion (301) and the positive potential portion (400) are arranged opposite to each other along the stacking direction, and the second potential transmission portion (302) and the negative potential portion (201) are arranged opposite to each other along the stacking direction; stacking a power supply negative electrode layer (202) on a side of the first circuit layer facing away from the first surface; laminating a metal weight layer (800) on a side of the weight insulation layer (700) facing away from the second surface; The top layer (100) is stacked on the side of the negative power supply layer (202) facing away from the first surface.

13. A method for manufacturing a packaging substrate, characterized in that: The production method comprises: A prefabricated layer group is provided, comprising a transmission layer group (500) having a first surface and a second surface, a power chip (600) embedded in the transmission layer group (500), and a first circuit layer stacked on the first surface, a second circuit layer stacked on the second surface, and a weighted insulating layer (700) stacked on the second circuit layer; wherein the first circuit layer is provided with a first potential transmission portion (301) and a negative potential portion (201) spaced apart from the first potential transmission portion (301), and the second circuit layer is provided with a second potential transmission portion (302) and a positive potential portion (400) spaced apart from the second potential transmission portion (302); the first potential transmission portion (301) and the positive potential portion (400) are arranged opposite to each other along the stacking direction, and the second potential transmission portion (302) and the negative potential portion (201) are arranged opposite to each other along the stacking direction; stacking a power supply negative electrode layer (202) on a side of the first circuit layer facing away from the first surface; laminating a portion of the thickness of the metal weight layer (800) along the lamination direction on a side of the weight insulation layer (700) facing away from the second surface; stacking a top layer (100) on a side of the negative power supply layer (202) facing away from the first surface; Another portion of the thickness of the metal weight layer (800) along the stacking direction is stacked on a side of the portion of the thickness away from the second surface.

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