Semiconductor package and packaging method

Abstract

The invention discloses a semiconductor package and a packaging method, and the semiconductor package comprises a first carrier plate which comprises a plurality of first assembly surfaces and a first surface where a signal switching port is exposed; the plurality of packaging structures are in one-to-one correspondence with the plurality of first assembling surfaces, are respectively welded on the plurality of first assembling surfaces of the first carrier plate and are respectively and electrically connected with the first carrier plate; the first support plate exposes a first end part, far away from the first surface, of at least one packaging structure; and the HBM structure is welded with one surface, facing the first support plate, of the first end part of the at least one packaging structure, and is electrically connected with the at least one packaging structure. According to the technical scheme, the integration level of the packaging structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing technology, and in particular to a semiconductor package and a packaging method. Background Art

[0002] Today's highly integrated packaging technology has achieved a compact layout of complex passive components, and the packaging process plays a key role in improving the performance and controlling the cost of passive components. Existing packaging technologies include ball grid array (BGA), chip scale package (CSP), wafer level package (WLP), three-dimensional package (3D Package) and system in package (SiP).

[0003] However, the existing packaging structure has the problem of low integration. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor package and a packaging method, which can improve the integration of the semiconductor package.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor package, including:

[0006] A first carrier board, comprising a first surface and a plurality of first assembly surfaces, wherein a signal exchange port is exposed on the first surface of the first carrier board;

[0007] A plurality of packaging structures corresponding to the plurality of first assembly surfaces of the first carrier board one by one, welded on the first assembly surface of the first carrier board, and electrically connected to the first carrier board; the first carrier board exposes a first end of at least one packaging structure away from the first surface;

[0008] The HBM structure is welded to a first end portion of the at least one packaging structure facing a surface of the first carrier board, and is electrically connected to the at least one packaging structure.

[0009] Optionally, the packaging structure includes any one of a chip packaging structure and a chip.

[0010] Optionally, the plurality of first assembly surfaces include a group of second surfaces and third surfaces that are disposed opposite to each other;

[0011] The packaging structure includes: a first packaging structure welded on the second surface of the first carrier and electrically connected to the first carrier; a second packaging structure welded on the third surface of the first carrier and electrically connected to the first carrier.

[0012] Optionally, the first carrier exposes a first end of the first packaging structure away from the first surface and a first end of the second packaging structure away from the first surface; the first carrier, the first end of the first packaging structure, and the first end of the second packaging structure form a reserved space;

[0013] The HBM structure is located in the reserved space, and is respectively welded to a side of the first end of the first packaging structure facing the first carrier board and a side of the first end of the second packaging structure facing the first carrier board, and is respectively electrically connected to the first packaging structure and the second packaging structure.

[0014] Optionally, the first packaging structure and the second packaging structure respectively include: a second carrier board including a second mounting surface; a first chip soldered to the second mounting surface of the second carrier board and electrically connected to the second carrier board; a first packaging molding layer located on the second carrier board and covering the first chip;

[0015] The HBM structure is respectively welded to a side of the second carrier of the first packaging structure exposed by the first carrier facing the first carrier and a side of the second carrier of the second packaging structure exposed by the first carrier facing the first carrier, and is respectively electrically connected to the second carrier of the first packaging structure and the second carrier of the second packaging structure.

[0016] Optionally, the first carrier exposes a first end portion of the first packaging structure away from the first surface;

[0017] The HBM structure is welded to a surface of the first end portion of the first packaging structure facing the first carrier board, and is electrically connected to the first packaging structure.

[0018] Optionally, the first packaging structure includes: a second carrier board including a second mounting surface; a first chip soldered to the second mounting surface of the second carrier board and electrically connected to the second carrier board; a packaging molding layer located on the second carrier board and covering the first chip;

[0019] The second packaging structure includes: a third carrier board including a third mounting surface; a second chip soldered to the third mounting surface of the third carrier board and electrically connected to the third carrier board; a second packaging molding layer located on the third carrier board and covering the second chip;

[0020] The HBM structure is welded to a surface of the second carrier of the first packaging structure exposed by the first carrier and facing the first carrier, and is electrically connected to the second carrier of the first packaging structure.

[0021] Optionally, the semiconductor package further includes: a first heat dissipation layer, located on a surface of the second carrier board where the second packaging structure and the HBM structure face away from the first packaging structure, and used for conducting heat generated by the second packaging structure and the HBM structure to the outside.

[0022] Optionally, the HBM structure includes a plurality of memory chips stacked in a longitudinal direction, and the plurality of memory chips are electrically connected to each other.

[0023] Optionally, the memory chip includes a DRAM chip.

[0024] Optionally, the semiconductor package further comprises: a first welding interconnection structure, located between the first packaging structure and the second surface of the first carrier, for welding the first packaging structure to the second surface of the first carrier and realizing electrical connection between the first packaging structure and the first carrier;

[0025] The second welding interconnection structure is located between the second packaging structure and the third surface of the first carrier board, and is used to weld the second packaging structure to the third surface of the first carrier board and realize electrical connection between the second packaging structure and the first carrier board.

[0026] Optionally, the first surface is a side surface of the first carrier board, the second surface is a back surface of the first carrier board, and the third surface is a front surface of the first carrier board.

[0027] Accordingly, an embodiment of the present invention further provides a packaging method, comprising:

[0028] Providing a first carrier board, comprising a first surface and a plurality of first assembly surfaces, wherein a signal exchange port is disposed on the first surface of the first carrier board;

[0029] Providing a plurality of packaging structures, wherein the plurality of packaging structures correspond one-to-one to the plurality of first assembly surfaces;

[0030] The plurality of package structures are respectively welded on the first assembly surface of the first carrier board, and the plurality of package structures are respectively electrically connected to the first carrier board; after the plurality of package structures are respectively welded on the first assembly surface of the first carrier board, and the plurality of package structures are electrically connected to the first carrier board, the first carrier board exposes a first end portion of at least one package structure away from the first surface;

[0031] Provide HBM structure;

[0032] The HBM structure is welded to a first end portion of the at least one packaging structure facing a surface of the first carrier, and electrical connection between the HBM structure and the at least one packaging structure is achieved.

[0033] Optionally, the packaging structure includes any one of a chip packaging structure and a chip.

[0034] Optionally, the first assembly surface includes a second surface and a third surface that are arranged opposite to each other;

[0035] The providing of a plurality of packaging structures comprises: providing a first packaging structure and a second packaging structure;

[0036] The step of welding the plurality of packaging structures respectively on the first assembly surface of the first carrier board and realizing electrical connection between the plurality of packaging structures and the first carrier board includes: welding the first packaging structure and the second packaging structure respectively on the second surface and the third surface of the first carrier board and realizing electrical connection between the first packaging structure and the second packaging structure and the first carrier board.

[0037] Optionally, after the plurality of package structures are respectively welded to the first assembly surface of the first carrier board and electrical connection between the plurality of package structures and the first carrier board is achieved, the first carrier board exposes a first end of the first package structure away from the first surface and a first end of the second package structure away from the first surface; the first carrier board and the first end of the first package structure and the first end of the second package structure form a reserved space;

[0038] The step of welding the HBM structure to the first end of the at least one packaging structure toward one side of the first carrier board and realizing electrical connection between the HBM structure and the at least one packaging structure includes: welding the HBM structure to the first end of the first packaging structure toward one side of the first carrier board and the first end of the second packaging structure toward one side of the first carrier board, respectively, and realizing electrical connection between the HBM structure and the first packaging structure and the second packaging structure, respectively.

[0039] Optionally, in the step of providing the first packaging structure and the second packaging structure, the first packaging structure and the second packaging structure respectively include: a second carrier board including a second assembly surface; a first chip soldered to the second assembly surface of the second carrier board and electrically connected to the second carrier board; a first packaging molding layer located on the second carrier board and covering the first chip;

[0040] The method of welding the HBM structure to a side of the first packaging structure with the first end facing the first carrier and a side of the second packaging structure with the first end facing the first carrier, and realizing electrical connection between the HBM structure and the first packaging structure and the second packaging structure, respectively, includes: welding the HBM structure to a side of the second carrier of the first packaging structure exposed by the first carrier facing the first carrier and a side of the second carrier of the second packaging structure exposed by the first carrier facing the first carrier, and realizing electrical connection between the HBM structure and the second carrier of the first packaging structure and the second carrier of the second packaging structure, respectively.

[0041] Optionally, after the first packaging structure and the second packaging structure are respectively welded to the second surface and the third surface of the first carrier, and electrical connections are respectively achieved between the first packaging structure and the second packaging structure and the first carrier, the first carrier exposes a first end of the first packaging structure away from the first surface;

[0042] The step of welding the HBM structure to a surface of the first carrier board on which the first end of the at least one packaging structure faces, and realizing electrical connection between the HBM structure and the at least one packaging structure, includes: welding the HBM structure to a surface of the first carrier board on which the first end of the first packaging structure faces, and realizing electrical connection between the HBM structure and the first packaging structure.

[0043] Optionally, in the step of providing the first packaging structure and the second packaging structure, the first packaging structure includes: a second carrier board including a second mounting surface; a first chip soldered on the second mounting surface of the second carrier board and electrically connected to the second carrier board; a packaging molding layer located on the second carrier board and covering the first chip; the second packaging structure includes: a third carrier board including a third mounting surface; a second chip soldered on the third mounting surface of the third carrier board and electrically connected to the third carrier board; a second packaging molding layer located on the third carrier board and covering the second chip;

[0044] The step of welding the HBM structure to a surface of the first end portion of the first packaging structure facing the first carrier board and realizing electrical connection between the HBM structure and the first packaging structure includes welding the HBM structure to a surface of the second carrier board of the first packaging structure exposed by the first carrier board and facing the first carrier board, and realizing electrical connection between the HBM structure and the second carrier board of the first packaging structure.

[0045] Optionally, the packaging method further includes: providing a first heat dissipation layer; and forming the first heat dissipation layer on a surface of a second carrier board facing away from the first packaging structure and the HBM structure.

[0046] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0047] An embodiment of the present invention provides a semiconductor package, comprising: a first carrier, comprising a first surface and a plurality of first assembly surfaces, a signal exchange port being arranged on the first surface of the first carrier; a packaging structure, corresponding one-to-one to the plurality of first assembly surfaces of the first carrier, welded on the first assembly surface of the first carrier, and electrically connected to the first carrier; the first carrier exposing a first end of at least one packaging structure away from the first surface; an HBM structure, welded to a side of the first end of the at least one packaging structure facing the first carrier, and electrically connected to the at least one packaging structure.

[0048] In the semiconductor package provided by an embodiment of the present invention, the first carrier includes multiple first assembly surfaces, each of which is welded with a corresponding packaging structure. Compared with the existing method of welding the packaging structure only on one side of the first carrier, the integration of the semiconductor package can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a structural schematic diagram of an embodiment of a semiconductor package provided by the technical solution of the present invention;

[0050] Figure 2 It is a structural schematic diagram of another embodiment of a semiconductor package provided by the technical solution of the present invention;

[0051] Figure 3 It is a structural schematic diagram of another embodiment of a semiconductor package provided by the technical solution of the present invention;

[0052] Figures 4 to 8 It is a schematic diagram of an intermediate structure formed by each step in an embodiment of a packaging method provided by the technical solution of the present invention;

[0053] Figures 9 to 11 This is a schematic diagram of the intermediate structure formed by each step in another embodiment of the packaging method provided by the technical solution of the present invention

[0054] Figure 12 to Figure 13 It is a schematic diagram of an intermediate structure formed by each step in another embodiment of the packaging method provided by the technical solution of the present invention. DETAILED DESCRIPTION

[0055] As can be seen from the background technology, the existing packaging structure has the problem of high cost.

[0056] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor package, including: a first carrier, including a first surface and a plurality of first assembly surfaces, a signal exchange port being exposed on the first surface of the first carrier; a packaging structure, corresponding one-to-one to the plurality of first assembly surfaces of the first carrier, welded on the first assembly surface of the first carrier, and electrically connected to the first carrier; the first carrier exposes a first end of at least one packaging structure away from the first surface; an HBM structure, welded to a side of the first end of the at least one packaging structure facing the first carrier, and electrically connected to the at least one packaging structure.

[0057] In the semiconductor package provided by an embodiment of the present invention, the first carrier includes multiple first assembly surfaces, each of which is welded with a corresponding packaging structure. Compared with the existing method of welding the packaging structure only on one side of the first carrier, the integration of the semiconductor package can be improved.

[0058] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0059] Figure 1 1 is a schematic diagram of the structure of a semiconductor package according to an embodiment of the present invention. Figure 1 A semiconductor package includes: a first carrier 100 including a first surface 102 and a first assembly surface 101 <1> , 101 <2> The first surface 102 of the first carrier 100 is provided with a signal exchange port 1021; the first packaging structure 200 <1> , welded to the first mounting surface 101 of the first carrier board 100 <1> and electrically connected to the first carrier 100, the first carrier 100 exposing the first packaging structure 200 <1> A first end portion (not labeled) away from the first surface 102; a second packaging structure 200 <2> , welded to the first mounting surface 101 of the first carrier board 100 <2> The HBM structure 400 and the first carrier 100 expose the first packaging structure 200. <1> and a second packaging structure 200 <2> At least one first end away from the first surface 102 is welded to a surface of the first carrier 100 and is electrically connected to the at least one packaging structure.

[0060] The first carrier board 100 is used to realize the first packaging structure 200 <1> and a second packaging structure 200 <2> The first substrate 100 and the first packaging structure 200 are welded together. <1> and a second packaging structure 200 <2> Packaging integration and electrical integration between them.

[0061] Specifically, the first carrier 100 has a conductive circuit therein, and the conductive circuit is used for the first packaging structure 200 <1> and a second packaging structure 200 <2> Providing power or exchanging signals, thereby realizing the first packaging structure 200 <1> and a second packaging structure 200 <2> At the same time, the first packaging structure 200 <1> and a second packaging structure 200 <2> Being integrated on the first carrier board 100 is beneficial to improving the integration of semiconductor packaging.

[0062] In this embodiment, the first carrier 100 includes a first dielectric layer 110 and a first wiring layer 120 located in the first dielectric layer 110 .

[0063] The first dielectric layer 110 is used to achieve electrical isolation between the first wiring layers 120 , thereby reducing the risk of electrical leakage between adjacent first wiring layers 120 .

[0064] As an example, the material of the first dielectric layer 110 includes one or more of silicon oxide, silicon nitride, silicon oxynitride and polyimide.

[0065] The first wiring layer 120 is used to connect to the first packaging structure 200. <1> and a second packaging structure 200 <2> The first packaging structure 200 can be electrically connected to the first wiring layer 120. <1> and a second packaging structure 200 <2> Redistributing the input ports and output ports on the device helps to improve the flexibility of electrical signal connection, and is beneficial to reducing the path length of electrical signal transmission and reducing the transmission delay of electrical signals.

[0066] As an example, the material of the first wiring layer 120 is copper. In other embodiments, the material of the wiring layer can also be at least one of aluminum and silver.

[0067] In this embodiment, a first interconnection via structure 115 is disposed in the first dielectric layer 110 between adjacent first wiring layers 120. The first interconnection via structure 115 enables electrical connection between adjacent first wiring layers 120.

[0068] As an example, the material of the first interconnection via structure 115 is copper. In other embodiments, the material of the first interconnection via structure can also be tungsten, cobalt, or a tungsten-cobalt alloy, etc. Those skilled in the art can set it according to actual needs, and it is not limited here.

[0069] In this embodiment, the first carrier board 100 includes a first assembly surface 101 <1> and 101 <2> Specifically, the first assembly surface 101 <1> and 101 <2> They are respectively the second surface and the third surface of the first carrier 100 . The second surface of the first carrier 100 is the back surface of the first carrier 100 , and the third surface of the first carrier 100 is the front surface of the first carrier 100 .

[0070] In this embodiment, the first mounting surface 101 of the first carrier board 100 <1> For implementing the first packaging structure 200 <1> The first mounting surface 101 of the first carrier board 100 is welded between <2> For implementing the second packaging structure 200 <2> Welding between.

[0071] In this embodiment, the first carrier 100 further includes a first surface 102. Specifically, the first surface 102 of the first carrier 100 is a side surface of the first carrier 100.

[0072] The first surface 102 of the first carrier 100 is used to realize signal exchange between the semiconductor package and the outside. Specifically, a signal exchange port 1021 is exposed on the first surface 102 of the first carrier 100, and the signal exchange port 1021 is used to realize signal exchange between the first carrier 100 and the outside, thereby realizing signal exchange between the semiconductor package and the outside. It can be understood that the signal exchange port 1021 can be set on the first surface 102 of the first carrier 100, and can also be set at the end of the first assembly surface of the first carrier 100 close to the first surface 102.

[0073] As an example, the first carrier 100 includes an organic substrate or a glass substrate having a circuit.

[0074] Please continue to refer to Figure 1 In this embodiment, the first packaging structure 200 <1> and the second packaging structure 200 <2> They respectively include: a second carrier 200 including a second assembly surface 201; a first chip 210 soldered on the second assembly surface 201 of the second carrier 200 and electrically connected to the second carrier 200; and a first packaging molding layer 220 located on the second carrier 200 and covering the first chip 210.

[0075] The second carrier board 200 is used to provide a process platform for packaging the first chip 210 .

[0076] In this embodiment, the second carrier 200 includes a second dielectric layer 201 ′ and a second wiring layer 202 ′ located in the second dielectric layer.

[0077] As an example, the material of the second dielectric layer 201 ′ includes one or more of silicon oxide, silicon nitride, silicon oxynitride and polyimide.

[0078] The second wiring layer 202' is used to electrically connect to the first chip 210. Through the second wiring layer 202', the input port and the output port on the first chip 210 can be reallocated, which helps to improve the flexibility of electrical signal connection, and is beneficial to reduce the path length of electrical signal transmission and reduce the transmission delay of electrical signals.

[0079] The second wiring layer 202' is also used to be electrically connected to the first carrier 100, so as to realize the first packaging structure 200 <1> and the second packaging structure 200 <2> The first carrier board 100 is electrically connected to the first carrier board 100 .

[0080] As an example, the second carrier 200 may be one of a silicon substrate, a re-distribution layer (RDL), a resin substrate, a printed circuit board (PCB), a ceramic substrate, a glass substrate or a flexible circuit board (FPC). As an example, the second carrier 200 may be a single-layer board or a multi-layer board.

[0081] The first chip 210 is used to achieve packaging integration and electrical integration with the second carrier board 200 to form a corresponding packaging structure to meet corresponding functional requirements.

[0082] Specifically, the first chip 210 may be manufactured using integrated circuit manufacturing technology. The first chip 210 generally includes devices such as NMOS devices and / or PMOS devices formed on a semiconductor substrate.

[0083] For example, the first chip 210 can be one or more of a system-on-chip (SoC), a memory chip, an application-specific integrated circuit (ASIC) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, and a field-programmable gate array (FPGA) chip.

[0084] According to actual needs, the number of the first chip 210 may be one or more. In the case where there are multiple first chips 210, the functions of the multiple first chips 210 are different.

[0085] Please continue to refer to Figure 1In this embodiment, the first chip 210 is soldered to the second assembly surface 201 of the second carrier 200. Specifically, the first packaging structure 200 <1> and the second packaging structure 200 <2> They also include: a fifth welding interconnection structure 230, located between the first chip 210 and the second carrier 200, used to weld the first chip 210 to the second assembly surface 201 of the second carrier 200, and to achieve electrical connection between the first chip 210 and the second carrier 200.

[0086] The fifth soldering interconnection structure 230 is used to electrically lead out the first chip 210, and is used to realize that the first chip 210 is disposed on the second wiring layer 202' at the top layer, thereby reducing the risk of the first chip 210 and the second wiring layer 202' being separated from each other. At the same time, the fifth soldering interconnection structure 230 is also used to realize the electrical connection between the first chip 210 and the second wiring layer 202', so that the first chip 210 can be electrically connected to the second carrier 200 through the fifth soldering interconnection structure 230.

[0087] In this embodiment, the fifth solder interconnect structure 230 is a bump.

[0088] Specifically, when forming the first packaging structure 200 <1> and the second packaging structure 200 <2> During the process, the fifth welding interconnection structure 230 is formed by adopting a bump process.

[0089] As an example, the material of the fifth solder interconnect structure 230 includes one or more of gold, lead tin, silver tin, gold tin and copper tin.

[0090] In other embodiments, the back side of the first chip can also be attached to the front side of the second carrier board, and can be electrically connected to the second carrier board through leads.

[0091] In this embodiment, the first packaging structure 200 <1> and the second packaging structure 200 <2> Each of them further includes: a first bottom filling layer 240 , which is located between the first chip 210 and the second carrier 200 and also fills the gaps between the fifth solder interconnect structures 230 .

[0092] The first bottom filling layer 240 can protect the first chip 210 from the influence of the external environment, can reduce the influence of the mismatch of the thermal expansion coefficient between the first chip 210 and the second carrier 200, can redistribute stress and strain, avoid the failure of the fifth welding interconnection structure 230, and help to improve the reliability of the welding between the first chip 210 and the second assembly surface 201 of the second carrier 200, thereby helping to improve the reliability of the obtained packaging structure.

[0093] As an example, the material of the first bottom filling layer 240 includes epoxy resin. In other embodiments, the material of the first bottom filling layer can also be made of other thermosetting materials, which can be selected by those skilled in the art according to actual needs, and is not limited here.

[0094] Please continue to refer to Figure 1 In this embodiment, the first packaging structure 200 <1> and the second packaging structure 200 <2> The system further includes: a second heat dissipation layer 250 formed on the first chip 210 and used for conducting heat generated during operation of the first chip 210 to the outside.

[0095] The second heat dissipation layer 250 is used to conduct heat generated during operation of the first chip 210 to the outside, which can prevent the first chip 210 from being damaged due to accumulation of heat generated during operation, thereby protecting the first chip 210 .

[0096] In this embodiment, the material of the second heat dissipation layer 250 is copper. Copper has excellent thermal conductivity and can quickly conduct the heat generated by the first chip 210 during operation to the outside, which is beneficial to improving the heat dissipation efficiency.

[0097] In other embodiments, the heat dissipation layer can also be made of a metal material or alloy material suitable for use as a heat sink, such as aluminum, gold, nickel, steel, or stainless steel.

[0098] Please continue to refer to Figure 1 In this embodiment, the first packaging structure 200 <1> and the second packaging structure 200 <2> Each of the first and second passive components 260 is further included, located on the second mounting surface 201 of the second carrier 200 exposed by the first chip 210 , and electrically connected to the second carrier 200 .

[0099] The first passive component 260 is a passive device. A passive device is a passive component that can display its characteristics without an external power supply, and mainly includes resistors, inductors, and capacitors, such as at least one of resistors, capacitors, inductors, converters, gradienters, matching networks, resonators, filters, mixers, and switches.

[0100] The first passive component 260 can be welded to the second assembly surface 201 of the second carrier board 200 through the bumps, and realize electrical connection with the second carrier board 200. In other embodiments, other feasible welding methods can also be adopted.

[0101] The first encapsulation molding layer 220 is used to seal the first chip 210 and the first passive component 260 therein, thereby sealing the first chip 210 and the first passive component 260 and reducing the probability of the first chip 210 and the first passive component 260 being damaged, contaminated or oxidized.

[0102] The first encapsulation molding layer 220 is made of a plastic encapsulation material. The plastic encapsulation material has a relatively high strength, which can correspondingly improve the strength of the first encapsulation molding layer 220 , thereby facilitating improving the strength of the encapsulation structure.

[0103] In this embodiment, the material of the first encapsulation molding layer 220 is epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost, so it is widely used as a packaging material for electronic devices and integrated circuits.

[0104] In other embodiments, the material of the first encapsulation molding layer can also be other suitable materials, such as thermosetting materials such as polyimide or silicone.

[0105] In this embodiment, the first encapsulation molding layer 220 exposes the top surface of the second heat dissipation layer 250 , so that the heat generated by the first chip 210 during operation can be quickly conducted to the outside, which is beneficial to improving the heat dissipation efficiency.

[0106] Please continue to refer to Figure 1 In this embodiment, the first packaging structure 200 <1> and the second packaging structure 200 <2> Each of the first and second passive components 270 is further included, located above the first chip 210 and electrically connected to the second carrier 200 .

[0107] The second passive component 270 is located above the first chip 210, that is, the second passive component 270 and the first chip 210 are stacked in the longitudinal direction. Compared with the situation where the first chip 210 and the second passive component 270 are laid out in a horizontal direction, the area of ​​the second carrier board 200 occupied by the second passive component 270 can be reduced, and the volume of the packaging structure can be reduced, which is helpful to improve the integration of the packaging structure and reduce the cost of the packaging structure.

[0108] In this embodiment, when a second heat dissipation layer 250 is attached to the first chip 210 and the first packaging molding layer 220 exposes the top surface of the second heat dissipation layer 250 , the second passive component 270 is located above the first packaging molding layer 220 and the second heat dissipation layer 250 .

[0109] As an example, the second passive element 270 is an inductor. In other embodiments, the second passive element can also be at least one of a capacitor, a resistor, a converter, a gradienter, a matching network, a resonator, a filter, a mixer, a switch, and the like.

[0110] Please continue to refer to Figure 1 In this embodiment, the first packaging structure 200 <1> and the second packaging structure 200 <2> They also include: a conductive column 280 located on the second carrier 200 where the first chip 210 is exposed, and used to achieve electrical connection between the second passive component 270 and the second carrier 200.

[0111] Specifically, one end of the conductive pillar 280 is electrically connected to the second carrier 200 , and the other end of the conductive pillar 280 is electrically connected to the second passive component 270 , thereby achieving electrical connection between the second passive component 270 and the second carrier 200 .

[0112] In this embodiment, the conductive pillar 280 is made of copper. In other embodiments, the conductive pillar may be made of metal materials such as aluminum, tin, and silver.

[0113] In this embodiment, there are a plurality of conductive pillars 280 , and the plurality of conductive pillars 280 are arranged at intervals from each other.

[0114] In this embodiment, the first encapsulation molding layer 220 also covers the sidewalls of the conductive pillars 280 , thereby reducing the probability of the conductive pillars 280 being damaged, contaminated or oxidized.

[0115] Please continue to refer to Figure 1 In this embodiment, the first packaging structure 200 <1> and the second packaging structure 200 <2> Each of them further includes: a first mounting layer 290 , located between the second passive component 270 and the first packaging molding layer 220 , and used for adhering the second passive component 270 to the first packaging molding layer 220 .

[0116] The first mounting layer 290 is used to adhere the second passive component 270 to the first packaging molding layer 220 , thereby further improving the fixing strength of the second passive component 270 .

[0117] In this embodiment, a second heat dissipation layer 250 is attached above the first chip 210, and the first packaging molding layer 220 exposes the top surface of the second heat dissipation layer 250, and the first mounting layer 290 is located between the second passive component 270, the second heat dissipation layer 250 and the first packaging molding layer 220.

[0118] In this embodiment, the material of the first mounting layer 290 includes one or both of a resin adhesive and a double-sided adhesive film.

[0119] The first packaging structure and the second packaging structure in the embodiment of the present invention are described above by taking the first packaging structure and the second packaging structure having the same structure as an example. It is understandable that the first packaging structure and the second packaging structure can also be different, which is not limited here.

[0120] The first packaging structure and the second packaging structure are described above by taking the first packaging structure and the second packaging structure as packaging structures respectively formed by ball grid array packaging process. In other embodiments, the first packaging structure and the second packaging structure can also be packaging structures formed by packaging processes such as chip size packaging, wafer level packaging, three-dimensional packaging and system packaging, which are not limited here.

[0121] In other embodiments, in addition to being chip packaging structures, at least one of the first packaging structure and the second packaging structure can also be a chip, and the chip packaging structure or the chip can be welded on the remaining side surfaces of the first carrier respectively to further improve the integration of the formed semiconductor package.

[0122] The high bandwidth memory (HBM) structure 300 is used to implement high-speed data transmission between a central processing unit (CPU) and a graphics processing unit (GPU).

[0123] In this embodiment, the HBM structure 500 includes a plurality of memory chips 510 stacked in sequence along the longitudinal direction.

[0124] As an example, the memory chip 510 is a dynamic random access memory (DRAM) chip. In other embodiments, the memory chip can also be other types of memory chips, which are not limited here.

[0125] In this embodiment, the HBM structure 500 further includes: a fifth welding interconnection structure 520 , located between adjacent memory chips 510 , and used to achieve welding and electrical connection between adjacent memory chips 510 .

[0126] In this embodiment, the fifth solder interconnection structure 520 is a solder ball. Accordingly, the fifth solder interconnection structure 520 is formed by a ball planting process.

[0127] In this embodiment, the material of the solder ball is tin. In other embodiments, the solder ball can also be made of other suitable metal materials or alloy materials, which are not limited here.

[0128] In other embodiments, the fifth solder interconnect structure can also be a micro-bump. Specifically, the micro-bump includes a first sub-micro-bump located on the assembly surface of the memory chip of the upper layer and a second sub-micro-bump located on the assembly surface of the memory chip of the lower layer.

[0129] In this embodiment, the HBM structure 500 further includes: a through-hole structure 530 , which at least partially penetrates the memory chip 510 in the longitudinal direction and is electrically connected to the fifth solder interconnection structure 520 .

[0130] The through-via structure 530 and the fifth soldering interconnection structure 520 are used together to realize the electrical connection between adjacent memory chips 510. Specifically, the through-via structure 530 in the memory chip 510 located in the upper layer and the through-via structure 530 in the memory chip 510 located in the lower layer are respectively electrically connected to the fifth soldering interconnection structure 520 located between the adjacent memory chips 510, thereby realizing the electrical connection between the adjacent memory chips 510.

[0131] In this embodiment, the material of the through-hole structure 530 is copper. In other embodiments, the through-hole structure can also be made of tungsten, cobalt, or tungsten-cobalt alloy.

[0132] Please continue to refer to Figure 1 The semiconductor package further comprises: a first solder interconnect structure 105 located in the first package structure 200 <1> and the second surface of the first carrier 100, for placing the first packaging structure 200 <1> Welded on the second surface of the first carrier 100 to achieve the first packaging structure 200 <1> Electrical connection with the first carrier board 100.

[0133] As an example, the first solder interconnect structure 105 is a solder ball or a bump. In other embodiments, other feasible connection methods may also be adopted, which are not limited here.

[0134] Accordingly, the first welding interconnection structure 105 is formed by adopting a ball planting process or a bump process.

[0135] Please continue to refer to Figure 1The semiconductor package further comprises: a second solder interconnect structure 205 located in the second package structure 200 <2> and the third surface of the first carrier 100, for placing the second packaging structure 200 <2> Welded on the third surface of the first carrier 100 to realize the second packaging structure 200 <2> Electrical connection with the first carrier board 100.

[0136] As an example, the second solder interconnect structure 205 is a solder ball or a bump. As an embodiment, the material of the solder ball includes tin. In other embodiments, other feasible ways of connection may also be adopted, which are not limited here.

[0137] Accordingly, the second welding interconnection structure 205 is formed by adopting a ball planting process or a bump process.

[0138] In this embodiment, the first carrier 100 exposes the first packaging structure 200 <1> A first end (not shown) away from the first surface and the second packaging structure 200 <2> A first end portion (not shown) away from the first surface, and the first carrier 100 and the first packaging structure 200 exposed by the first carrier 100 <1> The first end away from the first surface and the second packaging structure 200 exposed by the first carrier 100 <2> A first end portion away from the first surface forms a reserved space.

[0139] The HBM structure 500 is located in the reserved space and is spaced apart from the first package structure 200 exposed by the first carrier 100. <1> The first end away from the first surface is welded to one side of the first carrier 100 and is welded to the second packaging structure 200 exposed on the first carrier 100. <2> The first end away from the first surface is welded to one side of the first carrier 100 and is respectively connected to the first packaging structure 200 <1> and the second packaging structure 200 <2> Electrical connection.

[0140] Specifically, the HBM structure 500 and the first package structure 200 exposed by the first carrier 100 are respectively <1> The second carrier 200 faces one side of the first carrier 100 and the second package structure 200 exposed on the first carrier 100 <2> The second carrier 200 is welded to one side of the first carrier 100 and is respectively connected to the first packaging structure 200. <1> The second carrier 200 and the second packaging structure 200 <2> The second carrier 200 is electrically connected to realize the HBM structure 500 and the first packaging structure 200 <1> and the second packaging structure 200 <2> welding and electrical connections.

[0141] In this embodiment, the semiconductor package further includes: a third solder interconnect structure 505 located between the HBM structure 500 and the first package structure 200 <1> between the HBM structure 500 and the first packaging structure 200 <1> A fourth welding interconnect structure 505 ', located between the HBM structure 500 and the second packaging structure 200 <2> between the HBM structure 500 and the second packaging structure 200 <2> welding and electrical connections.

[0142] The third solder interconnect structure 505 is located between the HBM structure 500 and the first packaging structure 200. <1> The second carrier 200 is used to realize the HBM structure 500 and the first packaging structure 200. <1> The second carrier board 200 is welded and electrically connected to each other, thereby realizing the HBM structure 500 and the first packaging structure 200 <1> welding and electrical connections.

[0143] The fourth solder interconnect structure 505′ is located between the HBM structure 500 and the second packaging structure 200. <2> The second carrier 200 is used to realize the HBM structure 500 and the second packaging structure 200. <2> The second carrier board 200 is welded and electrically connected to each other, thereby realizing the HBM structure 500 and the second packaging structure 200 <2> welding and electrical connections.

[0144] In this embodiment, the third solder interconnection structure 505 and the fourth solder interconnection structure 505' are solder balls, respectively. Specifically, the material of the solder balls is tin.

[0145] Figure 2 FIG. 1 is a schematic diagram showing another embodiment of a semiconductor package provided by the technical solution of the present invention. The similarities between this embodiment and the above embodiment are not repeated here. Figure 2 The difference between this embodiment and the above-mentioned embodiment is that: the first carrier 100 only exposes the first packaging structure 200 <1> The first end portion is away from the first surface 102; accordingly, the HBM structure 500 is welded to the first packaging structure 200 <1> The first end of the first package structure 200 faces the first substrate 100 and is adjacent to the first package structure 200. <1> Electrical connection.

[0146] In this embodiment, the HBM structure 500 and the first package structure 200 exposed by the first carrier 100 <1> The second carrier 200 is welded to a surface facing the first carrier 100 and is connected to the first packaging structure 200. <1> The second carrier 200 is electrically connected to the first packaging structure 200. <1> Soldering and electrical connections between.

[0147] Please continue to refer to Figure 2 In this embodiment, the second packaging structure 200 <2> It includes: a third carrier board 300 including a third assembly surface 301; a second chip 310 soldered on the third assembly surface 301 of the third carrier board 300 and electrically connected to the third carrier board 300; and a second encapsulation molding layer 320 located on the third carrier board 300 and covering the second chip 310.

[0148] In this embodiment, the second packaging structure 200 <2> The device further includes: a third passive component 330 , which is located on the third carrier board 300 where the second chip 310 is exposed, and is electrically connected to the third carrier board 300 .

[0149] Regarding the second packaging structure 200 <2> For the third carrier board 300, the second chip 310, the second encapsulation molding layer 320 and the third passive component 330, please refer to the aforementioned descriptions of the second carrier board 200, the first chip 210, the first encapsulation molding layer 220 and the first passive component 260, which will not be repeated here.

[0150] It should be noted that the second chip 310 is different from the first chip 110 .

[0151] Figure 3 FIG. 1 is a schematic diagram showing another embodiment of a semiconductor package provided by the technical solution of the present invention. The similarities between this embodiment and the above embodiment are not repeated here. Figure 3 The difference between this embodiment and the above-mentioned embodiment is that: the semiconductor package further includes: a first heat dissipation layer 600, located in the second packaging structure 200 <2> The HBM structure 500 faces away from the first packaging structure 200. <1> The second carrier board 200 is used to place the second packaging structure 200 <2> The heat generated by the HBM structure 500 is conducted to the outside.

[0152] The first heat dissipation layer 600 is used to heat the second packaging structure 200 <2> The heat generated by the HBM structure 500 is conducted to the outside, thereby preventing the second packaging structure 200 <2> and the accumulation of heat generated by the HBM structure 500 during operation, thereby being able to heat the second packaging structure 200 <2> And the HBM structure plays a protective role.

[0153] In this embodiment, the material of the first heat dissipation layer 600 is copper. Copper has excellent thermal conductivity, which helps to <2> The heat generated by the HBM structure 500 during operation is quickly transferred to the outside, which is beneficial to improving the heat dissipation efficiency.

[0154] In this embodiment, the first heat dissipation layer 600 is attached to the second packaging structure 200 by welding. <2> The HBM structure 500 faces away from the first packaging structure 200. <1> on one surface of the second carrier board 200.

[0155] In other embodiments, other suitable methods may be used to form the first heat dissipation layer on a surface of the second carrier that is opposite to the first packaging structure and the HBM structure.

[0156] In this embodiment, the cross section of the first heat dissipation layer 600 is rectangular. In other embodiments, according to actual needs, the cross section of the heat sink can also adopt other suitable shapes to achieve close adhesion between the first heat dissipation layer and the second packaging structure and the side of the second carrier of the HBM structure facing away from the first packaging structure.

[0157] The thickness of the first heat dissipation layer 600 can be selected according to the requirements of welding performance and heat dissipation performance. As an example, the thickness of the first heat dissipation layer 600 is 200 μm to 250 μm. Of course, the thickness of the first heat dissipation layer 600 here is only an example. For different packaging structures, the first heat dissipation layer 600 of different thicknesses can be used, which is not limited here.

[0158] In this embodiment, the semiconductor package further includes: a second mounting layer 340 located between the first heat dissipation layer 600 and the HBM structure and the second chip 310 , and used for adhering the first heat dissipation layer 600 to the HBM structure 500 and the second chip 310 .

[0159] The second mounting layer 340 is used to adhere the first heat dissipation layer 600 to the HBM structure and the second chip 310 , thereby achieving fixed installation between the first heat dissipation layer 600 , the HBM structure 500 , and the second chip 310 .

[0160] In this embodiment, the material of the second mounting layer 340 includes one or both of a resin adhesive and a double-sided adhesive film.

[0161] Correspondingly, an embodiment of the present invention also provides a packaging method.

[0162] Figures 4 to 8 A schematic diagram of an intermediate structure formed by each step in an embodiment of a packaging method provided by the technical solution of the present invention is shown.

[0163] Please refer to Figure 4 , providing a first carrier board 100, including a first assembly surface 101 <1> , 101 <2> and a first surface 102 provided with a signal exchange port 1021 .

[0164] The first carrier 100 provides a process platform for forming the semiconductor package.

[0165] Specifically, the first carrier 100 is used to realize the first packaging structure 200 <1> (like Figure 5 as shown) and a second packaging structure 200 <2> (like Figure 5 As shown in FIG. 1 ), the first carrier 100 and the first packaging structure 200 are welded together. <1> and a second packaging structure 200 <2> Packaging integration and electrical integration between them.

[0166] In the step of providing the first carrier 100, the first carrier 100 has a conductive circuit therein, and the conductive circuit is used to form a first package structure 200. <1> and a second packaging structure 200 <2> Providing power or exchanging signals, thereby realizing the first packaging structure 200 <1> and a second packaging structure 200 <2> At the same time, the first packaging structure 200 <1> and a second packaging structure 200 <2> Being integrated on the first carrier board 100 is beneficial to improving the integration of semiconductor packaging.

[0167] In this embodiment, the first carrier 100 includes a first dielectric layer 110 and a first wiring layer 120 located in the first dielectric layer 110 .

[0168] The first dielectric layer 110 is used to achieve electrical isolation between the first wiring layers 120 , thereby reducing the risk of electrical leakage between adjacent first wiring layers 120 .

[0169] As an example, the material of the first dielectric layer 110 includes one or more of silicon oxide, silicon nitride, silicon oxynitride and polyimide.

[0170] The first wiring layer 120 is used to connect to the first packaging structure 200. <1> and a second packaging structure 200 <2> The first packaging structure 200 can be electrically connected through the first wiring layer 120. <1> and a second packaging structure 200 <2> The reallocation of the input ports and output ports on the MCU can improve the flexibility of the electrical signal connection, and is conducive to reducing the path length of the electrical signal transmission and reducing the transmission delay of the electrical signal.

[0171] As an example, the material of the first wiring layer 120 is copper. In other embodiments, the material of the wiring layer can also be at least one of aluminum and silver.

[0172] In this embodiment, a first interconnection via structure 115 is disposed in the first dielectric layer 110 between adjacent first wiring layers 120. The first interconnection via structure 115 enables electrical connection between adjacent first wiring layers 120.

[0173] As an example, the material of the first interconnection via structure 115 is copper. In other embodiments, the material of the first interconnection via structure can also be tungsten, cobalt, or tungsten-cobalt alloy, etc. Those skilled in the art can set it according to actual needs, which is not limited here.

[0174] In this embodiment, the first carrier board 100 includes a first assembly surface 101 <1> and 101 <2> Specifically, the first assembly surface 101 <1> and 101 <2> They are respectively the second surface and the third surface of the first carrier 100 . The second surface of the first carrier 100 is the back surface of the first carrier 100 , and the third surface of the first carrier 100 is the front surface of the first carrier 100 .

[0175] In this embodiment, the first mounting surface 101 of the first carrier board 100 <1> For implementing the first packaging structure 200 <1> The first mounting surface 101 of the first carrier board 100 is welded between <2> For implementing the second packaging structure 200 <2> Welding between.

[0176] In this embodiment, the first carrier 100 further includes a first surface 102. Specifically, the first surface 102 of the first carrier 100 is a side surface of the first carrier 100.

[0177] The first surface 102 of the first carrier 100 is used to realize signal exchange between the semiconductor package and the outside. Specifically, a signal exchange port 1021 is provided on the first surface 102 of the first carrier 100, and the signal exchange port 1021 is used to realize signal exchange between the first carrier 100 and the outside, thereby realizing signal exchange between the semiconductor package and the outside. As an example, the first carrier 100 includes an organic substrate or a glass substrate having a circuit.

[0178] Please refer to Figure 5 , providing a first mounting surface 101 <1> and 101 <2> One-to-one corresponding first packaging structure 200 <1> and a second packaging structure 200 <2> .

[0179] In this embodiment, the first carrier board 100 further includes a first assembly surface 101 <1> and 101 <2> Accordingly, when providing the first packaging structure 200 <1> and a second packaging structure 200 <2> In the step of providing the first packaging structure 200 <1> and the second packaging structure 200 <2> .

[0180] In this embodiment, the first packaging structure 200 is provided. <1> and the second packaging structure 200 <2> In the step, the first packaging structure 200 <1> and the second packaging structure 200 <2> They respectively include: a second carrier 200 including a second assembly surface 201; a first chip 210 soldered on the second assembly surface 201 of the second carrier 200 and electrically connected to the second carrier 200; and a first packaging molding layer 220 located on the second carrier 200 and covering the first chip 210.

[0181] The second carrier board 200 is used to provide a process platform for packaging the first chip 210 .

[0182] In this embodiment, the second carrier 200 includes a second dielectric layer 201 ′ and a second wiring layer 202 ′ located in the second dielectric layer 201 ′.

[0183] As an example, the material of the second dielectric layer 201 ′ includes one or more of silicon oxide, silicon nitride, silicon oxynitride and polyimide.

[0184] The second wiring layer 202' is used to electrically connect to the first chip 210. Through the second wiring layer 202', the input port and the output port on the first chip 210 can be reallocated, which helps to improve the flexibility of electrical signal connection, and is beneficial to reduce the path length of electrical signal transmission and reduce the transmission delay of electrical signals.

[0185] The second wiring layer 202' is also used to be electrically connected to the first carrier 100, so as to realize the first packaging structure 200 <1> and the second packaging structure 200 <2> The first carrier board 100 is electrically connected to the first carrier board 100 .

[0186] In this embodiment, a second interconnection via structure 215 is disposed in the second dielectric layer 201' between adjacent second wiring layers 202'. The second interconnection via structure 215 can realize electrical connection between adjacent second wiring layers 202'.

[0187] As an example, the material of the second interconnection via structure 215 is copper. In other embodiments, the material of the second interconnection via structure 215 can also be tungsten, cobalt, or a tungsten-cobalt alloy, etc. Those skilled in the art can set it according to actual needs, and it is not limited here.

[0188] As an example, the second carrier 200 may be one of a silicon substrate, a redistribution layer (RDL), a resin substrate, a printed circuit board (PCB), a ceramic substrate, a glass substrate or a flexible circuit board (FPC). As an example, the second carrier 200 may be a single-layer board or a multi-layer board.

[0189] The first chip 210 is used to achieve packaging integration and electrical integration with the second carrier board 200 to form a corresponding packaging structure to meet corresponding functional requirements.

[0190] Specifically, the first chip 210 may be manufactured using integrated circuit manufacturing technology. The first chip 210 generally includes devices such as NMOS devices and / or PMOS devices formed on a semiconductor substrate.

[0191] For example, the first chip 210 can be one or more of a system-on-chip (SoC), a memory chip, an application-specific integrated circuit (ASIC) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, and a field-programmable gate array (FPGA) chip.

[0192] According to actual needs, the number of the first chip 210 may be one or more. In the case where there are multiple first chips 210, the functions of the multiple first chips 210 are different.

[0193] In this embodiment, the first packaging structure 200 is provided. <1> and the second packaging structure 200 <2> In the step of soldering the first chip 210 to the second mounting surface 201 of the second carrier 200. <1> and the second packaging structure 200 <2> They also include: a fifth welding interconnection structure 230, located between the first chip 210 and the second carrier 200, used to weld the first chip 210 to the second assembly surface 201 of the second carrier 200, and to achieve electrical connection between the first chip 210 and the second carrier 200.

[0194] The fifth soldering interconnection structure 230 is used to electrically lead out the first chip 210, and is used to realize that the first chip 210 is disposed on the second wiring layer 202' at the top layer, thereby reducing the risk of the first chip 210 and the second wiring layer 202' being separated from each other. At the same time, the fifth soldering interconnection structure 230 is also used to realize the electrical connection between the first chip 210 and the second wiring layer 202', so that the first chip 210 can be electrically connected to the second carrier 200 through the fifth soldering interconnection structure 230.

[0195] In this embodiment, the fifth solder interconnect structure 230 is a bump.

[0196] Specifically, during the process of forming the first packaging structure and the second packaging structure, the fifth welding interconnection structure 230 is formed by using a bump process.

[0197] As an example, the material of the fifth solder interconnect structure 230 includes one or more of gold, lead tin, silver tin, gold tin and copper tin.

[0198] In other embodiments, in the steps of providing the packaging structure and the second packaging structure, the back surface of the first chip is attached to the front surface of the second carrier board, and is electrically connected to the second carrier board through leads.

[0199] In this embodiment, the first packaging structure 200 is provided. <1> and the second packaging structure 200 <2> In the step, the first packaging structure 200 <1> and the second packaging structure 200 <2> Each of them further includes: a first bottom filling layer 240 , which is located between the first chip 210 and the second carrier 200 and also fills the gaps between the fifth solder interconnect structures 230 .

[0200] The first bottom filling layer 240 can protect the first chip 210 from the influence of the external environment, can reduce the influence of the mismatch of the thermal expansion coefficient between the first chip 210 and the second carrier 200, can redistribute stress and strain, avoid the failure of the fifth welding interconnection structure 230, and help to improve the reliability of the welding between the first chip 210 and the second assembly surface 201 of the second carrier 200, thereby helping to improve the reliability of the obtained packaging structure.

[0201] As an example, the material of the first bottom filling layer 240 includes epoxy resin. In other embodiments, the material of the first bottom filling layer can also be made of other thermosetting materials, which can be selected by those skilled in the art according to actual needs and are not limited here.

[0202] As an example, an underfill process is used to form the first bottom filling layer 240. In other embodiments, other processes can also be used to form the first bottom filling layer, which is not limited here.

[0203] In this embodiment, the first packaging structure 200 is provided. <1> and the second packaging structure 200 <2> In the step, the first packaging structure 200 <1> and the second packaging structure 200 <2> The system further includes: a second heat dissipation layer 250 formed on the first chip 210 and used for conducting heat generated during operation of the first chip 210 to the outside.

[0204] The second heat dissipation layer 250 is used to conduct heat generated during the operation of the first chip 210 to the outside, so as to prevent the accumulation of heat generated during the operation of the first chip 210 from damaging the first chip 210 , thereby protecting the first chip 210 .

[0205] In this embodiment, the material of the second heat dissipation layer 250 is copper. Copper has excellent thermal conductivity and can quickly conduct the heat generated by the first chip 210 during operation to the outside, which is beneficial to improving the heat dissipation efficiency.

[0206] In other embodiments, the heat dissipation layer can also be made of a metal material or alloy material suitable for use as a heat sink, such as aluminum, gold, nickel, steel, or stainless steel.

[0207] In this embodiment, the first packaging structure 200 is provided. <1> and the second packaging structure 200 <2> In the step, the first packaging structure 200 <1> and the second packaging structure 200 <2> Each of the first and second passive components 260 is further included, located on the second mounting surface 201 of the second carrier 200 exposed by the first chip 210 , and electrically connected to the second carrier 200 .

[0208] The first passive component 260 is a passive device. A passive device is a passive component that can display its characteristics without an external power supply, and mainly includes resistors, inductors, and capacitors, such as at least one of resistors, capacitors, inductors, converters, gradienters, matching networks, resonators, filters, mixers, and switches.

[0209] The first passive component 260 can be welded to the second assembly surface 201 of the second carrier board 200 through the bumps, and realize electrical connection with the second carrier board 200. In other embodiments, other feasible welding methods can also be adopted.

[0210] The first encapsulation molding layer 220 is used to seal the first chip 210 and the first passive component 260 therein, thereby sealing the first chip 210 and the first passive component 260 and reducing the probability of the first chip 210 and the first passive component 260 being damaged, contaminated or oxidized.

[0211] The first encapsulation molding layer 220 is made of a plastic encapsulation material. The plastic encapsulation material has a relatively high strength, which can correspondingly improve the strength of the first encapsulation molding layer 220 , thereby facilitating improving the strength of the encapsulation structure.

[0212] In this embodiment, the material of the first encapsulation molding layer 220 is epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost, so it is widely used as a packaging material for electronic devices and integrated circuits.

[0213] In other embodiments, the material of the first encapsulation molding layer can also be other suitable materials, such as thermosetting materials such as polyimide or silicone.

[0214] In this embodiment, the first encapsulation molding layer 220 exposes the top surface of the second heat dissipation layer 250 , so that the heat generated by the first chip 210 during operation can be quickly conducted to the outside, which is beneficial to improving the heat dissipation efficiency.

[0215] In this embodiment, the first packaging structure 200 is provided. <1> and the second packaging structure 200 <2> In the step, the first packaging structure 200 <1> and the second packaging structure 200 <2> Each of the first and second passive components 270 is further included, located above the first chip 210 and electrically connected to the second carrier 200 .

[0216] The second passive component 270 is located above the first chip 210, that is, the second passive component 270 and the first chip 210 are stacked in the longitudinal direction. Compared with the situation where the first chip 210 and the second passive component 270 are laid out in a horizontal direction, the area of ​​the second carrier board 200 occupied by the second passive component 270 can be reduced, and the volume of the packaging structure can be reduced, which is helpful to improve the integration of the packaging structure and reduce the cost of the packaging structure.

[0217] In this embodiment, when a second heat dissipation layer 250 is attached to the first chip 210 and the first packaging molding layer 220 exposes the top surface of the second heat dissipation layer 250 , the second passive component 270 is located above the first packaging molding layer 220 and the second heat dissipation layer 250 .

[0218] As an example, the second passive element 270 is an inductor. In other embodiments, the second passive element can also be at least one of a capacitor, a resistor, a converter, a gradienter, a matching network, a resonator, a filter, a mixer, a switch, and the like.

[0219] In this embodiment, the first packaging structure 200 is provided. <1> and the second packaging structure 200 <2> In the step, the first packaging structure 200 <1> and the second packaging structure 200 <2> They also include: a conductive column 280 located on the second carrier 200 where the first chip 210 is exposed, and used to achieve electrical connection between the second passive component 270 and the second carrier 200.

[0220] Specifically, one end of the conductive pillar 280 is electrically connected to the second carrier 200 , and the other end of the conductive pillar 280 is electrically connected to the second passive component 270 , thereby achieving electrical connection between the second passive component 270 and the second carrier 200 .

[0221] In this embodiment, the conductive pillar 280 is made of copper. In other embodiments, the conductive pillar may be made of metal materials such as aluminum, tin, and silver.

[0222] In this embodiment, there are a plurality of conductive pillars 280 , and the plurality of conductive pillars 280 are arranged at intervals from each other.

[0223] In this embodiment, the first encapsulation molding layer 220 also covers the sidewalls of the conductive pillars 280 , thereby reducing the probability of the conductive pillars 280 being damaged, contaminated or oxidized.

[0224] In this embodiment, the first packaging structure 200 is provided. <1> and the second packaging structure 200 <2> In the step, the first packaging structure 200 <1> and the second packaging structure 200 <2> Each of them further includes: a first mounting layer 290 , located between the second passive component 270 and the first packaging molding layer 220 , and used for adhering the second passive component 270 to the first packaging molding layer 220 .

[0225] The first mounting layer 290 is used to adhere the second passive component 270 to the first packaging molding layer 220 , thereby further improving the fixing strength of the second passive component 270 .

[0226] In this embodiment, a second heat dissipation layer 250 is further disposed above the first chip 210 , and the first packaging molding layer 220 exposes the top surface of the second heat dissipation layer 250 , and the first mounting layer 290 is located between the second passive component 270 , the second heat dissipation layer 250 and the first packaging molding layer 220 .

[0227] In this embodiment, the material of the first mounting layer 290 includes one or both of a resin adhesive and a double-sided adhesive film.

[0228] The first packaging structure and the second packaging structure in the embodiment of the present invention are described above by taking the first packaging structure and the second packaging structure having the same structure as an example. It is understandable that the first packaging structure and the second packaging structure can also be different, which is not limited here.

[0229] The first packaging structure and the second packaging structure are described above by taking the first packaging structure and the second packaging structure as packaging structures respectively formed by ball grid array packaging process. In other embodiments, the first packaging structure and the second packaging structure can also be packaging structures formed by packaging processes such as chip size packaging, wafer level packaging, three-dimensional packaging and system packaging, which are not limited here.

[0230] In other embodiments, in addition to being chip packaging structures, at least one of the first packaging structure and the second packaging structure can also be a chip, and the remaining side surfaces of the first carrier can also be used to weld the chip packaging structure or the chip, respectively, to further improve the integration of the formed semiconductor package.

[0231] Please refer to Figure 6 , the first packaging structure 200 <1> The second packaging structure 200 is welded on the second surface of the first carrier 100. <2> are welded on the third surface of the first carrier 100, and the first packaging structure 200 is respectively realized <1> and a second packaging structure 200 <2> The first carrier board 100 is electrically connected to the first carrier board 100 .

[0232] In this embodiment, the first mounting surface 101 of the first carrier board 100 <1> and 101 <2> The first packaging structure 200 includes a second surface and a third surface of the first carrier 100, <1> and a second packaging structure 200 <2> A first packaging structure 200 is included <1> and a second packaging structure 200 <2> .

[0233] Accordingly, the first packaging structure 200 <1> and a second packaging structure 200 <2> are respectively welded to the first mounting surface 101 of the first carrier board 100 <1> and 101 <2> and realize the first packaging structure 200 <1> and a second packaging structure 200 <2> The step of electrically connecting the first substrate 100 includes: connecting the first packaging structure 200 <1> The second packaging structure 200 is welded on the second surface of the first carrier 100. <2> are welded on the third surface of the first carrier 100, and the first packaging structure 200 is respectively realized <1> and a second packaging structure 200 <2> The first carrier board 100 is electrically connected to the first carrier board 100 .

[0234] In this embodiment, the first packaging structure 200 <1> Welded on the second surface of the first carrier 100 to achieve the first packaging structure 200 <1> The step of electrically connecting the first substrate 100 includes: <1> A first welding interconnection structure 105 is disposed between the second carrier 200 and the first carrier 100; the first packaging structure 200 is connected to the first packaging structure 200 by the first welding interconnection structure 105. <1> Welded on the second surface of the first carrier 100 to achieve the first packaging structure 200 <1> The first carrier board 100 is electrically connected to the first carrier board 100 .

[0235] Among them, in the first packaging structure 200 <1> The step of providing a first soldering interconnection structure 105 between the second carrier 200 and the first carrier 100 includes: <1> The first soldering interconnection structure 105 is formed on a surface of the second carrier 200 facing the second surface of the first carrier 100, or the first soldering interconnection structure 105 is formed on the second surface of the first carrier 100, or the first packaging structure 200 is formed on the first packaging structure 200. <1> A first sub-welding interconnect structure is formed on one side of the second carrier 200 facing the second surface of the first carrier 100, and a second sub-welding interconnect structure is formed on the second surface of the first carrier 100. The first sub-welding interconnect structure and the second sub-welding interconnect structure constitute the first welding interconnect structure 105.

[0236] The second packaging structure 200 <2> Welded on the third surface of the first carrier 100 to realize the second packaging structure 200 <2> The step of electrically connecting the second packaging structure 200 to the first carrier 100 includes: <2> A second soldering interconnection structure 205 is provided between the second carrier 200 and the first carrier 100; the second packaging structure 200 is connected to the second packaging structure 200 by the second soldering interconnection structure 205; <2> The welding between the first carrier board 100 and the second packaging structure 200 is realized. <2> The first carrier board 100 is electrically connected to the first carrier board 100 .

[0237] Wherein, in the second packaging structure 200 <2> The step of providing a second soldering interconnection structure 205 between the second carrier 200 and the first carrier 100 includes: <2> The second soldering interconnection structure 205 is formed on a surface of the second carrier 200 facing the third surface of the first carrier 100, or the second soldering interconnection structure 205 is formed on the third surface of the first carrier 100, or the second packaging structure 200 is formed on the second packaging structure 200 <2> A third sub-welding interconnect structure is formed on a surface of the second carrier 200 facing the third surface of the first carrier 100, and the fourth sub-welding interconnect structure is formed on the third surface of the first carrier 100. The third sub-welding interconnect structure and the fourth sub-welding interconnect structure constitute the second welding interconnect structure 205.

[0238] In this embodiment, the first soldering interconnection structure 105 and the second soldering interconnection structure 205 are respectively bumps. Specifically, the material of the first soldering interconnection structure 105 and the second soldering interconnection structure 205 is tin.

[0239] As an example, the first soldering interconnection structure 105 and the second soldering interconnection structure 205 are respectively controllable collapse connections. The controllable collapse connection has excellent electrical and thermal properties, is also suitable for mass production, and is conducive to reducing the size and weight of the packaging structure.

[0240] In this embodiment, the first welding interconnection structure 105 and the second welding interconnection structure 205 are formed by using a bump process.

[0241] In this embodiment, the first packaging structure 200 <1> The second packaging structure 200 is welded on the second surface of the first carrier 100. <2> are welded on the third surface of the first carrier 100, and the first packaging structure 200 is respectively realized <1> and a second packaging structure 200 <2> After being electrically connected to the first carrier 100, the first carrier 100 exposes the first packaging structure 200 <1> A first end portion is away from the first surface 102 .

[0242] Please refer to Figure 7 , providing an HBM structure 500.

[0243] The high bandwidth memory (HBM) structure 500 is used to implement high-speed data transmission between a central processing unit (CPU) and a graphics processing unit (GPU).

[0244] In this embodiment, in the step of providing the HBM structure 500 , the HBM structure 500 includes a plurality of memory chips 510 stacked in sequence along a longitudinal direction.

[0245] As an example, the memory chip 510 is a dynamic random access memory (DRAM) chip. In other embodiments, the memory chip can also be other types of memory chips, which are not limited here.

[0246] In this embodiment, in the step of providing the HBM structure 500 , the HBM structure 500 further includes: a fifth welding interconnection structure 520 , located between adjacent memory chips 510 , for achieving welding and electrical connection between adjacent memory chips 510 .

[0247] In this embodiment, the fifth solder interconnection structure 520 is a solder ball. Accordingly, the fifth solder interconnection structure 520 is formed by a ball planting process.

[0248] In this embodiment, the material of the solder ball is tin. In other embodiments, the solder ball can also be made of other suitable metal materials or alloy materials, which are not limited here.

[0249] In other embodiments, the fifth solder interconnect structure can also be a micro-bump. Specifically, the adjacent memory chips include an upper memory chip and a lower memory chip, and correspondingly, the micro-bump includes a first sub-micro-bump located on the assembly surface of the upper memory chip and a second sub-micro-bump located on the assembly surface of the lower memory chip.

[0250] In this embodiment, in the step of providing the HBM structure 500 , the HBM structure 500 further includes: a through-hole structure 530 that penetrates at least a portion of the thickness of the memory chip 510 in the longitudinal direction and is electrically connected to the fifth solder interconnect structure 520 .

[0251] The through-via structure 530 and the fifth soldering interconnection structure 520 are used together to realize the electrical connection between adjacent memory chips 510. Specifically, the through-via structure 530 in the memory chip 510 located in the upper layer and the through-via structure 530 in the memory chip 510 located in the lower layer are respectively electrically connected to the fifth soldering interconnection structure 520 located between the adjacent memory chips 510, thereby realizing the electrical connection between the adjacent memory chips 510.

[0252] In this embodiment, the material of the through-hole structure 530 is copper. In other embodiments, the through-hole structure can also be made of tungsten, cobalt, or tungsten-cobalt alloy.

[0253] Please refer to Figure 8 , the HBM structure 500 is respectively connected to the first packaging structure 200 <1> The first end of the first package structure 200 faces one side of the first carrier 100 and the second package structure 200. <2> The first end of the first substrate 100 is welded to the first substrate 100, and the HBM structure 500 and the first packaging structure 200 are welded to each other. <1> and the second packaging structure 200 <2> The electrical connection between.

[0254] In this embodiment, the first packaging structure 200 <1> The second packaging structure 200 is welded on the second surface of the first carrier 100. <2> are welded on the third surface of the first carrier 100, and the first packaging structure 200 is respectively realized <1> and a second packaging structure 200 <2> After being electrically connected to the first carrier 100, the first carrier 100 exposes the first packaging structure 200 <1> A first end (not shown) away from the first surface and the second packaging structure 200 <2> A first end portion (not shown) away from the first surface, and the first carrier 100 and the first packaging structure 200 exposed by the first carrier 100 <1> The first end away from the first surface and the second packaging structure 200 exposed by the first carrier 100 <2> A first end portion away from the first surface forms a reserved space.

[0255] The HBM structure 500 is respectively connected to the first packaging structure 200 <1> The first end of the first package structure 200 faces one side of the first carrier 100 and the second package structure 200. <2> The first end of the first carrier plate 100 is welded to the first carrier plate 100, so that the HBM structure 500 is disposed in the reserved space.

[0256] In this embodiment, the HBM structure 500 is respectively connected to the first packaging structure 200 <1> The first end of the first package structure 200 faces one side of the first carrier 100 and the second package structure 200. <2> The first end of the first substrate 100 is welded to the first substrate 100, and the HBM structure 500 and the first packaging structure 200 are welded to each other. <1> and the second packaging structure 200 <2> The step of electrically connecting the HBM structure 500 to the first package structure 200 exposed by the first carrier 100 includes: connecting the HBM structure 500 to the first package structure 200 exposed by the first carrier 100 <1> The second carrier 200 faces one side of the first carrier 100 and the second package structure 200 exposed on the first carrier 100 <2> The second carrier 200 is welded to one side of the first carrier 100, and the HBM structure 500 and the first packaging structure 200 are respectively realized. <1> The second carrier 200 and the second packaging structure 200 <2> The electrical connection of the second carrier board 200 is shown in FIG.

[0257] In this embodiment, the first package structure 200 exposed by the HBM structure 500 or the first carrier 100 <1> A third soldering interconnection structure 505 is formed on a surface of the second carrier 200 facing the first carrier 100; the HBM structure 500 is connected to the first package structure 200 exposed by the first carrier 100 through the third soldering interconnection structure 505. <1> The second carrier 200 is welded to one side of the first carrier 100, and the HBM structure 500 is welded to the first package structure 200 exposed by the first carrier 100. <1> The electrical connection between the second carrier board 200 is provided.

[0258] In this embodiment, the second packaging structure 200 exposed by the HBM structure 500 or the first carrier 100 <2> A fourth soldering interconnection structure 505' is formed on a surface of the second carrier 200 facing the first carrier 100; the HBM structure 500 and the second package structure 200 exposed by the first carrier 100 are connected by the fourth soldering interconnection structure 505'. <2> The second carrier 200 is welded to one side of the first carrier 100, and the HBM structure 500 is welded to the second package structure 200 exposed by the first carrier 100. <2> The electrical connection between the second carrier board 200 is provided.

[0259] In this embodiment, the third solder interconnection structure 505 and the fourth solder interconnection structure 505' are solder balls. Specifically, the material of the bumps is tin.

[0260] Fig. 9 and Fig.11The schematic diagram of the intermediate structure formed by each step in another embodiment of the packaging method provided by the technical solution of the present invention is shown. The similarities between this embodiment and the previous embodiment are not repeated here. The difference between this embodiment and the previous embodiment is that:

[0261] Please refer to Fig. 9 , providing a first packaging structure 200 <1> and a second packaging structure 200 <2> In the step, the second packaging structure 200 <2> It includes: a third carrier board 300 including a third assembly surface 301; a second chip 310 soldered on the third assembly surface 301 of the third carrier board 300 and electrically connected to the third carrier board 300; and a second encapsulation molding layer 320 located on the third carrier board 300 and covering the second chip 310.

[0262] In this embodiment, the first packaging structure 200 is provided. <1> and a second packaging structure 200 <2> In the step, the second packaging structure 200 <2> The device further includes: a third passive component 330 , which is located on the third mounting surface 301 of the third carrier board 300 where the second chip is exposed, and is electrically connected to the third carrier board 300 .

[0263] Regarding the third carrier 300, the second chip 310, the second packaging mold layer 320 and the third passive component 330 in the second packaging structure, please refer to the aforementioned description of the second carrier 200, the first chip 210, the first packaging mold layer 220 and the first passive component 260, which will not be repeated here.

[0264] It should be noted that the second chip 310 is different from the first chip 110 .

[0265] Please refer to Fig.10 , the first packaging structure 200 <1> soldered on the second surface of the first carrier 100, and the second packaging structure 200 <2> Welded on the third surface of the first carrier 100 to achieve the first packaging structure 200 <1> and the second packaging structure 200 <2> Electrical connection with the first carrier board 100.

[0266] In this embodiment, the first packaging structure 200 <1> soldered on the second surface of the first carrier 100, and the second packaging structure 200 <2> Welded on the third surface of the first carrier 100 to achieve the first packaging structure 200 <1> and the second packaging structure 200 <2> After being electrically connected to the first carrier 100, the first carrier 100 exposes the first packaging structure 200 <1> The first end portion away from the first surface 101 is provided for subsequent connection of the HBM structure 500 with the first packaging structure 200. <1> The first ends away from the first surface 101 are welded to provide a space.

[0267] Please refer to Fig.11 After providing the HBM structure 500, the HBM structure 500 and the first packaging structure 200 <1> The first end portions away from the first surface 101 are welded together to realize the HBM structure 500 and the first packaging structure 200 <1> electrical connection.

[0268] In this embodiment, the HBM structure 500 and the first packaging structure 200 <1> The first end portions away from the first surface 101 are welded together to realize the HBM structure 500 and the first packaging structure 200 <1> The electrical connection refers to connecting the HBM structure 500 to the first package structure 200 exposed by the first carrier 100. <1> The first ends away from the first surface 101 are welded and electrically connected.

[0269] Specifically, the HBM structure 500 and the first package structure 200 exposed by the first carrier 100 are <1> The second carrier 200 is welded to a surface facing the first carrier 100 and is connected to the first packaging structure 200. <1> The second carrier 200 is electrically connected to the first packaging structure 200. <1> Soldering and electrical connections between.

[0270] Fig.12 and Fig.13 The schematic diagram of the intermediate structure formed by each step in another embodiment of the packaging method provided by the technical solution of the present invention is shown. The similarities between this embodiment and the previous embodiment are not repeated here. The difference between this embodiment and the previous embodiment is that:

[0271] Please refer to Fig.12 , providing a first heat dissipation layer 600.

[0272] The first heat dissipation layer 600 is used to heat the second packaging structure 200 <2> The heat generated by the HBM structure 500 is conducted to the outside, thereby preventing the second packaging structure 200 <2> and the accumulation of heat generated by the HBM structure 500 during operation, thereby being able to heat the second packaging structure 200 <2> And the HBM structure plays a protective role.

[0273] In this embodiment, the material of the first heat dissipation layer 600 is copper. Copper has excellent thermal conductivity, which helps to <2> The heat generated by the HBM structure 500 during operation is quickly transferred to the outside, which is beneficial to improving the heat dissipation efficiency.

[0274] In this embodiment, the cross section of the first heat dissipation layer 600 is rectangular. In other embodiments, according to actual needs, the cross section of the heat sink can also adopt other suitable shapes to achieve close adhesion between the first heat dissipation layer and the second packaging structure and the side of the second carrier of the HBM structure facing away from the first packaging structure.

[0275] The thickness of the first heat dissipation layer 600 can be selected according to the requirements of welding performance and heat dissipation performance. As an example, the thickness of the first heat dissipation layer 600 is 200 μm to 250 μm. Of course, the thickness of the first heat dissipation layer 600 here is only an example. For different packaging structures, the first heat dissipation layer 600 of different thicknesses can be used, which is not limited here.

[0276] Please refer to Fig.13 , the HBM structure 500 and the first packaging structure 200 <1> The first end portions away from the first surface 101 are welded together to realize the HBM structure 500 and the first packaging structure 200 <1> After the electrical connection is established, the first heat dissipation layer 600 is formed on the second packaging structure 200 <2> The HBM structure 500 faces away from the first packaging structure 200. <1> on one surface of the second carrier board 200.

[0277] In this embodiment, the first heat dissipation layer 600 is attached to the second packaging structure 200 by welding. <2> The HBM structure 500 faces away from the first packaging structure 200. <1> on one surface of the second carrier board 200.

[0278] In other embodiments, other suitable methods may be used to form the first heat dissipation layer on a surface of the second carrier that is opposite to the first packaging structure and the HBM structure.

[0279] The above-mentioned embodiments of the present invention are combinations of elements and features of the present invention. Unless otherwise mentioned, elements or features may be considered as optional. Each element or feature may be put into practice without being combined with other elements or features. In addition, embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some configurations of any one embodiment may be included in another embodiment, and may be replaced by the corresponding configuration of another embodiment. It is obvious to those skilled in the art that claims that do not have a clear reference relationship to each other in the attached claims may be combined into embodiments of the present invention, or may be included as new claims in the amendment after submitting this application.

[0280] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0281] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor package, characterized in that: include: A first carrier board including a plurality of first assembly surfaces and a first surface with a signal exchange port exposed; A plurality of packaging structures corresponding to the plurality of first assembly surfaces are respectively welded to the plurality of first assembly surfaces of the first carrier and are respectively electrically connected to the first carrier; the first carrier exposes a first end of at least one packaging structure away from the first surface; The HBM structure is welded to a surface of the first end portion of the at least one packaging structure facing the first carrier board, and is electrically connected to the at least one packaging structure.

2. The semiconductor package according to claim 1, wherein: The packaging structure includes any one of a chip packaging structure and a chip.

3. The semiconductor package according to claim 2, wherein: The plurality of first assembly surfaces include a set of second surfaces and third surfaces disposed opposite to each other; The packaging structure includes: a first packaging structure welded on the second surface of the first carrier and electrically connected to the first carrier; a second packaging structure welded on the third surface of the first carrier and electrically connected to the first carrier.

4. The semiconductor package according to claim 3, wherein: The first carrier exposes a first end of the first packaging structure away from the first surface and a first end of the second packaging structure away from the first surface; the first carrier, the first end of the first packaging structure and the first end of the second packaging structure form a reserved space; The HBM structure is located in the reserved space, and is respectively welded to a side of the first end of the first packaging structure facing the first carrier board and a side of the first end of the second packaging structure facing the first carrier board, and is respectively electrically connected to the first packaging structure and the second packaging structure.

5. The semiconductor package according to claim 4, wherein: The first packaging structure and the second packaging structure respectively include: a second carrier board including a second mounting surface; a first chip soldered on the second mounting surface of the second carrier board and electrically connected to the second carrier board; a first packaging molding layer located on the second carrier board and covering the first chip; The HBM structure is respectively welded to a side of the second carrier of the first packaging structure exposed by the first carrier facing the first carrier and a side of the second carrier of the second packaging structure exposed by the first carrier facing the first carrier, and is respectively electrically connected to the second carrier of the first packaging structure and the second carrier of the second packaging structure.

6. The semiconductor package according to claim 3, wherein: The first carrier exposes a first end portion of the first packaging structure away from the first surface; The HBM structure is welded to a surface of the first end portion of the first packaging structure facing the first carrier board, and is electrically connected to the first packaging structure.

7. The semiconductor package according to claim 6, wherein: The first packaging structure includes: a second carrier board including a second mounting surface; a first chip soldered to the second mounting surface of the second carrier board and electrically connected to the second carrier board; a packaging molding layer located on the second carrier board and covering the first chip; The second packaging structure includes: a third carrier board including a third mounting surface; a second chip soldered to the third mounting surface of the third carrier board and electrically connected to the third carrier board; a second packaging molding layer located on the third carrier board and covering the second chip; The HBM structure is welded to a surface of the second carrier of the first packaging structure exposed by the first carrier and facing the first carrier, and is electrically connected to the second carrier of the first packaging structure.

8. The semiconductor package according to claim 7, wherein: Also includes: The first heat dissipation layer is located on a surface of the second carrier board facing away from the first packaging structure and the HBM structure, and is used to conduct heat generated by the second packaging structure and the HBM structure to the outside.

9. The semiconductor package according to claim 1, wherein: The HBM structure includes a plurality of memory chips stacked in a longitudinal direction, and the plurality of memory chips are electrically connected to each other.

10. The semiconductor package according to claim 9, wherein: The memory chip includes a DRAM chip.

11. The semiconductor package according to claim 3, wherein: Also includes: a first welding interconnection structure, located between the first packaging structure and the second surface of the first carrier, and used for welding the first packaging structure to the second surface of the first carrier and realizing electrical connection between the first packaging structure and the first carrier; The second welding interconnection structure is located between the second packaging structure and the third surface of the first carrier board, and is used to weld the second packaging structure to the third surface of the first carrier board and realize electrical connection between the second packaging structure and the first carrier board.

12. The semiconductor package according to claim 3, wherein: The first surface is a side surface of the first carrier board, the second surface is a back surface of the first carrier board, and the third surface is a front surface of the first carrier board.

13. A packaging method, characterized in that: include: Providing a first carrier board, comprising a first surface and a plurality of first assembly surfaces, wherein a signal exchange port is exposed on the first surface of the first carrier board; Providing a plurality of packaging structures corresponding one-to-one to the plurality of first assembly surfaces; Welding the plurality of packaging structures to the first assembly surface of the first carrier board respectively, and achieving electrical connection between the plurality of packaging structures and the first carrier board respectively; After the plurality of package structures are respectively welded to the first assembly surface of the first carrier board and electrical connection between the plurality of package structures and the first carrier board is achieved, the first carrier board exposes a first end portion of at least one package structure away from the first surface; Provide HBM structure; The HBM structure is welded to a first end portion of the at least one packaging structure facing a surface of the first carrier, and electrical connection between the HBM structure and the at least one packaging structure is achieved.

14. The packaging method according to claim 13, characterized in that: The packaging structure includes any one of a chip packaging structure and a chip.

15. The packaging method according to claim 14, characterized in that: The plurality of first assembly surfaces include a set of second surfaces and third surfaces disposed opposite to each other; The providing of a plurality of packaging structures comprises: providing a first packaging structure and a second packaging structure; The step of welding the plurality of packaging structures respectively on the plurality of first assembly surfaces of the first carrier board and realizing electrical connection between the plurality of packaging structures and the first carrier board includes: welding the first packaging structure and the second packaging structure respectively on the second surface and the third surface of the first carrier board and realizing electrical connection between the first packaging structure and the second packaging structure and the first carrier board.

16. The packaging method according to claim 15, characterized in that: After the plurality of package structures are respectively welded to the plurality of first assembly surfaces of the first carrier board and electrical connection between the plurality of package structures and the first carrier board is achieved, the first carrier board exposes a first end of the first package structure away from the first surface and a first end of the second package structure away from the first surface; the first carrier board and the first end of the first package structure and the first end of the second package structure form a reserved space; The step of welding the HBM structure to the first end of the at least one packaging structure toward one side of the first carrier board and realizing electrical connection between the HBM structure and the at least one packaging structure includes: welding the HBM structure to the first end of the first packaging structure toward one side of the first carrier board and the first end of the second packaging structure toward one side of the first carrier board, respectively, and realizing electrical connection between the HBM structure and the first packaging structure and the second packaging structure, respectively.

17. The packaging method according to claim 16, characterized in that: In the step of providing a first package structure and a second package structure, the first package structure and the second package structure respectively include: a second carrier board including a second mounting surface; a first chip soldered on the second mounting surface of the second carrier board and electrically connected to the second carrier board; a first package molding layer located on the second carrier board and covering the first chip; The method of welding the HBM structure to a side of the first packaging structure with the first end facing the first carrier and a side of the second packaging structure with the first end facing the first carrier, and realizing electrical connection between the HBM structure and the first packaging structure and the second packaging structure, respectively, includes: welding the HBM structure to a side of the second carrier of the first packaging structure exposed by the first carrier facing the first carrier and a side of the second carrier of the second packaging structure exposed by the first carrier facing the first carrier, and realizing electrical connection between the HBM structure and the second carrier of the first packaging structure and the second carrier of the second packaging structure, respectively.

18. The packaging method according to claim 15, characterized in that: After the first packaging structure and the second packaging structure are respectively welded to the second surface and the third surface of the first carrier, and electrical connections are respectively achieved between the first packaging structure and the second packaging structure and the first carrier, the first carrier exposes a first end of the first packaging structure away from the first surface; The step of welding the HBM structure to a surface of the first carrier board on which the first end of the at least one packaging structure faces, and realizing electrical connection between the HBM structure and the at least one packaging structure, includes: welding the HBM structure to a surface of the first carrier board on which the first end of the first packaging structure faces, and realizing electrical connection between the HBM structure and the first packaging structure.

19. The packaging method according to claim 18, characterized in that: In the step of providing a first packaging structure and a second packaging structure, the first packaging structure includes: a second carrier board including a second mounting surface; a first chip welded on the second mounting surface of the second carrier board and electrically connected to the second carrier board; a first packaging molding layer located on the second carrier board and covering the first chip; the second packaging structure includes: a third carrier board including a third mounting surface; a second chip welded on the third mounting surface of the third carrier board and electrically connected to the third carrier board; a second packaging molding layer located on the third carrier board and covering the second chip; The step of welding the HBM structure to a surface of the first end portion of the first packaging structure facing the first carrier board and realizing electrical connection between the HBM structure and the first packaging structure includes welding the HBM structure to a surface of the second carrier board of the first packaging structure exposed by the first carrier board and facing the first carrier board, and realizing electrical connection between the HBM structure and the second carrier board of the first packaging structure.

20. The packaging method according to claim 19, characterized in that: Also includes: providing a first heat dissipation layer; The first heat dissipation layer is formed on a surface of the second carrier board facing away from the first packaging structure and the HBM structure.

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