Semiconductor radio frequency device and preparation method of grid electrode of semiconductor radio frequency device

Abstract

The invention discloses a semiconductor radio frequency device and a preparation method of a grid electrode of the semiconductor radio frequency device. The preparation method of the grid electrode of the semiconductor radio frequency device comprises the following steps: forming a supporting layer on an epitaxial structure, and forming a grid cap metal layer on the supporting layer; forming a continuous gate root metal layer with uniform thickness on the surfaces of the epitaxial structure and / or the supporting layer and the gate cap metal layer; the gate root metal layer is etched, at least the gate root metal layer covering the side wall of the gate cap metal layer or covering the side wall of the gate cap metal layer / the side wall of the supporting layer is reserved and serves as a gate root, and the gate root is matched with the gate cap metal layer to form a gate. According to the invention, the length of the gate is defined by depositing the gate metal film / etching the gate metal film, and the experimental result shows that the gate with the length of 30-300nm can be stably prepared by the scheme of the invention.

Description

Technical Field

[0001] The present invention particularly relates to a semiconductor radio frequency device and a method for preparing a gate thereof, and belongs to the field of micro-nano technology. Background Art

[0002] The main research direction of GaN HEMT is how to increase the operating frequency of the device. The gate length of the device is one of the most critical factors affecting the frequency performance of the device. In the process of pursuing higher frequency performance, the gate length of mainstream GaN HEMT devices has been successfully reduced to less than 100 nm. The extremely short gate line width poses an extremely severe challenge to the manufacturing process of the device.

[0003] In the manufacturing process of GaN HEMT RF devices, the preparation of nano-gates generally relies on electron beam lithography for nano-line lithography. To improve device performance, most devices use T-type gates, with gate caps of about 300nm~800nm, and gate roots generally below 150nm or even below 100nm. Long gate caps are used to reduce gate resistance, and short gate roots are used to increase transconductance. Therefore, the requirements for lithography are extremely strict. The process flow of the T-type gate is to first coat two or three layers of photoresist on the GaN / AlGaN heterojunction, then define the pattern through electron beam lithography, and finally deposit metal and then peel off to prepare the T-type gate. Similar solutions for preparing extremely short gates of GaN HEMT RF devices include self-aligned gate end technology, photoresist thermal reflow process, etc.

[0004] The existing electron beam lithography process flow is as follows: Figure 1 However, electron beam lithography still has some disadvantages, such as Figure 2 As shown, on the one hand, when preparing lines less than 100nm, the electron beam lithography machine will encounter problems such as charge accumulation and overlay deviation, as shown in the figure. These problems are related to many factors such as electron beam photoresist, electron beam lithography marks prepared by ultraviolet lithography, mark recognition, electron beam lithography dose, wafer conductivity, etc. Moreover, the intra-wafer consistency of the wafer is difficult to guarantee. In actual production, a lot of manpower and material resources are required for parameter verification. On the other hand, due to the characteristics of its process principle, electron beam lithography is very inefficient during processing. The electron beam needs to "write" each line on the wafer in turn, which takes a lot of time compared to ultraviolet lithography and other batch processing technologies. It often takes 5-6 hours for a 2-inch wafer to complete the preparation of all electron beam lithography.

[0005] Based on the drawbacks of electron beam lithography, some researchers in the industry have also developed many self-alignment technologies, such as: self-aligned gate end process, photoresist hot reflow process, two-time UV lithography to define gate length, etc. The self-aligned gate end process realizes the preparation of RF devices without electron beam lithography, but its gate length is defined by wet etching. In the actual application process, its gate length is difficult to accurately control. The gate length prepared in the literature is 210nm. The photoresist hot reflow process is relatively simple and can also achieve a smaller gate size, but whether the gate length can be prepared to less than 100nm remains to be discussed. In addition, through the method of photoresist hot reflow, on the one hand, its accuracy is difficult to control, and on the other hand, the cross-section of the photoresist after hot reflow is an irregular curve, and the gate root height of the device is difficult to control, which will increase the parasitic capacitance of the device. The solution of defining the gate length by two-time UV lithography is completely dependent on the overlay alignment capability of the lithography machine, and the error is large.

[0006] In summary, in the process of preparing GaN HEMT nano-gates, electron beam lithography is currently the main technology. Although it can achieve extremely short gate size, it also has many problems. For example, the charge accumulation effect will make it difficult to control the lithography line width; the overlay deviation problem will affect the gate alignment accuracy; the mechanical strength and processing efficiency of the gate are also difficult problems that need to be overcome in the preparation process. These problems make it difficult to achieve mass processing of GaN HEMTs prepared by electron beam lithography, and the yield is limited. In addition, for the current international environment, the introduction, repair and maintenance of electron beam lithography machines will be restricted. In order to solve the dependence of GaN HEMT nano-gates on electron beam lithography, some researchers have tried to develop a self-alignment process. Although this method can avoid the dependence on electron beam lithography technology, the prepared gate length is limited and the consistency of the gate length is difficult to control. Therefore, how to get rid of the dependence of nano-gate preparation on electron beam lithography machines and provide an effective solution that can avoid the use of electron beam lithography technology and prepare extremely short gates is still one of the problems that the industry needs to solve. Summary of the invention

[0007] The main purpose of the present invention is to provide a method for preparing a semiconductor radio frequency device and its gate, so as to solve the dependence of the preparation of nano-gate on electron beam lithography machine, gate alignment problems, process efficiency problems, etc., thereby overcoming the deficiencies in the prior art.

[0008] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes: A first aspect of an embodiment of the present invention provides a method for preparing a gate of a semiconductor radio frequency device, comprising: forming a support layer on the epitaxial structure, and forming a gate cap metal layer on the support layer; Forming a gate root metal layer with uniform and continuous thickness on the surface of the epitaxial structure and / or the support layer and the gate cap metal layer; The gate root metal layer is etched, and at least the gate root metal layer covering the gate cap sidewall or the gate cap sidewall / the support layer sidewall is retained and serves as a gate root, the gate cap metal layer serves as a gate cap, and the gate root and the gate cap electrically cooperate to form a gate.

[0009] A second aspect of an embodiment of the present invention provides a semiconductor radio frequency device, wherein a gate of the semiconductor radio frequency device is obtained by the method for preparing a gate of the semiconductor radio frequency device.

[0010] Compared with the prior art, the advantages of the present invention include: A method for preparing a semiconductor radio frequency device provided by an embodiment of the present invention has low requirements on equipment. The embodiment of the present invention prepares an extremely short gate by deposition-etching. The present invention does not require electron beam lithography technology at all, and domestic equipment can meet production needs.

[0011] A method for preparing a semiconductor radio frequency device provided by an embodiment of the present invention has high efficiency. The electron beam lithography used in the prior art has low efficiency and great process difficulty. The present invention defines the gate cap metal layer pattern through i-line lithography and defines the gate root through deposition-etching, which has higher efficiency and can be mass-produced. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a manufacturing flow chart of a single-grid root T-type grid in the prior art; Figure 2 It is a graphic illustration of the instability factors of the electron beam lithography process in the prior art; Figure 3 It is a schematic diagram of a manufacturing process of a semiconductor radio frequency device provided in an embodiment of the present invention; Figure 4 This is a diagram showing the side wall W layer coverage effect after the Ni layer is inserted in an embodiment of the present invention. DETAILED DESCRIPTION

[0013] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

[0014] A first aspect of an embodiment of the present invention provides a method for preparing a gate of a semiconductor radio frequency device, comprising: forming a support layer on the epitaxial structure, and forming a gate cap metal layer on the support layer; Forming a gate root metal layer with uniform and continuous thickness on the surface of the epitaxial structure and / or the support layer and the gate cap metal layer; The gate root metal layer is etched, and at least the gate root metal layer covering the gate cap sidewall or the gate cap sidewall / the support layer sidewall is retained and serves as a gate root, the gate cap metal layer serves as a gate cap, and the gate root and the gate cap electrically cooperate to form a gate.

[0015] Furthermore, the method for preparing the gate of the semiconductor radio frequency device includes: Forming a support layer on the epitaxial structure, the support layer comprising a first support portion, a second support portion and a third support portion arranged in sequence, the first support portion, the second support portion and the third support portion of the support layer respectively covering a first region, a second region and a third region of the epitaxial structure, one of a source region and a drain region being located in the first region, and the other being located in the third region; forming a gate cap metal layer on the second supporting portion of the supporting layer; Etching and removing the third supporting portion of the third supporting layer to expose the third region of the epitaxial structure; A continuous and uniformly thick gate root metal layer is formed on the surfaces of the first supporting portion of the supporting layer, the gate cap metal layer and the third region of the epitaxial structure, and then the gate root metal layer distributed outside the first side wall, the second side wall of the gate cap metal layer and the third side wall of the supporting layer is removed, and the remaining gate root metal layer on the second side wall of the gate cap metal layer and the third side wall of the supporting layer serves as a gate root, wherein the first side wall and the second side wall of the gate cap metal layer are arranged opposite to each other, the first side wall is a side wall close to the first supporting portion of the supporting layer, and the third side wall of the supporting layer is located on the same side as the second side wall.

[0016] Furthermore, the method for preparing the gate of the semiconductor radio frequency device specifically includes: forming a second mask on the first supporting portion of the supporting layer and a portion of the gate cap metal layer close to the first supporting portion; Using the second mask and the gate cap metal layer as masks, etching and removing the third support portion of the third support layer to expose the third region of the epitaxial structure; removing the second mask, and forming a continuous gate root metal layer with uniform thickness on the surfaces of the first supporting portion of the supporting layer, the gate cap metal layer, and the third region of the epitaxial structure; The gate root metal layer is etched by adopting anisotropic etching processes to simultaneously remove the gate root metal layer distributed on the first side wall, the second side wall of the gate cap metal layer and the third side wall of the support layer.

[0017] Furthermore, the second side wall of the gate cap metal layer and the third side wall of the support layer are both vertical, and the second side wall and the third side wall are located in the same vertical plane.

[0018] In a more specific embodiment, the method for preparing the gate of the semiconductor radio frequency device specifically includes: forming a Ti / Au / Cr / Ni metal stack as a gate cap metal layer on the second supporting portion of the supporting layer; Etching and removing the third supporting portion of the third supporting layer to expose the third region of the epitaxial structure; First, a Ni layer and a first W layer with uniform and continuous thickness are sequentially formed on the first supporting portion of the supporting layer, the gate cap metal layer and the surface of the third region of the epitaxial structure, thereby forming a Ni / W metal stack; Removing the Ni / W metal stack covering the surface of the gate cap metal layer and the Ni layer and the Cr layer on the surface of the gate cap metal layer; Then forming a second W layer with uniform and continuous thickness on the surface of the remaining Ni / W metal stack and the remaining gate cap metal layer, wherein the second W layer and the remaining Ni / W metal stack are stacked to form the gate root metal layer; Preferably, the Ni layer and the first W layer in the Ni / W metal stack are formed by physical vapor deposition, and the second W layer is formed by chemical vapor deposition; Furthermore, the method for removing the Ni / W metal stack covering the surface of the gate cap metal layer and the Ni layer and the Cr layer on the surface of the gate cap metal layer specifically includes: corroding and removing the Cr layer in the gate cap metal layer, and separating the Ni layer covering the Cr layer in the gate cap metal layer and the Ni / W metal stack covering the gate cap metal layer from the Au layer of the gate cap metal layer and removing them.

[0019] Furthermore, the thickness of the second W layer is greater than the thickness of the first W layer.

[0020] Furthermore, the method of removing the gate root metal layer except the first side wall, the second side wall of the gate cap metal layer and the third side wall of the support layer specifically includes: First, anisotropic etching processes are used to simultaneously remove the second W layer and the first W layer distributed on the first side wall, the second side wall of the gate cap metal layer, and the third side wall of the support layer, and then the Ni layer distributed on the first side wall, the second side wall of the gate cap metal layer, and the third side wall of the support layer is corroded.

[0021] Compared with the previous proposal of using only magnetron sputtering to form the gate metal, the present invention can provide better sidewall conformal coverage, higher gate metal work function, lower gate input resistance, and the Ni metal in the gate root metal layer can be used as an etching stop layer when etching W, thereby avoiding damage to the device during the over-etching W process.

[0022] Furthermore, the method for preparing the gate of the semiconductor radio frequency device specifically includes: forming a patterned first mask on the support layer, and then forming a gate cap metal layer in the area not covered by the first mask.

[0023] Furthermore, the material of the support layer includes at least one of an inorganic non-metallic material and an organic material, but is not limited thereto.

[0024] A second aspect of an embodiment of the present invention provides a semiconductor radio frequency device, wherein a gate of the semiconductor radio frequency device is obtained by the method for preparing a gate of the semiconductor radio frequency device.

[0025] Furthermore, the semiconductor radio frequency device comprises: An epitaxial structure and a source, a drain and a gate matched with the epitaxial structure, wherein the gate is arranged between the source and the drain, and the source and the drain are electrically connected via a carrier channel in the epitaxial structure; In addition, a supporting layer is also arranged on the epitaxial structure, and the supporting layer is arranged at least in the gate region. The drain region of the epitaxial structure is completely exposed, and the gate includes a gate root and a gate cap. The gate cap is arranged on the supporting layer, the gate cap has a second side wall, and the supporting layer has a third side wall. The second side wall and the third side wall are located in the same vertical plane, and the gate root is continuously covered on the second side wall of the gate cap and the third side wall of the supporting layer.

[0026] Furthermore, the epitaxial structure includes a GaN-based heterojunction or a GaAs-based heterojunction.

[0027] The technical solution, its implementation process and principles, etc. will be further explained below in conjunction with the accompanying drawings and specific implementation cases. Unless otherwise specified, the semiconductor epitaxy, photolithography, etching, metal deposition, device isolation and other processes and equipment used in the embodiments of the present invention may be known in the art, and the photoresist, epitaxial structure materials, electrode materials, etc. used may also be known in the art.

[0028] Example 1 See also Figure 3 , a method for preparing a semiconductor radio frequency device, comprising the following steps: (a) Producing an epitaxial structure including an AlGaN / GaN heterojunction. Of course, the epitaxial structure may also include a cap layer, a buffer layer, and structures thereof. The specific structure of the epitaxial structure may be known in the art and will not be described in detail herein.

[0029] (b) Device isolation is performed on the epitaxial structure. Specifically, device isolation can be achieved by forming an isolation region by ion implantation or forming an isolation trench by etching. Device isolation on the epitaxial structure is a conventional process known in the art and is not specifically limited here.

[0030] (c) Fabricating a source and a drain in the source region and the drain region of the epitaxial structure, and electrically connecting the source and the drain to the two-dimensional electron gas in the epitaxial structure; of course, an ohmic contact layer may be first formed in the source region and the drain region of the epitaxial structure, and then fabricating the source and the drain on the ohmic contact layer. The ohmic contact layer may be a heavily doped GaN layer, etc. Of course, the ohmic contact layer may also be fabricated by ion implantation, etc. It is understandable that forming an ohmic contact layer to achieve ohmic contact between the source and the drain and the epitaxial structure is a conventional process known in the art and is not specifically limited here.

[0031] (d) A layer of SiO2 is deposited on the surface of the epitaxial structure as a support layer. The thickness of the support layer and other parameters are not the key technology of the present invention and are not specifically limited here. The support layer is defined to include a first support portion, a second support portion and a third support portion which are sequentially arranged along its transverse direction.

[0032] (e) forming a patterned first mask on the support layer by means of a photoresist (PR) to define the position and pattern of the gate cap metal layer; specifically, the first mask covers the first support portion and the third support portion of the support layer.

[0033] (f) A Ti / Au / Cr / Ni metal stack is deposited on the second support portion (which can be understood as the gate region) on the surface of the support layer that is not covered by the first mask as a gate cap metal layer. The thickness of each layer is not specifically limited here. The bottom layer of the Ti / Au / Cr / Ni metal stack is the Ti layer.

[0034] (g) The first mask is stripped off to form a patterned gate cap metal layer. The first mask is stripped off by any method known in the art and is not specifically limited here.

[0035] (h) Photolithography, and covering the surface of the first supporting portion of the supporting layer and a portion of the gate cap metal layer close to its own first side wall with photoresist (PR) to form a second mask, and another portion of the gate cap metal layer close to its own second side wall and a third supporting portion of the supporting layer close to the second side wall of the gate cap metal layer are exposed, wherein the first side wall and the second side wall are arranged back to back, one of the first side wall and the second side wall faces the source, and the other faces the drain.

[0036] It should be noted that, in order to solve the problem of poor step coverage of the W metal layer prepared by magnetron sputtering (PVD), the present invention uses chemical vapor deposition (CVD) to prepare the gate root material W. When CVD prepares W, a high-temperature environment is used, and photoresist cannot be used as a photolithography mask. Other inorganic material masks will become more difficult to remove after experiencing high temperatures (such as SiO2), and the problem of removing corrosive chemicals for removing the inorganic material masks must also be considered. The present invention only exposes one side wall of the support layer close to the second side wall of the gate cap metal layer, and the other side of the support layer is used as a mask for depositing W. After depositing the W material, only the gate root metal layer located on the second side wall of the gate cap metal layer is in contact with the barrier layer to form an effective gate.

[0037] (i) Using the second mask and the gate cap metal layer as masks, the third support portion of the support layer close to the second side wall of the gate cap metal layer is etched away, exposing the surface area of ​​the epitaxial structure close to the second side wall of the gate cap metal layer, and the third side wall of the remaining second support portion of the support layer is located on the same side and in the same vertical plane as the second side wall of the gate cap metal layer.

[0038] (j) removing the second mask, and sequentially depositing a Ni layer and a first W layer on the surface of the structure formed in step (i) by a magnetron sputtering process, thereby forming a Ni / W metal stack. The Ni / W metal stack grown by the magnetron sputtering process can ensure that the top and side walls of the gate cap metal layer are covered.

[0039] (k) The Cr layer in the gate cap metal layer is removed by a wet etching process, and the Ni layer covering the Cr layer in the gate cap metal layer, the Ni / W metal stack covering the gate cap metal layer and the Au layer of the gate cap metal layer are separated and removed, thereby avoiding the problem of splitting between the gate root and the gate cap caused by etching the remaining Ni layer in step (n).

[0040] (l) using a chemical vapor deposition process to form a second W layer with uniform and continuous thickness on the surface of the structure formed in step (k), wherein the second W layer is stacked with the remaining Ni / W metal stack to form the gate root metal layer, such as Figure 4 As shown, the thickness of the second W layer is greater than the thickness of the first W layer. Exemplarily, the thickness of the second W layer is 120 nm.

[0041] The present invention adopts a CVD process to form the second W layer. The W layer formed by the CVD process has better step coverage. The aspect ratio (ratio of the side wall gate length to the coating thickness) of the W layer obtained by the PVD process is about 0.37. The aspect ratio of the W layer prepared by CVD is about 0.8-0.9, which basically achieves conformal coverage. In addition, the resistivity of the W layer formed by the CVD process is lower, which is beneficial to device improvement. The resistivity of the W layer prepared by PVD is about 120μΩ·cm; while the resistivity of the W layer prepared by CVD is about 18μΩ·cm. In addition, the W layer is formed by two processes, which is beneficial to the addition of the Ni etching stop layer. The work function of Ni is higher, which is 5.15 while that of W is 4.5. Usually, the gate of the HEMT device prepared by the AlGaN / GaN heterojunction is Ni / Au, Pt / Au, etc., and the contact layer is a high work function metal such as Ni and Pt. After the Ni layer is inserted under the W layer, the Ni layer can be used as an etching stop layer for etching the W layer to prevent the plasma of etching W from damaging the barrier layer. After the W layer is etched, the Ni layer on the surface can be removed by wet etching, while the Ni under the gate root is retained. Therefore, inserting a Ni layer under the W layer can greatly improve the performance of the device.

[0042] (m) The gate root metal layer is simultaneously etched using anisotropic etching processes, and the etching stops when the bottom Ni layer of the gate root metal layer is reached. The W layer on the surface of the gate root metal layer (including the first W layer and the second W layer being removed) except for the first side wall, the second side wall, and the third side wall of the second supporting portion of the supporting layer distributed on the gate cap metal layer is simultaneously removed, and the Au layer on the surface of the gate cap metal layer is exposed.

[0043] (n) A wet etching process is used to remove the Ni layer remaining on the surface of the first supporting portion of the supporting layer and the drain region of the epitaxial structure, and the gate root metal layer remaining on the second side wall of the gate cap metal layer and the third side wall of the second supporting portion of the supporting layer serves as a gate root, and the reserved Au layer serves as a gate cap, thereby forming a gate.

[0044] It should be noted that the preparation method also includes processing the residual W and the support layer covering the source after etching the gate root metal layer, as well as preparing leads, etc. The AlGaN / GaN heterojunction can also be replaced by a GaAs-based heterojunction, etc.

[0045] The W layer prepared by the CVD process of the present invention can achieve a better conformal coverage effect (under the condition of the same thickness of the deposited film, the side wall is thicker). Under the condition of unchanged etching conditions, depositing a thinner W can achieve the same effect as the previous case, and the resistivity of the W gate root is lower. After adding the Ni etching stop layer, the gate length can be reduced by increasing the over-etching time. The preparation method of a semiconductor radio frequency device provided by an embodiment of the present invention has low equipment requirements. The embodiment of the present invention prepares an extremely short gate by deposition-etching. The present invention can completely eliminate the need for electron beam lithography technology, and domestic equipment can meet production needs.

[0046] A method for preparing a semiconductor radio frequency device provided by an embodiment of the present invention has high efficiency. The electron beam lithography used in the prior art has low efficiency and great process difficulty. The present invention defines the gate cap metal layer pattern through i-line lithography and defines the gate root through deposition-etching, which has higher efficiency and can be mass-produced.

[0047] In view of the difficulty in preparing nano-gates of AlGaN / GaN HEMT RF devices, the present invention provides a more stable solution to achieve the preparation of nano-gates. For traditional single-gate RF devices, the present invention defines the gate length by depositing / etching the gate metal film. Experimental results show that gate lengths of 30nm-300nm can be stably prepared through the solution of the present invention.

[0048] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a gate of a semiconductor radio frequency device, characterized in that: include: forming a support layer on the epitaxial structure, and forming a gate cap metal layer on the support layer; Forming a gate root metal layer with uniform and continuous thickness on the surface of the epitaxial structure and / or the support layer and the gate cap metal layer; The gate root metal layer is etched, and at least the gate root metal layer covering the gate cap sidewall or the gate cap sidewall / the support layer sidewall is retained and serves as a gate root, the gate cap metal layer serves as a gate cap, and the gate root and the gate cap electrically cooperate to form a gate.

2. The method for preparing a gate of a semiconductor radio frequency device according to claim 1, characterized in that: include: Forming a support layer on the epitaxial structure, the support layer comprising a first support portion, a second support portion and a third support portion arranged in sequence, the first support portion, the second support portion and the third support portion of the support layer respectively covering a first region, a second region and a third region of the epitaxial structure, one of a source region and a drain region being located in the first region, and the other being located in the third region; forming a gate cap metal layer on the second supporting portion of the supporting layer; Etching and removing the third supporting portion of the third supporting layer to expose the third region of the epitaxial structure; A continuous and uniformly thick gate root metal layer is formed on the surfaces of the first supporting portion of the supporting layer, the gate cap metal layer and the third region of the epitaxial structure, and then the gate root metal layer distributed outside the first side wall, the second side wall of the gate cap metal layer and the third side wall of the supporting layer is removed, and the remaining gate root metal layer on the second side wall of the gate cap metal layer and the third side wall of the supporting layer serves as a gate root, wherein the first side wall and the second side wall of the gate cap metal layer are arranged opposite to each other, the first side wall is a side wall close to the first supporting portion of the supporting layer, and the third side wall of the supporting layer is located on the same side as the second side wall.

3. The method for preparing a gate of a semiconductor radio frequency device according to claim 2, characterized in that: Specifically include: forming a second mask on the first supporting portion of the supporting layer and a portion of the gate cap metal layer close to the first supporting portion; Using the second mask and the gate cap metal layer as masks, etching and removing the third support portion of the third support layer to expose the third region of the epitaxial structure; removing the second mask, and forming a continuous gate root metal layer with uniform thickness on the surfaces of the first supporting portion of the supporting layer, the gate cap metal layer, and the third region of the epitaxial structure; The gate root metal layer is etched by adopting anisotropic etching processes to simultaneously remove the gate root metal layer distributed on the first side wall, the second side wall of the gate cap metal layer and the third side wall of the support layer.

4. The method for preparing a gate of a semiconductor radio frequency device according to claim 2 or 3, characterized in that: The second side wall of the gate cap metal layer and the third side wall of the support layer are both vertical, and the second side wall and the third side wall are located in the same vertical plane.

5. The method for preparing a gate of a semiconductor radio frequency device according to claim 2 or 3, characterized in that: Specifically include: forming a Ti / Au / Cr / Ni metal stack as a gate cap metal layer on the second supporting portion of the supporting layer; Etching and removing the third supporting portion of the third supporting layer to expose the third region of the epitaxial structure; First, a Ni layer and a first W layer with uniform and continuous thickness are sequentially formed on the first supporting portion of the supporting layer, the gate cap metal layer and the surface of the third region of the epitaxial structure, thereby forming a Ni / W metal stack; Removing the Ni / W metal stack covering the surface of the gate cap metal layer and the Ni layer and the Cr layer on the surface of the gate cap metal layer; Then forming a second W layer with uniform and continuous thickness on the surface of the remaining Ni / W metal stack and the remaining gate cap metal layer, wherein the second W layer and the remaining Ni / W metal stack are stacked to form the gate root metal layer; Preferably, the Ni layer and the first W layer in the Ni / W metal stack are formed by physical vapor deposition, and the second W layer is formed by chemical vapor deposition; Preferably, the method for removing the Ni / W metal stack covering the surface of the gate cap metal layer and the Ni layer and the Cr layer on the surface of the gate cap metal layer specifically comprises: removing the Cr layer in the gate cap metal layer by etching, and the Ni layer covering the Cr layer in the gate cap metal layer and the Ni / W metal stack covering the gate cap metal layer are separated from the Au layer of the gate cap metal layer and removed; Preferably, the thickness of the second W layer is greater than the thickness of the first W layer.

6. The method for preparing a gate of a semiconductor radio frequency device according to claim 5, characterized in that: The method of removing the gate root metal layer except for the first side wall, the second side wall of the gate cap metal layer and the third side wall of the support layer specifically includes: First, anisotropic etching processes are used to simultaneously remove the second W layer and the first W layer distributed on the first side wall, the second side wall of the gate cap metal layer, and the third side wall of the support layer, and then the Ni layer distributed on the first side wall, the second side wall of the gate cap metal layer, and the third side wall of the support layer is corroded.

7. The method for preparing a gate of a semiconductor radio frequency device according to claim 1, characterized in that: Specifically include: A patterned first mask is formed on the support layer, and then a gate cap metal layer is formed in the area not covered by the first mask.

8. The method for preparing a gate of a semiconductor radio frequency device according to claim 1, characterized in that: The material of the support layer includes at least one of an inorganic non-metallic material and an organic material.

9. A semiconductor radio frequency device, characterized in that: The gate of the semiconductor radio frequency device is obtained by the method for preparing the gate of the semiconductor radio frequency device according to any one of claims 1-8.

10. The semiconductor radio frequency device according to claim 1, characterized in that: include: An epitaxial structure and a source, a drain and a gate matched with the epitaxial structure, wherein the gate is arranged between the source and the drain, and the source and the drain are electrically connected via a carrier channel in the epitaxial structure; In addition, a supporting layer is also arranged on the epitaxial structure, and the supporting layer is arranged at least in the gate region. The drain region of the epitaxial structure is completely exposed, and the gate includes a gate root and a gate cap. The gate cap is arranged on the supporting layer, the gate cap has a second side wall, and the supporting layer has a third side wall. The second side wall and the third side wall are located in the same vertical plane, and the gate root is continuously covered on the second side wall of the gate cap and the third side wall of the supporting layer.

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