Esd structure, esd device and esd chip
By designing a combined structure of substrate, buried layer, epitaxy, well region and active region, the problems of weak ESD capability, low breakdown voltage and latch-up risk of ESD structures are solved, achieving high breakdown voltage and strong ESD protection, which is suitable for ESD protection in high voltage environments.
CN119767794BActive Publication Date: 2026-07-03HANGZHOU SILAN MICROELECTRONICS CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU SILAN MICROELECTRONICS CO LTD
- Filing Date
- 2024-12-26
- Publication Date
- 2026-07-03
AI Technical Summary
Technical Problem
Existing ESD structures suffer from weak ESD capabilities, low breakdown voltage, and high latch-up risk.
Method used
An ESD structure was designed, including a substrate, a buried layer, an epitaxial layer, a first well region, a second well region, a third well region, a first active region, and a second active region. By combining diodes and parasitic transistors, current discharge is achieved, latch-up risk is reduced, and high breakdown voltage and strong ESD protection capability are provided in a small area.
Benefits of technology
It achieves high breakdown voltage and strong ESD protection in a small chip area, reduces hysteresis effect, avoids latch-up risk, and is suitable for ESD protection in high voltage environments.
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Smart Images
Figure CN119767794B_ABST
Abstract
The application provides an ESD structure, which comprises a substrate, a buried layer and an epitaxial layer stacked in sequence, a first well region is located in the epitaxial layer, a second well region extends from the epitaxial layer to contact the buried layer, M third well regions separated from each other are located in the second well region, a first isolation structure is connected across the first well region and the second well region, a first active region is located on part of the first well region and part of each third well region, a second active region is located on the second well region which is not covered by the first active region and the first isolation structure, and the first active region and the second active region on the second well region are isolated by a second isolation structure. The application can realize higher breakdown voltage and stronger ESD protection ability in smaller area, maintain high voltage, have wide voltage application range, greatly reduce the hysteresis effect and avoid the risk of latch-up.
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