Scanning chain fault positioning method and system based on special chain diagnosis vector

Abstract

The invention discloses a scanning chain fault positioning method and system based on special chain diagnosis vectors, and the method comprises the steps: firstly, determining the fault type in a to-be-tested functional circuit scanning chain through a chain test, and then generating a corresponding special chain diagnosis vector for each trigger, setting a fault value according to the fault type; adjusting the input value of the functional circuit, so that a previous trigger of the trigger captures an opposite value of the fault value; and finally, carrying out scanning chain fault test by utilizing the special chain diagnosis vector to obtain the position of the trigger with the fault. According to the method, the special chain diagnosis vector for each scanning trigger is generated, and the circuit logic analysis is combined, so that the fault position in the scanning chain can be more accurately positioned.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit testability design, in particular to a scan chain fault location method and system based on a dedicated chain diagnostic vector. Background Art

[0002] Scan Testing is a method for fault detection of digital circuits, especially integrated circuits (ICs). It has been widely used to detect defects generated during the manufacturing process of integrated circuits and can achieve high test coverage. This method uses the scan chain structure to effectively test the functions and performance of complex circuits by scanning and controlling the internal state of the circuit. The core principle of the scan chain is to connect multiple triggers in series into a chain through a specific circuit design, so that external test vectors can enter the chain in sequence, thereby sequentially stimulating and controlling each trigger of the circuit. This design enables the test signal to be transmitted through the scan chain and set the internal state of the circuit, thereby achieving effective testing of the internal functions of the circuit.

[0003] However, the integrity of the scan chain remains a major challenge for scan testing. The scan chain consists of multiple flip-flops connected in series. The chip area consumed by the scan elements, chain connections, and control circuits varies in different circuit designs, with the scan elements and clock parts potentially occupying about 30% of the chip area. More importantly, the incidence of scan chain failures varies from design to design, typically between 10% and 30%, with scan chain failures accounting for almost 50% of chip failures. Therefore, accurately diagnosing failures in the scan chain is critical to ensuring the effectiveness of scan testing.

[0004] At present, the methods for realizing scan chain fault location based on simulation usually use traditional test vectors and process the obtained simulation results to locate the location of scan chain faults. However, traditional test vector generation mainly detects faults in the functional part of the circuit, and the indicators usually concerned include fault coverage, number of test vectors, and test time. It is not specially generated for chain diagnosis, and its generation process does not consider the particularity of the chain structure, resulting in low efficiency and accuracy in scan chain fault location. Summary of the invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a scan chain fault location method and system based on a dedicated chain diagnostic vector with high accuracy and fast diagnostic speed.

[0006] Technical solution: The scan chain fault location method based on the dedicated chain diagnostic vector of the present invention comprises the following steps: Step 1, determining the fault type existing in the scan chain of the functional circuit to be tested through chain testing, wherein the fault type is a stuck-at-1 fault or a stuck-at-0 fault, and the corresponding fault value is 1 or 0; Step 2, generating a corresponding dedicated chain diagnostic vector for each bit of trigger, wherein the corresponding position of the trigger and its downstream trigger is set to a fault value according to the fault type; adjusting the input value of the functional circuit so that the previous trigger of the trigger captures the opposite value of the fault value; Step 3: Perform a scan chain fault test using the dedicated chain diagnostic vector to obtain the location of the trigger where the fault occurs.

[0007] Furthermore, in step 1, the circuit netlist file after insertion into the scan chain is read, and stuck-at-1 and stuck-at-0 faults are injected into each trigger in the scan chain to obtain a faulty circuit netlist; a chain test is performed using a periodic test vector to determine the type of fault existing in the functional circuit scan chain.

[0008] Furthermore, in step 2, in the dedicated chain diagnostic vector, the corresponding position of the upstream trigger of the trigger is a don't care bit, which is randomly set to 0 or 1.

[0009] Furthermore, in step 2, the method of adjusting the input value of the functional circuit so that the previous trigger of the trigger captures the opposite value of the fault value includes: Set constraints, input ports and output ports. The constraint is that the corresponding positions of the trigger and its downstream triggers in the dedicated chain diagnostic vector are fault values. By traversing all possible input combinations to calculate the output of the functional circuit, an input combination that meets the constraints is obtained.

[0010] Further, in step 2, the capture value of the trigger is set to the opposite value of the fault value.

[0011] Furthermore, step 3 specifically includes saving the chain diagnosis vector and generating a corresponding testbench file, and performing a scan chain fault test using the testbench file to obtain the location of the trigger where the fault occurs.

[0012] The scan chain fault location system based on the dedicated chain diagnostic vector of the present invention comprises: A fault type test unit, used to determine the fault type existing in the scan chain of the functional circuit to be tested through a chain test, wherein the fault type is a stuck-at-1 fault or a stuck-at-0 fault, and the corresponding fault value is 1 or 0; A dedicated chain diagnostic vector generating unit is used to generate a corresponding dedicated chain diagnostic vector for each bit of the trigger, wherein the corresponding position of the trigger and its downstream trigger is set to a fault value according to the fault type; and adjust the input value of the functional circuit so that the previous trigger of the trigger captures the opposite value of the fault value; The scan chain fault test unit is used to perform a scan chain fault test using the dedicated chain diagnostic vector to obtain a trigger position where a fault occurs.

[0013] Furthermore, in the fault type test unit, the circuit netlist file after insertion into the scan chain is read, and stuck-at-1 and stuck-at-0 faults are injected into each trigger in the scan chain to obtain a faulty circuit netlist; a chain test is performed using a periodic test vector to determine the fault type existing in the functional circuit scan chain; In the dedicated chain diagnostic vector generation unit, in the dedicated chain diagnostic vector, the corresponding position of the upstream flip-flop of the flip-flop is a don't care bit and is randomly set to 0 or 1; In a dedicated chain diagnostic vector generation unit, a method for adjusting a functional circuit input value so that an upper trigger of the trigger captures an opposite value of a fault value includes: Set constraints, input ports and output ports, where the constraints are that the corresponding positions of the trigger and its downstream triggers in the dedicated chain diagnostic vector are fault values, and calculate the output of the functional circuit by traversing all possible input combinations to obtain input combinations that meet the constraints; In the dedicated chain diagnostic vector generation unit, the capture value of the flip-flop is set to the opposite value of the fault value; In the scan chain fault test unit, the chain diagnosis vector is saved and the corresponding testbench file is generated. The scan chain fault test is performed using the testbench file to obtain the position of the trigger where the fault occurs.

[0014] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the scan chain fault location method based on the dedicated chain diagnostic vector is implemented.

[0015] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the method for locating a scan chain fault based on a dedicated chain diagnostic vector is implemented.

[0016] Beneficial effects: Compared with the prior art, the advantages of the present invention are as follows: (1) The traditional method is based on the vector generated by ATPG to detect functional circuit faults, while the present invention can more accurately locate the fault position in the scan chain by generating a dedicated chain diagnosis vector for each scan trigger and combining it with circuit logic analysis. Since each dedicated chain diagnosis vector is carefully designed, it can accurately stimulate different fault types, thereby improving the coverage and accuracy of diagnosis. (2) The present invention first determines the fault type existing in the scan chain through chain diagnosis, and generates corresponding diagnosis vectors for the identified fault type. Unlike the traditional method, the present invention does not need to introduce vectors of multiple fault types during the test process, thereby effectively reducing the number of required test vectors and significantly shortening the test time. (3) Compared with the hardware-based scan chain diagnosis method, the present invention has significant advantages, especially in that it can achieve efficient fault diagnosis without adding additional hardware overhead. Traditional hardware methods usually require the addition of additional diagnostic circuits or logic units in the circuit to facilitate fault detection and location, which often leads to an increase in chip area and power consumption, and may even affect the performance of the circuit. The present invention only relies on the scan chain and the generated diagnostic vectors, and completes the fault diagnosis through the simulation process, without changing the hardware structure or introducing additional hardware modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a flow chart of the scan chain fault location method of the present invention.

[0018] Figure 2 4 is a circuit structure diagram of S27 according to an embodiment of the present invention.

[0019] Figure 3 Schematic diagram of a stuck-at fault injection circuit according to an embodiment of the present invention.

[0020] Figure 4 Schematic diagram of calculating a dedicated chain diagnostic vector according to a circuit structure according to an embodiment of the present invention.

[0021] Figure 5 It is a schematic diagram of the dedicated chain diagnostic vector STILI format according to an embodiment of the present invention.

[0022] Figure 6 Schematic diagram of a dedicated chain diagnostic vector waveform according to an embodiment of the present invention.

[0023] Figure 7 A schematic diagram of a stuck-at-1 fault diagnosis vector STIIL file according to an embodiment of the present invention.

[0024] Figure 8 Schematic diagram of a dedicated chain diagnostic vector simulation waveform according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] First, the scan test process and test vectors are briefly introduced. In scan testing, test vector generation directly determines the effectiveness and efficiency of the test. A test vector is a set of bit vectors used to stimulate the input signal of the circuit. Each vector corresponds to a certain input configuration of the circuit. The purpose is to verify whether the circuit can output as expected after receiving a specific input signal. Generating high-quality test vectors is the key to ensuring the reliability, performance, and functional correctness of the circuit. Usually, the test vector stimulates the circuit and detects its response by simulating various input states of the circuit, thereby evaluating whether the circuit has manufacturing defects.

[0026] In scan testing, the test vector is first input into the circuit through the scan chain, a process called test vector shift-in. The scan chain is a series of flip-flops connected in series, allowing the test equipment to input test data into the circuit one by one. Next, the circuit is stimulated according to the input test vector, a process called capture operation. After the capture operation, the circuit performs corresponding functional calculations or operations according to the stimulus input signal and outputs its state. Finally, the test vector is shifted out to shift the output or internal state of the circuit out through the scan chain, and by comparing it with the expected output, it is determined whether the circuit responds to the input signal correctly. Test vector shift-in is the process of inputting the generated test vector into the circuit through the scan chain. The scan chain is a series of flip-flops connected in series, allowing the test equipment to input test data into the circuit one by one; the capture operation is the process of stimulating the circuit and performing calculations or operations according to the test vector after the test vector is shifted in. This step usually involves the normal functional operation of the circuit, adding stimulus to the input of the functional circuit, and calculating the corresponding output based on the stimulus input. Test vector shift-out is the process of shifting the output or internal state of the circuit out of the flip-flops in the scan chain. Through the shift-out operation, the captured state (i.e., circuit response) can be extracted and compared with the expected output to determine whether the circuit is correct.

[0027] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0028] like Figure 1 As shown, the scan chain fault location method based on the dedicated chain diagnostic vector of the present invention includes the following steps.

[0029] S1: Read in the circuit netlist file into which the scan chain structure is inserted, analyze the circuit netlist after the scan chain is inserted, and determine the length of the scan chain.

[0030] S2: Inject stuck-at-1 and stuck-at-0 faults into the SI port of each scan trigger (referred to as trigger) in the scan chain to obtain a faulty circuit netlist.

[0031] S3: Determine the fault type of the scan chain through chain testing.

[0032] In the chain test, firstly, the periodic test vector 0011 is shifted into the scan chain, and the internal state of the circuit is stimulated by triggers one by one. Then the output state is directly shifted out for comparison analysis. If the shifted out values ​​are all 0 or all 1, it can be determined that the circuit has a stuck-at-0 or stuck-at-1 fault.

[0033] S4: after determining the scan chain fault type, a corresponding dedicated chain diagnostic vector is generated for each bit of the trigger. The dedicated chain diagnostic vector needs to be designed for each bit of the trigger. Assuming that the trigger fails, its downstream vector is set to the fault value; After determining the downstream value of each bit flip-flop, further analyze the circuit logic to identify the propagation path of the downstream flip-flops. Analyze these propagation paths to determine the impact range of the fault flip-flops on the downstream flip-flops. Set the corresponding positions of its downstream flip-flops in the dedicated chain diagnostic vector to the fault value to reduce the impact of the fault value on the functional circuit, thereby ensuring the controllability of the captured value.

[0034] S5: Generate dedicated chain diagnostic vectors corresponding to different triggers.

[0035] In order to ensure that the impact of the fault trigger is effectively controlled, it is necessary to analyze the circuit logic and clarify the upstream value of the test vector and the functional circuit input (PI) value. According to the type of fault trigger, adjust the PI input of the functional circuit input so that the fault trigger and the previous trigger can capture the opposite value of the fault trigger (i.e., the fault reverse value), thereby determining the complete scan chain dedicated chain diagnosis vector.

[0036] S6: Save the generated dedicated chain diagnostic vector and generate a corresponding testbench file for it to ensure that the diagnostic vector is correctly verified in the simulation.

[0037] S7: Use the generated testbench file to simulate the faulty circuit, input the generated dedicated chain diagnostic vector through the VCS simulation tool, obtain the simulation results, and observe the test_so port output.

[0038] S8: Analyze the simulation results to obtain the accurate fault location.

[0039] When a scan chain has a fault, the faulty flip-flop will change the shift-out value of its upstream flip-flop during the shift-out phase. By designing dedicated chain diagnostic vectors in advance, it is possible to ensure that the captured value remains unchanged, and use the characteristics of these vectors to diagnose the location of the faulty flip-flop.

[0040] The present invention is described in detail from five aspects below.

[0041] (1) Scan chain fault location method process based on dedicated chain diagnostic vector.

[0042] A complete scan chain fault location process is divided into eight stages, namely, reading circuit files, fault injection, fault type determination, circuit structure analysis, chain diagnostic vector generation, testbench generation, simulation, and fault location results. Since the traditional scan chain diagnosis process requires the addition of additional circuits to the design to increase overhead, the diagnostic efficiency is low, and the fault recognition accuracy is limited, in order to solve this problem, the present invention provides a scan chain fault location method based on a dedicated chain diagnostic vector, which solves the problems of low accuracy and slow diagnostic speed of the traditional method. The specific steps include: analyzing the circuit netlist, determining the scan chain length and injecting stuck-at-1 and stuck-at-0 faults; stimulating the scan chain trigger through the periodic test vector 0011, and determining the fault type by judging whether the output value is all 0 or all 1; simulating the fault of each trigger to generate the corresponding dedicated chain diagnostic vector, and analyzing the propagation path of the downstream trigger to reduce the impact of the fault value on the functional circuit; adjusting the input end of the functional circuit to ensure that the opposite value of the fault trigger is captured; finally, generating and simulating the verification diagnostic vector.

[0043] The present invention effectively improves the accuracy and speed of scan chain fault location. Compared with the traditional hardware-based scan chain diagnosis method, the present invention has significant advantages, especially in that it can efficiently implement fault diagnosis without adding additional hardware overhead. Traditional methods usually require the addition of additional diagnostic circuits or logic units to the circuit, which not only increases the chip area and power consumption, but may also affect the circuit performance. The present invention only relies on the scan chain and the generated diagnostic vectors, and completes fault location through a simulation process without modifying the hardware structure or introducing additional hardware modules, thereby effectively avoiding related problems.

[0044] In addition, the present invention designs a special diagnostic vector for each trigger, and combines it with circuit logic analysis to locate the fault more accurately. Each test vector is carefully designed, and the corresponding diagnostic vector can be selected for accurate stimulation according to different fault types, thereby reducing the number of chain diagnostic vectors, improving diagnostic coverage and accuracy, shortening the test cycle, and reducing test time.

[0045] (2) Scan chain fault injection.

[0046] After reading the circuit netlist file after inserting the scan chain, the stuck at fault injection link is added. According to the scan chain structure of the circuit, the stuck at fault is injected into the SI end of each trigger.

[0047] Reference Figure 2, taking the S27 circuit netlist in the standard test circuit ISCAS'85 as an example, G0, G1, G2, G3 ports are function input ports, G17 is function output port; tests_si is scan input port, tests_so is scan output port; SE is scan enable port, when SE=1, the test vector is moved from tests_si to SFF2, SFF1, SFF0, and the previous test vector is moved out from test_so port, when SE=0, the scan trigger D port captures data from the combinational logic. blif_clk_net is the clock port, which provides clock for the scan trigger and is connected to the clk port of the trigger; rst is the reset port, when rst=1, all SFFs are set to zero. After analyzing its scan chain structure, the SI ports of the triggers SFF0, SFF1, and SFF2 in each scan chain are injected with stuck at-0 and stuck at-1 faults respectively, and the generated fault netlist is saved to prepare for the subsequent simulation verification of the fault location.

[0048] (3) Chain testing determines the type of faults that exist in the scan chain.

[0049] During the chain test, the periodic test vector 0011 is first shifted into the scan chain, the internal state of the circuit is stimulated by triggers one by one, and its output value is directly shifted out for comparison analysis. If the shifted out values ​​are all 0 or all 1, it can be determined that the circuit has a stuck-at-0 or stuck-at-1 fault.

[0050] Reference Figure 3 For the S27 circuit chain test, the test vector sequence is {SFF2, SFF1, SFF0}. The 001 vector is moved in from the test_si port, and its output value is directly moved out for comparison and analysis. When the test_so port output is 111, it means that one or several triggers in the scan chain have a stuck-at-1 fault; when the test_so port output is SFF2, SFF1, SFF0=000, it means that one or several triggers in the scan chain have a stuck-at-0 fault; when the test_so port output is 001, it means that the scan chain has no faults.

[0051] (4) Analyze the circuit structure to generate chain diagnosis vectors.

[0052] After determining the scan chain fault type, a corresponding dedicated chain diagnostic vector is generated for each trigger. The trigger connected to the faulty trigger and test_so is its downstream trigger, and the trigger connected to test_si is its upstream trigger.

[0053] When a fault occurs, the fault flip-flop will change its downstream value, resulting in a change in the captured value. By designing a dedicated chain diagnostic vector, it is assumed that when a fault flip-flop fails, the value of its downstream flip-flop is set to the fault value, thereby ensuring that the dedicated chain diagnostic vector that is moved in is not affected and the captured value of the scan chain is stable.

[0054] The circuit logic is further analyzed to identify the propagation path of the downstream flip-flop and mask it to reduce the impact of the fault. At the same time, during the scan shift-in period, the faulty flip-flop only affects the downstream value and does not change the upstream value. By adjusting the value of the functional circuit input (PI), it is ensured that the flip-flop one bit above the faulty flip-flop captures its fault opposite value, thereby generating a complete chain diagnostic vector.

[0055] The following is an introduction through a case.

[0056] Assume that the result after the chain test is 111, indicating that there is a stuck-at-1 fault in the scan chain. At this time, the corresponding chain diagnostic vectors need to be generated for the three flip-flops. When a stuck-at-1 fault occurs at the SI end of SFF1, the value of SFF0 will be changed when the scan is shifted in, and it will be stuck at 1, thus affecting the capture value of the scan chain. Therefore, when designing the diagnostic vector corresponding to the stuck-at-1 fault of SFF1, the values ​​of SFF1 and SFF0 need to be set to 1 to ensure that the capture value of the scan chain will not be affected regardless of whether the SI port of SFF1 fails. Therefore, the test_si port is shifted into the vector test_si=11X. Among them, X represents a don't care bit.

[0057] During the scan shift-out cycle, the value of the upstream flip-flop in the scan chain will be affected by the fault of the downstream flip-flop. For example, when SFF1 is stuck-at-1, no matter what value SFF2 captures, the value of SFF2 will be stuck at 1 when it is shifted out. In order to make the stuck-at-1 fault of SFF1 intuitively observable, the captured value of SFF2 should be set to 0. Figure 4 As shown in the figure, by analyzing the S27 circuit, we know that the captured value of SFF2 comes from the nor_1 gate, whose signal is controlled by n1 and n2, and n2 is only connected to the G0 port through a NOT gate, which has good controllability. Therefore, setting the G0 port to 0 and n2 to 1 can ensure that the captured value of SFF2 is 0.

[0058] At the same time, the capture value of SFF1 is set to 0. When scanning the output, if the value of SFF1 is 0 and can be shifted out normally, and the value of SFF2 is stuck at 1, it means that the fault occurs at the SI end of SFF1. According to the S27 circuit diagram, the capture value of SFF1 is controlled by the nor_2 gate, and the nor_n2 gate is controlled by the Q end of SFF2. When the output of SFF2 is 1, the capture value of the D end of SFF1 is 0.

[0059] Finally, it is determined that the chain diagnosis vector when SFF1 has a stuck-at-1 fault is test_si=111, PI=G0,G1,G2,G3=0X1X.

[0060] Based on the above method, two types of fixed faults of each trigger are simulated separately. First, when a stuck-at-0 fault occurs in the scan chain, setting test_si=000 can ensure that the scan-in value will not be affected by the fault. According to calculations, when the input PI is G0, G1, G2, G3=X0X1, the expected captured value test_so=010, if the actual shifted-out value test_so=000, the 1 captured by SFF1 is stuck as 0, proving that the fault occurs at the SI port of SFF0. If the actual shifted-out value test_so=010, the 1 captured by SFF1 can be If the value is shifted out normally, it means that the fault occurs in the upstream scan unit of SFF0; when test_si=000, and the input PI is G0, G1, G2, G3=1XXX, the expected captured value test_so=101, if the actual shifted out value test_so=101, the 1 captured by SFF2 can be shifted out normally, which proves that the fault occurs in the SI port of SFF2; if the actual shifted out value test_so=001, the 1 captured by SFF2 is changed to 0 by the downstream fault card, which means that the fault occurs in the SI port of SFF1; Similarly, if a stuck-at-1 fault occurs in the scan chain, setting test_si=111 can ensure that the scan shift-in process will not be affected by the stuck-at-1 fault. After calculation, when PI=G0,G1,G2,G3= 0011, the expected captured value test_so=000. Observe the shift-out value. If test_so=110, the fault occurs in SFF0; if test_so=100, the fault occurs in SFF1; if test_so=000, the fault occurs in SFF2.

[0061] In summary, for the fault diagnosis of the S27 circuit chain, the following diagnostic vectors are obtained: When stuck-at-1: pattern0: test_si=111, G0123=0X1X, test_so=000; When stuck-at-0: pattern0: test_si=000, G0123=X0X1, test_so=010; pattern1: test_si=000, G0123=1XXX, test_so=101; For stuck-at-0 faults, only two chain diagnostic vectors are needed, while for stuck-at-1 faults, only one chain diagnostic vector is needed to achieve accurate positioning. These diagnostic vectors can effectively locate the fault and accurately identify the location where the fault occurs.

[0062] (5) Save the chain diagnostic vector to generate a testbench file for simulation.

[0063] After obtaining the chain diagnosis vector of each trigger, its irrelevant bit X is randomly filled, and fault simulation is performed to obtain the capture value corresponding to each vector.

[0064] Reference Figure 5 , the STIL file format of the dedicated chain diagnostic vector is as follows. `pattern 0` indicates the 0th dedicated chain diagnostic vector, which is the dedicated chain diagnostic vector. In the `load_unload` stage, that is, the shift-in stage, the value of `test_si` is 001. In the `multiclock_capture` stage, the value of the `_pi` port is composed of the 11 input ports of the circuit, that is, `_pi= G0 + G1 + G2 + G3 + blif_clk_net + reset + scan_clk + scan_rst + test_mode+ test_se + test_si`. In this stage, by applying one or more clock cycles, the trigger is able to capture the signal in the functional circuit, and the `_po` port value is measured, `_po = G17 + test_so`, where H is high level 1 and L is low level 0. During the chain test process, since the circuit is not captured and the dedicated chain diagnostic vector is only shifted in and out, the `test_se` value is set to 1, which means that the trigger still obtains the value from the previous trigger.

[0065] After the chain diagnostic vector is organized into a stil format file, the corresponding testbench file can be generated and the circuit can be simulated through VCS and the simulation results can be observed through Verdi. After simulating the circuit, the generated `.fsdb` waveform file can be used to observe the simulation results through the Verdi tool. Figure 6 , is the chain test result. After the dedicated chain diagnostic vector `001` is input into the `test_si` port, the result shifted out from the `test_so` port is `111` in the `pattern1` cycle. This result indicates that there is a stuck-at-1 fault in the scan chain.

[0066] Reference Figure 7, which is the STIL file of the chain diagnosis vector corresponding to the stuck-at-1 fault found after the S27 circuit chain test. In the `load_unload` stage, the value of `test_si` is 111 in the shift-in stage. In the `multiclock_capture` stage, pi=0011P010100 is set, where G0, G1, G2, G3=0011, and blif_clk_net=P means applying a clock pulse. After saving, the testbench file is generated and the simulation results are observed.

[0067] Reference Figure 8 , the value shifted into `test_si` is 111, and when the capture clock is triggered, G0, G1, G2, G3 = 0011, and the result of shifting out of the `test_so` port is 000, and no value is stuck at 1. However, the result of the chain test shows that there is a stuck-at-1 fault in the scan chain, so it can be determined that the stuck-at-1 fault occurs at the SI port of SFF0.

[0068] The scan chain fault location system based on the dedicated chain diagnostic vector of the present invention comprises: A fault type test unit, used to determine the fault type existing in the scan chain of the functional circuit to be tested through a chain test, wherein the fault type is a stuck-at-1 fault or a stuck-at-0 fault, and the corresponding fault value is 1 or 0; A dedicated chain diagnostic vector generating unit is used to generate a corresponding dedicated chain diagnostic vector for each bit of the trigger, wherein the corresponding position of the trigger and its downstream trigger is set to a fault value according to the fault type; and adjust the input value of the functional circuit so that the previous trigger of the trigger captures the opposite value of the fault value; The scan chain fault test unit is used to perform a scan chain fault test using the dedicated chain diagnostic vector to obtain a trigger position where a fault occurs.

[0069] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the scan chain fault location method based on the dedicated chain diagnostic vector is implemented.

[0070] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the method for locating a scan chain fault based on a dedicated chain diagnostic vector is implemented.

[0071] The computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store program code in the form of instructions or data structures and that can be accessed by a computer.

[0072] The processor is used to execute the computer program stored in the memory to implement each step of the method involved in the above embodiment.

Claims

1. A scan chain fault location method based on a dedicated chain diagnostic vector, characterized in that: The steps include: Step 1, determining the fault type existing in the scan chain of the functional circuit to be tested through chain testing, wherein the fault type is a stuck-at-1 fault or a stuck-at-0 fault, and the corresponding fault value is 1 or 0; Step 2, generating a corresponding dedicated chain diagnostic vector for each bit of trigger, wherein the corresponding position of the trigger and its downstream trigger is set to a fault value according to the fault type; adjusting the input value of the functional circuit so that the previous trigger of the trigger captures the opposite value of the fault value; Step 3: Perform a scan chain fault test using the dedicated chain diagnostic vector to obtain the location of the trigger where the fault occurs.

2. The scan chain fault location method based on dedicated chain diagnostic vector according to claim 1, characterized in that: In step 1, read the circuit netlist file after inserting the scan chain, inject stuck-at-1 and stuck-at-0 faults into each trigger in the scan chain, and obtain the faulty circuit netlist; Use periodic test vectors to perform chain testing to determine the type of faults present in the functional circuit scan chain.

3. The scan chain fault location method based on dedicated chain diagnostic vector according to claim 1, characterized in that: In step 2, in the dedicated chain diagnostic vector, the corresponding position of the upstream trigger of the trigger is a don't care bit, which is randomly set to 0 or 1.

4. The scan chain fault location method based on dedicated chain diagnostic vector according to claim 1, characterized in that: In step 2, the method of adjusting the input value of the functional circuit so that the previous trigger of the trigger captures the opposite value of the fault value includes: Set constraints, input ports and output ports. The constraint is that the corresponding positions of the trigger and its downstream triggers in the dedicated chain diagnostic vector are fault values. By traversing all possible input combinations to calculate the output of the functional circuit, an input combination that meets the constraints is obtained.

5. The scan chain fault location method based on dedicated chain diagnostic vector according to claim 1, characterized in that: In step 2, the capture value of the flip-flop is set to the opposite value of the fault value.

6. The scan chain fault location method based on dedicated chain diagnostic vector according to claim 1, characterized in that: Step 3 specifically includes saving the chain diagnosis vector and generating its corresponding testbench file, and performing a scan chain fault test using the testbench file to obtain the location of the trigger where the fault occurs.

7. A scan chain fault location system based on a dedicated chain diagnostic vector, characterized in that: include: A fault type test unit, used to determine the fault type existing in the scan chain of the functional circuit to be tested through a chain test, wherein the fault type is a stuck-at-1 fault or a stuck-at-0 fault, and the corresponding fault value is 1 or 0; A dedicated chain diagnostic vector generating unit is used to generate a corresponding dedicated chain diagnostic vector for each bit of the trigger, wherein the corresponding position of the trigger and its downstream trigger is set to a fault value according to the fault type; and adjust the input value of the functional circuit so that the previous trigger of the trigger captures the opposite value of the fault value; The scan chain fault test unit is used to perform a scan chain fault test using the dedicated chain diagnostic vector to obtain a trigger position where a fault occurs.

8. The scan chain fault location system based on dedicated chain diagnostic vector according to claim 7, characterized in that: In the fault type test unit, read the circuit netlist file after inserting the scan chain, inject stuck-at-1 and stuck-at-0 faults into each trigger in the scan chain, and obtain the faulty circuit netlist; Use periodic test vectors to perform chain testing to determine the type of faults present in the functional circuit scan chain; In the dedicated chain diagnostic vector generation unit, in the dedicated chain diagnostic vector, the corresponding position of the upstream flip-flop of the flip-flop is a don't care bit and is randomly set to 0 or 1; In a dedicated chain diagnostic vector generation unit, a method for adjusting a functional circuit input value so that an upper trigger of the trigger captures an opposite value of a fault value includes: Set constraints, input ports and output ports, where the constraints are that the corresponding positions of the trigger and its downstream triggers in the dedicated chain diagnostic vector are fault values, and calculate the output of the functional circuit by traversing all possible input combinations to obtain input combinations that meet the constraints; In the dedicated chain diagnostic vector generation unit, the capture value of the flip-flop is set to the opposite value of the fault value; In the scan chain fault test unit, the chain diagnosis vector is saved and the corresponding testbench file is generated. The scan chain fault test is performed using the testbench file to obtain the trigger position where the fault occurs.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into a processor, the scan chain fault location method based on a dedicated chain diagnostic vector is implemented according to any one of claims 1 to 6.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the scan chain fault location method based on a dedicated chain diagnostic vector is implemented according to any one of claims 1 to 6.

Images