A highly integrated multi-channel data acquisition and processing system based on RFSoC and FPGA

Abstract

The present invention provides a highly integrated multi-channel data acquisition and processing system based on RFSoC and FPGA. For N arrays of N*M acquisition channels, the ADC data acquisition preprocessing module is N RFSoCs, and the ADC acquisition data scheduling module is 1 FPGA; the FPGA includes two types of FIFOs, namely, a cross-clock domain FIFO and a data cache FIFO, and a real-time scheduling module; the real-time scheduling module provides a matching and efficient data scheduling transmission strategy for multiple ADC data acquisition preprocessing modules based on RFSOC, and when the cross-clock domain FIFO is not empty, the data cached in the cross-clock domain FIFO is read out and written to the corresponding data cache FIFO; when a data cache FIFO is not empty, each data cache FIFO is polled in turn, and when a data cache FIFO is not empty and the corresponding frame end identifier is true, the data cached in the data cache FIFO and the array number and the optical fiber number of the corresponding optical fiber channel are read out and written to the FPGA output interface for data transmission. The present invention can effectively reduce the PCB board area and reduce system power consumption.

Description

Technical Field

[0001] The present invention relates to a multi-array multi-channel data acquisition and preprocessing technology, and in particular to a highly integrated multi-channel data acquisition and processing system based on a radio frequency system-on-chip (RFSoC) and a field programmable gate array (FPGA). Background Art

[0002] The multi-channel data acquisition and processing system mainly includes a multi-channel analog-to-digital conversion ADC data acquisition preprocessing module and a multi-channel ADC acquisition data scheduling module based on a high-performance field programmable gate array FPGA. With the continuous development of radar, communication and digital beamforming technology, high-performance data synchronization acquisition and preprocessing and data scheduling systems play an increasingly important role in these fields, especially in multi-array multi-channel data acquisition and signal processing, which requires the system to have real-time signal processing and real-time data transmission capabilities. For example, the multi-array antenna in the radar system needs to collect signals from multiple antenna arrays in parallel, and complete signal scheduling, data conversion, real-time processing and other functions, so as to achieve detection and tracking of targets. At the same time, in digital beamforming, it is necessary to collect and accurately schedule multi-array and multi-channel data, so as to achieve accurate estimation of the direction of the signal source and efficient interference suppression.

[0003] At present, the common solution is to use traditional high-performance ADC chips + FPGA to complete the real-time acquisition and preprocessing of multi-array multi-channel RF, and then use the FPGA's high-speed transmission capability to send the processed signal data to the data processing server to achieve specific functions. However, in actual applications, the above solution faces the problems of difficulty in synchronizing multiple ADC acquisition channels, large area of ​​PCB printed circuit boards composed of multiple ADC + FPGA chips, and high power consumption. For example, for an N-array antenna, each array has M acquisition channels, then N*M high-performance ADC chips are required for data acquisition preprocessing, N FPGAs are required to schedule the acquisition data of each array, and an additional module for scheduling the N array data is required. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a highly integrated multi-channel, high-frequency, and large-bandwidth system based on RFSoC to realize signal synchronous acquisition, real-time signal processing, and data transmission functions.

[0005] The technical solution adopted by the present invention to solve the above technical problems is a highly integrated multi-channel data acquisition and processing system based on RFSoC and FPGA, including an ADC data acquisition preprocessing module and an ADC acquisition data scheduling module; characterized in that, for N arrays of N*M acquisition channels, the ADC data acquisition preprocessing module is N RFSoCs, and the ADC acquisition data scheduling module is 1 FPGA;

[0006] Each RFSoC is used to complete parallel synchronous data acquisition and preprocessing for M acquisition channels of an array, package the preprocessed M acquisition channel data through the data packaging and sending unit, and output them to the FPGA in parallel through J fiber channels;

[0007] The FPGA includes two types of FIFO caches and a real-time scheduling module, wherein the two types of FIFO caches are cross-clock domain FIFOs and data cache FIFOs; one optical fiber channel corresponds to one cross-clock domain FIFO and one data cache FIFO, and a frame end identifier is set accordingly;

[0008] The cross-clock domain FIFO is used to cache the data from the corresponding fiber channel of the RFSoC, in response to the real-time scheduling module;

[0009] The data buffer FIFO is used to buffer data from the corresponding cross-clock domain FIFO, responsive to the real-time scheduling module;

[0010] The real-time scheduling module is used to read the cached data of the cross-clock domain FIFO and write it to the corresponding data cache FIFO when the cross-clock domain FIFO is not empty; when the cached data read out of the clock domain FIFO is the end of the data packet frame, set the end of frame flag to true;

[0011] When a data cache FIFO is not empty, the real-time scheduling module enters the data scheduling state and polls each data cache FIFO in turn. When a data cache FIFO is not empty and the corresponding frame end flag is true, the data cached in the data cache FIFO and the array number and fiber channel number of the corresponding fiber channel are read out and written to the FPGA output interface for data transmission. After the transmission is completed, the frame end flag corresponding to the fiber channel is set to false, and then each data cache FIFO continues to be polled; when all data cache FIFOs are empty, the real-time scheduling module enters the idle state.

[0012] The present invention adopts a multi-channel synchronous acquisition and preprocessing module based on RFSoC to replace the traditional M ADC chips + FPGA solution, and a highly integrated multi-channel data acquisition and processing system of N RFSoCs and 1 FPGA to replace the traditional N×MADC chips + N FPGAs + 1 general scheduling module solution. Multiple ADC acquisition channels and FPGAs are integrated into one RFSoC chip, which can effectively reduce the PCB board area and reduce system power consumption.

[0013] Specifically, the multi-channel synchronous acquisition and preprocessing module based on RFSoC includes an acquisition channel formed by M analog-to-digital conversion units ADC, digital down-conversion units DDC and finite-length unit impulse response FIR extraction filters connected in series, and a data packaging and transmission unit. The data packaging and transmission unit is connected to the ADC acquisition data scheduling module through a high-speed optical fiber interface, and the communication rate of each optical fiber interface is as high as 25Gbps, which can ensure low data latency for the entire system.

[0014] The two types of FIFO high-speed signal cache and real-time scheduling modules in the FPGA of the present invention can ensure that the N array N*M acquisition channels and the pre-processed signal data are quickly and accurately transmitted to the back-end computing server through the output interface of the FPGA to complete further signal processing or data processing to achieve specific functions.

[0015] The beneficial effect of the present invention is that it can provide a matching and efficient data scheduling and transmission strategy for multiple RFSOC-based ADC data acquisition preprocessing modules, ensure the real-time and accuracy of the entire data stream, and effectively reduce the PCB area and system power consumption. It has broad application prospects in the fields of radar, digital beamforming, etc. that have high requirements on system power consumption and system synchronization performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the embodiment system and real-time data scheduling. DETAILED DESCRIPTION

[0017] The specific implementation modes of the present invention are described clearly and completely below in conjunction with the accompanying drawings so that those skilled in the art can better understand the invention.

[0018] Figure 1 The figure shows a highly integrated multi-channel data acquisition preprocessing system block diagram based on RFSoC and high-performance FPGA, which mainly includes ADC data acquisition preprocessing module based on RFSoC and ADC acquisition data scheduling module based on high-performance FPGA. Considering different application scenarios, the number of arrays, the number of RFSoC synchronous acquisition preprocessing modules, and the number of high-speed signal channels can be flexibly configured.

[0019] The ADC data acquisition preprocessing module is N RFSoCs, and the ADC data acquisition scheduling module is 1 FPGA.

[0020] Each RFSoC includes M acquisition channels and 1 data packaging and sending unit; each RFSoC completes the synchronous data acquisition of multi-channel high-frequency and large-bandwidth signals for the M acquisition channels of an array in parallel, and the data packaging and sending unit based on the internal FPGA module of RFSoC then pre-processes and sends the acquired signals.

[0021] Each acquisition channel is formed by connecting an analog-to-digital converter (ADC), a digital down-conversion unit (DDC), and a finite-length unit impulse response (FIR) extraction filter in series. For an N-array M-channel antenna array, each output channel of each array is connected to one acquisition channel of the RFSoC via an RF cable.

[0022] The FPGA includes two types of FIFO caches, namely, cross-clock domain FIFO and data cache FIFO, for high-speed signal cache, and a real-time scheduling module. The input end of the FPGA is connected to N RFSoCs, and the output end is connected to the data processing server. N RFSoCs are connected to the FPGA via optical fibers. The FPGA caches the data sent by the N RFSoCs, and based on the real-time data scheduling method, sends the collected data to the back-end data processing server through PCIE for further processing.

[0023] In order to save FPGA high-speed interface resources, the data packaging and sending unit can package the data of M acquisition channels into data packets of J fiber channels for transmission, where J≤M, and J is determined by the fiber transmission rate and the total bandwidth of the M acquisition channel data.

[0024] One fiber channel corresponds to one cross-clock domain FIFO and one data cache FIFO. Both the cross-clock domain FIFO and the data cache FIFO include internal instantiations of J FIFO IPs, forming a FIFO matrix to cache data sent by multiple RFSoCs. The cross-clock domain FIFO is used to cache data from the corresponding fiber channel of the RFSoC, and the data cache FIFO is used to cache data from the corresponding cross-clock domain FIFO, both of which respond to the real-time scheduling module.

[0025] The present invention designs an efficient data scheduling and transmission method that matches multiple RFSoCs and is implemented by a real-time scheduling module. The data cached in the FIFO matrix is ​​scheduled and sent to a computing server through a high-speed serial computer expansion bus standard PCIe interface for further signal or data processing, thereby ensuring the real-time and accuracy of the entire data flow.

[0026] When the cross-clock domain FIFO is not empty, the real-time scheduling module reads the cached data of the cross-clock domain FIFO and writes it to the corresponding data cache FIFO; when the real-time scheduling module reads the cached data of the clock domain FIFO as the end of the data packet frame, the frame end flag is set to true.

[0027] When a data cache FIFO is not empty, the real-time scheduling module enters the data scheduling state and polls each data cache FIFO in turn. When a data cache FIFO is not empty and the corresponding frame end flag is true, the data cached in the data cache FIFO and the array number and fiber channel number of the corresponding fiber channel are read out and written to the FPGA output interface for data transmission. After the transmission is completed, the frame end flag corresponding to the fiber channel is set to false, and then each data cache FIFO continues to be polled; when all data cache FIFOs are empty, the real-time scheduling module enters the idle state.

[0028] In the embodiment, setting the end of frame flag to true is achieved by pulling the end of frame flag high, and setting the end of frame flag to false is achieved by pulling the end of frame flag low. The empty flag of FIFO is used to characterize the state of FIFO as empty or non-empty. Pulling the empty flag high indicates empty, and pulling the empty flag low indicates non-empty. Pulling high sets the flag bit to 1, and pulling low sets the flag bit to 0.

[0029] When the system is working, RFSoC completes the synchronous acquisition of the RF signals of each array and converts them into digital signals. The synchronization performance between the internal acquisition channels is determined by the internal signals of RFSoC, and the synchronization accuracy can reach ±1 / Ts, Ts=1 / Fs, Fs is the set sampling frequency. Then the sampled digital signal is sent to the FPGA inside RFSoC by the Axi-stream interface inside the chip for signal preprocessing. Signal preprocessing includes digital down-conversion of the signal, extraction and filtering processing, etc. It is worth mentioning that the multiple ADC acquisition channels integrated in RFSoC also integrate hard IPs such as digital down-conversion and extraction and filtering. Digital down-conversion and extraction and filtering processing of the collected signals can be realized through flexible parameter configuration to save FPGA logic resources. At the same time, these hard IP modules can also be used in conjunction with the extraction and filtering modules implemented in the hardware description language Verilog inside the FPGA to meet the final needs of the system.

[0030] When RFSoC completes the synchronous acquisition and preprocessing of RF signals, the data packaging and sending unit packages the data of M acquisition channels into J fiber channels and sends them to FPGA in parallel, and marks each acquisition data with the frame header and frame tail. The FPGA-based high-speed signal cache and real-time scheduling module implements multiple high-speed fiber transmission channels and is responsible for receiving and caching the signal data sent by multiple RFSoC modules.

[0031] The FPGA uses a FIFO matrix to cache these data. The first column of FIFOs is a cross-clock domain FIFO, which realizes the conversion from the data interface clock domain to the internal working clock domain of the FPGA. The second column of FIFOs is a data cache FIFO, which realizes the cache of the signal data of each acquisition channel. When the cross-clock domain FIFO is not empty, the FIFO data is immediately read out and written into the data cache FIFO. When the read data is the end of the data packet frame, the frame end flag of the current FIFO is pulled high. At the same time, the empty flag of each data cache FIFO is sent to the real-time scheduling module. When the logical AND result of the empty flags of all fiber channels is 0, it means that there is cached data. When the logical AND result of the empty flags of all fiber channels is 1, it means that there is no cached data.

[0032] When the high-speed signal cache and scheduling module is powered on, the real-time data real-time scheduling module works in an idle state. When the empty flag of any data cache FIFO is pulled low, it means that the current array has data to be sent, thereby entering the data scheduling state, and then polling the status of each data cache FIFO in the second column in turn. If the current data cache FIFO is not empty when polled and the frame tail flag of the current FIFO is high, the array number and fiber number corresponding to the current FIFO are written as the first data to be sent, and then the signal data is read from this FIFO in turn and sent to the PCIE module until the frame tail of the current data frame is read. At this time, the signal data of this frame has been completely sent to the back-end data processing server. After the current data frame is sent, the frame tail flag is pulled low. Then continue to poll the status of each FIFO until all data has been sent, and enter the idle state to wait for the arrival of the next signal data.

[0033] So far, a highly integrated multi-channel data acquisition preprocessing and signal data real-time scheduling system based on RFSoC and high-performance FPGA has been realized. Taking the four-sided array radar as an example, the system is implemented according to the above method.

[0034] Set the application scenario: four-array radar, each array collects target echo signals in five acquisition channels, including sum, difference, difference, and two auxiliary channels, according to the conventional radar system. Figure 1 N=4, M=5. The signal sampling rate is 1GHz, the center frequency is 240MHz, the signal bandwidth is 40MHz, the decimation factor is 20 times, and the signal sampling rate after decimation is 50MHz. N arrays, N RFSoCs. Each array has M RF channels, and the array antenna with N arrays has N*M acquisition channels.

[0035] Four RFSoC synchronous acquisition modules are used to synchronously sample signals from four arrays, a total of 20 RF channels. The sampled data signals are digitally down-converted and filtered by the down-conversion and extraction filtering modules integrated inside the RFSoC, and a 20-fold decimation filtering process is performed to obtain a baseband echo signal with a sampling rate of 50MHz (I, Q data, each I, Q data occupies 2 bytes).

[0036] The 5-channel echo data is packaged and marked with frame headers and tails by the data packaging and sending unit, and then sent to the high-speed signal cache and real-time scheduling module through a fiber channel. Figure 1 J = 2. The echo signal data rate is 50MHz*2 (I, Q data)*2 (two bytes for each data)*5 (acquisition channel)*8 (bits) = 8Gbps, which is less than the high-speed signal buffer and real-time scheduling module high-speed optical fiber rate: 2*25Gbps.

[0037] At the same time, a 4-row 2-column (N-row 2-column) FIFO matrix is ​​instantiated inside the high-speed signal buffer and real-time scheduling target for cross-clock domain processing of echo data. The first column of FIFO is used for cross-clock domain processing, and the second column of FIFO is used as data buffer.

[0038] Based on the real-time data real-time scheduling module, data is scheduled for each array FIFO and sent to the back-end data processing server through PCIE to realize radar functions such as target detection and recognition.

[0039] At this point, a highly integrated multi-array multi-channel data acquisition preprocessing and signal data real-time scheduling system can be realized based on RFSoC and high-performance FPGA. Although the above describes the illustrative specific implementation of the present invention to facilitate the understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific implementation. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. A highly integrated multi-channel data acquisition and processing system based on RFSoC and FPGA, including an ADC data acquisition preprocessing module and an ADC acquisition data scheduling module; characterized in that: For N arrays with N*M acquisition channels, the ADC data acquisition preprocessing module is N radio frequency system-level chips RFSoC, and the ADC acquisition data scheduling module is a field programmable gate array FPGA; After each RFSoC completes synchronous data acquisition and preprocessing for the M acquisition channels of an array in parallel, it packages the preprocessed data of the M acquisition channels and outputs them in parallel to the FPGA through the optical fiber channel; The FPGA includes two types of FIFO caches and a real-time scheduling module, wherein the two types of FIFO caches are cross-clock domain FIFOs and data cache FIFOs; one optical fiber channel corresponds to one cross-clock domain FIFO and one data cache FIFO, and a frame end identifier is set accordingly; The cross-clock domain FIFO is used to cache the data from the corresponding fiber channel of the RFSoC, in response to the real-time scheduling module; The data buffer FIFO is used to buffer data from the corresponding cross-clock domain FIFO, responsive to the real-time scheduling module; The real-time scheduling module is used to read the cached data of the cross-clock domain FIFO and write it to the corresponding data cache FIFO when the cross-clock domain FIFO is not empty; when the cached data read out of the clock domain FIFO is the end of the data packet frame, set the end of frame flag to true; When a data cache FIFO is not empty, the real-time scheduling module enters the data scheduling state and polls each data cache FIFO in turn. When a data cache FIFO is not empty and the corresponding frame end flag is true, the data cached in the data cache FIFO and the array number and fiber channel number of the corresponding fiber channel are read out and written to the FPGA output interface for data transmission. After the transmission is completed, the frame end flag corresponding to the fiber channel is set to false, and then each data cache FIFO continues to be polled; when all data cache FIFOs are empty, the real-time scheduling module enters the idle state.

2. The system according to claim 1, characterized in that: The RFSoC includes M acquisition channels and 1 data packaging and sending unit; each acquisition channel is formed by connecting an analog-to-digital conversion unit ADC, a digital down-conversion unit DDC and a finite-length unit impulse response FIR extraction filter in series.

3. The system according to claim 2, characterized in that: The digital down-conversion unit DDC and the finite-length unit impulse response FIR extraction filter in RFSoC are implemented in the hard IP of the ADC acquisition channel integrated inside RFSoC.

4. The system according to claim 3, characterized in that: The data packaging and sending unit in RFSoC is implemented by the FPGA module inside RFSoC.

5. The system according to claim 4, characterized in that: The data packaging and sending unit can package the data of M acquisition channels into data packets of J optical fiber channels for sending, where J≤M, and J is determined by the optical fiber transmission rate and the total bandwidth of the M acquisition channel data.

6. The system according to claim 5, characterized in that: The digital down-conversion unit DDC and the finite-length unit impulse response FIR extraction filter in RFSoC are implemented through the hard IP of the ADC acquisition channel integrated inside RFSoC and the hardware description language Verilog of the FPGA module inside RFSoC.

7. The system according to claim 1, characterized in that: The write clock of the cross-clock domain FIFO uses the clock domain of the input interface of the FPGA, and the read clock of the cross-clock domain FIFO uses the working clock domain inside the FPGA.

8. The system according to claim 1, characterized in that: The output interface of FPGA is the high-speed serial computer expansion bus standard PCIe interface.

9. The system according to claim 1, characterized in that: The output interface of the FPGA is connected to the data processing server.

10. The system according to claim 1, characterized in that: RFSoC and FPGA are connected via optical fiber.

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