Serial through techniques for memory device interfaces

Abstract

The invention relates to a serial through technology for a memory device interface. Memory interface circuitry may be configured to receive a command via a first interface having a first set of terminals to configure the memory interface circuitry to a pass-through mode. As part of the pass-through mode, the memory interface circuitry may receive data from an external device via the first interface and output the data to one or more memory devices via a second interface having a second set of terminals. In some examples, the received data may be associated with a write burst, where the memory interface circuitry may serially receive portions of the data for writing to a buffer of the memory interface circuitry. Upon reaching a threshold number of data, the buffer may output the portion of the data to the one or more memory devices via the second interface.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 774,431, filed by Hanna et al. on July 16, 2024, entitled “SERIAL PASS-THROUGH TECHNIQUES FOR MEMORY DEVICE INTERFACES,” and U.S. patent application No. 63 / 587,962, filed by Hanna et al. on October 4, 2023, entitled “SERIAL PASS-THROUGH TECHNIQUES FOR MEMORY DEVICE INTERFACES,” each of which is assigned to its assignee and the entire contents of each of which are expressly incorporated herein by reference.

[0003] TECHNICAL FIELD The field relates to serial pass-through technology for memory device interfaces. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long time, even in the absence of external power. Memory cells configured in a volatile configuration lose their stored state when disconnected from the external power source. Summary of the invention

[0006] A memory system is described. The memory system may include: a memory interface circuit system that is operable to couple with one or more memory devices; and a processing circuit system that is coupled to the memory interface circuit system and is configured so that the memory system: receives a command at the memory interface circuit system via a plurality of first terminals to configure the memory interface circuit system to receive data associated with a write burst, the plurality of first terminals being associated with a first number of terminals; writes the first portion of the data to a buffer of the memory interface circuit system during a first duration based at least in part on receiving the first portion of the data via the plurality of first terminals; writes the second portion of the data to the buffer of the memory interface circuit system during a second duration after the first duration based at least in part on receiving the second portion of the data via the plurality of first terminals; outputs the first portion of the data and the second portion of the data from the buffer to the one or more memory devices via a plurality of second terminals based at least in part on determining that an amount of data written to the buffer satisfies a threshold, the plurality of second terminals being associated with a second number of terminals greater than the first number of terminals.

[0007] A memory system is described. The memory system may include: a memory interface circuit system that is operable to couple with one or more memory devices; and a processing circuit system that is coupled to the memory interface circuit system and configured so that the memory system: receives a first command at the memory interface circuit system via a plurality of first terminals to write an indication of the one or more memory devices, the plurality of first terminals being associated with a first number of terminals; writes the indication of the one or more memory devices to the memory interface circuit system based at least in part on receiving the first command; receives a second command at the memory interface circuit system via the plurality of first terminals to configure the memory interface circuit system to generate a data sequence based at least in part on writing the indication; writes a first portion of the data sequence to a buffer of the memory interface circuit system based at least in part on generating the data sequence; outputs the first portion of the data sequence from the buffer to the one or more memory devices via a plurality of second terminals based at least in part on determining that an amount of data written to the buffer satisfies a threshold; and writes a second portion of the data sequence to the buffer based at least in part on generating the data sequence and transmitting the first portion.

[0008] A system is described. The system may include: one or more memory devices; a plurality of first terminals; a plurality of second terminals; a memory system controller coupled to the one or more memory devices and to the plurality of second terminals; and a memory interface circuit system coupled to the one or more memory devices and to the plurality of first terminals, the memory interface circuit system including a buffer and configured to: receive a command via the plurality of first terminals to configure the memory interface circuit system to receive data associated with a write burst; receive a first portion of the data written to the buffer via the plurality of first terminals during a first duration; receive a second portion of the data written to the buffer via the plurality of first terminals during a second duration after the first duration; and concurrently output the first portion of the data and the second portion of the data from the buffer to at least one of the one or more memory devices based at least in part on determining that an amount of data written to the buffer satisfies a threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting serial pass-through technology for a memory device interface according to examples disclosed herein is shown.

[0010] Figure 2 An example of memory interface circuitry supporting serial pass-through techniques for memory device interfaces according to examples disclosed herein is shown.

[0011] Figure 3 An example of a timing diagram supporting serial pass-through techniques for a memory device interface according to examples disclosed herein is shown.

[0012] Figure 4 An example of a memory interface architecture supporting serial pass-through technology for a memory device interface according to examples disclosed herein is shown.

[0013] Figure 5 A block diagram of a memory interface supporting serial pass-through technology for a memory device interface according to examples disclosed herein is shown.

[0014] Figure 6 and 7 A flow chart illustrating a method of supporting serial pass-through technology for a memory device interface according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0015] Some memory systems may implement a first interface, such as an open NAND flash interface (ONFI), to support communication between a memory system controller and one or more memory devices of the memory system. Additionally or alternatively, some memory systems may implement a second interface, such as a single command address (SCA) interface, which may alternatively be referred to as a single command interface or an independent command address (iCAD) interface, to support communication between a memory system (such as one or more memory devices of the memory system) and an external device (such as a host system or a tester device). In some examples, the second interface may support a pass-through mode to allow an external device to directly access one or more memory devices (such as raw NAND) of the memory system, which may include components that bypass the memory system controller. This pass-through mode may support various functionalities, such as allowing a manufacturer or integrator to test a memory device without implementing or accessing additional firmware that communicates with the memory system controller. Furthermore, this pass-through mode may allow a relatively uncomplex device (such as a device associated with a step-down market) to access a memory device without operating or otherwise implementing a relatively more complex memory system controller (e.g., omitting the memory system controller). However, some implementations of the second interface may support limited accessibility to the memory device (eg, fail to support aspects of pass-through mode bypassing the memory system controller).

[0016] As described herein, the memory interface circuit system is operable to couple with one or more memory devices and support a serial pass-through mode for accessing one or more memory devices. For example, the memory interface circuit system may be configured to receive a command via a first interface (e.g., an SCA interface) having a first set of terminals to configure the memory interface circuit system to a pass-through mode (e.g., a serial pass-through mode (SPTM)). As part of the pass-through mode, the memory interface circuit system may be configured to receive data from an external device via a first interface and output the data to one or more memory devices via a second interface (e.g., an ONFI interface) having a second set of terminals. In some examples, receiving data may be associated with a write burst, wherein the memory interface circuit system may serially receive multiple (e.g., two or more) portions of data to be written to a buffer of the memory interface circuit system. After reaching a threshold number of data, the buffer may output a portion of the data (e.g., concurrently, in parallel) to one or more memory devices via a second interface. In such examples, the memory interface circuit system may output a portion of the data based on the buffer storing a threshold number of data (e.g., in response to or otherwise based on the buffer becoming full). Configuring the memory interface circuitry to support a pass-through mode may allow an external device to bypass aspects of the memory system controller and thereby may provide the external device with direct access to one or more memory devices according to a simplified interface (e.g., using fewer terminals, according to a reduced command set, according to a reduced clock rate or data rate, according to reduced capabilities) relative to other interfaces.

[0017] In addition to being applied in the memory systems described herein, the techniques for serial pass-through technology for memory device interfaces may generally be implemented to support increased connectivity of electronic systems. As the use of systems that rely on interconnected electronic devices increases, the connectivity of these electronic devices becomes an increasingly relevant factor in the operation of the system. For example, delays associated with signals communicated between devices may become increasingly relevant as critical systems become more dependent on connectivity, as systems use a greater number of interconnected devices or if the number and complexity of signals communicated between devices increases. Implementing the techniques described herein may support techniques for increased connectivity in electronic systems by allowing increased flexibility in the types of test devices, which may increase the adaptability and use cases of electronic systems, as well as other benefits.

[0018] First, in reference Figure 1 Features of the present disclosure are described in the context of systems and devices. Figures 2 to 4 Features of the present disclosure are described in the context of memory interface circuitry and timing diagrams. Figures 5 to 7 These and other features of the present disclosure are further illustrated and described in the context of device diagrams and flow diagrams related to serial pass-through techniques for memory device interfaces.

[0019] Figure 1 An example of a system 100 supporting serial pass-through technology for a memory device interface according to examples disclosed herein is shown. The system 100 includes a host system 105 coupled to a memory system 110. The system 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device including a memory and a processing device.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

[0021] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). For example, the host system 105 may use the memory system 110 to write data to the memory system 110 and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0022] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate (e.g., exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105) via the physical host interface using an associated protocol. Examples of physical host interfaces may include, but are not limited to, an SCA interface, an iCAD interface, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM slot interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0023] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells, such as non-volatile memory cells, volatile memory cells, or any combination thereof. Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled and communicated with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled and communicated with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130, and other such operations, which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and the one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert responses (eg, data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105 .

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refreshes, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in the local memory 120 when it is read from or written to the memory device 130, and the data may be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0028] although Figure 1 The example of the memory system 110 in has been illustrated as including the memory system controller 115, but in some cases, the memory system 110 may not include the memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which may each be internal to the memory device 130 to perform the functions attributed herein to the memory system controller 115. In general, in some cases, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] The memory device 130 may include one or more non-volatile memory cell arrays. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistance random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more volatile memory cell arrays. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As illustrated in FIG. 1 , memory device 130 - a may include a local controller 135 - a and memory device 130 - b may include a local controller 135 - b .

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, a combination of one or more memory arrays and associated circuitry and a local (e.g., on-die or in-package) controller such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0033] In some cases, the memory system 110 may implement a first interface (e.g., ONFI) to support communication between the memory system controller 115 and one or more memory devices 130 of the memory system 110. Additionally or alternatively, the memory system 110 may implement a second interface (e.g., an SCA interface, which may alternatively be referred to as a separate command interface or an iCAD interface) to support communication between the memory system 110 (e.g., one or more memory devices 130 of the memory system 110) and an external device (e.g., a host system 105 or a tester device). In some examples, the second interface may support a pass-through mode to allow an external device to directly access one or more memory devices 130 (e.g., raw NAND) of the memory system 110, which may include components that bypass the memory system controller 115. This pass-through mode may support various functionalities, such as allowing a manufacturer or integrator to test a memory device without implementing additional firmware that communicates with the memory system controller 115. Furthermore, this pass-through mode may allow relatively unsophisticated devices (e.g., devices associated with the step-down market) to access the memory device 130 without operating or otherwise implementing a relatively more complex memory system controller 115 (e.g., omitting the memory system controller 115). However, some implementations of the second interface may support limited accessibility to the memory device 130 (e.g., fail to support aspects of the pass-through mode that bypass the memory system controller 115).

[0034] According to examples described herein, the memory interface circuitry 185 may be configured to couple with one or more memory devices 130, which may support direct access to the memory devices 130. The memory interface circuitry 185 may be operable to couple with an external device (e.g., a tester device), which may be an example of the host system 105, and may route data between the external device and the one or more memory devices 130. For example, the memory interface circuitry 185 may be configured to receive a command via a first interface (e.g., an SCA interface) having a first set of terminals to configure the memory interface circuitry 185 into a pass-through mode. As part of the pass-through mode, the memory interface circuitry 185 may receive data from the external device via the first interface and output the data to the one or more memory devices 130 via a second interface (e.g., an ONFI interface) having a second set of terminals. In some examples, receiving the data may be associated with a write burst, wherein the memory interface circuitry 185 may serially receive multiple (e.g., two or more) portions of the data to be written to a buffer of the memory interface circuitry 185. After reaching the threshold amount of data, the buffer may output portions of the data (e.g., concurrently, in parallel) via the second interface to the one or more memory devices 130. In such examples, the memory interface circuitry 185 may output portions of the data based on the buffer storing the threshold amount of data (e.g., in response to or otherwise based on the buffer becoming full).

[0035] Configuring the memory interface circuitry 185 to support the pass-through mode may allow an external device to bypass aspects of the memory system controller 115 or some portion thereof, and thus may provide external device direct access to one or more memory devices 130 according to a simplified interface (e.g., using fewer terminals, according to a reduced command set, according to a reduced clock rate or data rate, according to reduced capabilities) relative to other interfaces. Although examples of the memory interface circuitry 185 are illustrated as being external to the memory system controller 115, in some other examples, at least a portion (if not all) of the memory interface circuitry 185 may be included in the memory system controller 115 (e.g., which may support bypassing another portion of the memory system controller 115). Furthermore, while an example of memory interface circuitry 185 is illustrated as being part of memory system 110, in some other examples, memory interface circuitry 185 may be implemented in host system 105 or as part of or in communication with a different system, such as a test platform, which may combine aspects of host system 105 and memory system 110 and may otherwise provide instructions to and exchange data with one or more memory devices 130.

[0036] System 100 may include any number of non-transitory computer-readable media that support serial pass-through techniques for memory device interfaces. For example, host system 105, memory system 110, or memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein (e.g., attributed to memory interface circuitry 185). For example, such instructions, when executed by host system 105, memory system 110, memory device 130, or otherwise implemented memory interface circuitry 185 (e.g., in a standalone or other integrated implementation), may cause host system 105, memory system 110, memory device 130, or otherwise implemented memory interface circuitry 185 to perform the associated functions described herein.

[0037] Figure 2An example of a memory interface circuit system 185-a supporting serial pass-through technology for a memory device interface according to examples disclosed herein is shown. The memory interface circuit system 185-a may be an example of one or more aspects of the memory interface circuit system 185. The memory interface circuit system 185-a may include one or more terminals 225 (e.g., terminals 225-a, 225-b, 225-c) or one or more terminals 235 (e.g., terminals 235-a and 235-b), or both, which may support communication coupling with an external device (e.g., a host system 105, a test device). In some cases, the one or more terminals 235 may be different from (e.g., may be excluded, may not be included) one or more terminals 225. The memory interface circuitry 185-a may also include one or more terminals 230, including terminals 230-a (e.g., write enable (WE)), 230-b (e.g., address latch enable / command latch enable (ALE / CLE)), 230-c (e.g., chip enable (CE#) [1:0]), 230-d (e.g., DQS / DQ[7:0]), and 230-e (e.g., RE#), which may support communication coupling with one or more memory devices 130. In some examples, the terminals 230 may be associated with an interface 210 (e.g., ONFI) between the memory interface circuitry 185-a and such memory devices 130. In various implementations, the terminals 225, 230, or 235, or any combination thereof, may be accessible by an external device for coupling (e.g., as pins, as pads, at a physical boundary of an associated device). The memory interface circuitry 185 - a may be implemented in the memory system 110 or the host system 105 , as well as other implementations (eg, as part of a test platform) for supporting operations between the host and one or more memory devices 130 .

[0038] In some cases, terminals 225 and terminals 235 may be associated with interface 205, which may be an example of a UFS interface. For example, terminals 235 may include: one or more data terminals 235-a (e.g., DQS / DQ[7:0]), which may be configured to communicate data associated with access operations between an external device (e.g., host system 105) and a storage system controller (e.g., storage system controller 115) using interface 205; and one or more read enable terminals 235-b (e.g., RE#), which may support read operations using interface 205. The terminals 225 may include: one or more clock terminals 225-a (e.g., CA_CLK), which may support communication of clock signals; one or more command and address (CA) terminals 225-b (e.g., CA[1:0]), which may support receiving commands and addresses associated with access operations using the interface 205; and one or more identifier terminals 225-c (e.g., CE#[3:0]), which may support communication of indications (e.g., chip enable signals) of one or more memory devices 130. In some cases, the indications of the one or more memory devices 130 may be routed to one or more multiplexers 265 (e.g., multiplexers 265-a, 265-b, 265-c, 265-d, 265-e, and 265-f), which may route incoming signals to the one or more memory devices 130 associated with the indications (e.g., according to an index enabled by the indications). For example, interface 210, terminal 230, or both may be repeated (eg, duplicated) for each index of multiplexer 265, which may couple multiple memory devices (eg, at least one memory device associated with each index) with memory interface circuitry 185-a.

[0039] Additionally or alternatively, terminal 225 may be associated with interface 215, which may be an example of an SCA interface. Interface 215 may use terminal 225 to communicate commands, addresses, data, or any combination thereof associated with accessing memory device 130 coupled to memory interface circuit system 185-a. For example, terminal 225-b may be configured to receive commands and addresses associated with access operations and to communicate data associated with access operations. In some examples, interface 205, interface 215, or both may communicate according to double data rate (DDR) signaling. Thus, each terminal 225 and each terminal 235 may transmit one data bit on each rising edge of a clock cycle (e.g., a clock cycle associated with a clock signal communicated via clock terminal 225-a) and one data bit on each falling edge of a clock cycle. Additionally or alternatively, interface 205, interface 215, or both may communicate signaling according to a single data rate (SDR) procedure.

[0040] Interface 215, interface 210, or both may support the use of multiple (e.g., two) operation phases to communicate commands, addresses, and data. For example, interface 215 may support a first phase (e.g., a serial command phase) and a second phase (e.g., an independent parallel data bus transfer phase). In some examples, the first phase may be used to preset or equip the second phase by loading buffer 220-a with a channel selection, and may be associated with serially receiving commands and addresses via terminal 225-b. The second phase may be used to program or read one or more memory devices 130, which may involve parallel (e.g., concurrent) signaling via multiple terminals 230. In some cases, an external device (e.g., host system 105, tester device) may transmit one or more header cycle types via terminal 225-b to indicate the type of signaling following the header cycle type (e.g., cycle type, command type, data type). For example, Table 1 illustrates examples of cycle types and associated header cycle types that may be supported by memory interface circuitry 185-a.

[0041]

[0042] Table 1 - SCA header period type decoding

[0043] As described herein, rising and falling edges may refer to rising and falling clock signals, respectively, which may be driven by an external device via terminal 225-a. The header cycle types included in Table 1 may be communicated via terminal 225-b to indicate the data format of the signal transmitted after the header cycle type, and may assist in altering the functionality of memory interface circuitry 185-a. For example, an external device may enable or disable a "controller" cycle type by communicating the associated header cycle type from Table 1 via terminal 225-b and then signaling a 0 or 1 bit that disables or enables the "controller" cycle type, respectively.

[0044] Enabling the "controller" cycle type may enable mapping to map signaling received after the "address" header cycle type to various functions, and may enable the interface decoder 240 to receive subsequent signaling with the "address" header cycle type. Table 2 may illustrate mappings that may map received signals (e.g., information received after the "address" header cycle type) to functions of the interface decoder 240.

[0045] Function address Burst Data FIFO (Write) 4’b0000 Burst data FIFO empty / full 4’b0001 Burst Data FIFO (Read) 4’b0010 Start mode write 4’b0011 Start mode comparison 4’b0100 Mode Status 4’b0101 Mode failure 4’b0110 Pattern Seed 4’b0111

[0046] Table 2 - Memory Map

[0047] For example, to support a test mode (e.g., bypass test mode, SBTM) of the memory interface circuitry 185-a, an external device (e.g., a tester device, a host system 105) may transmit a "select chip enable" header cycle type via terminal 225-b and may transmit an indication of one or more memory devices 130 via one or more terminals 225-c. Based on receiving the "select chip enable" header cycle type and the indication of one or more memory devices 130, the memory interface circuitry 185-a (e.g., using the interface decoder 240) may store the indication in a buffer 220-a (e.g., a burst buffer, a burst FIFO). The indication of the one or more memory devices 130 may be routed to one or more multiplexers 265 (e.g., via the burst decoder 260), which may support routing of data output by the burst data block 250 to the indicated one or more memory devices 130. Because the interface 210 (eg, ONFI bus) may be shared across a group of memory devices 130, each memory device 130 included in the indication may receive and process signaling (eg, commands, data) from an external device.

[0048] After storing indications of one or more memory devices 130 in buffer 220-a, the external device may transmit a "controller" header cycle type to enable mapping, which may configure the interface decoder 240 to process commands (e.g., commands associated with an "address" header cycle type). For example, to perform a write operation (e.g., a burst data write), the external device may transmit a "burst data FIFO (write)" address type. The external device may then transmit (e.g., using a "data out" header cycle type) one or more portions of the data, such as one or more codewords (e.g., scrambled data, metadata, low density parity check (LDPC) parity information, or any combination thereof) via terminal 225-b.

[0049] To support translation of data from a bus width used by the interface 215 (e.g., the number of terminals 225-b) and a bus bandwidth used by the interface 210 (e.g., the number of terminals 230-d, which may be greater than the number of terminals 225-b), the interface decoder 240 may be configured to store portions of data received serially from an external device (e.g., according to the bus width of the interface 215) into a buffer 220-b (e.g., a data buffer, a burst data FIFO). If the buffer 220-b is full (e.g., based on a determination by the interface decoder 240 that the buffer 220-b stores a threshold amount of data), the memory interface circuitry 185-a may transfer the portion of data stored in the buffer 220-b to the indicated one or more memory devices 130 (e.g., may "flush" the data from the buffer 220-b). For example, the memory interface circuitry 185-a may output the portions of data concurrently (e.g., in parallel) to the one or more memory devices 130 indicated by the indication stored in the buffer 220-a via the burst data block 250 according to the bus width of the interface 210.

[0050] In some examples, after outputting the portion of the data, the interface decoder 240 may set the value of a flag associated with the buffer 220-b to indicate that the buffer 220-b is empty. The external device may poll the state of the flag (e.g., using a "burst data FIFO empty / full" address type) to determine whether the buffer 220-b is empty. Thus, if the buffer 220-b is empty, the external device may continue to transmit portions of the data so that each portion of the data may be stored to the buffer 220-b and output from the buffer 220-b to the one or more memory devices 130.

[0051] In some examples, the memory interface circuitry 185-a may support reading data by an external device. For example, if mapping is enabled, the external device may transmit a "Burst Data FIFO (Read)" address type, which may configure the memory interface circuitry 185-a for a read operation, and may then transmit one or more "Data In" header cycle types.

[0052] In response to each "data in" cycle type, the interface decoder 240 may retrieve portions of the data from the one or more memory devices 130 and store the portions to the buffer 220-b. In some cases, if the buffer 220-b is full (e.g., based on the interface decoder 240 determining that the buffer 220-b stores a threshold amount of data), the interface decoder 240 may set a value of a flag to indicate that the buffer 220-b is full. An external device may poll the status of the buffer 220-b (e.g., using a "burst data FIFO empty / full" address type), and if the buffer 220-b is full, the interface decoder 240 may serially output the portion of the data stored at the buffer 220-b to the external device via the interface 215. In some instances, the memory interface circuit system 185-a may transmit read data via a first terminal 225-b (e.g., a single terminal) and may concurrently transmit a clock signal (e.g., a clock signal generated at the memory interface circuit system 185-a, which may be generated based on the clock signal communicated via terminal 225-a) via a second terminal 225-b (e.g., a single terminal, different from the first signal) to support a portion of the output data.

[0053] In some examples, as an alternative to receiving data from an external device, the memory interface circuitry 185-a may support a sequence generator mode (e.g., to test one or more memory devices 130). For example, after using a "controller" cycle type to enable mapping and configure the memory interface circuitry, the external device may transmit a "start pattern write" address type. Next, the external device may transmit a "data output" cycle type, starting the pattern generator. The pattern generator may generate a random sequence (e.g., a PRBS) and store the generated sequence to the indicated one or more memory devices. The interface decoder 240 may support a "mode failure" address type, which may cause the interface decoder 240 to retrieve the generated sequence from the one or more memory devices and perform an error control operation to identify whether an error occurred when storing or retrieving the sequence. In response to receiving the "mode failure" address type, the interface decoder 240 transmits the results of the error control operation (e.g., an indication of whether any errors were detected) to the external device.

[0054] Figure 3 An example of a timing diagram 300 supporting serial pass-through techniques for a memory device interface according to examples disclosed herein is shown. Aspects of the timing diagram 300 may be referred to by reference Figure 1 and 2The described system 100 (e.g., memory interface circuitry 185) or various components thereof are implemented. Timing diagram 300 illustrates the use of a header portion 320 that may indicate a header cycle type of Table 1 and information 330 that may communicate configuration, commands, and data via command / address (CA) channels 305-a and 305-b. For example, timing diagram 300 illustrates signaling via one or more CA channels (e.g., CA1 305-a and CA0 305-b) (which may be communicated via respective terminals 225-b) and signaling of a CA clock (e.g., clock signal 315) associated with the CA channels (which may be communicated via terminals 225-a).

[0055] The signaling of the timing diagram 300 may implement an interface (e.g., interface 215, SCA interface) that supports serial pass-through technology for a memory device interface. The timing diagram 300 may illustrate an example of communication between an external device (e.g., host system 105, tester device) coupled to terminal 225 and one or more memory devices 130 coupled to terminal 230. For example, the timing diagram 300 may include CA1 305-a and CA0 305-b channels that the external device may use to communicate information. The external device may transmit one or more header cycle types (e.g., indicated by header portion 320, which may be associated with the header cycle types of Table 1) via CA1 305-a, CA0 305-b, or a combination thereof, followed by information 330 associated with each header cycle type (e.g., information 330-a, information 330-b). These header cycle types may identify commands and may be used by the memory interface circuitry 185 to determine how to decode the information 330 that follows the header cycle type.

[0056] The timing diagram 300 illustrates an example of signaling according to a DDR unit interval. For example, the external device may transmit header portions 320-a and 320-b according to a rising edge (e.g., a first unit interval) of the clock signal 315 and may transmit header portions 320-c and 320-d according to a falling edge (e.g., a second unit interval). In some cases, for each rising edge and for each falling edge, a single data bit may be communicated via each CA channel 305. For example, CA1 305-a may communicate a single bit of header portion 320-a at time t0 and may communicate a single bit of header portion 320-c at time t1. Similarly, CA0 305-b may transmit a single bit of header portion 320-b at time t0 and may transmit a single bit of header portion 320-d at time t1. Thus, the header portion 320 may indicate a header cycle type (e.g., of Table 1), which may include four bits mapped to the respective header portion 320. The external device may then transmit the associated information 330 via CA1 305-a, CA0 305-b, or both according to the DDR unit interval. In some cases, as part of a read operation, the interface 215 may be implemented to transmit data to the external device via one of CA1 305-a or CA0 305-b. For example, the memory interface circuitry 185 may transmit retrieved read data via CA1 305-a and may transmit a clock signal (e.g., a clock signal generated at the memory interface circuitry 185-a) via CA0 305-b.

[0057] Different types of information and commands may be communicated using CA channels 305-a and 305-b, and different types may be associated with different information 330. For example, a cycle type indicated by a header portion 320 may be communicated using a CA channel to enable a memory interface to decode information 330 following the header portion 320. For example, the memory interface circuitry 185 (e.g., interface decoder 240) may decode a 4-bit header cycle type (e.g., decoded as a combination of four header portions 320) and may identify the cycle type from the decoded header cycle type to decode (e.g., interpret) information 330 following the header portion 320 (e.g., information 330-a and 330-b). In some examples, different header cycle types may be used to indicate information about clock cycles associated with a memory system and buffers. For example, an external device may send a header portion 320 associated with a "data out" cycle type or a "data in" cycle type from Table 1 to indicate to the memory interface circuitry 185 that a data transfer may occur. Similarly, the external device may send an "address" header cycle type or a "command" header cycle type from Table 1, which may indicate information about the CA bus.

[0058] As described herein, the external device may send a "Select Chip Enable" header cycle type from Table 1 to activate (e.g., enable) the chip select line and enable data transfer, and the external device may send a "Select Chip Suspend" header cycle type from Table 1 to similarly deactivate the chip select line and suspend data transfer. Additionally, the external device may send a "Select Chip Terminate" header cycle type from Table 1 to trigger erasure of the channel select indicator from buffer 220-a and terminate data transfer.

[0059] Additionally, the external device may send a "controller" header cycle type to enable mapping, which may configure the memory interface circuitry 185 (e.g., interface decoder 240) to decode subsequent commands having an "address" header cycle type. For example, the memory interface circuitry 185 may determine to perform various functions in response to receiving the "address" header cycle type, and the specific function may be determined by the subsequent information 330 according to Table 2.

[0060] Figure 4 An example of a memory interface architecture 400 supporting serial pass-through techniques for memory device interfaces according to examples disclosed herein is shown. The memory interface architecture 400 may illustrate an example of implementing aspects of the memory interface circuitry 185 (e.g., may be included in the memory interface circuitry 185). For example, the memory interface architecture 400 may be coupled to an external device (e.g., a host system 105, a tester device) via an interface (e.g., interface 215), via a bus 405 (e.g., via terminal 225), and may be coupled to one or more memory devices 130 via a read enable terminal 230-e and one or more terminals 230-d. The memory interface architecture 400 may include an interface decoder 240-a that may receive signaling (e.g., commands, addresses, data) via the bus 405 and may output data to a buffer 220-b-1. Buffer 220-b-1 may also receive data from mode control 430 (e.g., mode generator logic) and may send and receive data to and from one or more memory devices 130 via data path 410 (e.g., via interface 210). Mode control 430 may be coupled with mode comparison circuit 435, which may be an example of an exclusive-OR (XOR) comparator. Data path 410 may optionally be coupled with one or more space circuits 415 (e.g., space circuit 415-a and space circuit 415-b) and may communicate data via read enable terminal 230-e and terminal 230-d.

[0061] The memory interface architecture 400 may support the generation of sequences (e.g., random sequences, PRBS) that may be used to evaluate the memory devices 130. For example, the memory interface architecture 400 may receive a first command, such as a "select chip enable" header cycle type, via the bus 405. As part of the first command, the memory interface architecture 400 may write an indication of one or more memory devices 130 to another buffer (e.g., buffer 220-a).

[0062] In some cases, an external device may use the header cycle types and address values ​​of Tables 1 and 2 as commands to generate a sequence from the memory interface architecture 400 and transmit it to one or more memory devices 130 coupled to the memory interface architecture 400. For example, the external device may transmit a "controller" header cycle type and a "1" bit to enable the memory mapping described in Table 2. Subsequently, the external device may transmit an "address" header cycle type from Table 1 and a "start mode write" address from Table 2 to configure the interface decoder 240-a to generate a sequence based on the indication stored in the first buffer.

[0063] The external device may transmit the "Data Out" header cycle type from Table 1 with a command to enable mode control 430 to begin generating the sequence. In some examples, mode control 430 may use a seed value (e.g., as a seed for a random number generator) when generating the sequence. The external device may transmit a command (e.g., a "mode seed" address type) to transmit and set the seed for mode control 430. In other cases, mode control 430 may generate a seed value for the sequence (e.g., autonomously).

[0064] In response to the "data out" header cycle type, the mode control 430 may generate a sequence and may write one or more portions of the sequence to the buffer 220-b-1. Based on determining that the buffer 220-b-1 is full, the memory interface architecture 400 may output the portion of the sequence from the buffer 220-b-1 to the indicated one or more memory devices 130. In some cases, the space circuit 415-b may track the amount of data written to the buffer 220-b-1 and may notify the memory interface architecture 400 when the amount of data written to the buffer 220-b-1 meets a threshold (e.g., when the buffer 220-b-1 is full). Subsequently, the mode control 430 may write additional portions of the sequence (e.g., a second portion, a third portion, etc.) to the buffer 220-b-1, and the buffer 220-b-1 may output the additional portions to the one or more indicated memory devices 130.

[0065] In some examples, the external device may transmit a command to poll the mode status register to determine whether the sequence has been transmitted from the mode control 430 and stored in one or more memory devices 130 coupled to the memory interface architecture 400. For example, the external device may transmit an "address" header cycle type from Table 1 and a "mode status" address from Table 2 to poll the mode status register of the memory interface architecture 400. In response, the memory interface architecture 400 may transmit to the external device an indication of whether the sequence is stored in the one or more memory devices 130 (e.g., whether the operation of generating and storing the sequence is complete). In some cases, the mode control 430 may use the buffer 220-b-1.

[0066] The header cycle types and addresses from Table 1 and Table 2 may similarly be used to determine whether a sequence is correctly stored to one or more memory devices 130. For example, an external device may transmit an "address" header cycle type from Table 1 and a "start pattern compare" address from Table 2, and may then transmit a "data out" header cycle type from Table 1 to enable the mode control 430 to begin a sequence read operation. In some examples, the external device may poll the mode status register to determine when the sequence read operation is complete. The mode control 430 may read a sequence from the one or more memory devices 130 using the buffer 220-b-1. For example, the space circuit 415-a may track the amount of data (e.g., sequence) read from the one or more memory devices 130 to the buffer 220-b-1. If the amount of data meets a threshold, the space circuit 415-a may alert the memory interface architecture 400, which may notify the buffer 220-b-1 to transfer the read data to the mode control 430.

[0067] In some examples, the memory interface architecture 400 may perform an error detection procedure to compare the retrieval sequence with the initially generated sequence. For example, based on (e.g., in response to) the retrieval sequence, the memory interface architecture 400 may generate a second sequence using the same seed used to generate the initial sequence. The memory interface architecture 400 may compare the second sequence with the retrieval sequence (e.g., using pattern comparison circuit 435), and may determine an error rate (e.g., the percentage of bits in the retrieval sequence that do not match the second sequence), a number of errors (e.g., the number of bits in the retrieval sequence that do not match the second sequence), or both. An external device may transmit a command (e.g., a "mode failure" address) to retrieve the error rate, the number of errors, or both. In some examples, the memory interface architecture 400 may provide the results of such comparison or determination (e.g., an indication of the presence or number of errors, a pass / fail indication) to an external device via bus 405.

[0068] Thus, according to these and other examples, the memory interface circuitry 185 may be configured to support a pass-through mode, which may allow an external device to bypass aspects of the memory system controller 115 and, in some examples, may provide external device direct access to one or more memory devices 130 according to a simplified interface (e.g., using fewer terminals, according to a reduced command set, according to a reduced clock rate or data rate, according to reduced capabilities) relative to other interfaces. Such techniques may support improved techniques for evaluating memory devices 130 (e.g., simplified techniques, techniques that may be supported even in a failed memory system controller 115), or may provide direct access to memory devices 130, such as for reuse implementations that may implement a lower performance interface, or which may bypass aspects of the memory system controller 115 (e.g., reuse a memory device 130 that is still functioning properly when a memory system controller 115 fails). Thus, implementing the techniques described herein may support techniques for increasing connectivity in electronic systems by allowing increased flexibility in the types of devices tested, which may increase the adaptability and use cases of the electronic system, among other benefits.

[0069] Figure 5 A block diagram 500 is shown of a memory interface 520 supporting serial pass-through technology for memory device interfaces according to examples disclosed herein. The memory interface 520 may be a reference Figures 1 to 4 5. The memory interface 520 or its various components may be examples of means for performing various aspects of the serial pass-through techniques for memory device interfaces described herein. For example, the memory interface 520 may include a receiving component 525, a buffer writing component 530, a buffer output component 535, a memory device indicating component 540, a pattern generating component 545, a transmitting component 550, an error control component 555, a buffer control component 560, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0070] In some examples, the memory interface 520 may be configured to support one or more first implementations of the serial pass-through technology for memory device interfaces disclosed herein. For example, the receiving component 525 may be configured to or otherwise support a means for receiving a command (e.g., a command to enable a "burst data FIFO" mode) at a memory interface circuit system coupled to one or more memory devices via a plurality of first terminals to configure the memory interface circuit system to receive data associated with a write burst, the plurality of first terminals being associated with a first number of terminals. The buffer write component 530 may be configured to or otherwise support a means for writing a first portion of data to a buffer of the memory interface circuit system during a first duration at least in part based on receiving a first portion of the data via the plurality of first terminals. In some examples, the buffer write component 530 may be configured to or otherwise support a means for writing a second portion of the data to a buffer of the memory interface circuit system during a second duration following the first duration at least in part based on receiving a second portion of the data via the plurality of first terminals. The buffer output component 535 may be configured to or otherwise support means for outputting a first portion of the data and a second portion of the data from the buffer to one or more memory devices via a plurality of second terminals based at least in part on determining that the amount of data written to the buffer satisfies a threshold, the plurality of second terminals being associated with a second number of terminals greater than the first number of terminals. In some examples, the first portion of the data and the second portion of the data may be output concurrently via the plurality of second terminals.

[0071] In some examples, receiving component 525 may be configured as or otherwise support means for receiving a second command (e.g., inputting a "select chip enable" cycle type command) at the memory interface circuitry via a plurality of first terminals to write an indication of one or more memory devices. In some examples, memory device indication component 540 may be configured as or otherwise support means for writing an indication of one or more memory devices to the memory interface circuitry based at least in part on receiving the second command, and transmitting the first portion of the data and the second portion of the data may be based at least in part on writing the indication.

[0072] In some examples, receiving component 525 may be configured as or otherwise support means for receiving indications of one or more memory devices at a memory interface circuit system via one or more third terminals excluding a plurality of first terminals, and indications of writing to the one or more memory devices may be based at least in part on receiving indications of the one or more memory devices.

[0073] In some examples, receiving component 525 may be configured as or otherwise support means for receiving a second command (e.g., a command inputting a "controller" cycle type) at the memory interface circuit system via a plurality of first terminals to enable a mapping associated with the header cycle type of the command and one or more functions of the memory interface circuit system, and receiving the command may be based at least in part on enabling the mapping.

[0074] In some examples, receiving component 525 may be configured to or otherwise support means for receiving a second command (e.g., a "burst data FIFO empty / full" command) at the memory interface circuitry via the plurality of first terminals after the second duration to determine whether the buffer is empty. In some examples, transmitting component 550 may be configured to or otherwise support means for outputting an indication that the buffer is empty via the plurality of first terminals based at least in part on transmitting the first portion of data and the second portion of data and in response to receiving the second command.

[0075] In some examples, the buffer control component 560 can be configured to or otherwise support means for determining that the buffer is empty based at least in part on the first portion of the output data and the second portion of the data. In some examples, the buffer control component 560 can be configured to or otherwise support means for setting a value of a flag of the memory interface circuitry based at least in part on the determination, wherein the indication that the buffer is empty includes the value of the flag. In some examples, the header cycle type of the command and the header cycle type of the second command can be associated with the same value.

[0076] In some examples, the receiving component 525 may be configured to or otherwise support means for receiving a second command (e.g., a "burst data FIFO (read)" command) at the memory interface circuitry via a plurality of first terminals to read data from one or more memory devices. In some examples, the buffer write component 530 may be configured to or otherwise support means for receiving a first portion of the data and a second portion of the data from the one or more memory devices via a plurality of second terminals based at least in part on receiving the second command. In some examples, the transmitting component 550 may be configured to or otherwise support means for outputting the first portion of the data via a subset of the plurality of first terminals during a third duration. In some examples, the transmitting component 550 may be configured to or otherwise support means for outputting the second portion of the data via a subset of the plurality of first terminals during a fourth duration subsequent to the third duration.

[0077] In some examples, the transmission component 550 can be configured or otherwise support means for outputting the clock signal via the second subset of the plurality of first terminals excluding the subset during the third time duration and during the fourth time duration.

[0078] In some examples, to support outputting the first portion of data and the second portion of data, the buffer output component 535 may be configured as or otherwise support means for outputting the first portion of data and the second portion of data from the buffer to a respective controller of each of the one or more memory devices.

[0079] In some examples, to support outputting a first portion of data and a second portion of data, the buffer output component 535 may be configured as or otherwise support means for outputting the first portion of data and the second portion of data from the buffer to a first memory device in one or more memory devices and a second memory device in one or more memory devices.

[0080] In some examples, a bus of the memory interface circuit system includes a plurality of first terminals, one or more third terminals, and a fourth terminal. In some examples, the plurality of first terminals may be associated with conveying commands, addresses, and data, the one or more third terminals may be associated with conveying an indication of one or more memory devices, and the fourth terminal may be associated with conveying a clock signal.

[0081] In some examples, the plurality of first terminals may be associated with the SCA interface and the plurality of second terminals may be associated with ONFI.

[0082] Additionally or alternatively, the memory interface 520 may be configured to support one or more second implementations of the serial pass-through technology for memory device interfaces disclosed herein. For example, the receiving component 525 may be configured to or otherwise support a means for receiving a first command (e.g., a "select chip enable" command) at a memory interface circuit system coupled to one or more memory devices via a plurality of first terminals to write an indication of one or more memory devices, the plurality of first terminals being associated with a first number of terminals. The memory device indication component 540 may be configured to or otherwise support a means for writing an indication of one or more memory devices to the memory interface circuit system based at least in part on receiving the first command. The receiving component 525 may be configured to or otherwise support a means for receiving a second command (e.g., a "start pattern write" command) at the memory interface circuit system via a plurality of first terminals to configure the memory interface circuit system to generate a data sequence based at least in part on the write indication. The pattern generation component 545 may be configured to or otherwise support a means for writing a first portion of a data sequence to a buffer of the memory interface circuit system based at least in part on generating the data sequence. The buffer output component 535 may be configured to or otherwise support means for outputting a first portion of the data sequence from the buffer to one or more memory devices via a plurality of second terminals based at least in part on determining that the amount of data written to the buffer satisfies a threshold. The pattern generation component 545 may be configured to or otherwise support means for writing a second portion of the data sequence to the buffer based at least in part on generating the data sequence and transmitting the first portion.

[0083] In some examples, receiving component 525 may be configured as or otherwise support means for receiving a third command (e.g., a "controller" command) at the memory interface circuit system via the plurality of first terminals to enable a mapping associated with a header cycle type of a second command and one or more functions of the memory interface circuit system, and receiving the second command may be based at least in part on enabling the mapping.

[0084] In some examples, receiving component 525 may be configured or otherwise support means for receiving a third command (e.g., a "mode status" command) at the memory interface circuitry via the plurality of first terminals to determine whether the data sequence is stored to one or more memory devices. In some examples, transmitting component 550 may be configured or otherwise support means for outputting an indication that the data sequence is stored from the memory interface circuitry via the plurality of first terminals in response to receiving the third command.

[0085] In some examples, receiving component 525 may be configured or otherwise support means for receiving a third command (e.g., a "start pattern comparison" command) at the memory interface circuitry via the plurality of first terminals to perform error evaluation of at least one of the one or more memory devices. In some examples, error control component 555 may be configured or otherwise support means for performing error evaluation of at least one of the one or more memory devices based at least in part on reading a data sequence from at least one of the one or more memory devices. In some examples, transmitting component 550 may be configured or otherwise support means for outputting a response to the third command based at least in part on performing error evaluation.

[0086] In some examples, to support performing error assessment, pattern generation component 545 may be configured or otherwise support means for generating a second data sequence based at least in part on a seed value. In some examples, to support performing error assessment, error control component 555 may be configured or otherwise support means for comparing the second data sequence with a data sequence read from at least one of the one or more memory devices to determine an error rate, and generating the data sequence may be based at least in part on the seed value.

[0087] In some examples, receiving component 525 can be configured or otherwise support means for receiving a third command via the plurality of first terminals to set a seed value, and generating the data sequence can be based at least in part on the seed value.

[0088] In some examples, the data sequence may include a PRBS.

[0089] Figure 6 A flowchart illustrating a method 600 for supporting serial pass-through technology for a memory device interface according to examples disclosed herein is shown. The operations of the method 600 may be implemented by the memory interface or components thereof described herein. For example, the operations of the method 600 may be implemented by reference to Figures 1 to 5 The described memory interface (e.g., memory interface circuitry operable to couple with one or more memory devices, a controller coupled with the memory interface and configured to support one or more of the operations of method 600) performs. In some examples, the memory interface may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory interface may use dedicated hardware to perform aspects of the described functions.

[0090] At 605, the method may include receiving a command at a memory interface circuit system coupled to one or more memory devices via a plurality of first terminals to configure the memory interface circuit system to receive data associated with a write burst, the plurality of first terminals being associated with a first number of terminals. Operation 605 may be performed according to examples disclosed herein. In some examples, aspects of operation 605 may be described with reference to Figure 5 The receiving component 525 described performs.

[0091] At 610, the method may include writing a first portion of the data to a buffer of the memory interface circuitry during a first duration based at least in part on receiving the first portion of the data via the plurality of first terminals. Operation 610 may be performed according to examples disclosed herein. In some examples, aspects of operation 610 may be described with reference to Figure 5 The described buffer write component 530 performs.

[0092] At 615, the method may include writing a second portion of the data to a buffer of the memory interface circuitry during a second duration after the first duration based at least in part on receiving the second portion of the data via the plurality of first terminals. Operation 615 may be performed according to examples disclosed herein. In some examples, aspects of operation 615 may be described with reference to Figure 5 The described buffer write component 530 performs.

[0093] At 620, the method may include outputting the first portion of the data and the second portion of the data from the buffer to one or more memory devices via a plurality of second terminals based at least in part on determining that the amount of data written to the buffer satisfies the threshold, the plurality of second terminals being associated with a second number of terminals greater than the first number of terminals. Operation 620 may be performed according to examples disclosed herein. In some examples, aspects of operation 620 may be described with reference to Figure 5 The described buffer output component 535 performs.

[0094] In some examples, an apparatus described herein may perform one or several methods, such as method 600. An apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0095] Aspect 1: A method, apparatus or non-transitory computer-readable medium includes operations, features, circuit systems, logic, components or instructions or any combination thereof for: at a memory interface circuit system coupled to one or more memory devices, receiving a command via a plurality of first terminals to configure the memory interface circuit system to receive data associated with a write burst, the plurality of first terminals being associated with a first number of terminals; during a first duration, writing the first portion of the data to a buffer of the memory interface circuit system based at least in part on receiving the first portion of the data via the plurality of first terminals; during a second duration after the first duration, writing the second portion of the data to the buffer of the memory interface circuit system based at least in part on receiving the second portion of the data via the plurality of first terminals; and outputting the first portion of the data and the second portion of the data from the buffer to one or more memory devices via a plurality of second terminals based at least in part on determining that an amount of data written to the buffer satisfies a threshold, the plurality of second terminals being associated with a second number of terminals greater than the first number of terminals.

[0096] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: at the memory interface circuit system, receiving a second command via the plurality of first terminals to write an indication of the one or more memory devices; and writing the indication of the one or more memory devices to the memory interface circuit system based at least in part on receiving the second command, wherein transmitting the first portion of the data and the second portion of the data is based at least in part on writing the indication.

[0097] Aspect 3: The method, apparatus or non-transitory computer-readable medium according to Aspect 2, further comprising the following operations, features, circuit systems, logic, components or instructions or any combination thereof: at the memory interface circuit system, receiving the indication of the one or more memory devices via excluding one or more third terminals of the multiple first terminals, wherein writing the indication of the one or more memory devices is at least partially based on receiving the indication of the one or more memory devices.

[0098] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: at the memory interface circuit system, receiving a second command via the plurality of first terminals to enable a mapping associated with a header cycle type of the command and one or more functions of the memory interface circuit system, wherein receiving the command is based at least in part on enabling the mapping.

[0099] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 4, further comprising the following operations, features, circuit systems, logic, components, or instructions, or any combination thereof: after the second duration, receiving a second command at the memory interface circuit system via the multiple first terminals to determine whether the buffer is empty; and outputting an indication that the buffer is empty via the multiple first terminals based at least in part on transmitting the first portion of the data and the second portion of the data and in response to receiving the second command.

[0100] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of Aspect 5, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: determining that the buffer is empty based at least in part on outputting the first portion of the data and the second portion of the data; and setting a value of a flag of the memory interface circuit system based at least in part on the determination, wherein the indication that the buffer is empty includes the value of the flag.

[0101] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 5 to 6, wherein the header period type of the command and the header period type of the second command are associated with the same value.

[0102] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 7, wherein the first portion of the data and the second portion of the data are output concurrently via the plurality of second terminals.

[0103] Aspect 9: A method, apparatus or non-transitory computer-readable medium according to any one of Aspects 1 to 8, further comprising the following operations, features, circuit systems, logic, components or instructions or any combination thereof: receiving a second command at the memory interface circuit system via the multiple first terminals to read the data from the one or more memory devices; receiving the first part of the data and the second part of the data from the one or more memory devices via the multiple second terminals based at least in part on receiving the second command; outputting the first part of the data via a subset of the multiple first terminals during a third duration; and outputting the second part of the data via the subset of the multiple first terminals during a fourth duration after the third duration.

[0104] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of Aspect 9, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for outputting a clock signal during the third duration and during the fourth duration via a second subset of the plurality of first terminals excluding the subset.

[0105] Aspect 11: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 10, wherein outputting the first portion of the data and the second portion of the data includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for outputting the first portion of the data and the second portion of the data from the buffer to a corresponding controller of each of the one or more memory devices.

[0106] Aspect 12: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 11, wherein outputting the first portion of the data and the second portion of the data includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for outputting the first portion of the data and the second portion of the data from the buffer to a first memory device among the one or more memory devices and a second memory device among the one or more memory devices.

[0107] Aspect 13: A method, apparatus or non-transitory computer-readable medium according to any one of Aspects 1 to 12, wherein a bus of the memory interface circuit system includes the plurality of first terminals, one or more third terminals and a fourth terminal, and the plurality of first terminals are associated with conveying commands, addresses and data, the one or more third terminals are associated with conveying indications of the one or more memory devices, and the fourth terminal is associated with conveying a clock signal.

[0108] Aspect 14: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 13, wherein the plurality of first terminals are associated with an SCA interface and the plurality of second terminals are associated with ONFI.

[0109] Figure 7 A flow chart illustrating a method 700 for supporting serial pass-through techniques for a memory device interface according to examples disclosed herein is shown. The operations of the method 700 may be implemented by a memory interface described herein (e.g., a memory interface circuitry operable to couple with one or more memory devices, a controller coupled with the memory interface and configured to support one or more of the operations of the method 700) or a component thereof. For example, the operations of the method 700 may be implemented by reference to Figures 1 to 5 The memory interface described herein performs. In some examples, the memory interface may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory interface may use dedicated hardware to perform aspects of the described functions.

[0110] At 705, the method may include, at a memory interface circuit system coupled to the one or more memory devices, receiving, via a plurality of first terminals, a first command to write an indication of the one or more memory devices, the plurality of first terminals being associated with a first number of terminals. Operation 705 may be performed according to examples disclosed herein. In some examples, aspects of operation 705 may be described with reference to Figure 5 The described receiving component 525 executes.

[0111] At 710, the method may include writing an indication of one or more memory devices to the memory interface circuit system based at least in part on receiving the first command. Operation 710 may be performed according to examples disclosed herein. In some examples, aspects of operation 710 may be described with reference to Figure 5 The depicted memory device instructs component 540 to execute.

[0112] At 715, the method may include, at the memory interface circuitry, receiving a second command via the plurality of first terminals to configure the memory interface circuitry to generate a data sequence based at least in part on the write indication. Operation 715 may be performed according to examples disclosed herein. In some examples, aspects of operation 715 may be described with reference to Figure 5 The receiving component 525 described performs.

[0113] At 720, the method may include writing a first portion of the data sequence to a buffer of the memory interface circuitry based at least in part on generating the data sequence. Operation 720 may be performed according to examples disclosed herein. In some examples, aspects of operation 720 may be described with reference to Figure 5 The described pattern generation component 545 executes.

[0114] At 725, the method may include outputting a first portion of the data sequence from the buffer to one or more memory devices via a plurality of second terminals based at least in part on determining that the amount of data written to the buffer satisfies a threshold. Operation 725 may be performed according to examples disclosed herein. In some examples, aspects of operation 725 may be described with reference to Figure 5 The described buffer output component 535 performs.

[0115] At 730, the method may include writing a second portion of the data sequence to the buffer based at least in part on generating the data sequence and transmitting the first portion. Operation 730 may be performed according to examples disclosed herein. In some examples, aspects of operation 730 may be described with reference to Figure 5 The described pattern generation component 545 executes.

[0116] In some examples, an apparatus described herein may perform one or several methods, such as method 700. An apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0117] Aspect 15: A method, apparatus, or non-transitory computer-readable medium includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: at a memory interface circuit system coupled to one or more memory devices, receiving a first command via a plurality of first terminals to write an indication of the one or more memory devices, the plurality of first terminals being associated with a first number of terminals; writing the indication of the one or more memory devices to the memory interface circuit system based at least in part on receiving the first command; at the memory interface circuit system, receiving a second command via the plurality of first terminals to configure the memory interface circuit system to generate a data sequence based at least in part on writing the indication; writing a first portion of the data sequence to a buffer of the memory interface circuit system based at least in part on generating the data sequence; outputting the first portion of the data sequence from the buffer to the one or more memory devices via a plurality of second terminals based at least in part on determining that an amount of data written to the buffer satisfies a threshold; and writing a second portion of the data sequence to the buffer based at least in part on generating the data sequence and transmitting the first portion.

[0118] Aspect 16: The method, apparatus, or non-transitory computer-readable medium of Aspect 15, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving a third command at the memory interface circuit system via the plurality of first terminals to enable a mapping associated with a header cycle type of the second command and one or more functions of the memory interface circuit system, wherein receiving the second command is based at least in part on enabling the mapping.

[0119] Aspect 17: The method, apparatus or non-transitory computer-readable medium according to any one of Aspects 15 to 16, further comprising the following operations, features, circuit systems, logic, components or instructions or any combination thereof: receiving a third command at the memory interface circuit system via the multiple first terminals to determine whether the data sequence is stored in the one or more memory devices; and outputting an indication that the data sequence is stored from the memory interface circuit system via the multiple first terminals in response to receiving the third command.

[0120] Aspect 18: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 15 to 17, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving a third command at the memory interface circuit system via the plurality of first terminals to perform an error evaluation of at least one of the one or more memory devices; performing the error evaluation of the at least one of the one or more memory devices based at least in part on reading the data sequence from at least one of the one or more memory devices; and outputting a response to the third command based at least in part on performing the error evaluation.

[0121] Aspect 19: A method, apparatus, or non-transitory computer-readable medium according to Aspect 18, wherein performing the error assessment includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: generating a second data sequence based at least in part on a seed value; and comparing the second data sequence with the data sequence read from at least one of the one or more memory devices to determine an error rate, wherein generating the data sequence is based at least in part on the seed value.

[0122] Aspect 20: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 15 to 19, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving a third command via the plurality of first terminals to set a seed value, wherein generating the data sequence is at least partially based on the seed value.

[0123] Aspect 21: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 15 to 20, wherein the data sequence comprises a pseudo-random binary sequence (PRBS).

[0124] It should be noted that the described techniques include possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0125] An apparatus is described. The following provides an overview of aspects of the apparatus described herein:

[0126] Aspect 22: A system comprising: one or more memory devices; a plurality of first terminals; a plurality of second terminals; a memory system controller coupled to the one or more memory devices and to the plurality of second terminals; and a memory interface circuit system coupled to the one or more memory devices and to the plurality of first terminals, the memory interface circuit system including a buffer and configured to: receive a command via the plurality of first terminals to configure the memory interface circuit system to receive data associated with a write burst; receive a first portion of the data written to the buffer via the plurality of first terminals during a first duration; receive a second portion of the data written to the buffer via the plurality of first terminals during a second duration after the first duration; and output the first portion of the data and the second portion of the data from the buffer concurrently to at least one of the one or more memory devices based at least in part on determining that the amount of data written to the buffer satisfies a threshold.

[0127] Aspect 23: A system according to Aspect 22, wherein the memory interface circuit system is further configured to: receive a second command via the plurality of first terminals to generate a data sequence; generate the data sequence for writing to the buffer based at least in part on the second command; and output the data sequence from the buffer to at least one of the one or more memory devices.

[0128] Aspect 24: The system of any of aspects 22-23, wherein the memory interface circuitry is configured to bypass the memory system controller for communicating with the one or more memory devices.

[0129] Aspect 25: The system according to any one of aspects 22 to 24, wherein the number of the plurality of second terminals is greater than the number of the plurality of first terminals.

[0130] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0131] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (or in conductive contact or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0132] The term "coupled" (e.g., "electrically coupled") may refer to a condition that transitions from an open circuit relationship between components (where signals cannot currently be communicated between components via conductive paths) to a closed circuit relationship between components (where signals can be communicated between components via conductive paths). If a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0133] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. If an open circuit exists between components, then they are isolated from each other. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0134] The terms "if," "when," "based on," or "based at least in part on" may be used interchangeably. In some instances, if the terms "if," "when," "based on," or "based at least in part on" are used to describe a connection between conditional actions, conditional processes, or parts of processes, the terms may be interchangeable.

[0135] The term "responsive to" may refer to one condition or action occurring at least in part, if not entirely, as a result of a prior condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the prior condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occurring after the first condition or action).

[0136] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" rather than "preferred" or "superior to other examples". The "Detailed Description" includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0137] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0138] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted by a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the described functions may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0139] For example, the various illustrative blocks and components described herein in connection with the present disclosure may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0140] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0141] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. Any other non-transitory media. Moreover, any connection is appropriately referred to as computer-readable media. For example, if the software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave), then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0142] The description herein is provided to enable persons skilled in the art to make or use the present disclosure. Persons skilled in the art will appreciate various modifications of the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system, comprising: memory interface circuitry operable to couple with one or more memory devices; and processing circuitry coupled to the memory interface circuitry and configured such that the memory system: receiving, at the memory interface circuitry, a command via a first plurality of terminals to configure the memory interface circuitry to receive data associated with a write burst, the first plurality of terminals being associated with a first number of terminals; writing the first portion of the data to a buffer of the memory interface circuitry based at least in part on receiving the first portion of the data via the plurality of first terminals during a first duration; writing a second portion of the data to the buffer of the memory interface circuitry based at least in part on receiving a second portion of the data via the plurality of first terminals during a second duration after the first duration; and The first portion of the data and the second portion of the data are output from the buffer to the one or more memory devices via a plurality of second terminals based at least in part on determining that the amount of data written to the buffer satisfies a threshold, the plurality of second terminals being associated with a second number of terminals greater than the first number of terminals.

2. The memory system of claim 1 , wherein the processing circuitry is further configured such that the memory system: receiving, at the memory interface circuitry, via the plurality of first terminals, an indication of a second command to write to the one or more memory devices; and The indication of the one or more memory devices is written to the memory interface circuitry based at least in part on receiving the second command, wherein transferring the first portion of the data and the second portion of the data is based at least in part on writing the indication.

3. The memory system of claim 2, wherein the processing circuitry is further configured such that the memory system: At the memory interface circuitry, the indication of the one or more memory devices is received via one or more third terminals excluding the plurality of first terminals, wherein writing the indication of the one or more memory devices is based at least in part on receiving the indication of the one or more memory devices.

4. The memory system of claim 1 , wherein the processing circuitry is further configured such that the memory system: At the memory interface circuitry, a second command is received via the plurality of first terminals to enable a mapping associated with a header cycle type of the command and one or more functions of the memory interface circuitry, wherein receiving the command is based at least in part on enabling the mapping.

5. The memory system of claim 1 , wherein the processing circuitry is further configured such that the memory system: After the second duration, receiving a second command at the memory interface circuitry via the plurality of first terminals to determine whether the buffer is empty; and Based at least in part on transferring the first portion of the data and the second portion of the data and in response to receiving the second command, outputting an indication that the buffer is empty via a plurality of first terminals.

6. The memory system of claim 5, wherein the processing circuitry is further configured such that the memory system: determining that the buffer is empty based at least in part on outputting the first portion of the data and the second portion of the data; and A value of a flag of the memory interface circuitry is set based at least in part on the determination that the buffer is empty, wherein the indication that the buffer is empty comprises the value of the flag. 7 . The memory system of claim 1 , wherein the first portion of the data and the second portion of the data are concurrently output via the plurality of second terminals.

8. The memory system of claim 1, wherein the processing circuitry is further configured such that the memory system: receiving, at the memory interface circuitry via the plurality of first terminals, a second command to read the data from the one or more memory devices; receiving the first portion of the data and the second portion of the data from the one or more memory devices via the plurality of second terminals based at least in part on receiving the second command; outputting the first portion of the data via a subset of the plurality of first terminals during a third duration; and During a fourth duration subsequent to the third duration, the second portion of the data is output via the subset of the plurality of first terminals.

9. The memory system of claim 8, wherein the processing circuitry is further configured such that the memory system: During the third time duration and during the fourth time duration, a clock signal is output via a second subset of the plurality of first terminals excluding the subset.

10. The memory system of claim 1, wherein outputting the first portion of the data and the second portion of the data is configured such that the memory system: The first portion of the data and the second portion of the data are output from the buffer to a respective controller of each of the one or more memory devices.

11. The memory system of claim 1 , wherein outputting the first portion of the data and the second portion of the data is configured such that the memory system: The first portion of the data and the second portion of the data are output from the buffer to a first memory device of the one or more memory devices and a second memory device of the one or more memory devices.

12. The memory system of claim 1 , wherein a bus of the memory interface circuit system comprises the plurality of first terminals, one or more third terminals and a fourth terminal, and the plurality of first terminals are associated with conveying commands, addresses and data, the one or more third terminals are associated with conveying indications of the one or more memory devices, and the fourth terminal is associated with conveying a clock signal.

13. The memory system of claim 1, wherein the plurality of first terminals are associated with a separate command address (SCA) interface and the plurality of second terminals are associated with an open NAND flash interface (ONFI).

14. A memory system comprising: memory interface circuitry operable to couple with one or more memory devices; and processing circuitry coupled to the memory interface circuitry and configured such that the memory system: receiving, at the memory interface circuitry, via a plurality of first terminals, a first command to write an indication of the one or more memory devices, the plurality of first terminals being associated with a first number of terminals; writing the indication of the one or more memory devices to the memory interface circuitry based at least in part on receiving the first command; receiving, at the memory interface circuitry via the plurality of first terminals, a second command to configure the memory interface circuitry to generate a data sequence based at least in part on writing the indication; writing a first portion of the data sequence to a buffer of the memory interface circuitry based at least in part on generating the data sequence; outputting the first portion of the sequence of data from the buffer to the one or more memory devices via a plurality of second terminals based at least in part on determining that an amount of data written to the buffer satisfies a threshold; and A second portion of the sequence of data is written to the buffer based at least in part on generating the sequence of data and transmitting the first portion.

15. The memory system of claim 14, wherein the processing circuitry is further configured such that the memory system: A third command is received at the memory interface circuitry via the plurality of first terminals to enable a mapping associated with a header cycle type of the second command and one or more functions of the memory interface circuitry, wherein receiving the second command is based at least in part on enabling the mapping.

16. The memory system of claim 14, wherein the processing circuitry is further configured such that the memory system: receiving, at the memory interface circuitry via the plurality of first terminals, a third command to determine whether the sequence of data is stored to the one or more memory devices; and An indication that the data sequence is stored is output from the memory interface circuitry via the plurality of first terminals in response to receiving the third command.

17. The memory system of claim 14, wherein the processing circuitry is further configured such that the memory system: receiving, at the memory interface circuitry via the plurality of first terminals, a third command to perform error evaluation of at least one of the one or more memory devices; performing the error evaluation of the at least one of the one or more memory devices based at least in part on reading the data sequence from the at least one of the one or more memory devices; and A response to the third command is output based at least in part on performing the error evaluation.

18. The memory system of claim 17, wherein performing the error evaluation is configured such that the memory system: generating a second data sequence based at least in part on the seed value; and The second data sequence is compared to the data sequence read from the at least one of the one or more memory devices to determine an error rate, wherein generating the data sequence is based at least in part on the seed value.

19. A system comprising: one or more memory devices; a plurality of first terminals; a plurality of second terminals; a memory system controller coupled to the one or more memory devices and to the plurality of second terminals; and a memory interface circuitry coupled to the one or more memory devices and to the plurality of first terminals, the memory interface circuitry comprising a buffer and configured to: receiving, via the plurality of first terminals, a command to configure the memory interface circuitry to receive data associated with a write burst; receiving, via the plurality of first terminals, a first portion of the data written to the buffer during a first duration; receiving, via the plurality of first terminals, a second portion of the data written to the buffer during a second duration following the first duration; and The first portion of the data and the second portion of the data are concurrently output from the buffer to at least one of the one or more memory devices based at least in part on determining that an amount of data written to the buffer satisfies a threshold.

20. The system of claim 19, wherein the memory interface circuitry is configured to bypass the memory system controller for communicating with the one or more memory devices.

Images