Multipath selector logic optimization method, electronic equipment and medium

Abstract

The invention relates to the technical field of integrated circuits, in particular to a multiplexer logic optimization method, electronic equipment and a medium, and the method comprises the steps: C1, obtaining a selection signal set corresponding to a multiplexer to be optimized; c2, optimizing a selection signal; c3, acquiring a data signal set corresponding to the multiplexer to be optimized; c4, if all the data signals are driven by constant, or all the data signals are unsteady signals, or all the data signals are connected to the same signal source, the logic optimization process is ended, and otherwise, the step C5 is executed; step C5, decomposing the multiplexer to be optimized to generate a multiplexer tree, wherein each node of the multiplexer tree corresponds to one multiplexer; and C6, generating an optimized multiplexer based on the multiplexer tree. According to the invention, the logic optimization degree and optimization efficiency of the multiplexer are improved. According to the invention, the logic optimization degree and optimization efficiency of the multiplexer are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a multiplexer logic optimization method, electronic equipment and medium. Background Art

[0002] Multiplexer (Mux) is a common component of digital systems, but its logic resource overhead is large. Field-programmable gate array (FPGA) provides a variety of dedicated modules on the chip to narrow the performance gap between it and application-specific integrated circuits, such as a dedicated multiplexer integrated with a look-up table (LUT). Mapping the multiplexer to the FPGA is conducive to reducing the overall area and delay. Before mapping the multiplexer to the FPGA, the multiplexer needs to be logically optimized. The existing multiplexer logic optimization method has a low degree of optimization and low optimization efficiency. It can be seen that how to improve the logic optimization degree and optimization efficiency of the multiplexer has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The object of the present invention is to provide a multiplexer logic optimization method, electronic equipment and medium, which improve the logic optimization degree and optimization efficiency of the multiplexer.

[0004] According to a first aspect of the present invention, a method for optimizing multiplexer logic is provided, comprising:

[0005] Step C1: Obtain the selection signal set corresponding to the multiplexer to be optimized {S 1 ,S 2 ,…,S n ,…,S N},S n is the nth selection signal, the value range of n is 1 to N, and N is the total number of selection signals;

[0006] Step C2, traverse each S n , if S n If the selection signal needs to be directly connected to the ground or the power supply, then S n Connect directly to ground or power supply, and connect S n Delete from the selection signal set, update N=N-1, and execute step C3 after the traversal is completed;

[0007] Step C3: Obtain the data signal set corresponding to the multiplexer to be optimized {D 1 ,D 2 ,…,D m ,…,D M}, Dm is the mth data signal, the value range of m is 1 to M, M is the number of data signals, M = 2 N ;

[0008] Step C4: If all D m All data signals are driven by constants, or all data signals are indeterminate signals, or all D m If both are connected to the same signal source, the logic optimization process ends; otherwise, step C5 is executed;

[0009] Step C5, decomposing the multi-way selector to be optimized to generate a multi-way selector tree, each node of the multi-way selector tree corresponds to a multi-way selector, and the multi-way selector tree satisfies: each non-leaf node corresponds to a two-choice selector, the input of the two-choice selector corresponding to the non-leaf node is the output of the multi-way selectors corresponding to the two child nodes of the non-leaf node, and all leaf nodes are first-class leaf nodes, second-class leaf nodes or third-class leaf nodes, wherein the input and output of the multi-way selector corresponding to the first-class leaf nodes are the same, the multi-way selector corresponding to the second-class leaf nodes does not have optimization space, and the input of the multi-way selector corresponding to the third-class leaf nodes is all constant;

[0010] Step C6: Generate an optimized multiplexer based on the multiplexer tree.

[0011] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0012] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0013] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the multiplexer logic optimization method, electronic device and medium provided by the present invention can achieve considerable technical advancement and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:

[0014] The present invention first optimizes the selection signal of the multiplexer to be optimized, and then optimizes the data signal of the multiplexer to be optimized. The data signal of the multiplexer to be optimized is optimized by decomposing the multiplexer to be optimized to generate a multiplexer tree, thereby improving the logic optimization degree and optimization efficiency of the multiplexer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A flow chart of a multiplexer logic optimization method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0018] The embodiment of the present invention provides a method for optimizing multiplexer logic. Figure 1 As shown, including:

[0019] Step C1: Obtain the selection signal set corresponding to the multiplexer to be optimized {S 1 ,S 2 ,…,S n ,…,S N},S n is the nth selection signal, the value range of n is 1 to N, and N is the total number of selection signals.

[0020] Step C2, traverse each S n , if S n If the selection signal needs to be directly connected to the ground (GND) or the power supply (PWR), then S n Connect directly to ground or power supply, and connect S n Delete from the selection signal set, update N=N-1, and execute step C3 after the traversal is completed.

[0021] It should be noted that, every time N is reduced by 1, the size of the multiplexer to be optimized can be reduced by half.

[0022] Step C3: Obtain the data signal set corresponding to the multiplexer to be optimized {D 1 ,D 2 ,…,D m ,…,D M}, D m is the mth data signal, the value range of m is 1 to M, M is the number of data signals, M = 2 N .

[0023] Step C4: If all D m All data signals are driven by constants, or all data signals are indeterminate (don't care) signals, or all D m If both are connected to the same signal source, the logic optimization process ends; otherwise, step C5 is executed.

[0024] Among them, a multiplexer driven entirely by constants is equivalent to a lookup table, so it may be directly mapped to the lookup table. A multiplexer whose all data signals are indeterminate signals can be directly deleted from the netlist. m The multiplexers connected to the same signal source are multiplexers driven by the same input signal and can be replaced by a buffer, which can be implemented as a net or a 1-input lookup table. A multiplexer may usually be a combination of the above three situations, so it is necessary to decompose the multiplexer so that the decomposed multiplexer meets the above optimization conditions.

[0025] Step C5, decompose the multiplexer to be optimized to generate a multiplexer tree, each node of the multiplexer tree corresponds to a multiplexer, and the multiplexer tree satisfies: each non-leaf node corresponds to a two-choice selector, the input of the two-choice selector corresponding to the non-leaf node is the output of the multiplexer corresponding to the two child nodes of the non-leaf node, and all leaf nodes are first-class leaf nodes, second-class leaf nodes or third-class leaf nodes, wherein the first-class leaf nodes are buffer leaf nodes, and the input and output of the multiplexer corresponding to the buffer leaf node are the same, and the second-class leaf nodes are regular leaf nodes, and the multiplexer corresponding to the regular leaf nodes does not have any pair of optimizable data, nor does it exist in an indeterminate state, that is, there is no optimization space, so there is no need to further decompose the regular leaf nodes. The third-class leaf nodes are constant leaf nodes, and the inputs of the multiplexers corresponding to the constant leaf nodes are all constants.

[0026] Step C6: Generate an optimized multiplexer based on the multiplexer tree.

[0027] Specifically, the multiplexer tree may be mapped onto the FPGA.

[0028] In the embodiment of the present invention, the basic decomposition method is to select a signal from the selection signal, decompose the M-to-1 multiplexer into two M / 2-to-1 selectors, and the two M / 2-to-1 selectors are connected to a 2-to-1 selector, and the two M / 2-to-1 selectors share the selection signal. In the decomposition process, the decomposed multiplexers can be further optimized logically. As an embodiment, step C5 includes:

[0029] Step C51: Set the multiplexer to be optimized as the multiplexer to be decomposed, the number of data signals of the multiplexer to be decomposed is X=M, and set {D 1 ,D 2 ,…,D m ,…,D M} is set as the currently selected signal set and executes step C52.

[0030] Step C52: Select a decomposed selection signal S from the current selection signal set. k , S k Delete from the current selection signal set, the value of k ranges from 1 to N.

[0031] Step C53: Decompose the multiplexer to be optimized into two X / 2 selectors P 1 k and P 2 k , P 1 k and P 2 k Share the selection signal in the current selection signal set, P 1 k The data signal is the S of the multiplexer to be optimized. k When it is 0, the selected data signal, P 2 k The data signal is the S of the multiplexer to be optimized. k When 1, the data signal is selected.

[0032] Step C54: If P 1 k and P 2 k If one of the X / 2 selector inputs is an indeterminate signal, then another X / 2 selector is returned; otherwise, two X / 2 selectors are returned.

[0033] It should be noted that since the multiplexer whose input signals are all indeterminate signals can be directly deleted from the netlist, when one of the X / 2 selector inputs is an indeterminate signal, the X / 2 selector can be directly optimized and only the other X / 2 selector can be returned. It can be understood that in step C54, it is impossible for the two X / 2 selectors to be indeterminate signals.

[0034] Step C55, determine whether the returned X / 2 selectors are leaf nodes. If all are, generate a multiplexer tree. Otherwise, set each X / 2 selector as a multiplexer to be decomposed, update X=X / 2, and return to step C52.

[0035] In step C55, when the returned X / 2 selector meets the characteristics of the first type of leaf node, the second type of leaf node or the third type of leaf node, the X / 2 selector is marked as a leaf node of the corresponding type, and the X / 2 selector is no longer decomposed. It should be noted that for the leaf nodes marked as the third type of leaf nodes, the following judgment can be further made: if there is a selection signal where each pair of data selected is the same or contains an indeterminate state, the multi-way selector corresponding to the leaf node is further reduced by half.

[0036] It should be noted that if the returned X / 2 selector meets the characteristics of the first type of leaf node, the second type of leaf node or the third type of leaf node, the X / 2 selector is marked as a leaf node of the corresponding type.

[0037] In the process of decomposing the multiplexer to be optimized to generate a multiplexer tree, only when the signals assigned to the same multiplexer meet the optimization conditions, that is, a pair of data are the same signal or are both constants or are both indeterminate states, can the optimization space be created. Therefore, in this process, how to choose to decompose the selection signal to obtain a larger optimization space as much as possible is particularly important. As an embodiment, the step C52 includes:

[0038] Step C521: Obtaining k Decomposition P 1 k The data signal set is {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k}, P 2 k The data signal set is {R 1 k , R 2 k ,…,R i k ,…,R X / 2 k}, where Q i k P 1 k The i-th data signal in the data signal set, R i k P 2 k The i-th data signal in the data signal set, i ranges from 1 to X / 2, Q i k and R ik The corresponding selection signals are the same.

[0039] Step C522, traverse {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k} and {R 1 k , R 2 k ,…,R i k ,…,R X / 2 k}, if Q i k and R i k Satisfy Q i k =R i k or Q i k , R i k All are indeterminate or Q i k , R i k are all constants, then (Q i k ,R i k ) is determined as an optimizable data pair, and {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k} and {R 1 k , R 2 k ,…,R i k ,…,R X / 2 k} can optimize the data pair (Q i k ,R i k ) k .

[0040] Step C523: k The S corresponding to the smallest k value k Determine the decomposition selection signal Sk .

[0041] Among them, E k The smaller the value, the more k The smaller the optimization space destroyed by the decomposition.

[0042] As an embodiment, in step C523, if E k There are multiple minimum k values, then for E k The smallest value {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k} and {R 1 k , R 2 k ,…,R i k ,…,R X / 2 k}implement:

[0043] Step C5231, traverse {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k}, if Q i k , Q j k Satisfy Q i k =Q j k or Q i k , Q j k All are indeterminate or Q i k , R i k are all constants, then (Q i k ,Q j k ) is determined as an optimizable data pair, where Q j k For {Q 1 k , Q 2 k ,…,Q i k ,…,QX / 2 k} the jth data signal in .

[0044] Traverse {R 1 k , R 2 k ,…,R i k ,…,R X / 2 k If R i k , R j k Satisfy R i k =R j k or R i k , R j k All are indeterminate or R i k , R i k are all constants, then (R i k ,R j k ) is determined as an optimizable data pair, where R j k For {R 1 k , R 2 k ,…,R i k ,…,R X / 2 k} the jth data signal in .

[0045] Among them, the value range of j is 1 to X / 2, and i≠j.

[0046] Step C5232, obtain {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k The number of optimizable data pairs in QE k , and {R 1 k , R 2 k ,…,R i k ,…,R X / 2 k The number of optimizable data pairs RE in}k .

[0047] Step C5233: Get each group of QE k and RE k The absolute value of the difference between QE k and RE k The k value with the largest absolute value of the difference between k Determine the decomposition selection signal S k .

[0048] Among them, QE k and RE k The larger the absolute value of the difference, the larger the optimization space of the multiplexer obtained after decomposition is on the basis of destroying the same optimization space.

[0049] As an example, if in step C5233, QE k and RE k If there are multiple k values ​​with the largest absolute value of the difference, then QE k and RE k The S with the largest k value among the k with the largest absolute value of the difference k Determine the decomposition selection signal S k .

[0050] As an example, if in step C5233, QE k and RE k If there are multiple k values ​​with the largest absolute value of the difference, then QE k and RE k The k with the largest absolute value of the difference is the S with the smallest k value. k Determine the decomposition selection signal S k .

[0051] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0052] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0053] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0054] The embodiment of the present invention first optimizes the selection signal of the multiplexer to be optimized, and then optimizes the data signal of the multiplexer to be optimized. The data signal of the multiplexer to be optimized is optimized by decomposing the multiplexer to be optimized to generate a multiplexer tree, thereby improving the logic optimization degree and optimization efficiency of the multiplexer.

[0055] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A multiplexer logic optimization method, characterized in that: include: Step C1: Obtain the selection signal set {S1, S2, ..., S n ,…,S N },S n is the nth selection signal, the value range of n is 1 to N, and N is the total number of selection signals; Step C2, traverse each S n , if S n If the selection signal needs to be directly connected to the ground or the power supply, then S n Connect directly to ground or power supply, and connect S n Delete from the selection signal set, update N=N-1, and execute step C3 after the traversal is completed; Step C3: Obtain the data signal set {D1, D2, ..., D m ,…,D M }, D m is the mth data signal, the value range of m is 1 to M, M is the number of data signals, M = 2 N ; Step C4: If all D m All data signals are driven by constants, or all data signals are indeterminate signals, or all D m If both are connected to the same signal source, the logic optimization process ends; otherwise, step C5 is executed; Step C5, decomposing the multi-way selector to be optimized to generate a multi-way selector tree, each node of the multi-way selector tree corresponds to a multi-way selector, and the multi-way selector tree satisfies: each non-leaf node corresponds to a two-choice selector, the input of the two-choice selector corresponding to the non-leaf node is the output of the multi-way selectors corresponding to the two child nodes of the non-leaf node, and all leaf nodes are first-class leaf nodes, second-class leaf nodes or third-class leaf nodes, wherein the input and output of the multi-way selector corresponding to the first-class leaf nodes are the same, the multi-way selector corresponding to the second-class leaf nodes does not have optimization space, and the input of the multi-way selector corresponding to the third-class leaf nodes is all constant; Step C6: Generate an optimized multiplexer based on the multiplexer tree.

2. The method according to claim 1, characterized in that The step C5 comprises: Step C51: Set the multiplexer to be optimized as the multiplexer to be decomposed, the number of data signals of the multiplexer to be decomposed is X=M, and {D1, D2, ..., D m ,…,D M } is set as the current selected signal set, and step C52 is executed; Step C52: Select a decomposed selection signal S from the current selection signal set. k , S k Delete from the current selection signal set, the value of k ranges from 1 to N; Step C53: Decompose the multiplexer to be optimized into two X / 2 selectors P1 k and P2 k , P1 k and P2 k Share the selection signal in the current selection signal set, P1 k The data signal is the S of the multiplexer to be optimized. k When it is 0, the selected data signal, P2 k The data signal is the S of the multiplexer to be optimized. k When it is 1, the data signal is selected; Step C54, if P1 k and P2 k If one of the X / 2 selector inputs is an indeterminate signal, then return the other X / 2 selector, otherwise, return two X / 2 selectors; Step C55, determine whether the returned X / 2 selectors are leaf nodes. If all are, generate a multiplexer tree. Otherwise, set each X / 2 selector as a multiplexer to be decomposed, update X=X / 2, and return to step C52.

3. The method according to claim 1, characterized in that The step C52 comprises: Step C521: Obtaining k Decomposition P1 k The data signal set is {Q1 k , Q2 k ,…,Q i k ,…,Q X / 2 k }, P2 k The data signal set is {R1 k , R2 k ,…,R i k ,…,R X / 2 k }, where Q i k For P1 k The i-th data signal in the data signal set, R i k For P2 k The i-th data signal in the data signal set, i ranges from 1 to X / 2, Q i k and R i k The corresponding selection signals are the same; Step C522, traverse {Q1 k , Q2 k ,…,Q i k ,…,Q X / 2 k } and {R1 k , R2 k ,…,R i k ,…,R X / 2 k }, if Q i k and R i k Satisfy Q i k =R i k or Q i k , R i k All are indeterminate or Q i k , R i k are all constants, then (Q i k ,R i k ) is determined as an optimizable data pair, and {Q1 k , Q2 k ,…,Q i k ,…,Q X / 2 k } and {R1 k , R2 k ,…,R i k ,…,R X / 2 k } can optimize the data pair (Q i k ,R i k ) k ; Step C523: k The S corresponding to the smallest k value k Determine the decomposition selection signal S k .

4. The method according to claim 3, characterized in that In step C523, if E k There are multiple minimum k values, then for E k The smallest value {Q1 k , Q2 k ,…,Q i k ,…,Q X / 2 k } and {R1 k , R2 k ,…,R i k ,…,R X / 2 k }implement: Step C5231, traverse {Q1 k , Q2 k ,…,Q i k ,…,Q X / 2 k }, if Q i k , Q j k Satisfy Q i k =Q j k or Q i k , Q j k All are indeterminate or Q i k , R i k are all constants, then (Q i k ,Q j k ) is determined as an optimizable data pair, where Q j k For {Q1 k , Q2 k ,…,Q i k ,…,Q X / 2 k } the jth data signal; Traverse {R1 k , R2 k ,…,R i k ,…,R X / 2 k If R i k , R j k Satisfy R i k =R j k or R i k , R j k All are indeterminate or R i k , R i k are all constants, then (R i k ,R j k ) is determined as an optimizable data pair, where R j k For {R1 k , R2 k ,…,R i k ,…,R X / 2 k } the jth data signal; The value range of j is 1 to X / 2, i≠j; Step C5232, obtain {Q1 k , Q2 k ,…,Q i k ,…,Q X / 2 k The number of optimizable data pairs in QE k , and {R1 k , R2 k ,…,R i k ,…,R X / 2 k The number of optimizable data pairs RE in} k ; Step C5233: Get each group of QE k and RE k The absolute value of the difference between QE k and RE k The k value with the largest absolute value of the difference between k Determine the decomposition selection signal S k .

5. The method according to claim 4, characterized in that If in step C5233, QE k and RE k If there are multiple k values ​​with the largest absolute value of the difference, then QE k and RE k The S with the largest k value among the k with the largest absolute value of the difference k Determine the decomposition selection signal S k .

6. The method according to claim 4, characterized in that If in step C5233, QE k and RE k If there are multiple k values ​​with the largest absolute value of the difference, then QE k and RE k The k with the largest absolute value of the difference is the S with the smallest k value. k Determine the decomposition selection signal S k .

7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method according to any one of the preceding claims 1-6.

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