A level conversion circuit and an electronic device

Abstract

The present application provides a level conversion circuit and an electronic device, relating to the technical field of level switching. The level conversion circuit includes an input port, a capacitor, a first level conversion module, a second level conversion module, and an output port. Two ends of the capacitor are electrically connected to the input port and the output port respectively. The input end of the first level conversion module is connected to the input port, the output end of the first level conversion module is electrically connected to the input end of the second level conversion module, and the output end of the second level conversion module is electrically connected to the output port. Wherein, when the signal frequency is not zero, the capacitor forms an AC path, and the first level conversion module and the second level conversion module form a DC path. And the first level conversion module is used to convert a first signal input at the input end into a second signal with the opposite polarity, and the second level conversion module is used to convert the second signal into a third signal with the opposite polarity. The present application has the advantages of small signal delay and duty cycle loss.

Description

Technical Field

[0001] This application relates to the technical field of level switching, and in particular, to a level conversion circuit and an electronic device. Background Art

[0002] In the fifth-generation protocol memory interface chip of DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), with the continuous improvement of speed and the improvement of the energy efficiency ratio of chip power consumption, the chip output power supply voltage drops to 1.1V. In order to pursue a higher energy efficiency ratio, a multi-voltage domain scheme is usually adopted in the design of TX (Transmitter), that is, the output stage uses a 1.1V voltage domain, and the previous stage uses a lower voltage domain to reduce power consumption.

[0003] In the multi-voltage domain scheme, the level switching between multiple voltage domains is completed by a level converter. As a bridge connecting different voltage domains, the level converter not only determines the quality of high-speed signal conversion but also determines the final performance of the entire output end.

[0004] The integrity of signals in a Double Data Rate (DDR) high-speed link is crucial for the performance of the entire system. Therefore, after high-speed signals are level-converted, good signal quality needs to be ensured, that is, the signal conversion needs to be fast enough; the delay during the conversion process needs to be small enough; and the duty cycle loss of the signal during the conversion process also needs to be small enough. However, since the voltage domains before and after a high-speed data signal are different after being converted by a level converter, the duty cycle of the signal is easily lost during the level conversion process. Moreover, in the current level converter circuit, NMOS protection transistors and high-voltage PMOS transistors are generally stacked, resulting in a large delay in the entire level converter.

[0005] In summary, there are problems in the prior art that the delay and duty cycle loss are relatively large during the level conversion process of the level converter. Summary of the Invention

[0006] The purpose of this application is to provide a level conversion circuit and an electronic device to solve the problems in the prior art that the delay and duty cycle loss are relatively large during the level conversion process of the level converter.

[0007] To achieve the above purpose, the technical solutions adopted in the embodiments of this application are as follows:

[0008] On the one hand, an embodiment of the present application provides a level conversion circuit. The level conversion circuit includes an input port, a capacitor, a first level conversion module, a second level conversion module, and an output port. Two ends of the capacitor are electrically connected to the input port and the output port respectively. An input end of the first level conversion module is connected to the input port. An output end of the first level conversion module is electrically connected to an input end of the second level conversion module. An output end of the second level conversion module is electrically connected to the output port. Wherein,

[0009] When the signal frequency is not zero, the capacitor forms an AC path, and the first level conversion module and the second level conversion module form a DC path. And the first level conversion module is configured to convert a first signal input at the input end into a second signal with the opposite polarity. The second level conversion module is configured to convert the second signal into a third signal with the opposite polarity.

[0010] The swing amplitudes of the first signal and the third signal are equal. The first signal is a signal in a first voltage domain. The third signal is a signal in a second voltage domain. And the supply voltage and the ground voltage of the second voltage domain are respectively greater than the supply voltage and the ground voltage of the first voltage domain.

[0011] Optionally, the first level conversion module includes a signal pull-down unit, a signal pull-up unit, and a feedback loop unit. The signal pull-up unit and the signal pull-down unit are both connected to the input port. The signal pull-up unit and the feedback loop unit are both connected to a first node. The signal pull-down unit is further connected to the ground of the first voltage domain. The signal pull-down unit, the feedback loop unit, and the input end of the second level conversion module are all connected to a second node. Wherein,

[0012] When the first signal is a high-level signal, the signal pull-down unit is turned on, and the signal pull-up unit is turned off.

[0013] When the first signal is a low-level signal, the signal pull-up unit is turned on, and the signal pull-down unit is turned off.

[0014] Optionally, the signal pull-down unit includes a first transistor and a second transistor. The feedback loop unit includes a third transistor and a fourth transistor. The signal pull-up unit includes a fifth transistor.

[0015] The gate of the first transistor is connected to the input port. The source of the first transistor is connected to the ground of the first voltage domain. The drain of the first transistor is electrically connected to the source of the second transistor. The gate of the second transistor is connected to the power supply of the first voltage domain. The drain of the second transistor is connected to the second node.

[0016] The gate of the third transistor and the drain of the fourth transistor are both connected to the first node. The drain of the third transistor and the gate of the fourth transistor are connected to the second node. The source of the third transistor and the source of the fourth transistor are both connected to the power supply of the second voltage domain.

[0017] The gate of the fifth transistor is connected to the power supply of the first voltage domain. The source of the fifth transistor is connected to the input port. The drain of the fifth transistor is connected to the first node.

[0018] Optionally, the first transistor, the second transistor, and the fifth transistor are low-voltage NMOS transistors, and the third transistor and the fourth transistor are high-voltage PMOS transistors; wherein,

[0019] The minimum breakdown voltage of the high-voltage PMOS transistor is greater than the maximum breakdown voltage of the low-voltage NMOS transistor.

[0020] Optionally, the width-to-length ratio of the fifth transistor is greater than or equal to twice the width-to-length ratio of the fourth transistor;

[0021] The width-to-length ratios of the first transistor and the second transistor are both greater than or equal to the width-to-length ratio of the third transistor.

[0022] Optionally, the level conversion circuit further includes a pull-up transition acceleration module, and the pull-up transition acceleration module is electrically connected to the output end of the capacitor and the input end of the second level conversion module respectively; wherein,

[0023] The pull-up transition acceleration module is used to accelerate the transition speed of the high level when the first level conversion module outputs a high level.

[0024] Optionally, the pull-up transition acceleration module includes a sixth transistor and a seventh transistor. The drain of the sixth transistor is connected to the input end of the second level conversion module. The gate of the sixth transistor is connected to the ground of the second voltage domain. The source of the sixth transistor is electrically connected to the drain of the seventh transistor. The source of the seventh transistor is connected to the power supply of the second voltage domain. The gate of the seventh transistor is connected to the output end of the capacitor.

[0025] Optionally, both the sixth transistor and the seventh transistor are low-voltage PMOS transistors.

[0026] Optionally, the second level conversion module includes an eighth transistor and a ninth transistor. The gates of the eighth transistor and the ninth transistor are both connected to the output terminal of the first level conversion module. The drains of the eighth transistor and the ninth transistor are both connected to the output port. The source of the eighth transistor is connected to the power supply of the second voltage domain, and the source of the ninth transistor is connected to the ground of the second voltage domain. Among them,

[0027] When the second signal is a high-level signal, the eighth transistor is turned off and the ninth transistor is turned on, and the third signal is a low-level signal;

[0028] When the second signal is a low-level signal, the eighth transistor is turned on and the ninth transistor is turned off, and the third signal is a high-level signal.

[0029] On the other hand, an embodiment of the present application also provides an electronic device, and the electronic device includes the above-mentioned level conversion circuit.

[0030] Compared with the prior art, the present application has the following beneficial effects:

[0031] The present application provides a level conversion circuit and an electronic device. The level conversion circuit includes an input port, a capacitor, a first level conversion module, a second level conversion module, and an output port. Two ends of the capacitor are electrically connected to the input port and the output port respectively. An input end of the first level conversion module is connected to the input port, an output end of the first level conversion module is electrically connected to an input end of the second level conversion module, and an output end of the second level conversion module is electrically connected to the output port. Wherein, when the signal frequency is not zero, the capacitor forms an AC path, and the first level conversion module and the second level conversion module form a DC path; and the first level conversion module is configured to convert a first signal input at the input end into a second signal with the opposite polarity, and the second level conversion module is configured to convert the second signal into a third signal with the opposite polarity; the swing amplitudes of the first signal and the third signal are equal, the first signal is a signal located in a first voltage domain, the third signal is a signal located in a second voltage domain, and the power supply voltage and the ground voltage of the second voltage domain are respectively greater than the power supply voltage and the ground voltage of the first voltage domain. Since an AC path formed by the capacitor is added in the level conversion circuit provided by the present application, when the signal frequency is not zero, the signal at the input port can be transmitted through the AC path and the DC path. Due to the self - characteristic of capacitor coupling, the level conversion of the signal can be greatly accelerated, and the time delay of the entire level conversion circuit is reduced to the picosecond level, significantly reducing the signal time delay of the entire level conversion circuit. Moreover, the DC path ensures the stability of the signal, so that while meeting the stability requirements, the signal time delay of the entire level conversion circuit is significantly reduced. In addition, since capacitor coupling can synchronize the signal transition, the duty cycle loss of the output signal is small, and thus the quality of the output signal can be higher.

[0032] To make the above - mentioned objects, features, and advantages of the present application more obvious and understandable, the following specifically gives preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can also be obtained based on these drawings.

[0034] Figure 1 FIG. is a circuit schematic diagram of one of the level converters in the prior art.

[0035] Figure 2 FIG. is a circuit schematic diagram of another level converter in the prior art.

[0036] Figure 3It is a circuit schematic diagram of the level conversion circuit provided by the embodiment of the present application.

[0037] Figure 4 It is another circuit schematic diagram of the level conversion circuit provided by the embodiment of the present application.

[0038] In the figure:

[0039] 110 - Input port; 120 - Capacitor; 130 - First level conversion module; 131 - Signal pull - down unit; 132 - Signal pull - up unit; 133 - Feedback loop unit; 140 - Second level conversion module; 150 - Output port; 160 - Pull - up transition acceleration module; M1 - First transistor; M2 - Second transistor; M3 - Third transistor; M4 - Fourth transistor; M5 - Fifth transistor; M6 - Sixth transistor; M7 - Seventh transistor; M8 - Eighth transistor; M9 - Ninth transistor. Detailed implementation manners

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0042] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for differential description and cannot be understood as indicating or implying relative importance.

[0043] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0044] The following will describe some embodiments of the present application in detail with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0045] As described in the background art, the level shifters in the prior art have problems of relatively high signal delay and relatively large duty cycle loss.

[0046] For example, please refer to Figure 1 , Figure 1 which shows a circuit schematic diagram of a level shifter in the prior art. In the figure, there are two voltage domains in the whole circuit, and both voltage domains include VSS (Voltage Source Source, ground voltage) and VDD (Voltage Drain Drain, power supply voltage). Therefore, in the figure, one voltage domain is VSS1~VDD1, and the other voltage domain is VSS2~VDD2, and VSS2 is greater than VSS1, and VDD2 is greater than VDD1. For example, VSS1~VDD1 can be 0V~0.8V, and VSS2~VDD2 can be 0.3V~1.1V. Among them, M1, M2, M3, and M4 are differential input negative polarity metal oxide semiconductors (Negative Metal Oxide Semiconductor, NMOS), and the signal input swing of M1 and M2 is VSS1~VDD1, and the signal output swing of the circuit is VSS2~VDD2.

[0047] It should be noted that the swing mentioned in this application means that the amplitude of the signal can be any value within the swing range. For example, if the input swing is VSS1~VDD1, then for the input signal, its amplitude is at least VSS1 and at most VDD1. Of course, the input signal can also have an amplitude between VSS1 and VDD1.

[0048] In order to improve the signal processing speed of the level shifter, M1 and M2 usually use low-voltage NMOS transistors, which have a lower conduction threshold, so the signal processing delay is lower than that of high-voltage transistors. Compared with high-voltage transistors, its conduction speed is faster and the delay can be smaller. However, the breakdown voltage value of low-voltage NMOS transistors is limited. Therefore, in order to protect the low-voltage transistors from overvoltage, M3 and M4 are used as protection transistors to make the drain voltage of M1 not exceed the VDD1 voltage value. And, the gates of M3 and M4 are both connected to the power supply VDD1 of the first voltage domain, so that when M1 conducts, M3 also conducts synchronously; when M2 conducts, M4 also conducts synchronously.

[0049] M5 and M6 are high-voltage positive polarity metal oxide semiconductors (Positive Metal Oxide Semiconductor, PMOS). Since the drain terminal of M6 is used as the output and its output voltage swing is VSS1~VDD2, high-voltage PMOS needs to be used to ensure that the device does not overvoltage. INV1 (Inverter) is an inverter composed of low-voltage transistors, and INV2 and INV3 are inverters composed of high-voltage transistors.

[0050] The working principle of the entire level shifter is as follows: When the input signal is at the voltage value of VSS1, M1 is cut off, M2 is turned on, and the voltage value at the drain terminal of M6 starts to drop; at the same time, M5 starts to gradually turn on, and the voltage value at its drain terminal gradually rises to VDD2. Due to the positive feedback effect, the voltage value at the drain of M5 will also accelerate the drop of the voltage value at the drain terminal of M6 (the voltage at the drain terminal of M5 rises to a high level, M6 is cut off, causing the voltage at the drain terminal of M6 to drop rapidly). Eventually, the output voltage at the drain terminal of M6 is VSS1. After passing through the inverter INV2, the output voltage is converted to VDD2, and after passing through the inverter INV3, its output voltage value is VSS2, thus completing the voltage conversion from VSS1 to VSS2.

[0051] Similarly, when the input signal jumps from VSS1 to VDD1, M1 is turned on, M2 is cut off, M6 gradually turns on, and under the action of positive feedback, the voltage at the drain terminal of M5 is pulled down, and the drain voltage of M6 gradually rises to VDD2; after the action of the inverter INV2 and the inverter INV3, the voltage conversion from VDD1 to VDD2 is completed.

[0052] The input transistors of this structure use low-voltage NMOS transistors with a lower conduction threshold and faster conduction speed. However, due to stacking one stage of NMOS protection transistors (M3 and M4) and high-voltage PMOS transistors (M5 and M6), the speed of the overall circuit is limited, resulting in a relatively large delay and making it difficult to meet the delay requirements of the link. At the same time, due to the existence of a positive feedback loop (the loop composed of M5 and M6) in this circuit, the pull-down ability of the input pair NMOS needs to be stronger than the pull-up ability of the PMOS to correctly distinguish the input signal. In this way, the duty cycle of the circuit output signal is naturally small, causing a large duty cycle loss.

[0053] Please refer to Figure 2 for the circuit schematic diagram of another level shifter in the prior art. Figure 2 In Figure 1 , VSS1~VDD1 and VSS2~VDD2 are different voltage domains, and VSS2 > VSS1, VDD2 > VDD1. Similar to

[0054] Figure 2The working principle of the circuit in the middle is as follows: When the input signal is at the voltage of VDD1, M1 is turned on, M2 is turned off, and M5 self-biases to generate a bias voltage that turns on both M5 and M6. At this time, under the pull-up action of M6, the output voltage at its drain terminal is pulled up to VDD2, thus completing the voltage conversion from VDD1 to VDD2. However, since M1, M3, and M5 are all in the on state, a current path is formed, that is, VDD2 flows to the ground VSS1 through M5, M3, and M1, resulting in a static power consumption in the left circuit when the input is VDD1. Similarly, when the input signal switches from VDD1 to VSS1, M1 is turned off, M2 is turned on, and M5 and M6 are both turned off. At this time, the voltage at the drain terminal of M6 is pulled down to VSS1 by M2 and M4; the signal then passes through the inverter INV2 and the inverter INV3 to obtain VSS2, completing the voltage conversion from VSS1 to VSS2.

[0055] Due to the self-bias of M5, the duty cycle of the output mainly depends on the ratio of PMOS to NMOS. By selecting an appropriate size ratio of the devices, a good duty cycle of the output signal can be obtained. However, the delay of this structure is still relatively large, the high-frequency response is not fast enough, and the static power consumption that exists when the input signal is VDD1 affects the energy efficiency of the DDR interface.

[0056] In view of this, in order to improve the above technical problems, the present application provides a level conversion circuit, which achieves the purpose of reducing signal delay and duty cycle loss by adding an AC path.

[0057] The following is an exemplary description of the level converter provided by the present application:

[0058] As an alternative implementation, please refer to Figure 3 and Figure 4, the level conversion circuit includes an input port 110, a capacitor 120, a first level conversion module 130, a second level conversion module 140, and an output port 150. Two ends of the capacitor 120 are electrically connected to the input port 110 and the output port 150 respectively. An input end of the first level conversion module 130 is connected to the input port 110. An output end of the first level conversion module 130 is electrically connected to an input end of the second level conversion module 140. An output end of the second level conversion module 140 is electrically connected to the output port 150. Wherein, when the signal frequency is not zero, the capacitor 120 forms an AC path, and the first level conversion module 130 and the second level conversion module 140 form a DC path. And the first level conversion module 130 is used to convert a first signal input at the input end into a second signal with the opposite polarity. The second level conversion module 140 is used to convert the second signal into a third signal with the opposite polarity. The swing amplitudes of the first signal and the third signal are equal. The first signal is a signal in a first voltage domain, and the third signal is a signal in a second voltage domain. And the power supply voltage and the ground voltage in the second voltage domain are respectively greater than the power supply voltage and the ground voltage in the first voltage domain.

[0059] It can be understood that since an AC path constructed by the capacitor 120 is added in the level conversion circuit provided in this application, when the input signal is a signal with a non-zero frequency, the signal can be transmitted through both the AC path and the DC path simultaneously. And due to the self-characteristics of the coupling of the capacitor 120, it can greatly accelerate the level conversion of high-speed signals, reduce the time delay of the entire level conversion circuit to the picosecond level, and significantly reduce the signal time delay of the entire level conversion circuit. At the same time, the DC path ensures the stability of the signal, so that while the entire level conversion circuit meets the stability requirements, the signal time delay is significantly reduced.

[0060] That is, when transmitting a signal with a non-zero frequency, the AC path constructed by the capacitor 120 can quickly couple the signal at the input port 110 to the output port 150 to achieve signal transmission with lower delay. At the same time, the signal at the input port 110 will also be transmitted to the output port 150 through the DC path constructed by the first level conversion module 130 and the second level conversion module 140. It should be noted that the signal transmission speed of the DC path is slower than that of the AC path. Therefore, the signal of the AC path will be transmitted to the output port 150 first, and the signal of the DC path will lag behind the signal of the AC path. And the stability of the DC path is stronger. Therefore, for the entire level conversion circuit, it can significantly shorten the signal time delay while meeting the stability requirements.

[0061] In addition, since the coupling of the capacitor 120 can synchronize the signal transitions, the duty cycle loss of the output signal is small, and thus the quality of the output signal can be better.

[0062] As an implementation manner, please refer to Figure 3 , the first level conversion module 130 includes a signal pull-down unit 131, a signal pull-up unit 132, and a feedback loop unit 133. The signal pull-up unit 132 and the signal pull-down unit 131 are both connected to the input port 110. The signal pull-up unit 132 and the feedback loop unit 133 are also both connected to a first node. The signal pull-down unit 131 is also connected to the ground of the first voltage domain. The signal pull-down unit 131, the feedback loop unit 133, and the input end of the second level conversion module 140 are all connected to a second node. Wherein, when the first signal is a high-level signal, the signal pull-down unit 131 is turned on, and the signal pull-up unit 132 is turned off; when the first signal is a low-level signal, the signal pull-up unit 132 is turned on, and the signal pull-down unit 131 is turned off.

[0063] It can be understood that the first signal described in this application is the input signal at the input port 110, the second signal is the signal at the position of the second node, and the third signal is the output signal at the output port 150. And, Figure 3 in, ground 1~power supply 1 represents the first voltage domain, ground 2~power supply 2 represents the second voltage domain, and ground 1 < ground 2, power supply 1 < power supply 2. On this basis, the swing of the first signal is from ground 1 to power supply 1, the swing of the second signal is from ground 1 to power supply 2, and the swing of the third signal is from ground 2 to power supply 2.

[0064] It should be noted that the signal pull-up unit 132 and the signal pull-down unit 131 described in this application are both for the signal at the output end of the first level conversion module 130, that is, for the signal at the second node. When the signal pull-up unit 132 is turned on, the signal at the second node is pulled up to a high level; when the signal pull-down unit 131 is turned on, the signal at the second node is pulled down to the ground.

[0065] It can be understood that in this application, the first level conversion module 130 realizes the function of an inverter. When a high-level signal of the first voltage domain is input at the input port 110, a low-level signal of the first voltage domain is output at the second node; and when a low-level signal of the first voltage domain is input at the input port 110, a high-level signal of the second voltage domain is output at the second node.

[0066] Among them, the signal pull-down unit 131 includes a first transistor M1 and a second transistor M2, the feedback loop unit 133 includes a third transistor M3 and a fourth transistor M4, and the signal pull-up unit 132 includes a fifth transistor M5; the gate of the first transistor M1 is connected to the input port 110, the source of the first transistor M1 is connected to the ground of the first voltage domain, the drain of the first transistor M1 is electrically connected to the source of the second transistor M2, the gate of the second transistor M2 is connected to the power supply of the first voltage domain, and the drain of the second transistor M2 is connected to the second node; the gates of the third transistor M3 and the fourth transistor M4 are both connected to the first node, the drain of the third transistor M3 and the gate of the fourth transistor M4 are connected to the second node, and the sources of the third transistor M3 and the fourth transistor M4 are both connected to the power supply of the second voltage domain; the gate of the fifth transistor M5 is connected to the power supply of the first voltage domain, the source of the fifth transistor M5 is connected to the input port 110, and the drain of the fifth transistor M5 is connected to the first node.

[0067] In this application, in order to minimize the delay of the signal in the DC path as much as possible, low-voltage transistors are used as much as possible in the entire level conversion circuit. Therefore, in the first level conversion module 130, the first transistor M1, the second transistor M2, and the fifth transistor M5 are low-voltage NMOS transistors, and the third transistor M3 and the fourth transistor M4 are high-voltage PMOS transistors; among them, the minimum breakdown voltage of the high-voltage PMOS transistor is greater than the maximum breakdown voltage of the low-voltage NMOS transistor. For example, the breakdown voltage of the low-voltage NMOS transistor is generally less than 1.05V, while the minimum breakdown voltage of the high-voltage PMOS transistor is generally greater than or equal to 1.1V.

[0068] Moreover, in the circuit implementation, if the initial voltage of the second node is regarded as 0V, the fourth transistor M4 can be regarded as in the conducting state. Therefore, when the fifth transistor M5 is conducting, it is necessary to ensure that the pull-down ability of the fifth transistor M5 is greater than the pull-up ability of the fourth transistor M4, so as to gradually pull down the voltage of the first node and drive the third transistor M3 to conduct. On this basis, this application sets the aspect ratio of the fifth transistor M5 to be greater than or equal to twice the aspect ratio of the fourth transistor M4 to ensure that when the fifth transistor M5 is conducting, the voltage of the first node can be quickly pulled down.

[0069] Similarly, for the first transistor M1 and the second transistor M2, their pull-down ability also needs to be greater than the pull-up ability of the third transistor M3. It should be noted that the second transistor M2 is used as a protection transistor for the first transistor M1. Generally, the parameters of the first transistor M1 and the second transistor M2 need to be set the same. Therefore, this application sets the aspect ratios of the first transistor M1 and the second transistor M2 to be greater than or equal to the aspect ratio of the third transistor M3.

[0070] Based on the circuit structure of the above first-level conversion module 130, further analysis reveals that: when a high-level signal is input at the input port 110, the first transistor M1 conducts. Since the first transistor M1 is a low-voltage transistor, the voltage of the second node can be quickly pulled down to ground 1. When a low-level signal is input at the input port 110, the fifth transistor M5 conducts, driving the third transistor M3 to conduct, and then pulling up the voltage of the second node to power supply 2. At this time, since the third transistor M3 is a high-voltage transistor, its conduction rate is slow, resulting in a relatively large actual difference in signal delay during the process of pulling up the voltage of the second node to power supply 2 and pulling it down to ground 1. That is, during the pulling-up process of the second node, the pulling-up transition delay is relatively high, which is not conducive to the stability of the operation of the entire circuit. Especially after the parameters of each transistor are determined, if the pulling-up transition delay of the second node is relatively large, it may lead to a deterioration in the operation performance of the entire circuit. For example, when the signal of the first cycle has been transmitted to the output port 150 through the AC path, if the signal delay difference between the DC path and the AC path is relatively large, it is possible that the DC path is still in the process of signal transmission while the AC path transmits the signal of the second cycle to the output port 150, and the signal of the second cycle of the AC path and the signal of the first cycle of the DC path will cancel each other out, resulting in a deterioration in the performance of the entire circuit.

[0071] In view of this, in order to improve the rate of signal transition to high level, the level conversion circuit provided in this application further includes a pull-up transition acceleration module 160. The pull-up transition acceleration module 160 is electrically connected to the output end of the capacitor 120 and the input end of the second-level conversion module 140 respectively; wherein, the pull-up transition acceleration module 160 is used to accelerate the transition speed of the high level when the first-level conversion module 130 outputs a high level.

[0072] In one implementation, the pull-up transition acceleration module 160 includes a sixth transistor M6 and a seventh transistor M7. The drain of the sixth transistor M6 is connected to the input end of the second-level conversion module 140. The gate of the sixth transistor M6 is connected to the ground of the second voltage domain. The source of the sixth transistor M6 is electrically connected to the drain of the seventh transistor M7. The source of the seventh transistor M7 is connected to the power supply of the second voltage domain. The gate of the seventh transistor M7 is connected to the output end of the capacitor 120. Both the sixth transistor M6 and the seventh transistor M7 are low-voltage PMOS transistors.

[0073] It can be understood that the sixth transistor M6 serves as a protection transistor for the seventh transistor M7. At the same time, since both the sixth transistor M6 and the seventh transistor M7 are low-voltage transistors, the conduction rate of the pull-up transition acceleration module 160 can be faster.

[0074] Moreover, by providing the pull-up transition acceleration module 160, when VSS1 is input at the input port 110, the AC path formed by the capacitor 120 can quickly couple the signal to the output port 150, causing the voltage at the output end of the capacitor 120 (the right side of the capacitor 120 in the figure) to quickly drop, driving the seventh transistor M7 to conduct, and then quickly raising the voltage of the second node to the power supply 2, achieving a fast flip transition of the high-level signal at the second node.

[0075] It can be seen that by providing the pull-up transition acceleration module 160, it can be ensured that overall in the circuit, the AC path will always be faster than the DC path, but the signal delay between the AC path and the DC path will not be too large, ensuring the stable operation of the entire circuit.

[0076] In this application, the second level conversion module 140 also performs the function of an inverter. As an implementation, the second level conversion module 140 adopts a push-pull structure, that is, the second level conversion module 140 includes an eighth transistor M8 and a ninth transistor M9. The gates of the eighth transistor M8 and the ninth transistor M9 are both connected to the output end of the first level conversion module 130. The drains of the eighth transistor M8 and the ninth transistor M9 are both connected to the output port 150. The source of the eighth transistor M8 is connected to the power supply of the second voltage domain, and the source of the ninth transistor M9 is connected to the ground of the second voltage domain; wherein, when the second signal is a high-level signal, the eighth transistor M8 is turned off and the ninth transistor M9 is turned on, and the third signal is a low-level signal; when the second signal is a low-level signal, the eighth transistor M8 is turned on and the ninth transistor M9 is turned off, and the third signal is a high-level signal.

[0077] It should be noted that the eighth transistor M8 can be a high-voltage PMOS transistor, and the ninth transistor M9 can be a low-voltage NMOS transistor.

[0078] The following combines Figure 4 to detail the working principle of the level conversion circuit provided in this application:

[0079] As Figure 4 shown, the level conversion circuit provided in the embodiment of this application has two signal paths. An AC path is formed by the capacitor 120, and a DC path is formed by the first level conversion module 130 and the second level conversion module 140. And the AC path and the DC path can process different frequency components of the signal respectively. When the signal frequency is 0, it represents an input DC voltage. At this time, the AC path is equivalent to an open circuit (the capacitor 120 has a DC-blocking characteristic), so the signal can only be transmitted through the DC path. When the signal frequency is not zero, the signal can be transmitted through both the AC path and the DC path, and the signal transmission speed of the DC path will lag behind that of the AC path.

[0080] For example, for the high-frequency part of a signal, such as the rising edge and falling edge during the switching process of a high-speed signal, they are transmitted through the high-frequency path formed by capacitor 120. The signal at the input port 110 can be quickly coupled to the output port 150 through capacitor 120. Since high-frequency signals need to be coupled through capacitor 120, in order to ensure the integrity of high-frequency signals, the swing amplitudes of the input signal and the output signal need to be consistent, i.e., Power Supply 1 - Ground 1 = Power Supply 2 - Ground 2. Therefore, Ground 2 = Power Supply 2 - (Power Supply 1 - Ground 1), where both Power Supply 1 - Ground 1 and Power Supply 2 - Ground 2 represent the swing amplitude values of the first voltage domain and the second voltage domain. For example, if the first voltage domain is from 0V to 0.8V, the swing amplitude value of the first voltage domain is 0.8V; if the swing amplitude value of the second voltage domain is from 0.3V to 0.8V, the swing amplitude value of the second voltage domain is also 0.8V. Among them, the voltage values of the first voltage domain and the second voltage domain can be generated by an on-chip low-dropout linear regulator (LDO) or other circuit methods.

[0081] After each power supply is successfully powered on, if the initial state of the input signal is the voltage value VDD1 of Power Supply 1, and the output voltage is the voltage value VDD2 of Power Supply 2 after passing through the direct current path, then the voltages of both plates of the feedback capacitor 120 are determined. At this time, the charge stored in capacitor 120 is:

[0082] Q0 = U * C = (VDD2 - VDD1) * C;

[0083] where U represents the voltage across capacitor 120, and C represents capacitor 120.

[0084] At the next data cycle moment, during the process when the input signal drops from the voltage value VDD1 to the voltage value VSS1 of Ground 1, the output voltage is Vout1, and the charge stored in capacitor 120 when the high-frequency signal reaches a steady state is:

[0085] Q1 = U * C = (Vout1 - VSS1) * C;

[0086] Since the signal during the switching process is a high-frequency signal, the high-frequency signal can quickly pass through the AC path formed by capacitor 120; while the direct current path can be equivalent to two groups of inverters, and the time for the high-frequency signal to pass through this direct current path is longer than that of the AC path. Therefore, for high-frequency signals, when reaching the output port 150 through the AC path, the signal on the direct current path has not arrived yet. At this time, the charge stored in capacitor 120 is conserved at different moments, that is, Q0 is equal to Q1, and we can get:

[0087] Vout1 = VDD2 - VDD1 + VSS1 = VDD2 - (VDD1 - VSS1);

[0088] That is, at this time Vout1 = VSS2.

[0089] Therefore, the coupling through capacitor 120 can greatly accelerate the transition of the output signal, and the delay of the AC path formed by capacitor 120 can reach within a few picoseconds. Similarly, when the input signal transitions from VSS1 to the voltage value of VDD1, the steady-state voltage of the AC path signal reaching the output port 150 is Vout2, and the electric charge stored in capacitor 120 is:

[0090] Q2 = (Vout2 - VDD1) * C;

[0091] Then, according to the conservation of electric charge before and after, Q2 is equal to Q1, that is, Vout2 = VDD1 + VSS2 - VSS1 = VDD2; thus, high-speed conversion of the voltage domain can be completed.

[0092] Meanwhile, due to the fact that both the rising edge and the falling edge of the signal are directly coupled to the output port 150 through capacitor 120, the rising and falling speeds of the output signal are synchronized with the input signal. Therefore, the duty cycle loss of the output signal is very small, less than 0.1%, ensuring good duty cycle performance during the high-speed signal level conversion process.

[0093] Meanwhile, the present invention also uses a feedback structure to effectively ensure a low static leakage current of the circuit. The first transistor M1 and the second transistor M2 serve as the paths for transmitting the input high level, and the fifth transistor M5, the third transistor M3 and capacitor 120, the seventh transistor M7, and the sixth transistor M6 respectively serve as the paths for transmitting the input low-level signal. When the input is at a low level, the fifth transistor M5 conducts, and the first transistor M1 is cut off. The first node is pulled to a low level under the action of the stronger driving fifth transistor M5; at this time, the third transistor M3 conducts, and the second node is pulled to a high level. The voltage of the second node is fed back to the fourth transistor M4, causing the fourth transistor M4 to turn off; finally, the first node reaches a steady-state low level, and the second node reaches the level value of power supply 2. Similarly, when the input is at a high level, the first transistor M1 and the second transistor M2 conduct, and the fifth transistor M5 is cut off. The second node is gradually pulled down under the strong driving of the first transistor M1 and the second transistor M2; the voltage of the second node is fed back to the fourth transistor M4, forcing the fourth transistor M4 to conduct, thereby pulling up the first node. Finally, the third transistor M3 turns off, the second node reaches the steady-state ground 1 level, and the first node reaches the voltage value of power supply 2, thus ensuring that there is no static current in the steady state. At the same time, since the swing of the signal at the second node is from ground 1 to power supply 2, and the voltage of ground 2 is higher than the voltage of ground 1, there is also no static leakage current in the eighth transistor M8 and the ninth transistor M9, and the static power consumption of the entire circuit is small.

[0094] It can be seen that compared with the traditional level converter, the level conversion circuit provided in this application has at least the following advantages:

[0095] 1. The level shifter adopts a capacitive coupling structure. Through the feedback capacitor 120, the level conversion of high-speed signals can be greatly accelerated. Its delay can reach the picosecond level, and a good duty cycle of the signal can be ensured.

[0096] 2. The level shifter has two signal paths, and the AC path can accelerate the signal transition. Moreover, the DC path can directly reset the voltages of the upper and lower plates of the capacitor 120 after the power is turned on, without an additional reset circuit.

[0097] 3. The level conversion circuit uses a feedback structure to achieve a low static leakage current of the level shifter. Moreover, the entire circuit has the advantages of a relatively simple structure, a small circuit area, and low static power consumption.

[0098] Based on the above implementation manner, an embodiment of the present application further provides an electronic device, which includes the above-mentioned level conversion circuit.

[0099] In summary, the present application provides a level conversion circuit and an electronic device. The level conversion circuit includes an input port, a capacitor, a first level conversion module, a second level conversion module, and an output port. The two ends of the capacitor are respectively electrically connected to the input port and the output port. The input end of the first level conversion module is connected to the input port, the output end of the first level conversion module is electrically connected to the input end of the second level conversion module, and the output end of the second level conversion module is electrically connected to the output port. Wherein, when the signal frequency is not zero, the capacitor forms an AC path, and the first level conversion module and the second level conversion module form a DC path. And the first level conversion module is used to convert the first signal input at the input end into a second signal with the opposite polarity, and the second level conversion module is used to convert the second signal into a third signal with the opposite polarity. The swing amplitudes of the first signal and the third signal are equal. The first signal is a signal in the first voltage domain, the third signal is a signal in the second voltage domain, and the power supply voltage and the ground voltage in the second voltage domain are respectively greater than the power supply voltage and the ground voltage in the first voltage domain. Since an AC path formed by a capacitor is added in the level conversion circuit provided by the present application, when the signal frequency is not zero, the signal at the input port can be transmitted through the AC path and the DC path. Due to the self-characteristics of capacitive coupling, the level conversion of the signal can be greatly accelerated, and the delay of the entire level conversion circuit can be reduced to the picosecond level, significantly reducing the signal delay of the entire level conversion circuit. Moreover, the DC path ensures the stability of the signal, thereby enabling the entire level conversion circuit to significantly reduce the signal delay while meeting the stability requirements. In addition, since capacitive coupling can synchronize the transition of the input signal, the duty cycle loss of the output signal is small, and thus the quality of the output signal can be higher.

[0100] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various modifications and variations can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

[0101] For those skilled in the art, it is obvious that the present application is not limited to the details of the above-described exemplary embodiments, and that the present application can be implemented in other specific forms without departing from the spirit or basic characteristics of the present application. Therefore, in any aspect, the embodiments should be regarded as exemplary and non-limiting. The scope of the present application is defined by the appended claims rather than the above description. Therefore, it is intended to embrace all changes falling within the meaning and scope of the equivalent elements of the claims in the present application. Any reference signs in the claims should not be construed as limiting the claims involved.

Claims

1. A level conversion circuit, characterized in that, The level conversion circuit includes an input port, a capacitor, a first level conversion module, a second level conversion module, and an output port. Both ends of the capacitor are electrically connected to the input port and the output port respectively. The input end of the first level conversion module is connected to the input port, the output end of the first level conversion module is electrically connected to the input end of the second level conversion module, and the output end of the second level conversion module is electrically connected to the output port. Among them, When the signal frequency is not zero, the capacitor forms an AC path, and the first level conversion module and the second level conversion module form a DC path. And the first level conversion module is used to convert a first signal input at the input end into a second signal with the opposite level, and the second level conversion module is used to convert the second signal into a third signal with the opposite level; The swing amplitudes of the first signal and the third signal are equal. The first signal is a signal in a first voltage domain, the third signal is a signal in a second voltage domain, and the power supply voltage and ground voltage of the second voltage domain are respectively greater than the power supply voltage and ground voltage of the first voltage domain; The first level conversion module includes a signal pull-down unit, a signal pull-up unit, and a feedback loop unit. The signal pull-up unit and the signal pull-down unit are both connected to the input port. The signal pull-up unit and the feedback loop unit are also both connected to a first node. The signal pull-down unit is also connected to the ground of the first voltage domain. The signal pull-down unit, the feedback loop unit, and the input end of the second level conversion module are all connected to a second node. Among them, When the first signal is a high-level signal, the signal pull-down unit is turned on, and the signal pull-up unit is turned off; When the first signal is a low-level signal, the signal pull-up unit is turned on, and the signal pull-down unit is turned off.

2. The level conversion circuit according to claim 1, wherein The signal pull-down unit includes a first transistor and a second transistor. The feedback loop unit includes a third transistor and a fourth transistor. The signal pull-up unit includes a fifth transistor; The gate of the first transistor is connected to the input port. The source of the first transistor is connected to the ground of the first voltage domain. The drain of the first transistor is electrically connected to the source of the second transistor. The gate of the second transistor is connected to the power supply of the first voltage domain. The drain of the second transistor is connected to the second node; The gates of the third transistor and the fourth transistor are both connected to the first node. The drain of the third transistor and the gate of the fourth transistor are connected to the second node. The sources of the third transistor and the fourth transistor are both connected to the power supply of the second voltage domain; The gate of the fifth transistor is connected to the power supply of the first voltage domain. The source of the fifth transistor is connected to the input port. The drain of the fifth transistor is connected to the first node.

3. The level conversion circuit according to claim 2, wherein The first transistor, the second transistor, and the fifth transistor are low-voltage NMOS transistors. The third transistor and the fourth transistor are high-voltage PMOS transistors. Among them, The minimum breakdown voltage of the high-voltage PMOS transistor is greater than the maximum breakdown voltage of the low-voltage NMOS transistor.

4. The level conversion circuit according to claim 2, wherein The aspect ratio of the fifth transistor is greater than or equal to twice the aspect ratio of the fourth transistor; The aspect ratios of the first transistor and the second transistor are both greater than or equal to the aspect ratio of the third transistor.

5. The level conversion circuit according to claim 1, wherein The level conversion circuit further includes a pull-up transition acceleration module, and the pull-up transition acceleration module is electrically connected to the output end of the capacitor and the input end of the second level conversion module respectively; wherein, The pull-up transition acceleration module is used to accelerate the transition speed of the high level when the first level conversion module outputs a high level.

6. The level conversion circuit according to claim 5, characterized in that, The pull-up transition acceleration module includes a sixth transistor and a seventh transistor. The drain of the sixth transistor is connected to the input end of the second level conversion module. The gate of the sixth transistor is connected to the ground of the second voltage domain. The source of the sixth transistor is electrically connected to the drain of the seventh transistor. The source of the seventh transistor is connected to the power supply of the second voltage domain. The gate of the seventh transistor is connected to the output end of the capacitor.

7. The level conversion circuit according to claim 6, characterized in that, Both the sixth transistor and the seventh transistor are low-voltage PMOS transistors.

8. The level conversion circuit according to claim 1, wherein The second level conversion module includes an eighth transistor and a ninth transistor. The gates of the eighth transistor and the ninth transistor are both connected to the output end of the first level conversion module. The drains of the eighth transistor and the ninth transistor are both connected to the output port. The source of the eighth transistor is connected to the power supply of the second voltage domain. The source of the ninth transistor is connected to the ground of the second voltage domain; wherein, When the second signal is a high-level signal, the eighth transistor is turned off, the ninth transistor is turned on, and the third signal is a low-level signal; When the second signal is a low-level signal, the eighth transistor is turned on, the ninth transistor is turned off, and the third signal is a high-level signal.

9. An electronic device, characterized in that, The electronic device includes the level conversion circuit according to any one of claims 1 to 8.

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