Manufacturing method of a TVS device with large current and small area

Abstract

The present invention belongs to the field of semiconductor / integrated circuit design and manufacturing, and specifically relates to a manufacturing method for a TVS device with large current-carrying capacity and small area. First, a P-type substrate with appropriate resistivity is selected, and an N-type epitaxial layer is grown on it by chemical vapor deposition. Then, an oxide layer is formed and deep isolation trenches are etched, and polysilicon isolation is filled. P-type wells are formed by ion implantation between the isolation trenches. After etching the trenches, N-type doped polysilicon is filled and sealed. After removing the surface layer, high-temperature diffusion is carried out, and then a via dielectric layer is deposited and vias are opened and filled with conductive metal. Finally, metal is deposited and lithographically etched to retain the metal in specific areas, and passivation treatment is performed to form a TVS device. By optimizing the structure and process, large current-carrying capacity and small area are achieved, the cost is reduced, the requirements of miniaturized electronic products are met, and the performance and reliability of electronic devices are improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor / integrated circuit design and manufacturing, and specifically relates to a manufacturing method for a TVS device with large current-carrying capacity and small area. Background Art

[0002] In the field of modern electronic technology, the performance and reliability of electronic devices are constantly improving, and semiconductor devices play a crucial role among them. As an important semiconductor protection device, the main function of a TVS device is to quickly clamp an excessive voltage within a safe range when a transient overvoltage occurs in a circuit, thereby protecting the subsequent electronic components from damage.

[0003] With the rapid development of electronic devices towards miniaturization, multi-functionality, and high performance, such as smartphones, tablets, wearable devices, etc., the internal circuits have become increasingly complex and the integration degree has become higher and higher. In a limited circuit board space, the size of components must be reduced as much as possible to meet the requirements of miniaturized design. However, traditional TVS devices face a severe challenge in the design and manufacturing process, that is, the contradiction between the current-carrying capacity and the chip area.

[0004] Generally, in order to achieve a large current-carrying capacity, a TVS device requires a larger chip area to accommodate sufficient PN junctions and other structures. This is because the current-carrying capacity is closely related to the area of the PN junction. A larger PN junction area can provide more carrier channels during a transient overvoltage event, thereby allowing a larger current to pass through. However, increasing the chip area not only increases the production cost but also runs counter to the trend of miniaturization of electronic devices, restricting its application in small electronic products.

[0005] In addition, traditional TVS devices have gradually shown limitations in some high-performance application scenarios. For example, in high-speed data transmission circuits, extremely high requirements are imposed on the response speed and clamping accuracy of TVS devices, while traditional devices may not be able to meet these stringent requirements. At the same time, with the continuous expansion of the operating voltage range of electronic devices, new challenges are also posed to the breakdown voltage capability of TVS devices. Traditional manufacturing methods are difficult to achieve higher breakdown voltage performance without significantly increasing the chip area. Summary of the Invention

[0006] Aiming at the deficiencies of the prior art, the present invention proposes a manufacturing method for a TVS device with large current-carrying capacity and small area. By optimizing the device structure and manufacturing process, while ensuring a large current-carrying capacity, the chip area is significantly reduced, the production cost is lowered, the applicability of the TVS device in miniaturized electronic products is improved, and the overall performance and reliability of the electronic device are enhanced.

[0007] The technical solution of the present invention is specifically as follows:

[0008] A manufacturing method of a TVS device with large current flow and small area, comprising:

[0009] Select a P-type substrate according to the resistivity, and form an N-type epitaxial layer on the P-type substrate by chemical vapor deposition process;

[0010] Form an oxide layer on the surface of the N-type epitaxial layer by thermal oxidation or chemical vapor deposition process, and then through photolithography and dry etching processes, etch a number of deep isolation grooves in the epitaxial layer and extend them all the way to the P-type substrate;

[0011] Fill the deep isolation grooves with in-situ polysilicon;

[0012] Adopt ion implantation process between the deep isolation grooves to form P-type wells;

[0013] Through photolithography and dry etching processes, etch grooves a, b, c, d in the N-type epitaxial layer;

[0014] Through the deposition process, fill the N-type doped polysilicon into grooves a, b, c, d and seal them;

[0015] Remove the surface N-type doped polysilicon and the oxide layer by etching process, and then perform high-temperature diffusion to push the junction to the required junction voltage performance;

[0016] Through the deposition process, deposit an oxide layer on the surface of the N-type epitaxial layer as a via dielectric layer, open vias on the via dielectric layer corresponding to the positions of grooves a, b, c, d by photolithography and etching processes, and fill the vias with conductive metal;

[0017] Through the deposition process, deposit metal on the via dielectric layer, and through photolithography and etching processes, retain the metal above grooves a and d, and between grooves b and c, and then perform the final passivation treatment to form the required TVS device.

[0018] Further, the P-type substrate is selected as a substrate with a resistivity between 0.001 and 0.008 Ω·cm.

[0019] Further, the thickness of the oxide layer formed on the surface of the N-type epitaxial layer is 100 - 10000 Å;

[0020] In the dry etching process, the etching gas is selected as a mixed gas of fluorine-based gas and inert gas;

[0021] The deep isolation grooves have a groove width of 0.5 - 1.2 μm and a depth of 3 - 25 μm.

[0022] Further, the in-situ polysilicon is filled into the deep isolation grooves by low-pressure chemical vapor deposition technology.

[0023] Further, in the ion implantation process, boron ions are selected as the implanted ions, the ion implantation energy is between 10 - 100 keV, and during the ion implantation process, rotational and scanning movements are performed.

[0024] Further, when etching grooves a, b, c, and d in the N-type epitaxial layer, the depths of grooves a, b, c, and d do not penetrate the N-type epitaxial layer.

[0025] Further, the doping concentration of the N-type doped polysilicon is 1E11 - 1E20 cm -3 。

[0026] Further, the thickness of the via dielectric layer is 2 - 3 um.

[0027] Further, the metal deposited on the via dielectric layer is metal AlCu or AlSiCu.

[0028] Further, the connection methods between the basic structural units of the TVS device include: using a parallel connection of multiple doped silicons and a series connection of multiple basic structural units.

[0029] The beneficial effects of the present invention are as follows:

[0030] 1. The present invention adopts deep trench isolation and trench filling doped polysilicon technology, which can greatly reduce the chip size.

[0031] 2. In the present invention, for the PN junction formed by the doped polysilicon trench, the doping concentration distribution is uniform, which improves the uniformity of current flow inside the device and effectively avoids the possibility of device failure caused by current concentration.

[0032] 3. In the present invention, for the PN junction formed by the doped polysilicon trench, its depth / width can be accurately adjusted according to requirements, which is beneficial to accurately adjusting the clamping voltage.

[0033] 4. In the present invention, for the PN junction formed by the doped polysilicon trench, its area is larger than that of the planar PN junction, effectively increasing the absorption capacity of the surge current, and the process is simple with less requirements for the machine platform.

[0034] 5. In the present invention, multiple doped polysilicon trenches are connected in parallel, which can reduce the bulk resistance of the PN junction, thereby obtaining a low clamping voltage. Description of the Drawings

[0035] Figure 1 It is the overall flowchart of the manufacturing method of the TVS device with large current and small area;

[0036] Figure 2 It shows the structural schematic diagram of forming an N-type epitaxial layer on a P-type substrate;

[0037] Figure 3Shows the structure after forming an oxide layer on the surface of the N-type epitaxial layer and etching out deep isolation trenches;

[0038] Figure 4 Is the structure after filling the deep isolation trenches with in-situ polysilicon;

[0039] Figure 5 Presents the structure after forming P-type wells between the deep isolation trenches;

[0040] Figure 6 Is the structure after etching trenches a, b, c, d in the N-type epitaxial layer;

[0041] Figure 7 Is the structure after filling the trenches with N-type doped polysilicon and sealing;

[0042] Figure 8 Is the structure after removing the surface N-type doped polysilicon and oxide layer and performing high-temperature diffusion and push junction;

[0043] Figure 9 Is the structure after depositing a via dielectric layer, opening vias, and filling with conductive metal;

[0044] Figure 10 Presents the finally formed TVS device structure;

[0045] Figure 11 Is a schematic diagram of the connection of the basic structural unit of the TVS device. Detailed implementation manners

[0046] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0047] Embodiment 1

[0048] In an electronic device, a TVS device is used to protect a circuit from transient overvoltage damage. However, it is difficult to balance large current-carrying capacity and small area design in traditional TVS devices. Large current-carrying capacity usually requires a larger chip area to achieve, which increases costs and is not conducive to the application of miniaturized electronic products.

[0049] Please refer to Figure 1 , which shows a manufacturing method of a TVS device with large current-carrying capacity and small area provided by an embodiment of the present invention, including:

[0050] S100: Select a P-type substrate according to the resistivity, and form an N-type epitaxial layer on the P-type substrate through a chemical vapor deposition process.

[0051] S200: Form an oxide layer on the surface of the N-type epitaxial layer through a thermal oxidation or chemical vapor deposition process, and then etch a number of deep isolation trenches in the epitaxial layer through photolithography and dry etching processes, extending all the way to the P-type substrate.

[0052] S300: Fill the deep isolation trenches with in-situ polysilicon.

[0053] S400: Use an ion implantation process between the deep isolation trenches to form a P-type well.

[0054] S500: Etch trenches a, b, c, and d in the N-type epitaxial layer through photolithography and dry etching processes.

[0055] S600: Fill trenches a, b, c, and d with N-type doped polysilicon through a deposition process and seal them.

[0056] S700: Remove the surface N-type doped polysilicon and the oxide layer through an etching process, and then perform high-temperature diffusion to push the junction to the required junction voltage performance.

[0057] S800: Deposit an oxide layer on the surface of the N-type epitaxial layer as a via dielectric layer through a deposition process. Open vias on the via dielectric layer corresponding to the positions of trenches a, b, c, and d through photolithography and etching processes, and fill the vias with a conductive metal.

[0058] S900: Deposit a metal on the via dielectric layer through a deposition process, and through photolithography and etching processes, retain the metal above trenches a and d, and between trenches b and c, and then perform a final passivation process to form the required TVS device.

[0059] By optimizing the device structure and manufacturing process, the TVS device of the present invention can effectively reduce the chip area and cost while achieving a large current-carrying capacity, which is beneficial to the miniaturization of electronic products.

[0060] S100 carefully selects a P-type substrate with a resistivity in the range of 0.001 - 0.008 Ω·cm, and uses a chemical vapor deposition process to grow an N-type epitaxial layer with a thickness of 2 - 20 μm on the P-type substrate under the condition of strictly controlling parameters such as temperature, gas flow rate, and pressure.

[0061] S100 specifically includes the following steps:

[0062] S110: Selection of the P-type substrate.

[0063] Screen P-type substrate materials with different resistivity values. Resistivity is an important parameter affecting the performance of TVS devices. Select a P-type substrate with a resistivity in the range of 0.001 - 0.008 Ω·cm. Too low a resistivity may lead to excessive leakage current, while too high a resistivity will affect the on-state performance of the device.

[0064] In a possible implementation, by conducting electrical property tests on the P-type substrate material, including resistivity measurement, carrier mobility analysis, etc., select the substrate material that meets the requirements.

[0065] S120: Form an N-type epitaxial layer on the P-type substrate, as Figure 2 shown.

[0066] Use chemical vapor deposition (CVD) technology to grow the N-type epitaxial layer. The growth temperature is one of the key factors, generally controlled between 900 - 1200 °C.

[0067] Meanwhile, adjust the flow rate and pressure of the reaction gases. The reaction gases usually include a silicon source gas (such as silane) and a doping gas (such as phosphine). The flow rate of the silicon source gas is generally controlled between 10 - 100 sccm, and the flow rate of the doping gas is adjusted according to the required doping concentration of the epitaxial layer, generally between 0.1 - 10 sccm. In terms of pressure, maintain it at 10 - 100 Torr.

[0068] During the growth process, by real-time monitoring the thickness and doping concentration of the epitaxial layer, use an optical interferometer to measure the thickness and the four-probe method to measure the resistivity to adjust the process parameters, ensure that the thickness of the epitaxial layer is within the range of 2 - 20 μm, and the doping concentration meets the design requirements, so as to form a good PN junction structure and lay the foundation for subsequent device manufacturing.

[0069] As Figure 3 shown, S200 first generates an oxide layer with a thickness of 100 - 10000 Å on the surface of the N-type epitaxial layer through thermal oxidation or chemical vapor deposition technology, and then successively implements a photolithography process and a dry etching process, thereby precisely etching a deep isolation trench on the epitaxial layer.

[0070] S200 specifically includes the following steps:

[0071] S210: Form an oxide layer on the surface of the N-type epitaxial layer.

[0072] The formation of the oxide layer can select thermal oxidation or chemical vapor deposition technology. In the thermal oxidation process, at 800 - 1200 °C, silicon reacts with oxygen to generate silicon dioxide. Its advantages are high-quality oxide layer, good compactness, and low interface state density with the silicon substrate.

[0073] Exemplarily, for the oxide layer thermally oxidized at 1000 °C, its breakdown electric field strength can reach above 10 MV / cm.

[0074] In the chemical vapor deposition process, an oxide layer is formed by the reaction of a silicon source gas (such as tetraethyl orthosilicate) and oxygen at 300 - 600 °C. The advantage of the chemical vapor deposition process is that the oxide layer deposition can be carried out after a process step that is not suitable for high-temperature treatment, and the thickness uniformity of the oxide layer can be better controlled.

[0075] In the present invention, a suitable process is selected according to the actual process requirements to form an oxide layer with a thickness of 100 - 10,000 Å. The thickness control is achieved by adjusting parameters such as the process time and gas flow rate. For example, in the thermal oxidation process, the longer the oxidation time, the thicker the oxide layer, and the growth thickness of the oxide layer per hour is approximately between 1000 - 5000 Å.

[0076] S220: Etch a number of deep isolation trenches in the epitaxial layer and extend them all the way to the P-type substrate.

[0077] Perform photoresist coating, soft baking, exposure, post-baking, and developing photolithography process operations to form a photoresist pattern. Ensure the accuracy and clarity of the photoresist pattern, thereby providing a guarantee for accurate etching of the trenches in the subsequent process.

[0078] Through the etching process, a number of deep isolation trenches are etched in the epitaxial layer and extend all the way to the P-type substrate. For the etching of the deep isolation trenches, a suitable etching gas is selected. Exemplarily, the etching gas is selected as a mixed gas of a fluorine-based gas and an inert gas. The etching time is calculated and adjusted according to the required depth of the deep isolation trenches to ensure that the width of the deep isolation trenches is 0.5 - 1.2 μm, the depth is 3 - 25 μm, and they extend all the way to the P-type substrate. During the etching process, the etching depth is monitored by an endpoint detection technique. When the characteristic spectral signal of the silicon substrate is detected, the etching is stopped to prevent over-etching from damaging the substrate.

[0079] As Figure 4 shown, S300 uses in-situ polysilicon to fill the deep isolation trenches to achieve the isolation effect.

[0080] The in-situ polysilicon deposition process uses low-pressure chemical vapor deposition (LPCVD) technology.

[0081] In a possible implementation, the silicon source gas is selected as silane, and the deposition is carried out under the conditions that the pressure in the reaction chamber is 10 - 100 mTorr and the temperature is 500 - 700 °C. The silane flow rate is controlled between 10 - 100 sccm, and hydrogen is used as the carrier gas with a flow rate of 100 - 1000 sccm.

[0082] Exemplarily, when the silane flow rate is 50 sccm, the hydrogen flow rate is 500 sccm, the reaction chamber pressure is 50 mTorr, and the temperature is 600 °C, a polysilicon layer with good quality and better filling performance can be obtained. During the deposition process, the growth rate of polysilicon is closely related to process parameters and is generally between 0.05 - 0.5 μm / min. By real-time monitoring the deposition rate and thickness and adjusting process parameters, it is ensured that the deep isolation trenches are completely filled.

[0083] As Figure 5 shown, in S400, an ion implantation process is used between the deep isolation trenches to form a P-type well.

[0084] First, a suitable impurity ion source is selected. Boron ions are usually selected as the implanted ions because boron atoms can provide hole carriers, thereby forming a P-type semiconductor region in the silicon material. The ion implantation energy is a key factor determining the depth of the P-type well, and its range is generally between 10 - 100 keV. By precisely adjusting the energy, the implantation depth and dose of boron ions in the silicon lattice can be controlled.

[0085] During the ion implantation process, in order to ensure that the entire wafer surface can receive ion implantation evenly, the wafer needs to perform precise rotation and scanning movements. The rotation and scanning movements can make the ions evenly distributed in the area between the deep isolation trenches, forming a P-type well with good uniformity and stable electrical properties.

[0086] As Figure 6 shown, in S500, trenches a, b, c, and d are etched in the N-type epitaxial layer through photolithography and dry etching processes.

[0087] S500 is similar to S220. Again, photolithography process operations such as photoresist coating, soft baking, exposure, post-baking, and development are performed to form a photoresist pattern corresponding to the patterns of trenches a, b, c, and d. Ensure the accuracy and clarity of the photoresist pattern, thereby providing guarantee for subsequent accurate etching of the trenches.

[0088] The etching gas is also selected as a mixed gas of fluorine-based gas and inert gas.

[0089] The etching time is calculated according to the depth requirements of the trenches to ensure that the trench depth does not penetrate the N-type epitaxial layer. During the etching process, by real-time monitoring the etching rate and depth and measuring with an optical interferometer or a scanning electron microscope (SEM), the dimensional accuracy and shape quality of the trenches are guaranteed.

[0090] As Figure 7 shown, in S600, a deposition process is used to fill the previously etched trenches with N-type doped polysilicon with a doping concentration of 1E11 - 1E20 cm -3 and perform a sealing operation.

[0091] The S600 specifically includes the following steps:

[0092] S610: Deposit N-type doped polysilicon trenches a, b, c, and d through low-pressure chemical vapor deposition process.

[0093] Deposit N-type doped polysilicon using low-pressure chemical vapor deposition process. The doping concentration of the doped polysilicon is 1E11 - 1E20 cm -3 , and different doping concentrations are achieved by adjusting the flow rate of the doping gas.

[0094] Exemplarily, the doping gas is selected as phosphine. When the flow rate of phosphine is 0.5 - 5 sccm, N-type doped polysilicon with a doping concentration in the range of 1E15 - 1E18 cm -3 can be obtained. During the deposition process, ensure that the trenches are completely filled while maintaining the uniformity of the doping concentration.

[0095] S620: Seal the trenches a, b, c, and d.

[0096] After filling the trenches with polysilicon, it is necessary to seal the trenches to prevent impurities from entering the trenches during subsequent process steps.

[0097] As Figure 8 shown, in S700, the surface N-type doped polysilicon and the oxide layer are removed through an etching process, and then high-temperature diffusion is performed to push the junction to the required junction voltage performance. The diffusion temperature is 900 - 1200 °C, and the diffusion time is 10 - 90 min. Among them, the trench spacing needs to ensure that the diffusion regions formed after high-temperature diffusion do not touch each other, and there is still a gap in the middle, and an NPN structure can still be formed.

[0098] S710: Remove the surface N-type doped polysilicon and the oxide layer through a dry etching process.

[0099] The etching gas is selected as a fluorine-based gas, such as CF 4 or SF 6 .

[0100] At the same time, adjust the etching parameters. The radio frequency power is between 300 - 1000 W, the reaction chamber pressure is between 5 - 50 mTorr, and the etching time is between 1 - 10 min.

[0101] During the etching process, use endpoint detection technology to ensure that the surface layer is completely removed while avoiding damage to the underlying structure caused by over-etching.

[0102] S720: Perform a high-temperature diffusion process within a specific temperature and time range.

[0103] The high-temperature diffusion process is carried out in a high-temperature furnace at 900 - 1200 °C, and the diffusion time is 10 - 90 min.

[0104] During the diffusion process, precise control of temperature and time is crucial for forming the desired junction voltage performance. Higher temperatures and longer times will increase the diffusion depth and reduce the junction voltage; conversely, the junction voltage will increase. Through simulation calculations and actual tests, determine the appropriate temperature and time combination to ensure that the diffusion regions formed after high-temperature diffusion do not touch each other at the trench spacing, and there is still a gap in the middle, and the NPN structure can still be formed. At the same time, during the diffusion process, ensure the stability and uniformity of the furnace atmosphere to avoid uneven impurity distribution and affect device performance.

[0105] As Figure 9 shown, S800 deposits an oxide layer as a via dielectric layer through a deposition process, with a thickness of 2 - 3 μm. Through photolithography and etching processes, vias are opened at the positions of trenches a, b, c, d, and conductive metals such as W are filled in the vias.

[0106] The specific steps of S800 include:

[0107] S810: Deposit an oxide layer as a via dielectric layer on the surface of the N-type epitaxial layer through a deposition process.

[0108] Deposit an oxide layer with a thickness of 2 - 3 μm as a via dielectric layer through chemical vapor deposition. During the deposition process, monitor the growth rate and thickness of the oxide layer in real time, and use equipment such as an optical interferometer for measurement to ensure that the thickness of the oxide layer meets the requirements of 2 - 3 μm.

[0109] S820: Open vias on the via dielectric layer corresponding to the positions of trenches a, b, c, d through photolithography and etching processes.

[0110] Perform photolithography process operations such as photoresist coating, soft baking, exposure, post-baking, and development to form a photoresist pattern on the via dielectric layer corresponding to the positions of trenches a, b, c, d. Ensure the accuracy and clarity of the photoresist pattern, thereby providing guarantee for subsequent accurate etching of the trenches.

[0111] Through the etching process, etch the photoresist pattern to open the vias.

[0112] S830: After the via etching is completed, perform metal filling.

[0113] Select a conductive metal and fill the vias using chemical vapor deposition (CVD) process. First, evacuate the reaction chamber to below 10 -4 Torr, then introduce tungsten hexafluoride (WF 6 ) as the tungsten source gas and hydrogen (H 2 ) as the reducing agent. The flow rate of WF 6 is 1 - 10 sccm, and the flow rate of H 2The flow rate is 10 - 100 sccm, the reaction chamber pressure is 10 - 100 mTorr, and the temperature is between 300 - 600 °C.

[0114] During the deposition process, a temperature sensor and a pressure sensor are used to monitor the reaction chamber temperature and pressure in real time. The gas flow rate is precisely adjusted through a flow controller to ensure the stability of process parameters. The deposition rate is generally between 0.05 - 0.5 μm / min. The deposition time is calculated based on the required via filling height to ensure that the vias are completely filled, while ensuring the uniformity and continuity of the filled metal, providing a reliable guarantee for the electrical connection of subsequent devices. After filling, the wafer is annealed at a temperature between 400 - 800 °C for 30 - 120 min to eliminate the stress generated during the metal filling process and improve the adhesion between the metal and the via wall and the underlying structure.

[0115] As Figure 10 shown, through the deposition process, metal AlCu or AlSiCu is deposited on the via dielectric layer with a thickness of 3 - 5 μm. Through photolithography and etching processes, the metal above trenches a and d, and between trenches b and c is retained, and after the final passivation treatment, the required TVS device is formed.

[0116] The specific steps of S900 include:

[0117] S910: Deposit metal AlCu or AlSiCu on the via dielectric layer through physical vapor deposition or chemical vapor deposition processes.

[0118] Taking physical vapor deposition as an example, using the sputtering process, the AlCu or AlSiCu target is sputter - deposited on the wafer surface in an argon (Ar) plasma environment. During the deposition process, the sputtering power is controlled between 100 - 1000 W, and the gas pressure is between 0.1 - 10 mTorr. For example, when the sputtering power is 500 W and the gas pressure is 1 mTorr, a metal layer with uniform thickness and good adhesion can be obtained. The thickness of the metal layer is controlled between 3 - 5 μm and is achieved by adjusting the deposition time and rate. The deposition rate is generally between 0.05 - 0.5 μm / min, and the deposition time is calculated according to the required thickness to ensure that the metal layer meets the design requirements.

[0119] S920: Through photolithography and etching processes, retain the metal above trenches a and d, and between trenches b and c

[0120] During the process of retaining the metal above trenches a and d, and between trenches b and c through photolithography and etching processes, photolithography operations are first carried out using a high-precision photolithography machine and a custom-designed mask. After the photolithography steps of photoresist coating, soft baking, exposure, post-baking, and development, a photoresist pattern that exactly corresponds to the desired metal retention pattern is formed. This photoresist pattern serves as a masking layer for subsequent etching to protect the metal areas that need to be retained. Then, metal etching is performed to accurately etch away the unwanted metal parts, only retaining the metal above trenches a and d, and between trenches b and c.

[0121] S910: After the metal patterning is completed, passivation treatment is carried out.

[0122] After the metal patterning is completed, passivation treatment is carried out to protect the device from the external environment. The passivation layer can be silicon nitride or silicon oxide.

[0123] Exemplarily, taking chemical vapor deposition of silicon nitride as an example, silane and ammonia are used as reaction gases, and deposition is carried out under the conditions that the reaction chamber pressure is 10 - 100 mTorr and the temperature is 300 - 600 °C. The silane flow rate is 1 - 10 sccm, and the ammonia flow rate is 10 - 100 sccm. The deposition thickness and quality of the passivation layer are crucial for the long-term stability and reliability of the device. By optimizing the process parameters, it is ensured that the passivation layer has no pinholes, cracks and other defects, effectively blocking the intrusion of impurities such as water vapor and ions, thereby improving the service life and performance stability of the TVS device, and finally forming the required large-current small-area TVS device.

[0124] Example 2

[0125] In the formation of the basic structural unit in S100 - S900 in Example 1, according to requirements, multiple doped silicon in parallel can be adopted, which can greatly increase the PN junction area, obtain a larger current-carrying capacity, reduce the bulk resistance, get a lower clamping voltage, and can also expand the series connection of multiple basic units to obtain the required breakdown voltage. As Figure 11 shown.

[0126] In the design of TVS devices, the construction and combination methods of the basic structural units have a key impact on their performance.

[0127] In terms of increasing the current-carrying capacity, the method of connecting multiple doped silicon elements in parallel is utilized. During the manufacturing process, a PN junction is formed in each doped silicon part. When multiple such PN junctions are connected in parallel, it is equivalent to connecting multiple conductive channels in parallel. At the same time, due to the existence of multiple conductive channels, the overall bulk resistance is reduced. According to Ohm's law, under the same current condition, a lower bulk resistance will result in a lower voltage drop, that is, a lower clamping voltage is obtained. This is crucial for protecting the backend circuit from excessive voltage impact because a lower clamping voltage can more effectively limit the transient overvoltage within a safe range and reduce the risk of damage to circuit components.

[0128] In terms of meeting the withstand voltage requirement, the method of connecting multiple basic units in series is adopted. Each basic unit can withstand a certain voltage in terms of its structure. When multiple basic units are connected in series, the total voltage they can withstand is equal to the sum of the withstand voltage values of each basic unit. In this way, according to the specific requirements for the withstand voltage of the TVS device in actual applications, the number of basic units connected in series can be flexibly selected, so as to accurately obtain the required withstand voltage value, ensuring that the TVS device can work reliably in circuit environments with various different voltage levels and effectively protecting the circuit from damage by excessive voltage.

[0129] This design that can flexibly adjust the current-carrying capacity and withstand voltage value enables the TVS device to better meet the needs of diverse electronic devices and circuit systems, improving its versatility and practicality.

[0130] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are only examples and not limitations. It cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present application. Additionally, the above-disclosed specific details are only for illustrative and easy-to-understand purposes, not limitations. The above details do not limit the present application to necessarily adopt the above specific details for implementation.

[0131] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present application are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any way. Words such as "including", "comprising", "having", etc. are open-ended terms, meaning "including but not limited to", and can be used interchangeably with each other. The words "or" and "and" used herein refer to the phrase "and / or", and can be used interchangeably with each other, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to", and can be used interchangeably with each other.

[0132] It should also be noted that in the devices, equipment and methods of the present application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations shall be regarded as equivalent solutions of the present application.

[0133] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

[0134] The foregoing is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for manufacturing a TVS device with large through-current and small area, characterized in that: include: A P-type substrate is selected according to the resistivity, and an N-type epitaxial layer is formed on the P-type substrate by a chemical vapor deposition process; An oxide layer is formed on the surface of the N-type epitaxial layer by thermal oxidation or chemical vapor deposition process, and then a plurality of deep isolation grooves are etched in the epitaxial layer and extended to the P-type substrate by photolithography and dry etching process; Using in-situ polysilicon to fill deep isolation trenches; An ion implantation process is used between the deep isolation trenches to form a P-type well; Through photolithography and dry etching processes, grooves a, b, c, and d are etched in the N-type epitaxial layer; Through a deposition process, N-type doped polysilicon is filled into trenches a, b, c, and d and sealed; The surface N-type doped polysilicon and oxide layer are removed by etching process, and then the junction is pushed to the required junction voltage performance by high-temperature diffusion; By means of a deposition process, an oxide layer is deposited on the surface of the N-type epitaxial layer as a through-hole dielectric layer, through holes are opened on the through-hole dielectric layer corresponding to the positions of the grooves a, b, c, and d by means of a photolithography and etching process, and conductive metal is filled in the through holes; Through the deposition process, metal is deposited on the through-hole dielectric layer, and through the photolithography and etching processes, the metal above the groove a and the groove d, and between the groove b and the groove c is retained, and then the final passivation treatment is performed to form the required TVS device; The metal deposited on the through-hole dielectric layer is metal AlCu or AlSiCu.

2. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: The P-type substrate is selected from a substrate with a resistivity between 0.001 and 0.008 Ω.cm.

3. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: The thickness of the oxide layer formed on the surface of the N-type epitaxial layer is 100-10000A; In the dry etching process, the etching gas is a mixture of fluorine-based gas and inert gas; The deep isolation trench has a width of 0.5-1.2 um and a depth of 3-25 um.

4. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: The in-situ polysilicon is filled into the deep isolation trench by using low pressure chemical vapor deposition technology.

5. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: In the ion implantation process, boron ions are selected as implanted ions, and the ion implantation energy is between 10-100 keV. Meanwhile, during the ion implantation process, rotation and scanning motion are performed.

6. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: When the grooves a, b, c, and d are etched in the N-type epitaxial layer, the depths of the grooves a, b, c, and d do not pass through the N-type epitaxial layer.

7. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: The doping concentration of the N-type doped polysilicon is 1E11-1E20cm -3 .

8. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: The through-hole dielectric layer has a thickness of 2-3 um.

9. A method for manufacturing a TVS device with large through-current and small area according to any one of claims 1 to 8, characterized in that: The connection method between the basic structural units of the TVS device includes: using a plurality of doped silicon in parallel or a plurality of basic structural units in series.

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