An etching method for improving ohmic contact resistance yield

Abstract

The present invention discloses an etching method for improving the yield of ohmic contact resistance, comprising the following steps: S1, using MOCVD epitaxial growth GaN and buffer GaN layer, GaN channel layer, AlGaN barrier layer, MOSiN cap layer and ALN stop layer on Si substrate layer or sapphire substrate layer; S2, depositing LPSIN dielectric layer; S3, making photolithography pattern on LPSIN dielectric layer; S4, using an etcher on the wafer prepared in the above steps, etching in the order of PR glue layer, LPSIN dielectric layer, ALN stop layer, MOSiN cap layer, AlGaN barrier layer and GaN channel layer to obtain the corresponding etched pattern; S5, performing degumming treatment; S6, again performing photolithography pattern on the LPSIN dielectric layer after degumming and the etched pattern surface formed after step S4 treatment, depositing metal electrodes, and then etching or stripping unnecessary metal to form a stable ohmic contact resistance. The etching method of the present invention can obtain an ohmic contact resistance with small contact resistance, good surface morphology, high contour clarity and stable and reliable.

Description

Technical Field

[0001] The invention relates to the field of reducing ohmic contact resistance, and in particular to an etching method for improving the yield rate of ohmic contact resistance. Background Art

[0002] At present, low ohmic contact resistance is the basis for achieving high quality. GaN materials and ohmic contacts with metal electrodes have an important impact on device performance. High-reliability ohmic contacts are necessary for GaN electronic devices. Too high ohmic contact resistance will generate more Joule heat, shortening the device life and performance. In addition, parasitic resistance will also deteriorate the optoelectronic performance of the device, and parasitic resistance mainly comes from the ohmic contact between GaN and the metal electrode. Since ohmic contact is a key process for manufacturing many optoelectronic devices, the research on ohmic contact of GaN devices has become one of the current topics of concern. The quality of ohmic contact directly affects the two key parameters of AlGaN / GaN HEMT—transconductance and saturation current. How to obtain ohmic contact with low contact resistance, good surface morphology, high contour clarity and stable and reliable is one of the important issues in the development of AlGaN / GaN HEMT.

[0003] In the process of making the ohmic contact of this step, the device needs to go through processes such as lithography, etching, degumming, and annealing. Different etching processes and etching methods and etching conditions (pressure, temperature, gas, power), and different annealing conditions (temperature, time) have an important impact on the formation and stability of the ohmic contact. Conventional etching will form a large angle in the AlN barrier layer or other barrier layers, resulting in abnormal filling metal, affecting the ohmic contact between the two-dimensional electron gas, and causing the ohmic contact in batch operations to be unstable or too large. The reason is that when conventionally etching LPSiN, F-based gas is used to etch to the AlN barrier layer or other barrier layer, and then Cl-based gas is switched to etch. After etching AlN or other etching barrier layers, F-based gas is switched again to etch the MOSiN cap layer. After etching MOSiN, Cl-based gas is switched to etch the AlGaN barrier layer, and etching is completed. Because after etching LPSiN with F-based gas, the gas is switched to etch AlN because of the addition of LPSiN hard mask, which makes it impossible to make the AlN etching angle smaller. Then, a clear two-segment angle is formed at AlN. When etching AlGaN next, the AlN etching angle is slightly larger due to the large-angle hard mask of AlN, as shown in Figure 3. Finally, after metal deposition, voids are formed at AlN and AlGaN, affecting the ohmic contact between the metal and the barrier layer, resulting in unstable and large ohmic contact resistance, with abnormal results of about 1 ohm / mm-1000 ohm / mm. Summary of the invention

[0004] In order to solve the existing problems, the present invention provides an etching method for improving the yield of ohmic contact resistance, and the specific scheme is as follows:

[0005] An etching method for improving the yield of ohmic contact resistance comprises the following steps:

[0006] S1, using MOCVD to epitaxially grow GaN and buffer GaN layers, GaN channel layers, AlGaN barrier layers, MOSiN cap layers and AlN stop layers on Si substrate layers or sapphire substrate layers;

[0007] S2, using low pressure vapor deposition of an LPSIN dielectric layer on the grown epitaxial layer;

[0008] S3, making a photolithography pattern on the LPSIN dielectric layer;

[0009] S4, using an etcher on the wafer prepared in the above steps, etching in the order of PR glue layer, LPSIN dielectric layer, ALN stop layer, MOSiN cap layer, AlGaN barrier layer, and GaN channel layer to obtain the corresponding etched pattern; the specific steps of etching are:

[0010] S41, first etch the PR glue layer and the LPSIN dielectric layer, first fast and then slow to improve the etching efficiency, and stop etching when the AlN layer is reached;

[0011] S42, switching the gas, and then etching the AlN stop layer and the MOSiN cap layer;

[0012] S43, etching until the remaining 2nm-30nm of the MOSiN cap layer is left, and then switching the gas again to etch the remaining MOSiN cap layer;

[0013] S44, switching the gas again to etch through the AlGaN barrier layer to a portion of the GaN channel layer;

[0014] S5, performing a degumming process;

[0015] S6, again performing photolithography patterning on the LPSIN dielectric layer after the resist is removed and the etched pattern surface formed after the processing in step S4, depositing metal electrodes, and then etching or stripping unnecessary metals to form a stable ohmic contact resistance.

[0016] Preferably, in step S1 , the thickness of the MOSiN cap layer is 20 nm-70 nm, and the thickness of the ALN stop layer is 2 nm-20 nm.

[0017] Preferably, the thickness of the LPSIN dielectric layer in step S2 is 100 nm-800 nm.

[0018] Preferably, the thickness of the PR glue of the photolithography pattern in step S3 is 500nm-3000nm.

[0019] Preferably, in step S41, when etching the LPSIN dielectric layer of 220nm-260nm, the etcher pressure is set to 2mT-20mT, the etching source power is 200W-1000W, the bias power is 30W-300W, the gases selected are Cl2 and Ar, the flow rates are 50sccm and 30sccm respectively, the etching temperature is 10 degrees Celsius-40 degrees Celsius, the back helium pressure is set to 5 Torr-15 Torr, and the etching time is 30 seconds-300 seconds; the pressure for etching the remaining LPSIN dielectric layer is set to 2mT-20mT, the etching source power is 100W-500W, the bias power is 20W-150W, the gases selected are SF6 and O2, the flow rates are 30sccm and 10-30sccm respectively, the etching temperature is 10 degrees Celsius-40 degrees Celsius, the back helium pressure is set to 5 Torr-15 Torr, and the etching time is 20s-150s.

[0020] Preferably, in step S42, the AlN stop layer and the MOSiN cap layer are etched synchronously, and the etching conditions for etching the AlN stop layer and part of the MOSiN cap layer are: pressure 2mT-20mT; etching source power is 200W-1000W, bias power is 30W-150W; gas selection Cl2 and Ar, flow rate is 50sccm and 30sccm respectively; etching temperature is 10 degrees Celsius-40 degrees Celsius; back helium pressure is set to 5 Torr-15 Torr; because the AlGaN barrier layer forms a two-dimensional electron gas, it cannot accept etching damage, and etching to the MOSiN When there are 2nm-30nm left in the cap layer, switch CF4 and N2, which do not damage the AlGaN barrier layer, as the main etching gas, with a pressure of 2mT-15mT; the etching source power is 100W-900W, and the bias power is 5W-130W; the CF4 and N2 flow rates are 20sccm and 80sccm respectively, and the etching temperature is 10 degrees Celsius-40 degrees Celsius; the back helium pressure is set to 5 Torr-15 Torr; then etch the AlGaN barrier layer, and the etching conditions are: pressure 2mT-20mT, etching source power 30W-1000W, bias power 20W-150W, gas selection Cl2 and BCl3, flow rates are 5sccm and 35sccm respectively; etching temperature is 10 degrees Celsius-40 degrees Celsius; the back helium pressure is set to 5 Torr-15 Torr, and the etching time is 20 seconds-200 seconds. This method can produce a consistent etching angle and a less steep morphology.

[0021] Preferably, the thickness of the etched portion of the GaN channel layer in step S44 is in the range of 10 nm to 30 nm.

[0022] Preferably, the desizing process in step S5 is performed by dry desizing, wet desizing, or a combination of dry and wet desizing, and the etching machine is not limited to the ICP model or the CCP model.

[0023] The present invention also discloses a computer-readable storage medium, on which a computer program is stored. After the computer program is run, any of the above methods is executed.

[0024] The present invention also discloses a computer system, including a processor and a storage medium, wherein a computer program is stored on the storage medium, and the processor reads and runs the computer program from the storage medium to execute any of the methods described above.

[0025] The beneficial effects of the present invention are:

[0026] The etching method of the present invention can obtain an ohmic contact resistance with low contact resistance, good surface morphology, high contour clarity and stable and reliable. It solves the problem that the etching angle is large and has obvious two-stage angles caused by defects in the timing of switching gas and selecting gas in traditional etching, and the problem that the two-stage angle is large and causes metal filling to form ohmic contacts with voids, causing abnormal ohmic contact resistance, cannot be solved even after reducing the photoresist angle. The use of optimized etching conditions and etching methods can significantly reduce the steepness and consistency of the angle after etching, thereby reducing the ohmic contact resistance and greatly improving the device yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 Schematic diagram of a layer before etching in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the layer after etching and de-resisting;

[0030] Figure 3 Schematic diagram of abnormal layers after traditional etching;

[0031] Figure 4 Schematic diagram of the layers of photolithography performed on the LPSIN dielectric layer in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] An etching method for improving the yield of ohmic contact resistance comprises the following steps:

[0034] S1, such as Figure 1 As shown, GaN and buffer GaN layer 102, GaN channel layer 103, AlGaN barrier layer 104, MOSiN cap layer 105 and ALN stop layer 106 are epitaxially grown on Si substrate layer or sapphire substrate layer 101 using MOCVD. The thickness of MOSiN cap layer 105 is 20nm-70nm, and the thickness of ALN stop layer 106 is 2nm-20nm. In a specific embodiment, the thickness of MOSiN cap layer 105 is 50nm, and the thickness of ALN stop layer 106 is 5nm.

[0035] S2, using low pressure vapor deposition on the grown epitaxial layer, a LPSIN dielectric layer 107 is formed; the thickness of the LPSIN dielectric layer 107 is 100 nm to 800 nm. In a specific embodiment, the thickness of the LPSIN dielectric layer 107 is 300 nm.

[0036] S3, such as Figure 4 As shown, a photolithography pattern is made on the LPSIN dielectric layer 107; the thickness of the PR glue of the photolithography pattern is 500nm-3000nm.

[0037] S4, using an etcher on the wafer prepared in the above steps, etching in the order of PR glue layer, LPSIN dielectric layer 107, ALN stop layer 106, MOSiN cap layer 105, AlGaN barrier layer 104, and GaN channel layer 103 to obtain the corresponding etched pattern; the specific steps of etching are:

[0038] S41 , first etch the PR glue layer and the LPSIN dielectric layer 107 , first fast and then slow to improve the etching efficiency, and stop etching when the AlN layer 106 is reached.

[0039] Specifically, when etching the LPSIN dielectric layer 107, 220nm-260nm, the etcher pressure is set to 2mT-20mT, the etching source power is 200W-1000W, the bias power is 30W-300W, the gases selected are Cl2 and Ar, the flow rates are 50sccm and 30sccm respectively, the etching temperature is 10 degrees Celsius-40 degrees Celsius, the back helium pressure is set to 5 Torr-15 Torr, and the etching time is 30 seconds-300 seconds; the pressure for etching the remaining LPSIN dielectric layer 107 is set to 2mT-20mT, the etching source power is 100W-500W, the bias power is 20W-150W, the gases selected are SF6 and O2, the flow rates are 30sccm and 10-30sccm respectively, the etching temperature is 10 degrees Celsius-40 degrees Celsius, the back helium pressure is set to 5 Torr-15 Torr, and the etching time is 20s seconds-150 seconds.

[0040] S42 , switching the gas, and then etching the AlN stop layer 106 and the MOSiN cap layer 105 .

[0041] Specifically, the AlN stop layer 106 and the MOSiN cap layer 105 are etched synchronously, and the etching conditions for etching the AlN stop layer 106 and part of the MOSiN cap layer 105 are: pressure 2mT-20mT; etching source power is 200W-1000W, bias power is 30W-150W; gas selection Cl2 and Ar, flow rate is 50sccm and 30sccm respectively; etching temperature is 10 degrees Celsius-40 degrees Celsius; back helium pressure is set at 5 Torr-15 Torr; because the AlGaN barrier layer 104 forms a two-dimensional electron gas, it cannot accept etching damage, and etching to the MOSiN When there is 2nm-30nm remaining on the cap layer 105, CF4 and N2 which do not damage the AlGaN barrier layer 104 are switched as the main etching gas, with a pressure of 2mT-15mT; the etching source power is 100W-900W, and the bias power is 5W-130W; the flow rates of CF4 and N2 are 20sccm and 80sccm respectively, and the etching temperature is 10 degrees Celsius-40 degrees Celsius; the back helium pressure is set to 5 Torr-15 Torr; then the AlGaN barrier layer 104 is etched, and the etching conditions are: pressure 2mT-20mT, etching source power 30W-1000W, bias power 20W-150W, gas selection Cl2 and BCl3, flow rates are 5sccm and 35sccm respectively; the etching temperature is 10 degrees Celsius-40 degrees Celsius; the back helium pressure is set to 5 Torr-15 Torr, and the etching time is 20 seconds-200 seconds. This method can produce a consistent etching angle and a less steep morphology.

[0042] S43, etching until the remaining 2nm-30nm of the MOSiN cap layer 105 is left, and then switching the gas again to etch the remaining MOSiN cap layer 105;

[0043] S44, switching the gas again to etch through the AlGaN barrier layer 104 to a portion of the GaN channel layer 103; wherein the thickness of the etched portion of the GaN channel layer 103 ranges from 10 nm to 30 nm.

[0044] S5, performing a degumming process; Figure 2 shown.

[0045] Specifically, the desizing process is performed by dry desizing, wet desizing, or a combination of dry and wet desizing, and the etching machine is not limited to the ICP model or the CCP model.

[0046] S6, again perform photolithography on the LPSIN dielectric layer 107 after the debonding and the etched pattern surface formed after the processing in step S4, deposit metal electrodes, and then etch or strip unnecessary metal to form a stable ohmic contact resistance. The resistance range of the formed ohmic contact resistance is: 0.06-0.15 ohm / mm.

[0047] The etching method of the present invention can obtain an ohmic contact resistance with low contact resistance, good surface morphology, high contour clarity and stable and reliable. It solves the problem that the etching angle is large and has obvious two-stage angles caused by defects in the timing of switching gas and selecting gas in traditional etching, and the problem that the two-stage angle is large and causes metal filling to form ohmic contacts with voids, causing abnormal ohmic contact resistance, cannot be solved even after reducing the photoresist angle. The use of optimized etching conditions and etching methods can significantly reduce the steepness and consistency of the angle after etching, thereby reducing the ohmic contact resistance and greatly improving the device yield.

[0048] The present invention also discloses a computer-readable storage medium and a computer system, wherein a computer program is stored on the medium, and after the computer program is run, any of the above methods is executed. A computer system includes a processor and a storage medium, wherein a computer program is stored on the storage medium, and the processor reads and runs the computer program from the storage medium to execute any of the above methods.

[0049] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. The technician may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the present invention.

[0050] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in cooperation with a DSP core, or any other such configuration.

[0051] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read and write information from / to the storage medium. In an alternative, a storage medium may be integrated into a processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and the storage medium may reside in a user terminal as discrete components.

[0052] In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented as a computer program product in software, each function may be stored on or transmitted by a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a computer. As an example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of an instruction or data structure and can be accessed by a computer. Any connection is also properly referred to as a computer-readable medium. For example, if the software is transmitted from a website, a server, or other remote source using a coaxial cable, a fiber optic cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, wherein disk often reproduces data magnetically, while disc reproduces data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0053] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

[0054] Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An etching method for improving the yield of ohmic contact resistance, characterized in that: The following steps are involved: S1, using MOCVD to epitaxially grow GaN and buffer GaN layers (102), GaN channel layers (103), AlGaN barrier layers (104), MOSiN cap layers (105) and AlN stop layers (106) on a Si substrate layer or a sapphire substrate (101); S2, using low pressure vapor deposition on the grown epitaxial layer LPSIN dielectric layer (107); S3, making a photolithography pattern on the LPSIN dielectric layer (107); S4, using an etcher on the wafer prepared in the above steps, etching in the order of PR glue layer, LPSIN dielectric layer (107), ALN stop layer (106), MOSiN cap layer (105), AlGaN barrier layer (104), and GaN channel layer (103) to obtain a corresponding etched pattern; the specific steps of etching are: S41, first etching the PR glue layer and the LPSIN dielectric layer (107), first fast and then slow to improve the etching efficiency, and stop etching when the AlN layer (106); S42, switching the gas, and then etching the AlN stop layer (106) and the MOSiN cap layer (105); S43, etching until the remaining 2nm-30nm of the MOSiN cap layer (105) is left, and then switching the gas again to etch the remaining MOSiN cap layer (105); S44, switching the gas again to etch through the AlGaN barrier layer (104) to a portion of the GaN channel layer (103); S5, performing a degumming process; S6, again photolithography is performed on the LPSIN dielectric layer (107) after the resist is removed and the etched pattern surface formed after the processing in step S4, metal electrodes are deposited, and then unnecessary metals are etched or stripped to form a stable ohmic contact resistance.

2. The method according to claim 1, characterized in that: The thickness of the MOSiN cap layer (105) in step S1 is 20nm-70nm, and the thickness of the ALN stop layer (106) is 2nm-20nm.

3. The method according to claim 1, characterized in that: The thickness of the LPSIN dielectric layer (107) in step S2 is 100 nm-800 nm.

4. The method according to claim 1, characterized in that: The thickness of the PR glue of the photolithography pattern in step S3 is 500nm-3000nm.

5. The method according to claim 1, characterized in that: In step S41, when etching the LPSIN dielectric layer (107) 220nm-260nm, the etcher pressure is set to 2mT-20mT, the etching source power is 200W-1000W, the bias power is 30W-300W, the gas is Cl2 and Ar, the flow rate is 50sccm and 30sccm respectively, the etching temperature is 10 degrees Celsius-40 degrees Celsius, the back helium pressure is set to 5 Torr-15 Torr, and the etching time is 3 0 seconds-300 seconds; the pressure for etching the remaining LPSIN dielectric layer (107) is set to 2mT-20mT, the etching source power is 100W-500W, the bias power is 20W-150W, SF6 and O2 are selected as gases, the flow rates are 30sccm and 10-30sccm respectively, the etching temperature is 10 degrees Celsius-40 degrees Celsius, the back helium pressure is set to 5 Torr-15 Torr, and the etching time is 20s seconds-150 seconds.

6. The method according to claim 5, characterized in that In step S42, the AlN stop layer (106) and the MOSiN cap layer (105) are etched synchronously. The etching conditions for etching the AlN stop layer (106) and a portion of the MOSiN cap layer (105) are as follows: pressure 2mT-20mT; etching source power 200W-1000W, bias power 30W-150W; gas selection Cl2 and Ar, flow rates of 50sccm and 30sccm respectively; etching temperature 10 degrees Celsius-40 degrees Celsius; back helium pressure set 5 Torr-15 Torr; due to the AlGaN barrier layer (104) forming a two-dimensional electron gas, it cannot accept etching damage, and etching to the MOSiN When the cap layer (105) has a remaining thickness of 2nm-30nm, CF4 and N2 which do not damage the AlGaN barrier layer (104) are switched as the main etching gas, with a pressure of 2mT-15mT; the etching source power is 100W-900W, and the bias power is 5W-130W; the CF4 and N2 flow rates are 20sccm and 80sccm respectively, and the etching temperature is 10 degrees Celsius-40 degrees Celsius; the back helium pressure is set at 5 Torr-15 Torr; then the AlGaN barrier layer (104) is etched, and the etching conditions are: pressure 2mT-20mT, etching source power 30W-1000W, bias power 20W-150W, gas selection Cl2 and BCl3, flow rates are 5sccm and 35sccm respectively; the etching temperature is 10 degrees Celsius-40 degrees Celsius; the back helium pressure is set at 5 Torr-15 Torr, and the etching time is 20 seconds-200 seconds.

7. The method according to claim 1, characterized in that: The thickness of the etched portion of the GaN channel layer (103) in step S44 is in the range of 10 nm to 30 nm.

8. The method according to claim 1, characterized in that: The descaling process in step S5 is performed by dry descaling, wet descaling, or a combination of dry and wet descaling, and the etching machine is not limited to the ICP model or the CCP model.

9. A computer-readable storage medium, characterized in that: A computer program is stored on the medium, and after the computer program is run, the method according to any one of claims 1 to 8 is executed.

10. A computer system, characterized in that: The method comprises a processor and a storage medium, wherein a computer program is stored in the storage medium, and the processor reads and runs the computer program from the storage medium to execute the method as claimed in any one of claims 1 to 8.

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