Chip manufacturing method, chip and electronic equipment

Abstract

The invention is suitable for the technical field of chip manufacturing, and provides a chip manufacturing method, a chip and electronic equipment, and the chip manufacturing method comprises the steps: providing an insulating substrate which is provided with a first surface; a transition conducting layer is provided and arranged on the first surface of the insulating substrate, the transition conducting layer comprises a flexible layer and a conducting layer formed on the flexible layer, and the flexible layer is located between the first surface and the conducting layer; and patterning the conductive layer to form a first circuit pattern. The flexible layer is directly attached to the insulating substrate, the problem that the adhesive force between the insulating substrate and the conductive layer is weak does not exist, a PVD technology is not needed, the whole technology is simpler, and the production efficiency can be effectively improved.

Description

Technical Field

[0001] The present application belongs to the technical field of chip preparation, and in particular, relates to a chip manufacturing method, a chip and an electronic device. Background Art

[0002] The chip usually includes a glass substrate, a metal seed layer and an electroplating layer. The chip manufacturing process is to first set a metal seed layer on the glass substrate through PVD (Physical Vapor Deposition) technology, and then add an electroplating layer on the metal seed layer.

[0003] However, the above-mentioned manufacturing process is to form a metal seed layer on a glass substrate. The adhesion between the glass substrate and the metal seed layer is relatively small, which makes the connection between the glass substrate and the conductive layer unreliable, resulting in reduced product yield, or surface treatment is required on the glass substrate to improve adhesion, thereby reducing production efficiency. Summary of the invention

[0004] The embodiment of the present application provides a chip manufacturing method, which aims to solve the problem of low product yield caused by the existing chip manufacturing process.

[0005] The embodiment of the present application is implemented by providing a chip manufacturing method, comprising:

[0006] Providing an insulating substrate, the insulating substrate having a first surface;

[0007] Providing a transition conductive layer, and disposing the transition conductive layer on the first surface of the insulating substrate, wherein the transition conductive layer comprises a flexible layer and a conductive layer formed on the flexible layer, and the flexible layer is located between the first surface and the conductive layer;

[0008] The conductive layer is patterned to form a first circuit pattern.

[0009] Furthermore, a second circuit pattern is formed on the first circuit pattern, and a projection of the second circuit pattern on the first surface at least partially covers a projection of the first circuit pattern on the first surface.

[0010] Furthermore, the thickness of the second circuit pattern is greater than the thickness of the first circuit pattern.

[0011] Furthermore, the transition conductive layer further includes an adhesive layer and a release layer located on the flexible layer away from the conductive layer, and the step of disposing the transition conductive layer on the first surface of the insulating substrate includes:

[0012] The release layer is removed, and the side of the transition conductive layer having the adhesive layer is disposed on the first surface.

[0013] Furthermore, before the step of providing the transition conductive layer, the preparation method further comprises:

[0014] An adhesive layer is arranged on the first surface, and the flexible layer is combined with the first surface through the adhesive layer.

[0015] Further, the step of providing a transition conductive layer comprises:

[0016] providing a flexible layer;

[0017] The conductive layer is sputtered onto the flexible layer.

[0018] Furthermore, the preparation method also includes:

[0019] Remove the insulating substrate.

[0020] In a second aspect, the present application provides a chip, which is manufactured using the above-mentioned manufacturing method.

[0021] In a third aspect, the present application provides a chip, the chip comprising:

[0022] an insulating substrate having a first surface; and

[0023] A transition conductive layer disposed on a first surface of the insulating substrate;

[0024] The transition conductive layer includes a flexible layer and a conductive layer formed on the flexible layer. The flexible layer is located between the first surface and the conductive layer. The conductive layer includes a first circuit pattern.

[0025] Furthermore, it also includes a second circuit pattern, which is arranged on the first circuit pattern, and the projection of the second circuit pattern on the first surface at least partially covers the projection of the first circuit pattern on the first surface.

[0026] Furthermore, the transition conductive layer further comprises an adhesive layer, the adhesive layer is located on a side of the flexible layer away from the conductive layer, and the flexible layer is bonded to the first surface via the adhesive layer.

[0027] Furthermore, the insulating substrate is a glass substrate.

[0028] In a fourth aspect, the present application also provides an electronic device, comprising the chip as described above.

[0029] Beneficial effects of the present application: The chip manufacturing method provided by the present application includes providing an insulating substrate, the insulating substrate having a first surface; providing a transition conductive layer, and setting the transition conductive layer on the first surface of the insulating substrate, the transition conductive layer including a flexible layer and a conductive layer formed on the flexible layer, the flexible layer being located between the first surface and the conductive layer; and patterning the conductive layer to form a first circuit pattern. By directly bonding the flexible layer to the insulating substrate, there is no problem of weak adhesion between the insulating substrate and the conductive layer, and no PVD process is required, the overall process is simpler, and production efficiency can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a flow chart of an embodiment of a chip manufacturing method provided in the present application;

[0031] Figure 2 It is a schematic diagram of the film layer structure of a manufacturing process of an embodiment of a chip manufacturing method provided by the present application;

[0032] Figure 3 It is a flow chart of an embodiment of a chip manufacturing method provided by the present application, in which a second circuit pattern is provided;

[0033] Figure 4 It is a schematic diagram of a film layer structure provided with a second circuit pattern in one embodiment of a chip manufacturing method provided in the present application;

[0034] Figure 5 It is a partial structural schematic diagram of a second circuit pattern provided in an embodiment of a chip manufacturing method provided in the present application;

[0035] Figure 6 It is a schematic structural diagram of an embodiment of the chip manufacturing method provided by the present application, in which the transition conductive layer includes an adhesive layer and a release layer;

[0036] Figure 7 It is a structural schematic diagram of setting a glue layer in one embodiment of the chip manufacturing method provided in the present application.

[0037] Explanation of reference numerals: 100 - insulating substrate, 200 - transition conductive layer, 210 - flexible layer, 220 - conductive layer, 230 - adhesive layer, 240 - release layer, 221 - first circuit pattern, 300 - second circuit pattern, 400 - adhesive layer. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, in which the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0039] In the description of the present application, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0040] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0041] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0042] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0043] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference values ​​and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0044] The chip manufacturing method provided in the present application includes providing an insulating substrate, the insulating substrate having a first surface; providing a transition conductive layer, and setting the transition conductive layer on the first surface of the insulating substrate, the transition conductive layer including a flexible layer and a conductive layer formed on the flexible layer, the flexible layer being located between the first surface and the conductive layer; and patterning the conductive layer to form a first circuit pattern. By directly bonding the flexible layer to the insulating substrate, there is no problem of weak adhesion between the insulating substrate and the conductive layer, and no PVD process is required, the overall process is simpler, and production efficiency can be effectively improved.

[0045] like Figures 1 to 7 As shown, an embodiment of the present application provides a chip manufacturing method, comprising:

[0046] S1100, providing an insulating substrate 100, wherein the insulating substrate 100 has a first surface;

[0047] The insulating substrate 100 is a carrier of the chip, used to carry the transition conductive layer 200. During implementation, the insulating substrate 100 in the present application includes but is not limited to a glass substrate, a ceramic substrate, a silicon substrate, a polymer substrate or other well-known materials, without specific limitation.

[0048] In some embodiments, the insulating substrate 100 of the present application is preferably a glass substrate. The insulating substrate 100 may be a rectangular plate structure, such as Figure 2 Of course, the insulating substrate 100 may also be a circular, irregular or other shaped plate structure, without specific limitation.

[0049] As a possible implementation, the thickness range of the insulating substrate 100 is 5μm to 10mm. Preferably, the thickness range of the insulating substrate 100 is 200μm to 500μm. For example, the thickness range of the insulating substrate 100 is 250μm, 300μm, 350μm, 400μm or 450μm, etc., without limitation.

[0050] S1200, providing a transition conductive layer 200, and disposing the transition conductive layer 200 on the first surface of the insulating substrate 100, wherein the transition conductive layer 200 comprises a flexible layer 210 and a conductive layer 220 formed on the flexible layer 210, wherein the flexible layer 210 is located between the first surface and the conductive layer 220;

[0051] The transition conductive layer 200 includes a flexible layer 210 and a conductive layer 220. Figure 2 As shown in (b) and (c) in the figure, the flexible layer 210 is made of a flexible insulating material, such as PI (Polyimide Film), PET (Polyethylene Terephthalate), rubber, silicone or other flexible plastics. The conductive layer 220 is made of metal or other conductive materials, such as a copper layer, an aluminum layer, a conductive plastic or a conductive rubber, etc. For example, the conductive rubber is made by evenly distributing conductive particles such as glass silver-plated, aluminum silver-plated or silver in the silicone rubber, and the conductive particles are brought into contact by pressure to achieve a good conductive effect.

[0052] Optionally, the thickness of the flexible layer 210 ranges from 2 microns to 50 microns, preferably from 10 microns to 35 microns. For example, the thickness of the flexible layer is 12 microns, 18 microns, 20 microns, 25 microns, 30 microns or any value in the range of 10 microns to 35 microns.

[0053] Optionally, the thickness of the conductive layer 220 ranges from 1 micron to 20 microns, preferably from 2 microns to 15 microns. For example, the thickness of the conductive layer 220 is 5 microns, 8 microns, 10 microns, 11 microns, 12 microns, 13 microns, 14 microns or any value in the range of 2 microns to 15 microns.

[0054] In some embodiments, the insulating substrate 100 and the transition conductive layer 200 are both finished devices, and the step of providing the transition conductive layer 200 includes:

[0055] providing a flexible layer 210;

[0056] The conductive layer 220 is formed on the flexible layer 210 by sputtering.

[0057] The flexible layer 210 may be a rectangular, circular or other shaped plate-shaped film structure, without limitation. Then, the conductive layer 220 is prepared by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), PCVD (Plasma Chemical Vapor Deposition) or electroplating to obtain the transition conductive layer 200.

[0058] S1300 , patterning the conductive layer 220 to form a first circuit pattern 221 .

[0059] During implementation, an insulating layer (not shown) can be prepared on the surface of the conductive layer 220, for example, by spraying photoresist on the surface of one side of the conductive layer 220 away from the flexible layer 210 to form an insulating layer. The thickness of the photoresist ranges from 1 μm to 20 μm, for example, the thickness of the photoresist is set to 2 μm, 5 μm, 8 μm, 10 μm, 15 μm or 18 μm, etc., without limitation. In some embodiments, the thickness of the photoresist can be controlled by controlling the spraying amount and the number of passes, which will not be described in detail. The thickness of the first circuit pattern 221 is the same as the thickness of the conductive layer 220.

[0060] The insulating layer made of photoresist forms the desired preset pattern, which corresponds to the first circuit pattern 221. Exemplarily, a photomask is used to expose the insulating layer once, the mask covers the preset pattern to be formed, and the rest is exposed to light (such as ultraviolet rays, etc.); then the exposed insulating layer is immersed in a 2.38% developer for photochemical reaction to develop, and the unexposed photoresist is insoluble in the developer. The exposed photoresist can be removed by the above method, and the preset pattern can be processed on the insulating layer. Optionally, the developer can use a common developer on the market, which will not be described in detail. The preset pattern is formed on the insulating layer using a graphical photoresist method.

[0061] Then, the conductive layer 220 is etched based on the preset pattern to form a first circuit pattern 221. Figure 2 As shown in (d) in .

[0062] In some possible embodiments, before spraying the photoresist to form the insulating layer, the conductive layer 220 may be cleaned to remove pollutants such as particles, organic matter, and process residues on the surface of the conductive layer 220 to enhance the adhesion between the conductive layer 220 and the photoresist.

[0063] As a possible implementation, the first circuit pattern 221 may also be manufactured by mechanical means, which will not be described in detail.

[0064] In some embodiments, after the first circuit pattern 221 is formed, the role of the insulating layer has been completed, and a stripping solution is required to completely remove the remaining photoresist to expose the first circuit pattern 221. In this embodiment, the mass fraction of the stripping solution is 3% to 5%; the stripping temperature is 55° C. to 65° C.; and the stripping line speed is 0.8 m / min to 2.0 m / min.

[0065] The chip manufacturing method provided in the present application includes providing an insulating substrate 100, the insulating substrate 100 having a first surface; providing a transition conductive layer 200, and setting the transition conductive layer 200 on the first surface of the insulating substrate 100, the transition conductive layer 200 including a flexible layer 210 and a conductive layer 220 formed on the flexible layer 210, the flexible layer 210 being located between the first surface and the conductive layer 220; and patterning the conductive layer 220 to form a first circuit pattern 221. By directly bonding the flexible layer 210 to the insulating substrate 100, there is no problem of weak adhesion between the insulating substrate 100 and the conductive layer 220, and no PVD process is required, the overall process is simpler, and production efficiency can be effectively improved.

[0066] Furthermore, if Figure 3 As shown, the second circuit pattern 300 is formed on the first circuit pattern 221, and the projection of the second circuit pattern 300 on the first surface at least partially covers the projection of the first circuit pattern 221 on the first surface.

[0067] The second circuit pattern 300 can be formed by first electroplating a metal conductive layer (hereinafter referred to as "electroplating layer") on the transition conductive layer 200, and then by photolithography. The thickness of the electroplating layer ranges from 5 microns to 50 microns, and the preferred thickness range is from 10 microns to 40 microns. For example, the thickness of the electroplating layer is 12 microns, 13 microns, 14 microns, 15 microns, 20 microns, 25 microns, 30 microns or any value between 10 microns and 40 microns. The thickness of the second circuit pattern 300 is the same as the thickness of the electroplating layer. By setting the second circuit pattern 300, the cross-sectional area of ​​the first circuit pattern 221 and the second circuit pattern 300 as a whole can be increased, such as Figure 4 (j) and Figure 5 Through the above settings, the resistance can be effectively reduced, the electrical loss can be reduced, and the transmission efficiency of the line can be improved.

[0068] Optionally, the thickness of the second circuit pattern 300 is greater than the thickness of the first circuit pattern 221, which can further increase the overall cross-sectional area of ​​the first circuit pattern 221 and the second circuit pattern 300, resulting in lower resistance, less power loss, and higher transmission efficiency.

[0069] During implementation, the material of the second circuit pattern 300 may refer to the material of the first circuit pattern 221 , and no further details are given.

[0070] In some embodiments, the transition conductive layer 200 further includes an adhesive layer 230 (not shown) and a release layer 240 (not shown) located on the flexible layer 210 away from the conductive layer 220. The step of disposing the transition conductive layer 200 on the first surface of the insulating substrate 100 includes:

[0071] The release layer 240 is removed, and the side of the transition conductive layer 200 having the adhesive layer 230 is disposed on the first surface.

[0072] In the present application, an adhesive layer 230 and a release layer 240 are arranged on the side of the flexible layer 210 away from the conductive layer 220. Figure 6 As shown in (a) and (e) in FIG. 2 , the release layer 240 is used to protect the adhesive layer 230 , and the release layer 240 becomes movable at high temperature, so that the release layer 240 can be easily removed. Figure 6 As shown in (f) in FIG. 1 , the adhesive layer 230 can be more smoothly adhered and bonded to the first surface of the insulating substrate 100. Figure 6 That is, the overall structure of the chip is, from top to bottom, a conductive layer 220, a flexible layer 210, an adhesive layer 230 and an insulating substrate 100, as shown in (g) in FIG. Figure 6 As shown in (h) in FIG. 1 , the bonding stability and reliability of the insulating substrate 100 and the transition conductive layer 200 are improved.

[0073] In some embodiments, before the step of providing the transition conductive layer 200, the chip manufacturing method provided by the present application further includes:

[0074] The adhesive layer 400 is disposed on the first surface, and the flexible layer 210 is combined with the first surface through the adhesive layer 400 .

[0075] The adhesive layer 400 of the present application can refer to the above-mentioned adhesive layer 230, except that the adhesive layer 230 is prefabricated on the transition conductive layer 200, while the adhesive layer 400 is disposed on the first surface of the insulating substrate 100 by coating or spraying. In other words, the adhesive layer 400 is first prepared on the provided insulating substrate 100, such as Figure 7 As shown in (a), (i) and (b) in FIG. 1 , the flexible layer 210 is then bonded to the adhesive layer 400, as shown in FIG. Figure 7 As shown in (c) in FIG. 1 , the overall structure of the chip is, from top to bottom, a conductive layer 220, a flexible layer 210, a glue layer 400 and an insulating substrate 100. Figure 7 As shown in (d), the manufacturing process is simple and efficient.

[0076] In some embodiments, the chip manufacturing method provided in the present application further includes:

[0077] The insulating substrate 100 is removed.

[0078] After removing the insulating substrate 100, the transition conductive layer 200 can be installed and combined with other components or circuits to achieve corresponding functions. At this time, the chip is based on the flexible layer 210, which can improve the flexibility of the chip and help the chip adapt to more external folding environments.

[0079] As a possible implementation, a large insulating substrate 100 may be provided, and then a transition conductive layer 200 corresponding to the insulating substrate 100 may be provided. The conductive layer 220 of the transition conductive layer 200 may include a plurality of first circuit patterns 221 arranged in an array, and these first circuit patterns 221 are arranged at intervals from each other. That is, a plurality of first circuit patterns 221 may be prepared on the conductive layer 220 at one time, and then cut according to the position of each first circuit pattern 221 to be divided into a plurality of chips. At this time, each chip includes the insulating substrate 100, the flexible layer 210 and the first circuit pattern 221 arranged in a stacked manner, which can effectively improve production efficiency.

[0080] Similarly, in another embodiment, a large insulating substrate 100 may be provided, and then a transition conductive layer 200 corresponding to the insulating substrate 100 may be provided. The conductive layer 220 of the transition conductive layer 200 includes a plurality of first circuit patterns 221 arranged in an array, and these first circuit patterns 221 are arranged at intervals from each other. That is, a plurality of first circuit patterns 221 may be prepared on the conductive layer 220 at one time, and then the insulating substrate 100 is removed, and then the first circuit patterns 221 are cut according to the position of each first circuit pattern 221 to be divided into a plurality of chips. At this time, each chip includes a flexible layer 210 and a first circuit pattern 221 arranged in a stacked manner, which can effectively improve production efficiency.

[0081] In some embodiments, the present application provides a chip, which is manufactured using the chip manufacturing method as described above.

[0082] The chip manufacturing method provided in the present application includes providing an insulating substrate 100, the insulating substrate 100 having a first surface; providing a transition conductive layer 200, and setting the transition conductive layer 200 on the first surface of the insulating substrate 100, the transition conductive layer 200 including a flexible layer 210 and a conductive layer 220 formed on the flexible layer 210, the flexible layer 210 being located between the first surface and the conductive layer 220; and patterning the conductive layer 220 to form a first circuit pattern 221. By directly bonding the flexible layer 210 to the insulating substrate 100, there is no problem of weak adhesion between the insulating substrate 100 and the conductive layer 220, and no PVD process is required, the overall process is simpler, and production efficiency can be effectively improved.

[0083] In some embodiments, the present application provides a chip, including:

[0084] An insulating substrate 100 having a first surface; and

[0085] A transition conductive layer 200 is disposed on the first surface of the insulating substrate 100;

[0086] The transition conductive layer 200 includes a flexible layer 210 and a conductive layer 220 formed on the flexible layer 210 . The flexible layer 210 is located between the first surface and the conductive layer 220 . The conductive layer 220 includes a first circuit pattern 221 .

[0087] The insulating substrate 100 is a carrier of the chip, used to carry the transition conductive layer 200. During implementation, the insulating substrate 100 in the present application includes but is not limited to a glass substrate, a ceramic substrate, a silicon substrate, a polymer substrate or other well-known materials, without specific limitation.

[0088] In some embodiments, the insulating substrate 100 of the present application is preferably a glass substrate. The insulating substrate 100 may be a rectangular plate structure, and of course, the insulating substrate 100 may also be a circular, irregular or other shaped plate structure, without specific limitation.

[0089] As a possible implementation, the thickness range of the insulating substrate 100 is 5μm to 10mm. Preferably, the thickness range of the insulating substrate 100 is 200μm to 500μm. For example, the thickness range of the insulating substrate 100 is 250μm, 300μm, 350μm, 400μm or 450μm, etc., without limitation.

[0090] The transition conductive layer 200 includes a flexible layer 210 and a conductive layer 220, wherein the flexible layer 210 is made of a flexible insulating material, such as PI (Polyimide Film), PET (Polyethylene Terephthalate), rubber, silicone or other flexible plastics. The conductive layer 220 is made of metal or other conductive materials, such as a copper layer, an aluminum layer, conductive plastic or conductive rubber, etc. For example, the conductive rubber is made by evenly distributing conductive particles such as glass silver-plated, aluminum silver-plated or silver in silicone rubber, and contacting the conductive particles by pressure to achieve a good conductive effect.

[0091] The flexible layer 210 may be a rectangular, circular or other shaped plate-shaped film structure, without limitation. Then, the conductive layer 220 is prepared by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), PCVD (Plasma Chemical Vapor Deposition) or electroplating to obtain the transition conductive layer 200.

[0092] During implementation, an insulating layer may be prepared on the surface of the conductive layer 220, for example, by spraying photoresist on the surface of the conductive layer 220 away from the flexible layer 210 to form an insulating layer. The thickness of the photoresist ranges from 1 μm to 20 μm, for example, the thickness of the photoresist is set to 2 μm, 5 μm, 8 μm, 10 μm, 15 μm or 18 μm, etc., without limitation. In some embodiments, the thickness of the photoresist may be controlled by controlling the spraying amount and the number of passes, which will not be described in detail.

[0093] The insulating layer made of photoresist forms the desired preset pattern, which corresponds to the first circuit pattern 221. Exemplarily, a photomask is used to expose the insulating layer once, the mask covers the preset pattern to be formed, and the rest is exposed to light (such as ultraviolet rays, etc.); then the exposed insulating layer is immersed in a 2.38% developer for photochemical reaction to develop, and the unexposed photoresist is insoluble in the developer. The exposed photoresist can be removed by the above method, and the preset pattern can be processed on the insulating layer. Optionally, the developer can use a common developer on the market, which will not be described in detail. The preset pattern is formed on the insulating layer using a graphical photoresist method.

[0094] Then, the conductive layer 220 is etched based on the preset pattern to form a first circuit pattern 221 .

[0095] In some possible embodiments, before spraying the photoresist to form the insulating layer, the conductive layer 220 may be cleaned to remove pollutants such as particles, organic matter, and process residues on the surface of the conductive layer 220 to enhance the adhesion between the conductive layer 220 and the photoresist.

[0096] As a possible implementation, the first circuit pattern 221 may also be manufactured by mechanical means, which will not be described in detail.

[0097] In some embodiments, after the first circuit pattern 221 is formed, the role of the insulating layer has been completed, and a stripping solution is required to completely remove the remaining photoresist to expose the first circuit pattern 221. In this embodiment, the mass fraction of the stripping solution is 3% to 5%; the stripping temperature is 55° C. to 65° C.; and the stripping line speed is 0.8 m / min to 2.0 m / min.

[0098] Furthermore, it also includes a second circuit pattern 300, which is arranged on the first circuit pattern 221, and the projection of the second circuit pattern 300 on the first surface at least partially covers the projection of the first circuit pattern 221 on the first surface.

[0099] The second circuit pattern 300 can be manufactured by electroplating. By providing the second circuit pattern 300, the overall cross-sectional area of ​​the first circuit pattern 221 and the second circuit pattern 300 can be increased, the resistance can be reduced, the power loss can be reduced, and the transmission efficiency of the circuit can be improved.

[0100] Optionally, the thickness of the second circuit pattern 300 is greater than the thickness of the first circuit pattern 221, which can further increase the overall cross-sectional area of ​​the first circuit pattern 221 and the second circuit pattern 300, resulting in lower resistance, less power loss, and higher transmission efficiency.

[0101] During implementation, the material of the second circuit pattern 300 may refer to the material of the first circuit pattern 221 , and no further details are given.

[0102] Furthermore, the transition conductive layer 200 further includes an adhesive layer 230 . The adhesive layer 230 is located on a side of the flexible layer 210 away from the conductive layer 220 . The flexible layer 210 is bonded to the first surface via the adhesive layer 230 .

[0103] In some embodiments, an adhesive layer 230 is disposed on the side of the flexible layer 210 facing away from the conductive layer 220 , that is, the overall structure of the chip from top to bottom is the conductive layer 220 , the flexible layer 210 , the adhesive layer 230 and the insulating substrate 100 .

[0104] In some embodiments, the above-mentioned chip may be an inductor chip, an isolator chip, a resistor chip, etc.

[0105] In some embodiments, an electronic device is also provided, comprising the chip as described above.

[0106] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the structure and implementation principle of the chip of the electronic device described above can refer to the corresponding structure and implementation principle in the aforementioned embodiments, and will not be repeated here.

[0107] The electronic device provided in this application can be some semi-finished devices such as power supply devices, radio frequency devices, digital circuits, filter devices, etc., and can also be a terminal device such as consumer electronic products, communication electronic products, medical equipment, automotive electronics, etc. The electronic device contains the chip mentioned in the above embodiment.

[0108] The chip manufacturing method provided in the present application includes providing an insulating substrate 100, the insulating substrate 100 having a first surface; providing a transition conductive layer 200, and setting the transition conductive layer 200 on the first surface of the insulating substrate 100, the transition conductive layer 200 including a flexible layer 210 and a conductive layer 220 formed on the flexible layer 210, the flexible layer 210 being located between the first surface and the conductive layer 220; and patterning the conductive layer 220 to form a first circuit pattern 221. By directly bonding the flexible layer 210 to the insulating substrate 100, there is no problem of weak adhesion between the insulating substrate 100 and the conductive layer 220, and no PVD process is required, the overall process is simpler, and production efficiency can be effectively improved.

[0109] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for manufacturing a chip, characterized in that: include: Providing an insulating substrate having a first surface; Providing a transition conductive layer, and disposing the transition conductive layer on the first surface of the insulating substrate, the transition conductive layer comprising a flexible layer and a conductive layer formed on the flexible layer, the flexible layer being located between the first surface and the conductive layer; The conductive layer is patterned to form a first circuit pattern.

2. The method according to claim 1, characterized in that: A second circuit pattern is formed on the first circuit pattern, and a projection of the second circuit pattern on the first surface at least partially covers a projection of the first circuit pattern on the first surface.

3. The method according to claim 2, characterized in that: The thickness of the second circuit pattern is greater than the thickness of the first circuit pattern.

4. The method according to claim 1, characterized in that: The transition conductive layer further includes an adhesive layer and a release layer located on the flexible layer away from the conductive layer. The step of disposing the transition conductive layer on the first surface of the insulating substrate includes: The release layer is removed, and the side of the transition conductive layer having the adhesive layer is disposed on the first surface.

5. The method according to claim 1, characterized in that: Before the step of providing the transition conductive layer, the preparation method further comprises: An adhesive layer is disposed on the first surface, and the flexible layer is combined with the first surface through the adhesive layer.

6. The method according to claim 1, characterized in that: The step of providing a transition conductive layer comprises: providing the flexible layer; The conductive layer is generated on the flexible layer by sputtering.

7. The method according to any one of claims 1 to 6, characterized in that: The preparation method further comprises: The insulating substrate is removed.

8. A chip, characterized in that: The chip is manufactured by the manufacturing method according to any one of claims 1 to 7.

9. A chip, characterized in that: The chip comprises: an insulating substrate having a first surface; and A transition conductive layer disposed on the first surface of the insulating substrate; The transition conductive layer includes a flexible layer and a conductive layer formed on the flexible layer, the flexible layer is located between the first surface and the conductive layer, and the conductive layer includes a first circuit pattern.

10. The chip according to claim 9, characterized in that It also includes a second circuit pattern, which is arranged on the first circuit pattern, and the projection of the second circuit pattern on the first surface at least partially covers the projection of the first circuit pattern on the first surface.

11. The chip according to claim 9, characterized in that: The transition conductive layer further includes an adhesive layer, which is located on a side of the flexible layer away from the conductive layer, and the flexible layer is bonded to the first surface via the adhesive layer.

12. The chip according to any one of claims 9 to 11, characterized in that: The insulating substrate is a glass substrate.

13. An electronic device, characterized in that: Comprising the chip as claimed in any one of claims 9 to 12.

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