Buck converter in COT mode

Abstract

The invention provides a step-down converter in a COT mode, the step-down converter comprises a main comparator, a conduction time generation module and a PWM generation module, the main comparator is used for comparing a feedback voltage with a reference voltage, the conduction time generation module is used for providing a conduction time signal of the COT mode, and the PWM generation module is set as follows: when the conduction time signal is changed from 0 to 1, the conduction time signal is converted from 0 to 1; judging whether the feedback voltage is smaller than reference voltage; and if the feedback voltage is less than the reference voltage, skipping the turn-off time to enable the high-side power tube to be continuously conducted until the feedback voltage is greater than or equal to the reference voltage, and turning off the high-side power tube of the buck converter. According to the buck converter in the COT mode, the output voltage of the main comparator serves as a judgment standard to judge whether the turn-off time is reduced or skipped, so that the turn-on time of a high-side power tube is prolonged, the output voltage obtains more power, and the buck converter in the COT mode is more beneficial to scenes needing more power.

Description

Technical Field

[0001] The present invention relates to a buck converter, and in particular to a buck converter in a COT mode. The buck converter in the COT mode may be a conventional buck converter in a COT mode, or may be a buck converter in other types of COT modes, such as a buck converter in an ACOT (Adaptive Constant On-Time) mode. Background Art

[0002] Figure 1 The most basic example of a buck converter in ACOT (Adaptive Constant On-Time) mode is shown. The buck converter in ACOT mode includes a main comparator Cp1, an on-time generation module T1, a PWM generation module P1 connected to the output terminals of both, and a driver D1 connected to the output terminal of the PWM generation module P1.

[0003] In the buck converter in ACOT mode, the output end of the driver D1 is connected to the gate of the high-side power tube HS and the low-side power tube LS of the Buck circuit (i.e., the buck converter), so that the PWM generation module P1 uses the driver D1 to amplify the PWM signal to drive the large MOSFET. One of the input ends of the main comparator Cp1 is connected to the feedback signal FB of the buck converter, and the other input end is connected to the reference voltage V ref The gate of the high-side power tube HS, the gate of the low-side power tube LS and an inductor are connected to a switch node SW, and the other end of the inductor is the voltage output end of the buck converter. Therefore, part of the inductor current IL flows through the equivalent series resistance ESR and output capacitor C of the buck converter. out The capacitor current i C , and the other part is used as the output current I O (That is, load current ILOAD).

[0004] like Figure 2 As shown in the figure, the feedback voltage FB can be divided into the voltage ripple of the equivalent series resistor ESR and the capacitor voltage ripple. C The product of the capacitor current i and the equivalent series resistance ESR is the voltage across the equivalent series resistance ESR. Therefore, the change in the voltage across the equivalent series resistance ESR is caused by the capacitor current i C The peak value of the voltage ripple of ESR is the capacitor current i C The product of the difference between the maximum and minimum values ​​of the capacitor and the equivalent series resistance ESR. Capacitor voltage ripple is the voltage ripple generated by the change of the internal charge of the capacitor, which is caused by the capacitor current i C Caused by changes.

[0005] The main comparator Cp1 compares the feedback voltage FB with the reference voltage V ref When the feedback voltage FB drops to the reference voltage V ref When the output voltage Vea of ​​the main comparator Cp1 is lower than 1, the output voltage Vea of ​​the main comparator Cp1 will become high level, and because the output terminal of the main comparator Cp1 is connected to the set terminal Set of the PWM generation module P1, the high level of the output voltage Vea of ​​the main comparator Cp1 causes a turn-on pulse (i.e. HSON = 1) in the high-side power tube conduction signal HSON generated by the PWM generation module P1, which is used to drive the high-side power tube HS to conduct through the driver D1. The high-side power tube conduction signal HSON is proportional to the switch node voltage VSW.

[0006] At the same time, since the PWM generation module generates a PWM signal and sends it to the driver D1, and the PWM generation module is connected to a voltage-controlled on-time generation module T1 to receive the on-time signal Ton, the on-time signal Ton becomes a high level at the end of the on-time, therefore, the on-pulse (i.e., HSON = 1) drives the high-side power tube HS to turn on through the driver D1, until the on-time generation module T1 sends a high-level on-time signal Ton to reset the high-side power tube conduction signal HSON, and the high-side power tube conduction signal HSON becomes 0, so that the high-side power tube HS is disconnected and the low-side power tube is disconnected.

[0007] Among them, the on-time generating module T1 needs to be connected to the voltage input terminal of the buck converter to detect the input voltage VIN, so that when the input voltage VIN changes, the on-time is proportional to the input voltage VIN to achieve a constant switching frequency. Similarly, the on-time generating module T1 needs to be connected to the voltage output terminal of the buck converter to detect the output voltage VOUT (also recorded as Vout) of the buck converter, and then when the output voltage VOUT reaches different voltage values, the on-time is proportional to the output voltage VOUT to achieve a constant switching frequency.

[0008] As Figure 2 As shown, when the feedback voltage FB drops below the reference voltage V ref When the high-side power tube is turned on, the ESR ripple and capacitor ripple will rise again. Soon, the feedback voltage FB will be higher than the reference voltage V again. ref , so that the output voltage Vea of ​​the main comparator Cp1 immediately becomes a low level. Therefore, from the analysis of the existing buck converter in ACOT mode, when working normally in COT mode, the duty cycle of the output voltage Vea of ​​the main comparator Cp1 is very small, and its pulse shape is a thin waveform. In fact, when all COT mode buck converters work normally, the waveform output by their error amplifier Vea is relatively thin.

[0009] Figure 3 and Figure 4 Two operating scenarios are shown where the existing buck converter in ACOT mode is limited in operation. Figure 3 The waveform of the high-side power tube conduction signal HSON when the load step increases is shown. Figure 4 The waveform of the maximum duty cycle of the high-side power tube conduction signal HSON when the input voltage VIN drops stepwise to below the output voltage regulation point is shown. The output voltage regulation point refers to the DC value of the output voltage VOUT corresponding to the feedback voltage FB when the valley value of the feedback voltage FB is equal to the reference voltage Vref. In fact, the average value VFB_average of the feedback voltage FB is equal to the sum of the reference voltage Vref and 1 / 2 of the feedback voltage ripple.

[0010] exist Figure 3 In the operating scenario shown, the load current ILOAD increases in a step and is higher than the average value of the inductor current IL, which causes the output voltage VOUT to drop below the output voltage regulation point, and the feedback voltage FB is lower than the reference voltage Vref. Subsequently, the output voltage Vea of ​​the main comparator Cp1 is maintained at 1 for a relatively long time until the average value of the inductor current IL is higher than the load current ILOAD, at which time the ripple of the feedback voltage FB is higher than the reference voltage Vref again.

[0011] exist Figure 4 In the operation scenario shown, since the input voltage VIN is lower than the output voltage regulation point, the maximum output voltage VOUT that can be obtained is equal to the input voltage VIN×the maximum duty cycle of the high-side power tube conduction signal HSON, so the maximum output voltage VOUT is also far lower than the output voltage regulation point, and the feedback voltage FB will always be lower than Vref. In this case, the output voltage Vea of ​​the main comparator Cp1 is always equal to 1.

[0012] Although the above two situations are different, they have a common point: "the output voltage Vea of ​​the main comparator Cp1 is equal to 1 for a long time (temporarily or permanently)". Therefore, the waveform of Vea is not a conventional thin waveform. Moreover, the output voltage Vea of ​​the main comparator Cp1 is still equal to 1 even at the end of the on-time of the high-side power tube conduction signal HSON. The end of the on-time of the power tube conduction signal HSON is achieved by the on-time generation module T1 sending the conduction signal Ton.

[0013] like Figure 3 As shown in FIG. 1 , once the load changes from a light load to a heavy load, the load current ILOAD increases in a step-up manner, causing the output voltage VOUT to decrease. The existing buck converter in ACOT mode will try to turn on the high-side field effect transistor to make the inductor current reach the current load level.

[0014] However, if the load step change is fast and large, the existing ACOT mode or COT mode buck converter may need multiple COT (constant on-time) cycles to allow the inductor current to rise. Each COT cycle is separated by at least a minimum off-time (Min OFF-TIME).

[0015] Obviously, a longer minimum off-time will have a negative impact on the COT load step response. To get a better load step response, the minimum off-time needs to be reduced, or the off-time needs to be temporarily skipped based on some criteria. Summary of the invention

[0016] The object of the present invention is to provide a buck converter in COT mode, so as to increase the maximum duty cycle of the high-side power tube conduction signal by extending the conduction time and improve the fast load step response.

[0017] In order to achieve the above-mentioned object, the present invention provides a buck converter in COT mode, a main comparator, an on-time generating module and a PWM generating module, wherein the main comparator is used to compare a feedback voltage and a reference voltage, the on-time generating module is used to provide an on-time signal of the COT mode, and the PWM generating module is configured to: when the on-time signal changes from 0 to 1, determine whether the feedback voltage is less than the reference voltage; if the feedback voltage is less than the reference voltage, skip the off-time so that the high-side power tube continues to be turned on until the feedback voltage is greater than or equal to the reference voltage, and the high-side power tube of the buck converter is turned off.

[0018] The PWM generation module is also configured to: turn off the high-side power tube when the timing time from the start of the high-side power tube being turned on reaches the maximum on-time.

[0019] The PWM generation module receives the extended on-time signal obtained by processing the on-time signal and the output voltage of the main comparator, and uses it as a reset signal of the high-side power tube on-time signal. The high-side power tube on-time signal is reset to turn off the high-side power tube.

[0020] The buck converter in the COT mode includes a delay module connected to the on-time signal, an on-time extension capability detection module connected to the on-time signal and the output voltage of the main comparator, and an AND gate; the two input ends of the AND gate are respectively connected to the on-time delay signal output by the delay module and the on-time extension detection signal output by the on-time extension capability detection module, and the AND gate is used to output the extended on-time signal.

[0021] The delay module is configured to perform a fixed delay on the on-time signal to obtain an on-time delay signal.

[0022] The fixed delay is 3ns-7ns.

[0023] The on-time extension capability detection module is a D flip-flop, whose clock terminal is connected to the on-time signal, the data port is connected to a high level, the reset terminal is connected to the output voltage of the main comparator, and the inverting output terminal outputs the on-time extension detection signal.

[0024] The reset end of the on-time extension capability detection module is connected to the output signal of an NOR gate to connect the inverted signal of the output voltage of the main comparator, and one of the maximum current indication signal and the maximum on-time signal of the high-side power tube through the NOR gate.

[0025] The maximum current indication signal of the high-side power tube changes from 0 to 1 when the current of the high-side power tube reaches the maximum protection current; the maximum on-time signal changes from 0 to 1 when the timing time from the start of the high-side power tube conduction reaches the maximum on-time; the output voltage of the main comparator changes from 1 to 0 when the feedback voltage is greater than the reference voltage; the on-time extension capability detection module is reset when the output signal of the NOR gate is equal to 0, so that the on-time extension detection signal becomes 1, thereby turning off the high-side power tube of the buck converter.

[0026] The PWM generation module is also configured to: if the feedback voltage is less than the reference voltage when the maximum on-time is reached for a consecutive preset number of times, the buck converter enters a 100% duty cycle mode, wherein the high-side power tube can be turned on forever and is only turned off when the feedback voltage is greater than or equal to the reference voltage or when the current of the high-side power tube reaches the maximum protection current.

[0027] The buck converter in the COT mode of the present invention uses the output voltage of the main comparator as a judgment standard to determine whether to reduce or skip the shutdown time to extend the conduction time of the high-side power tube, so that the output voltage obtains more power, which is more beneficial to the scenario that requires more power. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is the most basic example diagram of a buck converter in the existing ACOT (Adaptive Constant On-Time) mode.

[0029] Figure 2 It is a waveform diagram of the existing buck converter in ACOT mode when it is working.

[0030] Figure 3 and Figure 4 The following are waveform diagrams of the existing buck converter in ACOT mode under two operating scenarios. Figure 3 The waveform of the high-side power tube conduction signal when the load step increases is shown. Figure 4The waveform of the maximum duty cycle of the high-side power tube conduction signal when the input voltage drops stepwise to below the output voltage regulation point is shown.

[0031] Figure 5 , Fig. 6A and Figure 6B A comparison diagram of the waveform of the existing buck converter and the waveform of the buck converter of the present invention using the output voltage of the main comparator at the end of the on-time of the high-side power tube as the judgment standard for skipping the off-time is shown, wherein: Figure 5 The waveform when the load increases step by step is shown. Fig. 6A The waveform shows the maximum duty cycle when the input voltage drops below the output voltage regulation point. Figure 6B The waveform of the maximum duty cycle of the high-side power tube conduction signal when the input voltage drops stepwise to above the output voltage regulation point is shown.

[0032] Figure 7 4 is a specific structural diagram of a buck converter in COT mode according to an embodiment of the present invention.

[0033] Figure 8 is a circuit diagram of an improved portion of a buck converter in a COT mode according to an embodiment of the present invention.

[0034] Fig. 9 This is a schematic diagram of the generation principle of the second charging current.

[0035] Fig.10 It is a typical waveform diagram of the buck converter in the COT mode of the present invention.

[0036] Fig.11 It is a waveform diagram of a conventional buck converter in ACOT mode in a simulation scenario, and the simulation scenario corresponds to a situation where the load jumps rapidly.

[0037] Fig.12 It is a waveform diagram of the buck converter in the ACOT mode of the present invention in a simulation scenario, and the simulation scenario corresponds to the situation where the load jumps rapidly.

[0038] Fig.13 It is a waveform comparison diagram of the buck converter in ACOT mode of the prior art and the present invention in a simulation scenario, and the simulation scenario corresponds to the maximum duty cycle limitation.

[0039] Fig.14 Shows Fig.13 The following is a partial enlarged diagram of the waveforms of the buck converters in ACOT mode of the prior art and the present invention under the simulation scenario of the maximum duty cycle limitation.

[0040] Fig.15is an actual load step response diagram of the buck converter in the ACOT mode of the present invention.

[0041] Figure 16A to Figure 16D The oscilloscope waveform diagram of the buck converter in the ACOT mode of the present invention is shown in the scenario of maximum duty cycle. DETAILED DESCRIPTION

[0042] The buck converter in COT mode of the present invention is mainly based on the following principles: A longer minimum off-time will cause the output voltage to be underpowered in some scenarios, which will adversely affect the COT load step response. When the output voltage needs more power, the key idea is to extend the on-time of the high-side power tube HS. In order to obtain a better load step response, the output voltage can obtain more power by reducing the minimum off-time, or temporarily skipping the off-time according to certain standards, and further increasing the duty cycle of the high-side power tube conduction signal HSON.

[0043] In the present invention, the output voltage Vea of ​​the main comparator CP1 is used as a criterion to determine whether to reduce or skip the off time to extend the on time of the high-side power tube so that the output voltage obtains more power.

[0044] As described above, in normal operation, the output voltage Vea of ​​the main comparator CP1 has a thin waveform and is equal to 1 only in a short time of the rising edge of the switch node SW. Therefore, the present invention can add a logic to detect the state of the output voltage Vea of ​​the main comparator CP1 when the on-time of the high-side power tube HS is about to end. If the output voltage Vea of ​​the main comparator CP1 is still equal to 1 when the on-time of the high-side power tube HS ends (that is, the on-time signal Ton changes from 0 to 1), it means that the integrated circuit is in an abnormal state. In this case, the buck converter obviously needs more power. Therefore, in this case, the off-time will be skipped and the on-time will continue until the output voltage Vea of ​​the main comparator CP1 is zero or the timing time starting from the high-side power tube turning on (that is, HSON changes to 1) reaches the maximum on-time (that is, the maximum on-time signal TON_MAX changes from 0 to 1).

[0045] Figure 5 , Fig. 6A and Figure 6B A comparison diagram of the waveform of the existing buck converter and the waveform of the buck converter of the present invention using the output voltage Vea of ​​the main comparator CP1 at the end of the on-time of the high-side power tube HS as the judgment standard for skipping the off-time is shown, wherein: Figure 5 The waveform when the load increases step by step is shown. Fig. 6AThe waveform of the maximum duty cycle when the input voltage VIN drops below the output voltage regulation point is shown. Figure 6B The waveform of the maximum duty cycle of the high-side power tube conduction signal HSON is shown when the input voltage VIN drops stepwise to above the output voltage regulation point. Figure 5 , Fig. 6A and Figure 6B In this embodiment, the buck converter in the COT mode specifically adopts the buck converter in the ACOT mode, the waveform of the new buck converter is orange, and the waveform of the new buck converter further increases the duty cycle of the high-side power tube conduction signal HSON.

[0046] like Figure 5 As shown in FIG. 1 , in the case of a load step increase, if the output voltage Vea of ​​the main comparator CP1 is still equal to 1 when the on-time of the high-side power tube HS ends (ie, the on-time signal Ton=1), the off-time is skipped, as shown in FIG. Figure 5 The blue circle shows

[0047] The maximum duty cycle limit of the buck converter can be combined with the change before and after the improvement Fig. 6A and Figure 6B to describe.

[0048] like Fig. 6A As shown in the figure, when the input voltage VIN drops below the output voltage regulation point, the output voltage VOUT corresponding to the input voltage VIN is lower than the target output voltage VOUT_SETTING. Therefore, the output voltage VOUT is always lower than the output voltage regulation point. In this case, the duty cycle is discussed. At this time, the output voltage Vea of ​​the main comparator is always at a high level.

[0049] In fact, the average output voltage VOUT can only reach: VIN×max_duty = VIN×(T-min_off_time) / T, Wherein, VIN is the input voltage, max_duty is the maximum duty cycle of the high-side power tube conduction signal, and T is the switching period.

[0050] For example, in an existing buck converter, if the minimum off time min_off_time = 150ns and the switching frequency is 600khz (ie, the switching period T = 1.667μs), and the input voltage VIN = the target output voltage VOUT_SETTING = 5V, the maximum output voltage VOUT is equal to: 5×(1.667-0.15) / 1.667 = 4.55V.

[0051] Therefore, in Fig. 6AIn order to increase the output voltage, the existing buck converter faces the following problems: Figure 5 In the same case of load step increase shown in the figure, it is necessary to reduce the minimum off time min_off_time or increase the on time On-time to increase the duty cycle. However, the existing buck converter in ACOT mode does not support these two methods.

[0052] In this embodiment, the buck converter in ACOT mode is set to perform the following logic: When the on-time of the high-side power tube HS ends (i.e., the on-time signal Ton changes from 0 to 1), it is determined whether the output voltage Vea of ​​the main comparator CP1 is 1; if the output voltage Vea of ​​the main comparator is equal to 1 (i.e., the feedback voltage FB < the reference voltage Vref), the off-time will be skipped, so that the high-side power tube HS continues to be turned on until the output voltage Vea of ​​the main comparator is zero or the timing time from the high-side power tube being turned on (i.e., HSON becomes 1) reaches the maximum on-time, at which time the high-side power tube HS is turned off.

[0053] The same logic can also be applied to the buck converter in the normal COT mode to improve the maximum duty cycle limit of the high-side power tube turn-on signal HSON of the existing buck converter.

[0054] In other embodiments, the maximum on-time is not set. When the buck converter executes the above logic and the value of the input voltage VIN is not enough to make VOUT reach the target output voltage VOUT_SETTING, if the maximum on-time is not set, the buck converter will keep the high-side power tube HS turned on forever. This is the working condition of the buck converter in the continuous conduction mode with 100% duty cycle.

[0055] Although the 100% duty cycle continuous conduction mode is feasible, it is often necessary to set up other charge pump circuits or periodically turn on the low-side power tube LS for a short period of time to charge the bootstrap capacitor, or set the high-side power tube HS to a PMOS tube to support the continuous conduction of the high-side power tube HS.

[0056] In this embodiment, the present invention uses an NMOS tube as a high-side power tube. In order to drive this NMOS tube, a voltage 5V higher than the voltage of the switch node SW is required. A common method to achieve this purpose is to add an additional circuit called a bootstrap capacitor. The bootstrap capacitor is simply a capacitor, one terminal of which is connected to the drive circuit and powered by a 5V voltage source through a diode, and the other terminal is connected to the switch node SW. When the low-side power tube LS is turned on, the 5V voltage source will charge the bootstrap capacitor. The buck converter of the present invention will use the energy stored in the bootstrap capacitor to drive the high-side power tube HS.

[0057] However, in the 100% duty cycle mode, since the low-side power tube LS is not turned on, there is no time to restore energy for the bootstrap capacitor. The bootstrap capacitor will gradually lose energy over time, so we need other circuits such as a charge pump circuit to supplement this part of the lost energy of the bootstrap capacitor. Therefore, if the buck converter of the present invention is expected to operate in a 100% duty cycle continuous conduction mode with an NMOS tube as the high-side power tube HS, a charge pump circuit needs to be set at the power supply terminal of the capacitor to supplement the energy lost by the bootstrap capacitor.

[0058] In other embodiments, if the high-side power tube HS is a PMOS tube, then the present invention does not need a newly added charge pump to support the continuous conduction of the high-side power tube HS at a 100% duty cycle. In addition, if the present invention allows the low-side power tube LS to be turned on within the maximum on-time TON_MAX after the high-side power tube HS is turned on, then there is no need for a newly added charge pump. Because as mentioned above, after the low-side power tube LS is turned on, the energy in the bootstrap capacitor will be recovered.

[0059] In this embodiment, the maximum on-time = 30μs. Since the maximum on-time is only 30μs, the energy lost in the bootstrap capacitor during this period is actually negligible, so a good output voltage can be maintained, thereby extending the battery life. In addition, the energy is refreshed every time the low-side FET is turned on. Therefore, in this embodiment, no additional charge pump circuit is required. At the same time, the maximum on-time of 30μs makes the switching frequency produce no audible noise.

[0060] In this embodiment, the maximum on-time = 30μs, and the minimum off-time min_off_time = 150ns. When the high-side power tube conduction signal reaches the maximum duty cycle, the switching period T is the sum of the maximum on-time and the minimum off-time min_off_time, so the duty cycle is 99.5%. On the basis of a duty cycle of 99.5%, since the input voltage is 5V, the output voltage can reach 4.975V. The output voltage of the buck converter of the present invention is significantly improved compared with the calculated output voltage of 4.55V of the existing buck converter.

[0061] like Figure 6B As shown, when the input voltage VIN drops but is still above the output voltage regulation point, the maximum value of the output voltage VOUT corresponding to the input voltage VIN is still slightly higher than the target output voltage VOUT_SETTING, but due to the limitation of the COT mode, the average output voltage VOUT cannot reach the target output voltage VOUT_SETTING. In this case, the duty cycle is discussed.

[0062] For example, in the existing buck converter in COT mode, under the conditions of input voltage VIN=5.2V, switching frequency of 600khz (ie, switching period T=1.667μs), and minimum off time min_off_time of 150ns, the maximum output voltage VOUT is only equal to: VOUT = (1.667-0.15) / 1.667×5.2 = 4.73V Obviously, in the existing buck converter in COT mode, the 5.2V input voltage VIN cannot support a 5V output.

[0063] However, in this embodiment, the buck converter in COT mode is set to perform the following logic: When the on-time of the high-side power tube HS ends (i.e., the on-time signal TON=1), it is determined whether the output voltage Vea of ​​the main comparator CP1 is 1; if the output voltage Vea of ​​the main comparator is equal to 1, the off-time will be skipped, so that the high-side power tube HS continues to be on until the output voltage Vea of ​​the main comparator is zero or the timing time from the high-side power tube being on (i.e., HSON becomes 1) reaches the maximum on-time. At this time, the high-side power tube HS is turned off.

[0064] Therefore, in this embodiment, the on-time is extended to VOUT / (VIN-VOUT)×min_off_time = 3.75μs, but has not yet reached the maximum on-time (30μs). Therefore, in theory, the buck converter in COT mode of the present invention can support 5V output with 5.2V input.

[0065] In this embodiment, since the input voltage VIN is still high enough, the buck converter in the COT mode of the present invention can pull the feedback voltage FB above the reference voltage Vref. Then, the high-side power tube conduction signal HSON is reset when the output voltage Vea of ​​the main comparator CP1 is 0. The conduction time of the high-side power tube HS depends on the time length of the output voltage Vea of ​​the main comparator CP1 = 1.

[0066] Therefore, in fact, Figure 6B In this case, the buck converter in the COT mode of the present invention will operate in a fixed off-time (i.e., off-time = minimum off-time min_off-time) and variable on-time operation mode. The buck converter of the present invention executes the above logic to convert the buck converter from the constant on-time mode to the constant off-time mode.

[0067] Combine the following Figure 7 and Figure 8The specific structure of the buck converter in COT mode according to one embodiment of the present invention is described. Figure 7 and Figure 8 In the illustrated embodiment, the buck converter in the COT mode is a buck converter in the ACOT mode.

[0068] like Figure 7 and Figure 8 As shown, the buck converter in the COT mode of the present invention includes a main comparator Cp1, an on-time generating module T1, a PWM generating module P1, and a driver D1 connected to the output end of the PWM generating module P1.

[0069] The main comparator is used to compare the feedback voltage FB with the reference voltage Vref, and when the feedback voltage FB is less than the reference voltage Vref, the output voltage Vea of ​​the main comparator becomes a high level (Vea=1). The on-time generating module is used to provide an on-time signal TON of the COT mode.

[0070] The PWM generation module P1 is connected to the output voltage Vea of ​​the main comparator Cp1 to use it as a set 1 signal for the high-side power tube conduction signal HSON. The high level of the output voltage Vea of ​​the main comparator Cp1 causes the high-side power tube conduction signal HSON generated by the PWM generation module P1 to become a high level.

[0071] Furthermore, the PWM generation module is configured to: when the on-time signal Ton of the high-side power tube HS changes from 0 to 1, determine whether the feedback voltage FB is less than the reference voltage Vref; if the feedback voltage FB is less than the reference voltage Vref, skip the off-time, so that the high-side power tube HS continues to be on, until the feedback voltage FB is greater than or equal to the reference voltage Vref, and the high-side power tube HS is turned off. Specifically, the PWM generation module P1 is connected to the extended on-time signal TON_EXT obtained by processing the on-time signal of the on-time generation module T1 and the output voltage Vea of ​​the main comparator Cp1 to use it as a reset signal of the high-side power tube on-time signal HSON, thereby realizing the above functions.

[0072] Therefore, the extended on-time signal TON_EXT replaces the existing on-time signal TON which is the reset signal of the high-side power tube on-time signal HSON. When the extended on-time signal TON_EXT is at a high level (ie, TON_EXT=1), the high-side power tube on-time signal HSON is reset to turn off the high-side power tube HS.

[0073] One input terminal of the main comparator Cp1 is connected to the feedback signal FB of the buck converter, and the other input terminal is connected to the reference voltage V refThe output terminal is used to output the output voltage Vea of ​​the main comparator CP1.

[0074] Since in this embodiment, the buck converter in the COT mode adopts the buck converter in the ACOT mode, and the on-time provided by it varies with the input voltage and the output voltage, the on-time generating module T1 includes a second comparator Cp2, the inverting input terminal of the second comparator Cp2 is connected to the voltage output terminal of the buck converter to receive the output voltage VOUT, the non-inverting input terminal of the second comparator Cp2 is simultaneously connected to the grounded first timing capacitor Cton, the grounded first ground switch tube NM3, and the first charging current Iton, and the output terminal of the second comparator Cp2 is the output terminal of the on-time generating module T1 and is used for the on-time signal TON. When the on-time signal TON is 1, it indicates that the on-time of the high-side power tube HS ends, so that the on-time can be provided.

[0075] The source of the first grounding switch tube NM3 is grounded, the drain is connected to the non-inverting input terminal of the second comparator Cp2, and the gate is connected to the high-side power tube conduction signal HSON output by the PWM generation module P1 through the NOT gate NOT1, which is used to turn on the first grounding switch tube NM3 when the high-side power tube conduction signal HSON output by the PWM generation module P1 is 0, thereby causing the first timing capacitor Cton to be unable to charge, so that the on-time generating module T1 starts timing from the high-side power tube conduction signal HSON=1. Therefore, the on-time signal TON becomes 1 when the timing time starting from the high-side power tube being turned on (that is, HSON becomes 1) reaches the on-time.

[0076] Since the inverting input terminal of the second comparator Cp2 is connected to the voltage output terminal of the buck converter to receive the output voltage VOUT, when the output voltage reaches different voltage values, a constant switching frequency is achieved by the on-time being proportional to the output voltage VOUT.

[0077] The first current source is used to provide a first charging current Iton proportional to the input voltage VIN. In this embodiment, the first current source is the current output end of the first current mirror, wherein the source electrodes of all the switch tubes of the first current mirror are connected to the voltage input end of the buck converter to receive the input voltage VIN, and the current output end of the first current mirror is connected to the non-inverting input end of the second comparator Cp2, which means that the current entering the first timing capacitor Cton is proportional to the input voltage VIN. Therefore, the current entering the first timing capacitor Cton of the current source is proportional to the input voltage VIN, and when the input voltage VIN changes, the constant switching frequency is achieved by the conduction time being proportional to the input voltage VIN.

[0078] In this embodiment, the first current mirror is a PMOS current mirror, which includes a first current mirror switch tube PM1 and a second current mirror switch tube PM2 whose gates are connected to each other, and the sources of the two are connected to the input voltage VIN. The drain of the first current mirror switch tube PM1 is connected to the gate, and the drain is grounded through a current mirror resistor Rvin and connected to the current output end of the second current mirror. Thus, the current mirror resistor Rvin can set the output current of the first current mirror, and the set output current is proportional to the input voltage VIN. The drain of the second current mirror switch tube PM2 is the current output end of the first current mirror, which is used to provide the first charging current Iton.

[0079] The second current mirror is an NMOS current mirror, which includes a third current mirror switch tube NM1 and a fourth current mirror switch tube NM2 whose gates are connected to each other. The drain of the third current mirror switch tube NM1 is connected to the gate and connected to the input voltage VIN through the first resistor R1, and the source of the third current mirror switch tube NM1 is grounded through a current mirror grounding switch tube PM3 in the form of a diode connection. The drain of the fourth current mirror switch tube NM2 is the current output end of the second current mirror, and the source is grounded through the second current mirror resistor Rvin2, and the resistance value of the second current mirror resistor Rvin2 is the same as the resistance value of the current mirror resistor Rvin.

[0080] In this embodiment, since the ratio of the first current mirror is 1x / 1x, the first charging current Iton is the current flowing through the second current mirror switch tube PM2, which is equal to the current flowing through the first current mirror switch tube PM1.

[0081] The current flowing through the first current mirror switch tube PM1 is equal to the sum of the current flowing into the current mirror resistor Rvin and the second current mirror resistor Rvin2.

[0082] The current flowing through the second current mirror resistor Rvin2 = the voltage threshold of the current mirror grounding switch PM3 / the second current mirror resistor Rvin2 = VT_PM3 / Rvin, The current flowing through the current mirror resistor Rvin = (input voltage VIN-voltage threshold of the first current mirror switch PM1) / current mirror resistor Rvin = (VIN-VT_PM1) / Rvin, Therefore, the first charging current Iton is: Iton=(VIN-VT_PM1) / Rvin+VT_PM3 / Rvin, Because the first current mirror switch tube PM1 and the current mirror grounding switch tube PM3 are in the same process and are similar to each other, the voltage threshold VT_PM1 of the first current mirror switch tube is similar to the voltage threshold VT_PM3 of the current mirror grounding switch tube.

[0083] The first charging current Iton is: Iton=(VIN-VT_PM1) / Rvin+VT_PM3 / Rvin=VIN / Rvin+(VT_PM3-VT_PM2) / Rvin=VIN / Rvin Therefore, the first charging current Iton provided by the first current source is proportional to the input voltage VIN. The actual circuit for implementing the first charging current Iton (ie, the bias current proportional to the input voltage VIN) may be more complicated.

[0084] The above structures of the present invention are consistent with the specific structures of the existing buck converters in ACOT mode. Therefore, in ACOT mode, the on-time generating module T1 sets the high-side power tube on-signal HSON to 1 according to the rising edge of the output signal Vea of ​​the comparator, so that the high-side power tube HS starts to be turned on; and resets the high-side power tube on-signal HSON according to the rising edge of the on-time signal TON to turn off the high-side power tube HS.

[0085] The on-time generating module T1 generates the on-time (eg Figure 8 The red box in the middle shows the time when the voltage in the first timing capacitor Cton reaches or exceeds the voltage at the inverting input terminal of the second comparator Cp2 (i.e., the output voltage VOUT). According to the basic equation for storing charge in a capacitor: Q=V×C=I×t, the on-time Ton of the buck converter can be obtained as: Ton=V×C / I=VOUT×Cton / Iton, The first charging current Iton calculated in advance is equal to VIN / Rvin. Therefore, the on-time Ton of the buck converter is obtained as: Ton = VOUT×Cton / (VIN / Rvin) = (VOUT / VIN)×(Cton×Rvin) Therefore, in the ACOT mode, the on-time set by the on-time signal TON is proportional to both the output voltage VOUT and the input voltage VIN.

[0086] For a buck converter, when we know its on-time, we can also easily calculate its switching period or switching frequency.

[0087] T (buck converter) = Ton / D, where duty cycle D = VOUT / VIN ->T (buck converter) = Ton / (VOUT / VIN) = (VIN / VOUT) × Ton Substituting the on-time calculated in the ACOT mode into the equation above, the switching period T(ACOT) of the buck converter in ACOT is obtained: T(ACOT)=(VIN / VOUT)×Ton=(VIN / VOUT)×(VOUT / VIN)×(Cton×Rvin)=Cton×Rvin, The final result of the switching cycle here does not include VIN and VOUT. It only depends on the preselected first timing capacitor Cton and the current mirror resistor Rvin. Therefore, we can say that in ACOT mode, the switching frequency is constant and has nothing to do with the input voltage VIN and the output voltage VOUT values. This is the meaning of the letter "A" (Adaptive) in the buck converter in ACOT mode.

[0088] like Figure 8 As shown, the buck converter in the COT mode of the present invention adds the following modules on the basis of the existing buck converter in the COT mode: a delay module DL1, a conduction time extension capability detection module DET1, and an AND gate AND1 whose two input ends are respectively connected to the conduction time delay signal TON_DL of the delay module DL1 and the conduction time extension detection signal nExt_TON of the conduction time extension capability detection module DET1. Among them, the extended conduction time signal TON_EXT output by the AND gate AND1 serves as the reset signal of the high-side power tube conduction signal HSON. The extended conduction time signal TON_EXT replaces the existing conduction time signal TON as the reset signal of the high-side power tube conduction signal HSON. When the extended conduction time signal TON_EXT is at a high level (i.e., TON_EXT=1), the high-side power tube conduction signal HSON is reset to turn off the high-side power tube HS.

[0089] The delay module DL1 is an RC delay timer. The delay module DL1 is set to perform a fixed delay of 5ns on the on-time signal TON to obtain the on-time delay signal TON_DL, so as to leave room for the operation of the detection circuit DET1. In fact, the increased delay will cause the on-time to slightly exceed the ratio of the output voltage VOUT / input voltage VIN. However, this effect is too small to be ignored.

[0090] The time range of the fixed delay of the delay module DL1 is equal to 5 ns (±40%), which means that the delay time of the delay module DL1 will range from 3 ns to 7 ns.

[0091] The on-time extension capability detection module DET1 is a D flip-flop, whose clock terminal CLK is connected to the on-time signal TON, the data port D is connected to a high level (5V), and the reset terminal R is connected to an output signal nEXT_RS of a NOR gate NOR, so as to connect the high-side power tube maximum current indication signal IMAX, the maximum on-time signal TON_MAX, and the inverted signal of the output voltage Vea of ​​the main comparator through the NOR gate NOR. The inverted output terminal QB of the on-time extension capability detection module DET1 outputs the on-time extension detection signal nExt_TON.

[0092] In some other embodiments, the high-side power tube maximum current indication signal IMAX and the maximum on-time signal TON_MAX can be omitted, so the reset terminal R can be directly connected to the output voltage Vea of ​​the main comparator. Alternatively, one of the high-side power tube maximum current indication signal IMAX and the maximum on-time signal TON_MAX can be omitted, so that the reset terminal R is connected to the inverted signal of the output voltage Vea of ​​the main comparator and one of the high-side power tube maximum current indication signal IMAX and the maximum on-time signal TON_MAX through the NOR gate NOR.

[0093] The on-time extension capability detection module DET1 is a traditional D flip-flop, the output of the positive phase output terminal Q of the D flip-flop will be equal to the input of its data port D at the rising edge of the signal of the clock terminal CLK, and will be reset to the default state when the signal of the reset terminal R is 0, that is, the output of the positive phase output terminal Q becomes 0, and the output of the inverting output terminal QB becomes 1. In this circuit, the on-time signal TON is the input clock of the on-time extension capability detection module DET1.

[0094] Since the output signal nEXT_RS of the NOR gate NOR is connected to the reset terminal R of the conduction time extension capability detection module DET1, when the output signal nEXT_RS of the NOR gate NOR received by the reset terminal R of the conduction time extension capability detection module DET1 is equal to 0, the conduction time extension capability detection module DET1 will be reset to a default state, and the conduction time extension detection signal nExt_TON outputted from its inverting output terminal becomes 1.

[0095] In this embodiment, the three input terminals of the NOR gate are respectively connected to the maximum current indication signal IMAX of the high-side power tube, the maximum on-time signal TON_MAX, and the inverted signal of the output voltage Vea of ​​the main comparator.

[0096] The high-side power tube maximum current indication signal IMAX changes from 0 to 1 when the current of the high-side power tube reaches the maximum protection current. The maximum on-time signal TON_MAX changes from 0 to 1 when the timing time from the high-side power tube being turned on (i.e. HSON becomes 1) reaches the maximum on-time. The output voltage Vea of ​​the main comparator changes from 1 to 0 when the feedback voltage FB is greater than the reference voltage Vref.

[0097] Therefore, the on-time extension capability detection module DET1 is reset when the output signal nEXT_RS of the NOT gate NOR is equal to 0 (i.e., the output voltage Vea of ​​the comparator is 0 or TON_MAX is 1 or IMAX is 1), so that the on-time extension detection signal nExt_TON outputted from its inverting output terminal becomes 1, so that the high-side power tube HS of the buck converter is turned off. If none of the above three situations exist, the on-time extension capability detection module DET1 will latch the result of the high level at the rising edge of the on-time signal TON, so that the on-time extension detection signal nExt_TON outputted from its inverting output terminal becomes 0 (i.e., 0V) within less than 1ns after the on-time signal TON=1. During the period when the on-time extension detection signal nExt_TON has not changed, the on-time delay signal TON_DL is still equal to 0, because the delay time of the on-time delay signal TON_DL is 5ns greater than that of the on-time signal TON.

[0098] Therefore, at the rising edge of the on-time signal TON, if the output voltage Vea of ​​the main comparator is 1 (at this time, the high-side power tube HS has just been turned on, and TON_MAX=0 and IMAX=0 must be satisfied), the on-time extension detection signal nExt_TON=0 will block the output of the on-time delay signal TON_DL, and keep the extended on-time signal TON_EXT equal to zero (0V), so that the high-side power tube HS continues to be turned on; until one of the following three situations occurs (Vea=0, TON_MAX=1, IMAX=1), the extended on-time signal TON_EXT becomes 1, so that the high-side power tube HS is turned off.

[0099] Therefore, the present invention successfully converts the constant on-time mode into the constant off-time mode through the simple circuit composed of the delay module DL1, the on-time extension capability detection module DET1, and the AND gate AND1.

[0100] The high-side power tube maximum current indication signal IMAX is the output of the high-side power tube maximum current protection circuit. When the high-side power tube HS is turned on, the current sensing circuit senses the current passing through the high-side power tube HS, and when the current reaches the maximum protection current, the high-side power tube maximum current indication signal IMAX changes from 0 to 1 to turn off the high-side power tube HS. This is to ensure that the high-side power tube HS operates in the current safety operating area.

[0101] The maximum time generation module is a timer, and the maximum time generation module is used to generate a maximum on-time signal TON_MAX, and the maximum on-time signal TON_MAX changes from 0 to 1 when the timing time starting from the high-side power tube being turned on (ie, HSON becomes 1) reaches the maximum on-time.

[0102] The maximum time generation module includes a third comparator Cp3, the inverting input terminal of the third comparator Cp3 is connected to the third comparator reference voltage (1.2V), and the non-inverting input terminal is simultaneously connected to the grounded second timing capacitor Ctmax, the grounded second ground switch tube NM4 and the second charging current Itmax. Therefore, the maximum on-time provided by the maximum on-time signal TON_MAX is the time when the second charging current Itmax is charged into the second timing capacitor Ctmax until the voltage of the second timing capacitor Ctmax reaches the third comparator reference voltage (1.2V), and the maximum on-time is very accurate.

[0103] The maximum on-time is in the range of 30μs (±15%), which means it will be in the range of 25.5μs to 34.5μs. The second charging current Itmax is a constant current and is generated by a simple bias current circuit. Specifically, Fig. 9 As shown, the second charging current Itmax is a mirror current of the base bias current, and the base bias circuit includes a buffer B1 for generating a base bias current and a third current mirror whose current input terminal is connected to the base bias current, and the output terminal of the third current mirror is used to output the second charging current Itmax. The positive input terminal of the buffer B1 is connected to the buffer input voltage (1.2V), the negative input terminal of the buffer B1 is connected to the third current mirror resistor R3 and connected to the source of the fifth switch tube NM5, the output terminal of the buffer B1 is connected to the gate of the fifth switch tube NM5, and the source of the fifth switch tube NM5 is connected to the current input terminal of the third current mirror and generates a base bias current. Therefore, the base bias current generated by the buffer B1 is equal to 1.2V / R3. The third current mirror resistor R3 has a trimming network to perform trimming operations on the maximum time generation module during mass production.

[0104] The typical waveform of the buck converter in the COT mode of the present invention is as follows: Fig.10 As shown. Fig.10 In the example, the input voltage VIN of about 5.75V is quite low for the target output voltage of 5.5V. At the rising edge of the on-time signal TON, we can see that the output voltage Vea of ​​the main comparator is 1 (i.e., the feedback voltage FB < the reference voltage Vref). Therefore, the on-time extension capability detection module DET1 will detect the Vea state within about 1ns and set the on-time extension detection signal nExt_TON = 0.

[0105] The on-time delay signal TON_DL indicates a signal delayed by 5.5ns from the on-time signal TON. The extended on-time signal TON_EXT is an AND function of the on-time delay signal TON_DL and the on-time extension detection signal nExt_TON. The extended on-time signal TON_EXT remains at 0 until the feedback voltage FB is higher than VREF (i.e., the output voltage Vea of ​​the main comparator = 0) to reset the on-time extension capability detection module DET1 and reset the high-side power tube conduction signal HSON. The on-time is extended from 1.3565μs to 5.064μs to increase the maximum duty cycle.

[0106] Fig.11 and Fig.12 The waveform diagram of the buck converter in ACOT mode of the prior art and the present invention in a simulation scenario is shown, and the simulation scenario corresponds to the case of a rapid load jump (the load current changes from 0 -> 8A in 1 μs).

[0107] Fig.11 It shows that VIN=12V, VOUT=5.5V, the load current step is 0 -> 8A, it takes 1μs, and the output voltage undershoot of the existing buck converter in ACOT mode is 344.5mV.

[0108] Fig.12 It shows that when VIN=12V, VOUT=5.5V, the load step is 0 -> 8A, and the time is 1μs, the output voltage undershoot drops to 283mV after using the buck converter in the ACOT mode of the present invention.

[0109] Fig.13 A waveform comparison diagram of the buck converter in ACOT mode of the prior art and the present invention is shown in a simulation scenario, wherein the simulation scenario corresponds to the maximum duty cycle limitation.

[0110] 13 shows a comparison of the maximum duty cycle simulation results of the buck converter in ACOT mode of the prior art and the present invention, wherein the output voltage VOUT is set to 5.54V, the load current ILOAD is set to 2A, and the input voltage VIN is reduced from 6.25V to 5.5V.

[0111] The blue waveform is the waveform of the buck converter (output voltage VOUT, switch node voltage VSW, inductor current IL) in the ACOT mode of the present invention. The pink waveform is the waveform of the buck converter (output voltage VOUT, switch node voltage VSW, inductor current IL) in the existing ACOT mode. In the simulation, the output voltage VOUT of the existing circuit starts to drop when the input voltage VIN=6V. In the circuit of the present invention, when VIN=5.48V, since the on-time of the switch node SW is scalable, the output voltage VOUT is still close to 5.42V (maximum duty cycle ~ 99%).

[0112] Fig.14 Shows Fig.13 The following is a partial enlarged diagram of the waveforms of the buck converters in ACOT mode of the prior art and the present invention under the simulation scenario of the maximum duty cycle limitation. Fig.14 The maximum duty cycle of the circuit of the present invention is extended to two periods relative to the existing circuit. In period 1, VIN is still high enough to support the output, and the on-time of the integrated circuit is determined by the output voltage Vea of ​​the main comparator. In period 2, the input voltage VIN is low, and if the maximum on-time is set, the on-time of the entire circuit of the present invention is limited by the maximum on-time signal TON_MAX.

[0113] Among them, the blue waveform is the waveform of the buck converter in the COT mode of the present invention (1-output voltage VOUT, 3-switch node voltage VSW, 4-inductor current IL). The pink waveform is the waveform of the circuit in the existing COT mode (2-output voltage VOUT, 5-inductor current IL, 6-switch node voltage VSW). It can be easily seen in the partial enlarged diagram that in the circuit of the present invention, the on-time is continuously extended in "period 1", while the input voltage VIN is decreasing. The on-time will only be reset when the output voltage Vea of ​​the main comparator is zero or the on-time reaches the maximum on-time. In "period 2", the on-time of the integrated circuit is limited by the maximum on-time. As mentioned above, if the maximum on-time is not set (the maximum on-time is infinite), the circuit of the present invention can enter a 100% duty cycle working mode, so that the simulation results depend only on the relationship between the input voltage VIN, the output voltage VOUT and the load. However, if the on-time is too long, other charge pump circuits are required to maintain the power supply of the high-side power tube HS. In addition, another purpose of setting the maximum on-time is to not allow the integrated circuit to switch at an audible frequency. If a 100% duty cycle is required, other logic can be added to enable the circuit of the present invention to jump to a 100% duty cycle mode. For example, the PWM generation module can be set to: if the feedback voltage FB is less than the reference voltage Vref (i.e., the output voltage Vea of ​​the main comparator = 1) for a preset number of consecutive times (such as 8 times) when the maximum on-time is reached, the buck converter in the COT mode of the present invention can jump to a 100% duty cycle mode, wherein the high-side power tube can be turned on forever and only turned off when the feedback voltage (FB) is greater than or equal to the reference voltage (Vref) or when the current of the high-side power tube reaches the maximum protection current, and no longer according to the maximum on-time for the high-side power tube.

[0114] Fig.15 FIG. 2 shows the experimental results of a silicon wafer, that is, the actual load step response diagram of the buck converter in the ACOT mode of the present invention on the silicon wafer. Fig.15 As shown, the conduction time of the high-side power tube is extended as expected. The blue in the figure represents the input voltage VIN, the yellow signal represents the switch node voltage SW (whose waveform is consistent with the high-side power tube conduction signal HSON), and the red signal represents the load current ILOAD.

[0115] Figure 16A to Figure 16D The oscilloscope waveform of the buck converter in ACOT mode of the present invention is shown in the scenario of maximum duty cycle, where the input voltage VIN is swept upward from 20 V and the output voltage VOUT is set to = 20 V. When the input voltage VIN is low, the on-time represented by the switch node SW is extended.

[0116] The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The above embodiments of the present invention can also be modified in various ways. All simple, equivalent changes and modifications made according to the claims and the description of the present invention fall within the scope of protection of the claims of the present invention. The contents not described in detail in the present invention are all conventional technical contents.

Claims

1. A buck converter in COT mode, a main comparator (Cp1), an on-time generating module and a PWM generating module (P1), wherein the main comparator (Cp1) is used to compare a feedback voltage (FB) and a reference voltage (Vref), and the on-time generating module is used to provide an on-time signal (TON) in COT mode, characterized in that: The PWM generation module (P1) is set to: When the on-time signal (TON) changes from 0 to 1, it is determined whether the feedback voltage (FB) is less than the reference voltage (Vref); if the feedback voltage (FB) is less than the reference voltage (Vref), the off-time will be skipped so that the high-side power tube (HS) continues to be turned on until the feedback voltage (FB) is greater than or equal to the reference voltage (Vref), at which time the high-side power tube (HS) of the buck converter is turned off.

2. The buck converter in COT mode according to claim 1, characterized in that: The PWM generation module (P1) is also configured to: turn off the high-side power tube (HS) when the timing time from the start of the high-side power tube being turned on reaches the maximum on-time.

3. The buck converter in COT mode according to claim 1, characterized in that: The PWM generation module (P1) receives an extended on-time signal (TON_EXT) obtained by processing an on-time signal (TON) and an output voltage (Vea) of a main comparator, and uses the extended on-time signal (TON_EXT) as a reset signal of a high-side power tube on-time signal (HSON). The high-side power tube (HS) is turned off when the high-side power tube on-time signal (HSON) is reset.

4. The buck converter in COT mode according to claim 3, characterized in that: The invention comprises a delay module (DL1) connected to a conduction time signal, a conduction time extension capability detection module (DET1) connected to the conduction time signal and an output voltage (Vea) of a main comparator, and an AND gate (AND1); two input ends of the AND gate (AND1) are respectively connected to a conduction time delay signal (TON_DL) output by the delay module (DL1) and a conduction time extension detection signal (nExt_TON) output by the conduction time extension capability detection module (DET1); and the AND gate (AND1) is used to output the extended conduction time signal (TON_EXT).

5. The buck converter in COT mode according to claim 4, characterized in that: The delay module (DL1) is configured to perform a fixed delay on the on-time signal (TON) to obtain an on-time delay signal (TON_DL).

6. The buck converter in COT mode according to claim 5, characterized in that: The fixed delay is 3ns-7ns.

7. The buck converter in COT mode according to claim 4, characterized in that: The on-time extension capability detection module (DET1) is a D-type flip-flop, whose clock terminal (CLK) is connected to the on-time signal (TON), the data port (D) is connected to a high level, the reset terminal (R) is connected to the output voltage (Vea) of the main comparator, and the inverting output terminal (QB) outputs the on-time extension detection signal (nExt_TON).

8. The buck converter in COT mode according to claim 7, characterized in that: The reset terminal (R) of the on-time extension capability detection module (DET1) is connected to an output signal (nEXT_RS) of a NOR gate (NOR) to connect the inverted signal of the output voltage (Vea) of the main comparator, and one of the maximum current indication signal (IMAX) and the maximum on-time signal (TON_MAX) of the high-side power tube through the NOR gate (NOR).

9. The buck converter in COT mode according to claim 8, characterized in that: The high-side power tube maximum current indication signal (IMAX) changes from 0 to 1 when the current of the high-side power tube reaches the maximum protection current; the maximum on-time signal (TON_MAX) changes from 0 to 1 when the timing time from the start of the high-side power tube conduction reaches the maximum on-time; the output voltage (Vea) of the main comparator changes from 1 to 0 when the feedback voltage (FB) is greater than the reference voltage (Vref); The on-time extension capability detection module (DET1) is reset when the output signal (nEXT_RS) of the NOR gate (NOR) is equal to 0, so that the on-time extension detection signal (nExt_TON) becomes 1, thereby turning off the high-side power tube (HS) of the buck converter.

10. The buck converter in COT mode according to claim 2, characterized in that: The PWM generation module (P1) is further configured to: if the feedback voltage (FB) is less than the reference voltage (Vref) when the maximum on-time is reached for a continuous preset number of times, the buck converter enters a 100% duty cycle mode, wherein the high-side power tube can be turned on forever and is only turned off when the feedback voltage (FB) is greater than or equal to the reference voltage (Vref) or when the current of the high-side power tube reaches the maximum protection current.

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