Common mode level generating circuit with buffer module, electronic circuit and electronic device

Abstract

The application provides a common-mode level generation circuit with a buffer module, an electronic circuit and an electronic device. The circuit comprises a buffer module, a transconductance operational amplifier module and a first resistor. The buffer module respectively performs level shifting on a first output voltage and a second output voltage output by an integrator and a first reference voltage and a second reference voltage and outputs the first output voltage, the second output voltage, the first reference voltage and the second reference voltage to a transconductance operational amplifier. The transconductance operational amplifier is used for transconductance amplification and addition of input voltages to obtain a first current and a second current respectively. If the first current is greater than the second current, the transconductance operational amplifier module outputs a voltage reduction current. The voltage reduction current flows through the first resistor to generate a voltage drop, so as to reduce the output common-mode level. Therefore, the single side modulation technology of the application not only greatly reduces the power consumption of the power supply in the case of the D class power amplifier being idle, but also greatly improves the efficiency of the D class power amplifier in the case of low power, and avoids the influence of the over-saturation of the first output voltage and the second output voltage on the THDN performance of the circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of class D amplifier, in particular to a common mode level generating circuit with a buffer module, an electronic circuit and an electronic device. BACKGROUND

[0002] The working of class D amplifier needs to convert the output analog signal into pulse width modulation signal, which is modulated by the input sine signal through the integrator and compared with a higher frequency triangle wave through the comparator. If the voltage of the sine signal is higher than the triangle wave at a certain time, the comparator outputs high level, and vice versa. The duration of high and low level is determined by the time generated by the difference between the two, so the continuous sine signal will be modulated into continuous pulse width modulation wave with different width.

[0003] The prior art can realize single side modulation by adjusting the output common mode level of the integrator of class D amplifier, so as to output smaller duty cycle when the class D amplifier is in idle state, thereby saving power consumption. However, when the input signal increases, single side signal clipping is easy to occur, which leads to the decline of audio signal quality. Therefore, there is an urgent need for a dynamic and economical common mode level generating circuit which can realize small duty cycle in idle state and avoid the problem of THDN rising when the output signal power becomes large. SUMMARY

[0004] The present application provides a common mode level generating circuit with a buffer module, an electronic circuit and an electronic device, which is used for outputting dynamic common mode level according to the first output voltage and the second output voltage of the integrator in the class D amplifier and the input reference common mode level. The circuit comprises:

[0005] a buffer module, which is used for;

[0006] level shifting the first output voltage and the second output voltage respectively to output the first output buffer voltage and the second output buffer voltage;

[0007] level shifting the first reference voltage and the second reference voltage respectively to output the first reference buffer voltage and the second reference buffer voltage;

[0008] a transconductance operational amplifier module, which is used for transconductance amplifying and adding the first output buffer voltage and the second output buffer voltage, and the obtained variable is recorded as the first current; the transconductance operational amplifier module is also used for transconductance amplifying and adding the first reference buffer voltage and the second reference buffer voltage, and the obtained variable is recorded as the second current; the transconductance operational amplifier module is also used for comparing the first current and the second current, and if the first current is greater than the second current, the transconductance operational amplifier module outputs the step-down current;

[0009] a first resistor, a first end of the first resistor being connected to an input reference common mode level, a second end of the first resistor being connected to an output end of the trans-impedance operational amplifier module and serving as an output end of a common mode level generating circuit of the buffer module, the buck current flowing through the first resistor and outputting the common mode level from the second end of the first resistor.

[0010] Optionally, the buffer module comprises a first buffer unit, a second buffer unit, a third buffer unit and a fourth buffer unit.

[0011] The first buffer unit is configured to perform level shifting on the first output voltage and output the first output buffer voltage.

[0012] The second buffer unit is configured to perform level shifting on the second output voltage and output the second output buffer voltage.

[0013] The third buffer unit is configured to perform level shifting on the first reference voltage and output the first reference buffer voltage.

[0014] The fourth buffer unit is configured to perform level shifting on the second reference voltage and output the second reference buffer voltage.

[0015] Optionally, the first buffer unit comprises a first MOS transistor and a first current source, a gate end of the first MOS transistor being connected to the first output voltage, a drain end of the first MOS transistor being connected to a power supply voltage of the integrator, a source end of the first MOS transistor being connected to a positive end of the first current source and an output end of the first output buffer voltage, a negative end of the first current source being grounded.

[0016] The second buffer unit comprises a second MOS transistor and a second current source, a gate end of the second MOS transistor being connected to the second output voltage, a drain end of the second MOS transistor being connected to the power supply voltage of the integrator, a source end of the second MOS transistor being connected to a positive end of the second current source and an output end of the second output buffer voltage, a negative end of the second current source being grounded.

[0017] The third buffer unit comprises a third MOS transistor and a third current source, a gate end of the third MOS transistor being connected to the first reference voltage, a drain end of the third MOS transistor being connected to the power supply voltage of the integrator, a source end of the third MOS transistor being connected to a positive end of the third current source and an output end of the first reference buffer voltage, a negative end of the third current source being grounded.

[0018] The fourth buffer unit comprises a fourth MOS transistor and a fourth current source, a gate terminal of the fourth MOS transistor is connected to the second reference voltage, a drain terminal of the fourth MOS transistor is connected to a power supply voltage of the integrator, a source terminal of the fourth MOS transistor is connected to a positive terminal of the fourth current source and an output terminal of the second reference buffer voltage, and a negative terminal of the fourth current source is grounded;

[0019] Optionally, the transconductance operational amplifier module comprises:

[0020] a voltage-to-current conversion unit, configured to convert a sum of the first output buffer voltage and the second output buffer voltage into a first current and output the first current, and convert the first reference buffer voltage and the second reference buffer voltage into a second current and output the second current;

[0021] a first current mirror unit, configured to compare the first current and the second current, and output a third current if the first current is less than the second current;

[0022] a second current mirror unit, configured to convert the third current into the step-down current output.

[0023] Optionally, a value of the third current is equal to a difference between the first current and the second current, and the value of the third current is equal to a value of the step-down current.

[0024] Optionally, the voltage-to-current conversion unit comprises a fifth current source, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a second resistor, and a third resistor.

[0025] The positive terminal of the fifth current source is connected to the power supply voltage of the integrator, and the negative terminal of the fifth current source is connected to the first terminal of the second resistor and the first terminal of the third resistor, respectively; the second terminal of the second resistor is connected to the source terminal of the fifth MOS tube and the source terminal of the sixth MOS tube, respectively, and the second terminal of the third resistor is connected to the source terminal of the ninth MOS tube and the source terminal of the tenth MOS tube, respectively; the gate terminal of the fifth MOS tube and the gate terminal of the eighth MOS tube are connected to the buffer voltage of the first output voltage, the gate terminal of the sixth MOS tube and the gate terminal of the seventh MOS tube are connected to the buffer voltage of the second output voltage, the gate terminal of the ninth MOS tube and the gate terminal of the twelfth MOS tube are connected to the buffer voltage of the first reference voltage, and the gate terminal of the tenth MOS tube and the gate terminal of the eleventh MOS tube are connected to the buffer voltage of the second reference voltage; the drain terminal of the fifth MOS tube is connected to the source terminal of the seventh MOS tube, the drain terminal of the sixth MOS tube is connected to the source terminal of the eighth MOS tube, the drain terminal of the ninth MOS tube is connected to the source terminal of the eleventh MOS tube, and the drain terminal of the tenth MOS tube is connected to the source terminal of the twelfth MOS tube; and the source terminal of the seventh MOS tube and the source terminal of the eighth MOS tube jointly output the first current, and the source terminal of the eleventh MOS tube and the source terminal of the twelfth MOS tube jointly output the second current.

[0026] Optionally, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube, and the twelfth MOS tube are complementary MOS tubes of the first MOS tube, the second MOS tube, the third MOS tube, and the fourth MOS tube.

[0027] If the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube, and the twelfth MOS tube all include PMOS tubes, the first MOS tube, the second MOS tube, the third MOS tube, and the fourth MOS tube all include NMOS tubes.

[0028] If the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube, and the twelfth MOS tube all include NMOS tubes, the first MOS tube, the second MOS tube, the third MOS tube, and the fourth MOS tube all include PMOS tubes.

[0029] Optionally, the first current mirror unit comprises a thirteenth MOS tube and a fourteenth MOS tube, the gate end of the thirteenth MOS tube is connected with the drain end, and the output end of the first current is connected; the gate end of the thirteenth MOS tube is also connected with the gate end of the fourteenth MOS tube; the drain end of the fourteenth MOS tube is connected with the second current; the source end of the thirteenth MOS tube and the source end of the fourteenth MOS tube are both grounded;

[0030] The second current mirror unit comprises a fifteenth MOS tube and a sixteenth MOS tube, the gate end of the fifteenth MOS tube is connected with the drain end, and the gate end of the sixteenth MOS tube is connected; the drain end of the fifteenth MOS tube is connected with the output end of the second current; the source end of the fifteenth MOS tube and the source end of the sixteenth MOS tube are both grounded; the drain end of the sixteenth MOS tube outputs the voltage-reduced current.

[0031] When the first current is greater than the second current, the voltage-reduced current flows through the fifteenth MOS tube and the sixteenth MOS tube; when the first current is less than or equal to the second current, the fifteenth MOS tube and the sixteenth MOS tube are both turned off.

[0032] According to the second aspect of the present application, an electronic circuit is provided, characterized by comprising the common-mode level generating circuit with the buffer module.

[0033] According to the third aspect of the present application, an electronic device is provided, characterized by comprising the electronic circuit.

[0034] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0035] The common mode voltage generating circuit with a buffer module provided by the embodiment of the present application comprises a buffer module, a transconductance operational amplifier module and a first resistor. The buffer module is used to perform level shifting on the first output voltage and the second output voltage and the first reference voltage and the second reference voltage, so as to ensure that the input stage of the transconductance operational amplifier module will not appear saturation or cutoff. The transconductance operational amplifier module is used to compare a first current and a second current. The first current is used to represent an added variable obtained after the first output voltage and the second output voltage output by an integrator are amplified by the transconductance of the transconductance operational amplifier module, and the second current is used to represent an added variable obtained after the first reference voltage and the second reference voltage are amplified by the transconductance of the transconductance operational amplifier module. If the first current is greater than the second current, the transconductance operational amplifier module outputs a voltage reduction current. The voltage reduction current generates a voltage drop through the first resistor, so that the output common mode voltage is lower than the input reference common mode voltage, so as to affect the output voltage of the integrator. Therefore, the single side modulation technology of the present application not only reduces the power consumption of the power supply in the case of D class power amplifier idle, but also improves the output efficiency in the case of low power of D class power amplifier, and avoids the influence of the THDN performance of the circuit caused by the over-saturation of the first output voltage and the second output voltage. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 FIG. 1 is a circuit block diagram of the common mode voltage generating circuit with a buffer module provided by the embodiment of the present application;

[0037] Figure 2 FIG. 2 is a circuit structure schematic diagram of the common mode voltage generating circuit with a buffer module provided by the embodiment of the present application;

[0038] Figure 3 FIG. 3 is a circuit structure schematic diagram of the common mode voltage generating circuit with a buffer module provided by the embodiment of the present application; Figure Two

[0039] Figure 4 FIG. 4 is a circuit structure schematic diagram of the common mode voltage generating circuit with a buffer module provided by the embodiment of the present application; Figure Three

[0040] Figure 5 FIG. 5 is a circuit structure schematic diagram of the common mode voltage generating circuit with a buffer module provided by the embodiment of the present application; Figure Four

[0041] FIG. 6 is a circuit structure schematic diagram of the common mode voltage generating circuit with a buffer module provided by the embodiment of the present application;

[0042] OUTN- the first output voltage;

[0043] OUTP- the second output voltage;

[0044] REFN- the first reference voltage; ​​​

[0045] REFP - second reference voltage;

[0046] VREF - input reference common mode level;

[0047] VCOM - common mode level;

[0048] OUTN_BUF - first output buffer voltage;

[0049] OUTP_BUF - second output buffer voltage;

[0050] REFN_BUF - first reference buffer voltage;

[0051] REFP_BUF - second reference buffer voltage;

[0052] AVDD - power supply voltage for integrator;

[0053] Q1 - first MOS transistor;

[0054] Q2 - second MOS transistor;

[0055] Q3 - third MOS transistor;

[0056] Q4 - fourth MOS transistor;

[0057] Q5 - fifth MOS transistor;

[0058] Q6 - sixth MOS transistor;

[0059] Q7 - seventh MOS transistor;

[0060] Q8 - eighth MOS transistor;

[0061] Q9 - ninth MOS transistor;

[0062] Q10 - tenth MOS transistor;

[0063] Q11 - eleventh MOS transistor;

[0064] Q12 - twelfth MOS transistor;

[0065] Q13 - thirteenth MOS transistor;

[0066] Q14 - fourteenth MOS transistor;

[0067] Q15 - fifteenth MOS transistor;

[0068] Q16 - sixteenth MOS transistor;

[0069] D1 - first current source;

[0070] D2 - second current source;

[0071] D3 - third current source;

[0072] D4 - fourth current source;

[0073] D5 - fifth current source;

[0074] I1 - first current;

[0075] I2 - second current;

[0076] I3 - third current;

[0077] I4 - buck current;

[0078] R1 - first resistance;

[0079] R2 - second resistance;

[0080] R3 - third resistance. DETAILED DESCRIPTION

[0081] The embodiments in the present application will be described below in detail with the accompanying drawings of the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments in the present application, but not all the embodiments in the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. The terms "first", "second", "third", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to the clearly listed steps or units, but can include other steps or units that are not clearly listed or inherent to the process, method, product or device.

[0082] As described in the background, in order to achieve smaller idle state power consumption, the common mode level of the integrator is generally preset to a certain fixed value, and a common mode level higher than 1 / 2 power supply voltage is selected to realize unidirectional modulation, but when the power rises, the output is prone to unidirectional clipping, resulting in a decrease in THD+N index, and it is impossible to simultaneously consider idle power consumption and THDN performance at high power.

[0083] Therefore, the present application creatively proposes a new common mode level generation circuit with a buffer module.

[0084] wherein, Figure 1The circuit block diagram of the common-mode level generation circuit with a buffer module is provided by the embodiment of the present application.

[0085] Please refer to Figure 1 The embodiment of the present application provides a common-mode level generation circuit with a buffer module, which is used for outputting a dynamic common-mode level according to a first output voltage and a second output voltage of an integrator in a class-D amplifier and an input reference common-mode level, and the circuit comprises the following components:

[0086] a buffer module 2, which is used for

[0087] performing level shifting on the first output voltage OUTN and the second output voltage OUTP respectively to output a first output buffer voltage OUTN_BUF and a second output buffer voltage OUTP_BUF;

[0088] performing level shifting on the first reference voltage REFN and the second reference voltage REFP respectively to output a first reference buffer voltage REFN_BUF and a second reference buffer voltage REFP_BUF;

[0089] a transconductance operational amplifier module 1, which is used for adding the first output buffer voltage OUTN_BUF and the second output buffer voltage OUTP_BUF after transconductance amplification, and the obtained variable is recorded as a first current; the transconductance operational amplifier module is also used for adding the first reference buffer voltage REFN_BUF and the second reference buffer voltage REFP_BUF after transconductance amplification, and the obtained variable is recorded as a second current, and the transconductance operational amplifier module 1 is also used for comparing the first current with the second current, and if the first current is greater than the second current, the transconductance operational amplifier module outputs a step-down current;

[0090] a first resistor R1, a first end of the first resistor R1 is connected to an input reference common-mode level VREF, a second end of the first resistor R1 is also connected to an output end of the transconductance operational amplifier module 1, the second end of the first resistor R1 is connected to the output end of the transconductance operational amplifier module 1 and serves as an output end of the common-mode level generation circuit with a buffer module, and the first resistor R1 is used for receiving the step-down current of the transconductance operational amplifier module 1 and outputting the common-mode level.

[0091] The common-mode level VCOM is outputted as the output end of the common-mode level generation circuit with a buffer module.

[0092] Through the above technical means, the embodiment of the present application can provide a common-mode level generation circuit with a buffer module, which can not only realize a small duty cycle in an idle state, but also can avoid the THDN rising problem when the output signal power becomes large. The specific principle is as follows:

[0093] In the common mode level generating circuit with a buffer module in the embodiment of the present application, a transconductance operational amplifier module 1 is arranged to add the first output buffer voltage OUTN_BUF and the second output buffer voltage OUTP_BUF after transconductance amplification, and the resultant variable is referred to as a first current; the transconductance operational amplifier module is also arranged to add the first reference buffer voltage REFN_BUF and the second reference buffer voltage REFP_BUF after transconductance amplification, and the resultant variable is referred to as a second current. The transconductance operational amplifier module 1 is also arranged to compare the first current and the second current. Before the output of the integrator is saturated, if the first current is less than the second current, the transconductance operational amplifier module 1 does not output a current, so the common mode level of the integrator is still the input reference common mode level VREF of the integrator, thereby reducing the duty cycle of the output of the class-D amplifier, so as to not only greatly reduce the power consumption of the power supply in the case of no load of the class-D power amplifier, but also greatly improve the output efficiency in the case of low power of the class-D power amplifier. After the output of the integrator is saturated, if the first current is greater than the second current, the transconductance operational amplifier module 1 outputs a step-down current, the step-down current generates a voltage drop through the first resistor R1, so that the common mode level generating circuit outputs a new common mode level VCOM which is less than the input reference common mode level VREF, thereby reducing the input reference common mode level VREF of the integrator, and further avoiding the increase of THDN of the class-D amplifier, and the embodiment of the present application does not need to adjust the common mode level of the triangular wave.

[0094] Meanwhile, since the integrator generally adopts a differential common mode structure, the range of the first output voltage OUTN and the second output voltage OUTP output by the integrator fluctuates between 0V and the power supply voltage, so the transconductance operational amplifier module 1 will make the first output voltage OUTN and the second output voltage OUTP exceed the working range of the input pair of the transconductance operational amplifier module 1, regardless of whether NMOS input pair or PMOS input pair is adopted, which leads to that the transconductance operational amplifier module 1 cannot work normally in the full swing range. Therefore, the buffer module 2 is arranged to perform level shifting on the first output voltage OUTN and the second output voltage OUTP and the first reference voltage REFN and the second reference voltage REFP, so as to ensure that the transconductance operational amplifier module 1 can work normally in the full swing range.

[0095] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0096] As a specific embodiment, the buffer module comprises a first buffer unit 21, a second buffer unit 22, a third buffer unit 23 and a fourth buffer unit 24.

[0097] The first buffer unit 21 is configured to perform level shifting on the first output voltage OUTN and output a first output buffer voltage OUTN_BUF.

[0098] The second buffer unit 22 is configured to perform level shifting on the second output voltage OUTP and output a second output buffer voltage OUTP_BUF.

[0099] The third buffer unit 23 is configured to perform level shifting on the first reference voltage REFN and output a first reference buffer voltage REFN_BUF.

[0100] The fourth buffer unit 24 is configured to perform level shifting on the second reference voltage REFP and output a second reference buffer voltage REFP_BUF.

[0101] Wherein, Figure 2 is a circuit structure diagram of a common-mode level generation circuit with a buffer module provided by an embodiment of the application.

[0102] Please refer to Figure 2 The first buffer unit 21 comprises a first MOS tube Q1 and a first current source D1, a gate end of the first MOS tube Q1 is connected to the first output voltage, a drain end of the first MOS tube Q1 is connected to a power supply voltage AVDD of the integrator, a source end of the first MOS tube Q1 is connected to a positive end of the first current source D1 and an output end of the first output buffer voltage OUTN_BUF, and a negative end of the first current source D1 is grounded.

[0103] The second buffer unit 22 comprises a second MOS tube Q2 and a second current source D2, a gate end of the second MOS tube Q2 is connected to the second output voltage, a drain end of the second MOS tube Q2 is connected to the power supply voltage AVDD of the integrator, a source end of the second MOS tube Q2 is connected to a positive end of the second current source D2 and an output end of the second output buffer voltage OUTP_BUF, and a negative end of the second current source D2 is grounded.

[0104] The third buffer unit 23 comprises a third MOS tube Q3 and a third current source D3, the gate end of the third MOS tube Q3 is connected to the first reference buffer voltage REFN_BUF, the drain end of the third MOS tube Q3 is connected to the power supply voltage AVDD of the integrator, the source end of the third MOS tube Q3 is connected to the positive end of the third current source D3 and the output end of the first reference buffer voltage REFN_BUF, and the negative end of the third current source D3 is grounded.

[0105] The fourth buffer unit 24 comprises a fourth MOS tube Q4 and a fourth current source D4, the gate end of the fourth MOS tube Q4 is connected to the second reference buffer voltage REFP_BUF, the drain end of the fourth MOS tube Q4 is connected to the power supply voltage AVDD of the integrator, the source end of the fourth MOS tube Q4 is connected to the positive end of the fourth current source D4 and the output end of the second reference buffer voltage REFP_BUF, and the negative end of the fourth current source D4 is grounded.

[0106] Figure 3 The circuit structure diagram of the common mode level generation circuit with a buffer module provided by the embodiment of the present application Figure Two .

[0107] Please refer to Figure 3 , as a specific embodiment, the transconductance operational amplifier module 1 comprises:

[0108] A voltage-to-current conversion unit 11, which is configured to add the first output buffer voltage OUTN_BUF and the second output buffer voltage OUTP_BUF after transconductance amplification, and output the first current I1, and is configured to add the first reference buffer voltage REFN_BUF and the second reference buffer voltage REFP_BUF after transconductance amplification, and output the second current I2;

[0109] A first current mirror unit 12, which is configured to compare the first current I1 and the second current I2, and output a third current I3 if the first current I1 is less than the second current I2.

[0110] A second current mirror unit 13, which is configured to convert the third current I3 into the step-down current I4.

[0111] The value of the third current I3 is equal to the difference between the first current I1 and the second current I2, and the value of the third current I3 is equal to the value of the step-down current I4.

[0112] Figure 4The circuit structure diagram of the common mode level generating circuit with a buffer module Figure Three .

[0113] Please refer to Figure 4 , as a specific embodiment, the voltage current conversion unit 11 includes the fifth current source D5, the fifth MOS tube Q5, the sixth MOS tube Q6, the seventh MOS tube Q7, the eighth MOS tube Q8, the ninth MOS tube Q9, the tenth MOS tube Q10, the eleventh MOS tube Q11, the twelfth MOS tube Q12, the second resistance R2 and the third resistance R3;

[0114] The positive terminal of the fifth current source D5 is connected with the power supply voltage AVDD of the integrator, and the negative terminal of the fifth current source D5 is connected with the first terminal of the second resistance R2 and the first terminal of the third resistance R3 respectively; the second terminal of the second resistance R2 is connected with the source terminal of the fifth MOS tube Q5 and the source terminal of the sixth MOS tube Q6 respectively, the second terminal of the third resistance R3 is connected with the source terminal of the ninth MOS tube Q9 and the source terminal of the tenth MOS tube Q10 respectively, the gate terminal of the fifth MOS tube Q5 and the gate terminal of the eighth MOS tube Q8 are connected with the first output buffer voltage OUTN_BUF, the gate terminal of the sixth MOS tube Q6 and the gate terminal of the seventh MOS tube Q7 are connected with the second output buffer voltage OUTP_BUF, the gate terminal of the ninth MOS tube Q9 and the gate terminal of the twelfth MOS tube Q12 are connected with the first reference buffer voltage REFN_BUF, the gate terminal of the tenth MOS tube Q10 and the gate terminal of the eleventh MOS tube Q11 are connected with the second reference buffer voltage REFP_BUF, the drain terminal of the fifth MOS tube Q5 is connected with the source terminal of the seventh MOS tube Q7, the drain terminal of the sixth MOS tube Q6 is connected with the source terminal of the eighth MOS tube Q8, the drain terminal of the ninth MOS tube Q9 is connected with the source terminal of the eleventh MOS tube Q11, the drain terminal of the tenth MOS tube Q10 is connected with the source terminal of the twelfth MOS tube Q12, and the source terminal of the seventh MOS tube Q7 and the source terminal of the eighth MOS tube Q8 commonly output the first current I1, and the source terminal of the eleventh MOS tube Q11 and the source terminal of the twelfth MOS tube Q12 commonly output the second current I2.

[0115] Wherein, the MOS tube type in the voltage current conversion unit and the MOS tube type in the buffer module are complementary, so as to ensure that the transconductance operational amplifier module can work normally in the full swing range.

[0116] Specifically, if the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube all include PMOS tubes, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube all include NMOS tubes, so as to shift the first output voltage and the second output voltage and the first reference voltage and the second reference voltage downward.

[0117] If the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube all include NMOS tubes, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube all include PMOS tubes, so as to shift the first output voltage and the second output voltage and the first reference voltage and the second reference voltage upward.

[0118] Figure 5 is the circuit structure diagram of the common mode level generating circuit with a buffer module provided by the embodiment of the application Figure Four .

[0119] Please refer to Figure 5 , as a specific embodiment, the first current mirror unit 12 includes a thirteenth MOS tube Q13 and a fourteenth MOS tube Q14, the gate end of the thirteenth MOS tube Q13 is connected with the gate end of the fourteenth MOS tube Q14, the drain end of the thirteenth MOS tube Q13 is connected with the output end of the first current I1 and the gate end of the thirteenth MOS tube Q13 respectively, the drain end of the fourteenth MOS tube Q14 is connected with the second current I2, and the source end of the thirteenth MOS tube Q13 and the source end of the fourteenth MOS tube Q14 are both grounded.

[0120] The second current mirror unit 13 includes a fifteenth MOS tube Q15 and a sixteenth MOS tube Q16, the gate end of the fifteenth MOS tube Q15 is connected with the gate end of the sixteenth MOS tube Q16, the drain end of the fifteenth MOS tube Q15 is connected with the gate end of the fifteenth MOS tube Q15 and the drain end of the fourteenth MOS tube Q14 respectively, the source end of the fifteenth MOS tube Q15 and the source end of the sixteenth MOS tube Q16 are both grounded, and the drain end of the sixteenth MOS tube Q16 outputs the voltage reduction current I4.

[0121] The thirteenth MOS tube Q13, the fourteenth MOS tube Q14, the fifteenth MOS tube Q15 and the sixteenth MOS tube Q16 include N-channel MOS tubes.

[0122] Please refer to Figure 5 The working principle of the common-mode level generating circuit with buffer module is as follows:

[0123] Before the saturation of the output of the integrator, the value of the first current is less than the second current, so that the first current I1 output by the voltage-to-current conversion module is greater than the second current I2. Since the thirteenth MOS tube Q13 and the fourteenth MOS tube Q14 constitute the first current mirror unit 12, the current flowing through the thirteenth MOS tube Q13 will be mirrored to the fourteenth MOS tube Q14, but because the first current is greater than the second current, there is not enough current flowing into the fourteenth MOS tube Q14, so the current flowing through the thirteenth MOS tube Q13 cannot be mirrored to the fourteenth MOS tube Q14, and the current flowing into the fourteenth MOS tube Q14 is the second current I2, and no current will flow into the fifteenth MOS tube Q15, so that the transconductance operational amplifier module 1 has no step-down current I4 output. At this time, the common-mode level of the integrator is equal to the input reference common-mode level VREF, and the input reference common-mode level VREF is a certain fixed value between AVDD / 2 and AVDD, wherein the second current value represents the output voltage value of the integrator when the integrator is in critical saturation.

[0124] After the saturation of the output of the integrator, the first current is greater than the second current, so that the first current I1 output by the voltage-to-current conversion module is less than the second current I2. Since the thirteenth MOS tube Q13 and the fourteenth MOS tube Q14 constitute the first current mirror unit 12, the current flowing through the thirteenth MOS tube Q13 will be mirrored to the fourteenth MOS tube Q14, so that the current flowing into the fourteenth MOS tube Q14 is equal to the value of the first current I1, and the remaining current flows into the fifteenth MOS tube Q15, i.e. the third current I3. Since the sixteenth MOS tube Q16 and the fifteenth MOS tube Q15 constitute the second current mirror unit 13, the third current I3 flowing through the fifteenth MOS tube Q15 will be mirrored to the sixteenth MOS tube Q16 and output through the drain of the sixteenth MOS tube Q16, i.e. the step-down current I4. The step-down current I4 passes through the first resistor R1 to generate a voltage drop, and the voltage drop generated by the first resistor R1 is proportional to the difference between the first current and the second current, so that a new common-mode level VCOM smaller than the input reference common-mode level VREF is output, and the output common-mode level VCOM will not be lower than AVDD / 2.

[0125] In summary, the common-mode level generating circuit with a buffer module in the embodiment of the present application is provided with a buffer module, a transconductance operational amplifier module and a first resistor, the transconductance operational amplifier module is used to add the first output voltage and the second output voltage output by the integrator in the class-D amplifier after transconductance amplification, and the resultant variable is recorded as a first current; the transconductance operational amplifier module is also used to add the first reference voltage and the second reference voltage after transconductance amplification, and the resultant variable is recorded as a second current. The transconductance operational amplifier module is also used to compare the first current and the second current. When the output of the integrator is saturated, the first current is less than the second current, the transconductance operational amplifier module does not output current, so the common-mode level of the integrator is still the input reference common-mode level of the integrator, so as to reduce the duty cycle of the class-D amplifier output, thereby not only greatly reducing the power consumption of the class-D power amplifier in the case of no load, but also greatly improving the output efficiency in the case of low power of the class-D power amplifier. When the output of the integrator is saturated, the first current is greater than the second current, the transconductance operational amplifier module outputs a step-down current, the step-down current generates a voltage drop through the first resistor, so that the common-mode level generating circuit outputs a new common-mode level which is less than the input reference common-mode level, thereby reducing the input reference common-mode level of the integrator, and avoiding the increase of THDN of the class-D amplifier, and the embodiment of the present application does not need to adjust the common-mode level of the triangular wave.

[0126] Meanwhile, the buffer module is used to perform level shifting on the first output voltage, the second output voltage, the first reference voltage and the second reference voltage, so as to ensure that the transconductance operational amplifier module can normally work in the full swing range.

[0127] The embodiment of the present application also provides an electronic circuit, which comprises the common-mode level generating circuit with a buffer module and other parts of the electronic circuit.

[0128] The embodiment of the present application also provides an electronic device, which comprises the electronic circuit and other parts of the electronic device.

[0129] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A common-mode level generation circuit with a buffer module, characterized in that, The circuit is used to output a dynamic common-mode level based on the first and second output voltages of the integrator in the Class D amplifier and the input reference common-mode level. A buffer module, wherein the buffer module is used for; The first output voltage and the second output voltage are respectively level shifted to output the first output buffer voltage and the second output buffer voltage; The first reference voltage and the second reference voltage are respectively level shifted to output the first reference buffer voltage and the second reference buffer voltage; The transconductance operational amplifier module is used to amplify the first output buffer voltage and the second output buffer voltage through transconductance and then add them together, with the resulting variable being denoted as the first current; the transconductance operational amplifier module is also used to amplify the first reference buffer voltage and the second reference buffer voltage through transconductance and then add them together, with the resulting variable being denoted as the second current; the transconductance operational amplifier module is also used to compare the first current and the second current, and if the first current is greater than the second current, the transconductance operational amplifier module outputs a step-down current; A first resistor has its first end connected to an input reference common-mode level, and its second end connected to the output of the transconductance operational amplifier module and serving as the output of the common-mode level generation circuit with a buffer module. The step-down current flows through the first resistor and outputs the common-mode level from its second end.

2. The common-mode level generation circuit with buffer module according to claim 1, characterized in that, The buffer module includes a first buffer unit, a second buffer unit, a third buffer unit, and a fourth buffer unit; The first buffer unit is used to perform level shifting on the first output voltage and output the first output buffer voltage; The second buffer unit is used to perform level shifting on the second output voltage and output the second output buffer voltage; The third buffer unit is used to perform level shifting on the first reference voltage and output the first reference buffer voltage; The fourth buffer unit is used to perform level shifting on the second reference voltage and output the second reference buffer voltage.

3. The common-mode level generation circuit with buffer module according to claim 2, characterized in that, The first buffer unit includes a first MOSFET and a first current source. The gate terminal of the first MOSFET is connected to the first output voltage, the drain terminal of the first MOSFET is connected to the power supply voltage of the integrator, the source terminal of the first MOSFET is connected to the positive terminal of the first current source and the output terminal of the first output buffer voltage, and the negative terminal of the first current source is grounded. The second buffer unit includes a second MOS transistor and a second current source. The gate terminal of the second MOS transistor is connected to the second output voltage, the drain terminal of the second MOS transistor is connected to the power supply voltage of the integrator, the source terminal of the second MOS transistor is connected to the positive terminal of the second current source and the output terminal of the second output buffer voltage, and the negative terminal of the second current source is grounded. The third buffer unit includes a third MOS transistor and a third current source. The gate terminal of the third MOS transistor is connected to the first reference voltage, the drain terminal of the third MOS transistor is connected to the power supply voltage of the integrator, the source terminal of the third MOS transistor is connected to the positive terminal of the third current source and the output terminal of the first reference buffer voltage, and the negative terminal of the third current source is grounded. The fourth buffer unit includes a fourth MOS transistor and a fourth current source. The gate terminal of the fourth MOS transistor is connected to the second reference voltage, the drain terminal of the fourth MOS transistor is connected to the power supply voltage of the integrator, the source terminal of the fourth MOS transistor is connected to the positive terminal of the fourth current source and the output terminal of the second reference buffer voltage, and the negative terminal of the fourth current source is grounded.

4. The common-mode level generation circuit with buffer module according to claim 3, characterized in that, The transconductance operational amplifier module includes: A voltage-to-current conversion unit is configured to convert the sum of the first output buffer voltage and the second output buffer voltage into a first current and output it, and is also configured to convert the first reference buffer voltage and the second reference buffer voltage into a second current and output it. The first current mirror unit is used to compare the first current and the second current. If the first current is less than the second current, the first current mirror unit outputs a third current. The second current mirror unit is used to convert the third current into the step-down current output.

5. The common-mode level generation circuit with buffer module according to claim 4, characterized in that, The value of the third current is equal to the difference between the first current and the second current, and the value of the third current is equal to the value of the step-down current.

6. The common-mode level generation circuit with buffer module according to claim 5, characterized in that, The voltage-to-current conversion unit includes a fifth current source, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a second resistor, and a third resistor; The positive terminal of the fifth current source is connected to the power supply voltage of the integrator, and the negative terminal of the fifth current source is connected to the first terminal of the second resistor and the first terminal of the third resistor, respectively. The second terminal of the second resistor is connected to the source terminals of the fifth MOSFET and the sixth MOSFET, respectively. The second terminal of the third resistor is connected to the source terminals of the ninth MOSFET and the tenth MOSFET, respectively. The gate terminals of the fifth MOSFET and the eighth MOSFET are both connected to the buffer voltage of the first output voltage. The gate terminals of the sixth MOSFET and the seventh MOSFET are both connected to the buffer voltage of the second output voltage. The gate terminals of the ninth MOSFET and the twelfth MOSFET are both connected to the buffer voltage of the second output voltage. A buffer voltage of the first reference voltage is connected. The gate terminals of the tenth and eleventh MOSFETs are both connected to the buffer voltage of the second reference voltage. The drain terminal of the fifth MOSFET is connected to the source terminal of the seventh MOSFET. The drain terminal of the sixth MOSFET is connected to the source terminal of the eighth MOSFET. The drain terminal of the ninth MOSFET is connected to the source terminal of the eleventh MOSFET. The drain terminal of the tenth MOSFET is connected to the source terminal of the twelfth MOSFET. The drain terminals of the seventh and eighth MOSFETs jointly output the first current. The drain terminals of the eleventh and twelfth MOSFETs jointly output the second current.

7. The common-mode level generation circuit with buffer module according to claim 6, wherein the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor and the twelfth MOS transistor are all complementary MOS transistors of the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor; If the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, and the twelfth MOS transistor all include PMOS transistors, then the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor all include NMOS transistors; If the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, and the twelfth MOS transistor all include NMOS transistors, then the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor all include PMOS transistors.

8. The common-mode level generation circuit with buffer module according to claim 4, characterized in that, The first current mirror unit includes a thirteenth MOS transistor and a fourteenth MOS transistor. The gate and drain of the thirteenth MOS transistor are connected and connected to the output terminal of the first current. The gate of the thirteenth MOS transistor is also connected to the gate of the fourteenth MOS transistor. The drain of the fourteenth MOS transistor is connected to the second current. The source terminals of the thirteenth MOS transistor and the fourteenth MOS transistor are both grounded. The second current mirror unit includes a fifteenth MOS transistor and a sixteenth MOS transistor. The gate terminal and drain terminal of the fifteenth MOS transistor are connected and connected to the gate terminal of the sixteenth MOS transistor. The drain terminal of the fifteenth MOS transistor is connected to the output terminal of the second current. The source terminals of the fifteenth MOS transistor and the sixteenth MOS transistor are both grounded. The drain terminal of the sixteenth MOS transistor outputs the step-down current. When the first current is greater than the second current, the step-down current flows through the fifteenth MOSFET and the sixteenth MOSFET; when the first current is less than or equal to the second current, both the fifteenth MOSFET and the sixteenth MOSFET are turned off.

9. An electronic circuit, characterized in that, The common-mode level generation circuit with a buffer module as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the electronic circuit described in claim 9.

Images