Clock circuit and integrated circuit

Abstract

The present disclosure provides a clock circuit and an integrated circuit thereof. The clock circuit includes a bias current circuit, a current control circuit, a clock cycle control circuit and a ramp voltage generating circuit; the bias current circuit is used to generate a first current signal under the drive of a ramp peak voltage signal and transmit it to the current control circuit; the current control circuit is used to transmit the first current signal to the clock cycle control circuit, and the current control circuit is also used to adjust the first current signal under the drive of an external voltage signal to form a second current signal; the clock cycle control circuit is used to output a clock frequency signal and a clock cycle signal under the drive of the first current signal; the ramp voltage generating circuit is used to detect a ramp peak voltage signal during a charge and discharge cycle, and transmit the ramp peak voltage signal to the bias current circuit to form a loop. The present disclosure can achieve precise control of the clock frequency and obtain a wider clock frequency range.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to a clock circuit and an integrated circuit thereof. Background Art

[0002] Clock signals play an important role in mixed analog and digital circuits. With the rapid development of SOC (system-on-chip) technology, high-precision clock circuits integrated on-chip have become an inevitable choice, especially high-precision clock circuits on-chip that are compatible with low-cost standard CMOS (complementary metal oxide semiconductor) technology. This can not only reduce the manufacturing cost of the chip, but also significantly improve the reliability of the overall circuit.

[0003] Among them, the ring oscillator (OSC) is a closed loop composed of an odd number of inverters, which can generate oscillations without an external clock signal. It is widely used in most circuits due to its simple structure, output range can be adjusted by modifying the inverters, and it is easy to integrate.

[0004] Take the ring oscillator composed of three inverters INV as an example. Figure 1 As shown, each stage of the inverter connects the output to the input of the next stage of the inverter. The level is flipped after each stage of the inverter. The output of the last inverter is connected to the input of the first stage to form a loop. Its oscillation frequency is determined by the delay of the inverter. Therefore, the frequency output can be changed by modifying the parameters or number of inverters.

[0005] However, the frequency range of the ring oscillator is small, and the delay of the inverter is determined by the charging and discharging speed of the capacitor at the output node, which makes the output frequency of the ring oscillator easily affected by factors such as temperature, power supply voltage, and process deviation. Therefore, in some applications that require high precision, high frequency stability, and low noise, a high-precision clock circuit with a simple structure and high stability is needed. Summary of the invention

[0006] The technical problem to be solved by the present disclosure is to overcome the defects in the prior art that the frequency range generated by the ring oscillator is small and the output frequency of the ring oscillator is easily affected by factors such as temperature, power supply voltage, and process deviation. A clock circuit and its integrated circuit are provided to adjust the clock frequency signal by modifying the current, so as to achieve low-cost acquisition of high-precision clock signals in a wide frequency range.

[0007] The present invention solves the above technical problems through the following technical solutions:

[0008] According to a first aspect of the present disclosure, there is provided a clock circuit, the clock circuit comprising a bias current circuit, a current control circuit, a clock cycle control circuit and a ramp voltage generating circuit;

[0009] The bias current circuit, the current control circuit, the clock cycle control circuit and the ramp voltage generating circuit form a ring circuit;

[0010] The bias current circuit is used to generate a first current signal and transmit it to the current control circuit under the drive of the ramp peak voltage signal;

[0011] The current control circuit is used to transmit the first current signal to the clock cycle control circuit, and the current control circuit is also used to adjust the first current signal under the drive of an external voltage signal to form a second current signal;

[0012] The clock cycle control circuit is used to output a clock frequency signal and a clock cycle signal under the drive of the first current signal, and control the current control circuit to transmit the second current signal to the charging and discharging cycle of the ramp voltage generating circuit according to the clock cycle signal;

[0013] The slope voltage generating circuit is used to detect the slope peak voltage signal during the charge and discharge cycle, and transmit the slope peak voltage signal to the bias current circuit to form a loop.

[0014] Preferably, the current control circuit comprises a first circuit unit, a second circuit unit and a current adjustment circuit unit connected in sequence; the clock cycle control circuit comprises a ring oscillator and a clock control circuit connected in sequence;

[0015] The first circuit unit is used to receive the first current signal;

[0016] The second circuit unit and the first circuit unit form a first output branch, and the first circuit unit and the current trimming circuit unit form a second output branch;

[0017] The first output branch is used to transmit the first current signal to the ring oscillator;

[0018] The second output branch is used to adjust the first current signal under the drive of the external voltage signal to generate the second current signal;

[0019] The ring oscillator generates and outputs a clock frequency signal under the drive of the first current signal, and transmits the clock frequency signal to the clock control circuit;

[0020] The clock control circuit generates the clock period signal under the drive of the clock frequency signal;

[0021] Among them, the clock cycle signal includes a charging cycle signal and a discharging cycle signal, the charging cycle signal is used to control the charging cycle of the second output branch to transmit the second current signal to the ramp voltage generating circuit, and the discharging cycle signal is used to control the discharging cycle of the ramp voltage generating circuit.

[0022] Preferably, the current trimming circuit unit includes a first sub-circuit structure and a plurality of second sub-circuit structures, the first sub-circuit structure includes a first PMOS (P-Channel-Oxide-Semiconductor) tube, a second PMOS tube and a third PMOS tube, the second sub-circuit structure includes a fourth PMOS tube and a fifth PMOS tube, wherein the drain of the fourth PMOS tube in the same second sub-circuit structure is connected to the source of the fifth PMOS tube;

[0023] The source of the first PMOS tube and the source of each of the fourth PMOS tubes are connected to the power supply voltage, the gate of the first PMOS tube and the gate of each of the fourth PMOS tubes are connected to the first circuit unit and the second circuit unit, and the drain of the first PMOS tube is connected to the source of the second PMOS tube;

[0024] The gate of each of the fifth PMOS tubes is connected to the external voltage signal, and the drain of each of the fifth PMOS tubes is connected to the drain of the second PMOS tube and the source of the third PMOS tube;

[0025] The gate of the second PMOS tube is connected to the first circuit unit and the second circuit unit, the gate of the third PMOS tube is connected to the output end of the clock control circuit and the output end of the ramp voltage generating circuit, and the drain of the third PMOS tube is connected to the input end of the ramp voltage generating circuit.

[0026] Preferably, the first circuit unit includes a sixth PMOS tube and a seventh PMOS tube, and the second circuit unit includes an eighth PMOS tube and a ninth PMOS tube;

[0027] The source of the sixth PMOS tube and the source of the eighth PMOS tube are both connected to the power supply voltage;

[0028] The gate of the sixth PMOS tube is connected to the drain of the sixth PMOS tube, the source of the seventh PMOS tube, the gate of the eighth PMOS tube, the gate of the first PMOS tube, and the gate of the fourth PMOS tube;

[0029] The gate of the seventh PMOS tube is connected to the drain of the seventh PMOS tube, the bias current circuit, the gate of the ninth PMOS tube, and the gate of the second PMOS tube;

[0030] The drain of the eighth PMOS tube is connected to the source of the ninth PMOS tube, and the drain of the ninth PMOS tube is connected to the ring oscillator.

[0031] Preferably, the current ratio of the fourth PMOS transistor and the fifth PMOS transistor in the same second sub-circuit structure is the same;

[0032] The current ratios of different second sub-circuit structures are different.

[0033] Preferably, the current trimming circuit unit includes four of the second sub-circuit structures;

[0034] The gates of the fifth PMOS transistors in different second sub-circuit structures are connected to different external voltage signals.

[0035] Preferably, the ring oscillator comprises a level converter and an odd number of inverters;

[0036] The output end of the inverter of each stage is connected to the input end of the inverter of the next stage, and the output end of the inverter of the last stage is respectively connected to the input end of the inverter of the first stage and the input end of the level converter, and the output end of the level converter is connected to the clock control circuit, wherein the power supply voltage of the inverter is the first current signal.

[0037] Preferably, the ramp voltage generating circuit comprises a first NMOS (N-Metal-Oxide-Semiconductor) tube, a capacitor and a ramp voltage detecting circuit;

[0038] The gate of the first NMOS transistor is connected to the output end of the clock control circuit, the drain of the first NMOS transistor is connected to the second output branch of the current control circuit, one end of the capacitor, and the input end of the ramp voltage detection circuit, and the source of the first NMOS transistor and the other end of the capacitor are both grounded;

[0039] The output end of the slope voltage detection circuit is connected to the bias current circuit.

[0040] Preferably, the bias current circuit comprises an amplifier, a second NMOS tube and a resistor;

[0041] The positive input terminal of the amplifier is connected to the output terminal of the ramp voltage generating circuit, the reverse input terminal of the amplifier is connected to the source of the second NMOS tube and one end of the resistor, the output terminal of the amplifier is connected to the gate of the second NMOS tube, and the drain of the second NMOS tube is connected to the current control circuit; the other end of the resistor is grounded.

[0042] According to a second aspect of the present disclosure, an integrated circuit is provided, wherein the integrated circuit comprises the clock circuit described in the first aspect of the present disclosure.

[0043] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0044] The positive progress of the present disclosure is that the clock frequency can be precisely controlled by modifying the power supply voltage of the ring oscillator to a voltage related to the clock, and the clock frequency can be precisely controlled by modifying the resistor and capacitor to obtain a wider clock frequency range. At the same time, the clock frequency can be further controlled by current adjustment to reduce the influence of process and other factors. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a schematic diagram of the circuit structure of an existing ring oscillator;

[0046] Figure 2 is a schematic diagram of a first circuit structure of a clock circuit disclosed in the present invention;

[0047] Figure 3 is a schematic diagram of a second circuit structure of the clock circuit disclosed in the present invention;

[0048] Figure 4 is a schematic diagram of a third circuit structure of the clock circuit disclosed in the present invention;

[0049] Figure 5 is a schematic diagram of a fourth circuit structure of the clock circuit disclosed in the present invention;

[0050] Figure 6 is a schematic diagram of a fifth circuit structure of the clock circuit disclosed in the present invention;

[0051] Figure 7 is a sixth circuit structure schematic diagram of the clock circuit disclosed in the present invention;

[0052] Figure 8 is a seventh circuit structure schematic diagram of the clock circuit disclosed in the present invention;

[0053] Fig. 9 is a schematic diagram of an eighth circuit structure of the clock circuit disclosed in the present invention;

[0054] Fig.10Schematic diagram of the waveform of the signal in the clock circuit of the present invention. DETAILED DESCRIPTION

[0055] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0056] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0057] In the embodiments of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0058] Example 1

[0059] In a specific embodiment of the present disclosure, a clock circuit is provided, such as Figure 2 As shown, the clock circuit includes a bias current circuit 1, a current control circuit 2, a clock cycle control circuit 3 and a ramp voltage generating circuit 4;

[0060] The bias current circuit 1, the current control circuit 2, the clock cycle control circuit 3 and the ramp voltage generating circuit 4 form a ring circuit;

[0061] The bias current circuit 1 is used to generate a first current signal and transmit it to the current control circuit 2 under the drive of the ramp peak voltage signal;

[0062] The current control circuit 2 is used to transmit the first current signal to the clock cycle control circuit 3. The current control circuit 2 is also used to adjust the first current signal under the drive of the external voltage signal to form a second current signal.

[0063] The clock cycle control circuit 3 is used to output a clock frequency signal and a clock cycle signal under the drive of the first current signal, and control the current control circuit 2 to transmit the second current signal to the charging and discharging cycle of the ramp voltage generating circuit 4 according to the clock cycle signal;

[0064] The ramp voltage generating circuit 4 is used to detect the ramp peak voltage signal during the charge and discharge cycle, and transmit the ramp peak voltage signal to the bias current circuit 1 to form a loop.

[0065] Specifically, the input voltage of the bias current circuit 1 is the slope peak voltage signal V detected by the slope voltage generating circuit 4 during the charge and discharge cycle. ref , forming a first current signal in a path between the current control circuit 2 and the bias current circuit 1;

[0066] The current control circuit 2 copies the first current signal and transmits the first current signal to the clock cycle control circuit 3, providing the clock cycle control circuit 3 with an input voltage V in , to drive the clock cycle control circuit 3 to generate a clock frequency signal OSC_OUT and a clock cycle signal for output, wherein the clock cycle signal includes a charging cycle signal CLK_OUT and a discharging cycle signal B_pull (the discharging cycle signal B_pull is not shown in the figure), and the clock cycle control circuit 3 also transmits the clock cycle signal to the current control circuit 2 and the ramp voltage generating circuit 4; at the same time, the current control circuit 2 is also used to receive an external voltage signal to adjust the first current signal to form a second current signal, and under the control of the clock cycle signal provided by the clock cycle control circuit 3, the second current signal is transmitted to the ramp voltage generating circuit 4 to charge and discharge the ramp voltage generating circuit 4.

[0067] The ramp voltage generating circuit 4 performs charging and rapid discharging according to the clock cycle signal to generate a ramp voltage signal, and obtains a ramp peak voltage signal V by detecting the ramp voltage signal. ref , the ramp peak voltage signal V ref Transmitted to bias current circuit 1 to form a loop.

[0068] In a specific embodiment, Figure 3 As shown, the current control circuit 2 includes a first circuit unit 21, a second circuit unit 22 and a current adjustment circuit unit 23 connected in sequence; the clock cycle control circuit 3 includes a ring oscillator 31 and a clock control circuit 32 connected in sequence;

[0069] The first circuit unit 21 is used to receive a first current signal;

[0070] The second circuit unit 22 and the first circuit unit 21 form a first output branch, and the first circuit unit 21 and the current trimming circuit unit 23 form a second output branch;

[0071] The first output branch is used to transmit the first current signal to the ring oscillator 31;

[0072] The second output branch is used to adjust the first current signal under the drive of the external voltage signal to generate a second current signal;

[0073] The ring oscillator 31 generates and outputs a clock frequency signal OSC_OUT under the drive of the first current signal, and transmits the clock frequency signal OSC_OUT to the clock control circuit 32;

[0074] The clock control circuit 32 generates a clock cycle signal under the drive of the clock frequency signal OSC_OUT;

[0075] Among them, the clock cycle signal includes a charging cycle signal CLK_OUT and a discharging cycle signal B_pull. The charging cycle signal CLK_OUT is used to control the second output branch to transmit the second current signal to the charging cycle of the ramp voltage generating circuit 4, and the discharging cycle signal B_pull is used to control the discharging cycle of the ramp voltage generating circuit 4.

[0076] Specifically, the first circuit unit 21 of the current control circuit 2 is connected to the bias current circuit 1 for receiving a first current signal. The second circuit unit 22 copies the first current signal of the first circuit unit 21 and outputs it to the ring oscillator 31 of the clock period control circuit 3 to provide voltage for the ring oscillator 31. The ring oscillator 31 generates a clock frequency signal OSC_OUT with a period of T, and transmits the clock frequency signal OSC_OUT to the clock control circuit 32 to drive the clock control circuit 32 to provide a charging cycle signal CLK_OUT and a discharging cycle signal B_pull for the current control circuit 2 and the ramp voltage generating circuit 4.

[0077] The charging cycle signal CLK_OUT generated by the clock control circuit 32 may also be output for use by external devices.

[0078] In a specific embodiment, Figure 4 As shown, the current trimming circuit unit 23 includes a first sub-circuit structure and a plurality of second sub-circuit structures, the first sub-circuit structure includes a first PMOS tube P1, a second PMOS tube P2 and a third PMOS tube P3, the second sub-circuit structure includes a fourth PMOS tube P4 and a fifth PMOS tube P5, wherein the drain of the fourth PMOS tube P4 in the same second sub-circuit structure is connected to the source of the fifth PMOS tube P5;

[0079] The source of the first PMOS transistor P1 and the source of each fourth PMOS transistor P4 are connected to the power supply voltage VCC, the gate of the first PMOS transistor P1 and the gate of each fourth PMOS transistor P4 are connected to the first circuit unit 21 and the second circuit unit 22, and the drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2;

[0080] The gate of each fifth PMOS tube P5 is connected to the external voltage signal I_trim, and the drain of each fifth PMOS tube P5 is connected to the drain of the second PMOS tube P2 and the source of the third PMOS tube P3;

[0081] The gate of the second PMOS tube P2 is connected to the first circuit unit 21 and the second circuit unit 22, the gate of the third PMOS tube P3 is connected to the output end of the clock control circuit 32 and the output end of the ramp voltage generating circuit 4, and the drain of the third PMOS tube P3 is connected to the input end of the ramp voltage generating circuit 4.

[0082] In a specific embodiment, Figure 5 As shown, the first circuit unit 21 includes a sixth PMOS transistor P6 and a seventh PMOS transistor P7, and the second circuit unit 22 includes an eighth PMOS transistor P8 and a ninth PMOS transistor P9;

[0083] The source of the sixth PMOS transistor P6 and the source of the eighth PMOS transistor P8 are both connected to the power supply voltage VCC;

[0084] The gate of the sixth PMOS tube P6 is connected to the drain of the sixth PMOS tube P6, the source of the seventh PMOS tube P7, the gate of the eighth PMOS tube P8, the gate of the first PMOS tube P1, and the gate of the fourth PMOS tube P4;

[0085] The gate of the seventh PMOS tube P7 is connected to the drain of the seventh PMOS tube P7, the bias current circuit 1, the gate of the ninth PMOS tube P9, and the gate of the second PMOS tube P2;

[0086] The drain of the eighth PMOS transistor P8 is connected to the source of the ninth PMOS transistor P9 , and the drain of the ninth PMOS transistor P9 is connected to the ring oscillator 31 .

[0087] Specifically, the first circuit unit 21 and the second circuit unit 22 replicate the first current signal through a current mirror formed by the sixth PMOS tube P6 and the eighth PMOS tube P8, and the replicated first current signal is transmitted to the ring oscillator 31 via the ninth PMOS tube P9 to provide an input voltage V for the ring oscillator 31. in The first circuit unit 21 and the current trimming circuit unit 23 replicate the first current signal through a current mirror composed of the sixth PMOS tube P6, the first PMOS tube P1, and the fourth PMOS tube P4. By adjusting the external voltage signal I_trim, the current output by the third PMOS tube P3 can be changed, thereby changing the charging current of the ramp voltage generating circuit 4 and changing the clock frequency output by the ring oscillator 31.

[0088] Among them, the current ratio of the fourth PMOS tube P4 and the fifth PMOS tube P5 in the same second sub-circuit structure is the same, the current ratios of different second sub-circuit structures are different, and the gate of the fifth PMOS tube P5 in different second sub-circuit structures is connected to different external voltage signals I_trim, thereby adjusting the current output by the third PMOS tube P3 of various sizes to obtain a high-precision clock signal with a wide frequency range.

[0089] For example, the current trimming circuit unit 23 includes four second sub-circuit structures, each of which is controlled by a different external voltage signal I_trim, and then The current output by the third PMOS tube P3 has different sizes.

[0090] In a specific embodiment, Figure 6 As shown, the ring oscillator 31 includes a level converter and an odd number of inverters;

[0091] The output end of each stage of the inverter is connected to the input end of the next stage of the inverter, and the output end of the last stage of the inverter is connected to the input end of the first stage of the inverter and the input end of the level converter respectively. The output end of the level converter is connected to the clock control circuit 32, wherein the power supply voltage of the inverter is the input voltage V provided by the current control circuit 2. in .

[0092] Specifically, since the input voltage V of the ring oscillator 31 in It is provided by the current control circuit 2 related to the clock, so the inverter will not be affected by the charging and discharging speed of the capacitor at the output node, thereby being able to achieve precise control of the clock frequency signal OSC_OUT.

[0093] It should be noted that Figure 6 The three inverters are only used for illustration, and the number of inverters can be set according to actual needs during the specific implementation.

[0094] In a specific embodiment, Figure 7 As shown, the ramp voltage generating circuit 4 includes a first NMOS transistor N1, a capacitor C and a ramp voltage detecting circuit 41;

[0095] The gate of the first NMOS transistor N1 is connected to the output end of the clock control circuit 32, the drain of the first NMOS transistor N1 is connected to the second output branch of the current control circuit 2, one end of the capacitor C, and the input end of the ramp voltage detection circuit 41, and the source of the first NMOS transistor N1 and the other end of the capacitor C are grounded;

[0096] An output terminal of the slope voltage detection circuit 41 is connected to the bias current circuit 1 .

[0097] Specifically, the current control circuit 2 provides a charging current to the capacitor C in the ramp voltage generating circuit 4 under the driving of the charging cycle signal CLK_OUT, and charges the capacitor C. At the same time, the ramp voltage generating circuit 4 provides a fast discharge path to the capacitor C through the first NMOS tube N1 under the driving of the discharge cycle signal B_pull, so that the capacitor C completes the charging and discharging process and generates a ramp voltage signal. The ramp voltage detection circuit 41 detects the charging voltage of the capacitor C, generates a ramp peak voltage signal, and transmits the ramp peak voltage signal to the bias current circuit 1 to form a loop. Therefore, in the circuit design stage, the clock frequency signal OSC_OUT can be changed by changing the capacitance value of the capacitor C.

[0098] In a specific embodiment, Figure 8 As shown, the bias current circuit 1 includes an amplifier A, a second NMOS tube N2 and a resistor R;

[0099] The positive input terminal of the amplifier A is connected to the output terminal of the ramp voltage generating circuit 4, the reverse input terminal of the amplifier A is connected to the source of the second NMOS tube N2 and one end of the resistor R, the output terminal of the amplifier A is connected to the gate of the second NMOS tube N2, the drain of the second NMOS tube N2 is connected to the current control circuit 2; the other end of the resistor R is grounded.

[0100] Specifically, the slope voltage generating circuit 4 detects the slope peak voltage signal V during the charge and discharge cycle. ref Input to the positive input terminal of amplifier A. According to the virtual short principle of amplifier A, , so the first current signal can be obtained Therefore, in the circuit design stage, the clock frequency signal OSC_OUT can be changed by changing the resistance value of R.

[0101] In a specific example, if Figure 9-10 As shown, the capacitor C forms a ramp voltage signal by charging and discharging, and the amplifier A detects the ramp voltage signal to obtain a ramp peak voltage signal V ref The current I1 is generated by the drive of P6, P7, P8, and P9, and the current mirror formed by P6, P7, P8, and P9 copies the current I1 and provides the input voltage V to the ring oscillator OSC. in , OSC generates a clock frequency signal OSC_OUT with a period of T, and sends it to the clock control circuit to provide P3 and N1 with a charging cycle signal CLK_OUT and a discharging cycle signal B_pull with a period of 4T.

[0102] The current mirror composed of P6, P1, P41, P42, P43, and P44 copies the current I1. Taking the number of adjustment bits n=4 as an example, assuming that the number of P41 and P51 is m=8, the number of P42 and P52 is m=4, the number of P43 and P53 is m=2, and the number of P44 and P54 is m=1, then the currents of P41, P42, P43, and P44 are 2 3 *I1,2 2 *I1,2 1 *I1,2 0 *I1, that is, the current ratio of P6 to P41 is 1:8, the current ratio of P6 to P42 is 1:4, the current ratio of P6 to P43 is 1:2, and the current ratio of P6 to P44 is 1:1. When the external voltage signal I_trim<3:0> (indicates I_trim <0> 、I_trim <1> 、I_trim <2> 、I_trim <3> When the signals corresponding to the four different voltage signals are all 0, P51, P52, P53, and P54 will be turned on, and the currents of P41, P42, P43, and P44 will be output to P3 to form current I2. P3 is turned on or off under the control of the charging cycle signal CLK_OUT. When P3 is turned on, the output current I3 charges the capacitor C.

[0103] Under the control of the discharge cycle signal B_pull, N1 provides a fast discharge path for the capacitor C, so that the capacitor C completes the charge and discharge process and generates a ramp voltage signal. Among them, the clock frequency f of the clock frequency signal OSC_OUT can be known from the capacitor charge and discharge formula: .

[0104] Therefore, the clock frequency signal OSC_OUT can be precisely controlled by adjusting the external voltage signal to adjust the current I2 output to P3, and adjusting the resistance value of the resistor R and the capacitance value of the capacitor C.

[0105] This embodiment achieves precise control of the clock frequency by modifying the power supply voltage of the ring oscillator to a voltage related to the clock, and can achieve precise control of the clock frequency by modifying the resistor and capacitor to obtain a wider clock frequency range. At the same time, the clock frequency can be further controlled by current adjustment to reduce the influence of factors such as process.

[0106] Example 2

[0107] In a specific embodiment of the present disclosure, an integrated circuit is provided. The integrated circuit includes the clock circuit described in any of the above embodiments.

[0108] This embodiment achieves precise control of the clock frequency by modifying the power supply voltage of the ring oscillator to a voltage related to the clock, and can achieve precise control of the clock frequency by modifying the resistor and capacitor to obtain a wider clock frequency range. At the same time, the clock frequency can be further controlled by current adjustment to reduce the influence of factors such as process.

[0109] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A clock circuit, characterized in that: The clock circuit includes a bias current circuit, a current control circuit, a clock cycle control circuit and a ramp voltage generating circuit; The bias current circuit, the current control circuit, the clock cycle control circuit and the ramp voltage generating circuit form a ring circuit; The bias current circuit is used to generate a first current signal and transmit it to the current control circuit under the drive of the ramp peak voltage signal; The current control circuit is used to transmit the first current signal to the clock cycle control circuit, and the current control circuit is also used to adjust the first current signal under the drive of an external voltage signal to form a second current signal; The clock cycle control circuit is used to output a clock frequency signal and a clock cycle signal under the drive of the first current signal, and control the current control circuit to transmit the second current signal to the charging and discharging cycle of the ramp voltage generating circuit according to the clock cycle signal; The slope voltage generating circuit is used to detect the slope peak voltage signal during the charge and discharge cycle, and transmit the slope peak voltage signal to the bias current circuit to form a loop.

2. The clock circuit according to claim 1, characterized in that: The current control circuit comprises a first circuit unit, a second circuit unit and a current adjustment circuit unit connected in sequence; the clock cycle control circuit comprises a ring oscillator and a clock control circuit connected in sequence; The first circuit unit is used to receive the first current signal; The second circuit unit and the first circuit unit form a first output branch, and the first circuit unit and the current trimming circuit unit form a second output branch; The first output branch is used to transmit the first current signal to the ring oscillator; The second output branch is used to adjust the first current signal under the drive of the external voltage signal to generate the second current signal; The ring oscillator generates and outputs a clock frequency signal under the drive of the first current signal, and transmits the clock frequency signal to the clock control circuit; The clock control circuit generates the clock period signal under the drive of the clock frequency signal; Among them, the clock cycle signal includes a charging cycle signal and a discharging cycle signal, the charging cycle signal is used to control the charging cycle of the second output branch to transmit the second current signal to the ramp voltage generating circuit, and the discharging cycle signal is used to control the discharging cycle of the ramp voltage generating circuit.

3. The clock circuit according to claim 2, characterized in that: The current trimming circuit unit includes a first sub-circuit structure and a plurality of second sub-circuit structures, the first sub-circuit structure includes a first PMOS tube, a second PMOS tube and a third PMOS tube, the second sub-circuit structure includes a fourth PMOS tube and a fifth PMOS tube, wherein the drain of the fourth PMOS tube in the same second sub-circuit structure is connected to the source of the fifth PMOS tube; The source of the first PMOS tube and the source of each of the fourth PMOS tubes are connected to the power supply voltage, the gate of the first PMOS tube and the gate of each of the fourth PMOS tubes are connected to the first circuit unit and the second circuit unit, and the drain of the first PMOS tube is connected to the source of the second PMOS tube; The gate of each of the fifth PMOS tubes is connected to the external voltage signal, and the drain of each of the fifth PMOS tubes is connected to the drain of the second PMOS tube and the source of the third PMOS tube; The gate of the second PMOS tube is connected to the first circuit unit and the second circuit unit, the gate of the third PMOS tube is connected to the output end of the clock control circuit and the output end of the ramp voltage generating circuit, and the drain of the third PMOS tube is connected to the input end of the ramp voltage generating circuit.

4. The clock circuit according to claim 3, characterized in that: The first circuit unit includes a sixth PMOS tube and a seventh PMOS tube, and the second circuit unit includes an eighth PMOS tube and a ninth PMOS tube; The source of the sixth PMOS tube and the source of the eighth PMOS tube are both connected to the power supply voltage; The gate of the sixth PMOS tube is connected to the drain of the sixth PMOS tube, the source of the seventh PMOS tube, the gate of the eighth PMOS tube, the gate of the first PMOS tube, and the gate of the fourth PMOS tube; The gate of the seventh PMOS tube is connected to the drain of the seventh PMOS tube, the bias current circuit, the gate of the ninth PMOS tube, and the gate of the second PMOS tube; The drain of the eighth PMOS tube is connected to the source of the ninth PMOS tube, and the drain of the ninth PMOS tube is connected to the ring oscillator.

5. The clock circuit according to claim 4, characterized in that: The current ratio of the fourth PMOS transistor and the fifth PMOS transistor in the same second sub-circuit structure is the same; The current ratios of different second sub-circuit structures are different.

6. The clock circuit according to claim 5, characterized in that: The current trimming circuit unit includes four of the second sub-circuit structures; The gates of the fifth PMOS transistors in different second sub-circuit structures are connected to different external voltage signals.

7. The clock circuit according to any one of claims 2 to 6, characterized in that: The ring oscillator comprises a level converter and an odd number of inverters; The output end of the inverter of each stage is connected to the input end of the inverter of the next stage, the output end of the inverter of the last stage is respectively connected to the input end of the inverter of the first stage and the input end of the level converter, the output end of the level converter is connected to the clock control circuit, wherein the power supply voltage of the inverter is the first current signal.

8. The clock circuit according to any one of claims 2 to 6, characterized in that: The ramp voltage generating circuit comprises a first NMOS tube, a capacitor and a ramp voltage detecting circuit; The gate of the first NMOS transistor is connected to the output end of the clock control circuit, the drain of the first NMOS transistor is connected to the second output branch of the current control circuit, one end of the capacitor, and the input end of the ramp voltage detection circuit, and the source of the first NMOS transistor and the other end of the capacitor are both grounded; The output end of the slope voltage detection circuit is connected to the bias current circuit.

9. The clock circuit according to any one of claims 1 to 6, characterized in that: The bias current circuit includes an amplifier, a second NMOS tube and a resistor; The positive input terminal of the amplifier is connected to the output terminal of the ramp voltage generating circuit, the reverse input terminal of the amplifier is connected to the source of the second NMOS tube and one end of the resistor, the output terminal of the amplifier is connected to the gate of the second NMOS tube, and the drain of the second NMOS tube is connected to the current control circuit; the other end of the resistor is grounded.

10. An integrated circuit, characterized in that: The integrated circuit comprises the clock circuit according to any one of claims 1 to 9.

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