Manufacturing method of FPC (Flexible Printed Circuit), FPC and electronic equipment

Abstract

The invention provides a manufacturing method of an FPC (Flexible Printed Circuit), the FPC and electronic equipment. The manufacturing method of the FPC comprises the steps that photoresist is arranged on the surface of a base material, exposure and development are conducted on the photoresist, and a circuit pattern is formed in the area, exposed after exposure and development, of the surface of the base material; forming a through hole in the area of the circuit pattern; forming a conductive medium layer on the surface of the circuit pattern in the substrate, the surface of the photoresist and the inner wall of the through hole; forming a metal layer on the conductive dielectric layer; and removing the photoresist and the conductive dielectric layer and the metal layer on the surface of the photoresist to obtain a metal circuit and a metal via hole of the FPC. According to the method, the fine metal circuit of the FPC can be processed and manufactured, and the area of the FPC can be compressed.

Description

Technical Field

[0001] The present application relates to the technical field of printed circuit boards, and in particular to a method for manufacturing a flexible printed circuit (FPC), an FPC and an electronic device. Background Art

[0002] Flexible circuit boards (FPCs) have the characteristics of high wiring density, light weight, thin thickness, and bendability and foldability, and have been widely used in various consumer electronic products. As the demand for integration, lightweight, and high performance of electronic products becomes higher and higher, the demand for further compression of the area of ​​FPCs is becoming more and more urgent, that is, the requirements for the design of line structure such as line width / line spacing are getting higher and higher. However, the existing FPC or FPC manufacturing method has complex procedures and low precision, and it is difficult to meet the above requirements.

[0003] Therefore, how to realize the processing and manufacturing of fine metal circuits of FPC is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present application provides a method for manufacturing an FPC, an FPC and an electronic device, which can realize the processing and manufacturing of fine metal circuits of the FPC, and is conducive to compressing the area of ​​the FPC.

[0005] In a first aspect, a method for manufacturing an FPC is provided, comprising: disposing a photoresist on a surface of a substrate, exposing and developing the photoresist, and forming a circuit pattern in the exposed surface area of ​​the substrate after the exposure and development; forming a through hole in the area of ​​the circuit pattern; forming a conductive dielectric layer on the surface of the circuit pattern in the substrate, the surface of the photoresist, and the inner wall of the through hole; forming a metal layer on the conductive dielectric layer; removing the photoresist, and the conductive dielectric layer and the metal layer on the surface of the photoresist to obtain a metal circuit and a metal via of the FPC.

[0006] Through the above implementation, a circuit pattern can be formed on the surface of the substrate using a photoresist, and based on the circuit pattern, a metal circuit and a metal via can be directly formed on the surface of the substrate to realize a manufacturing process of integrated wire and hole. The technical solution provided in the embodiment of the present application can solve the problem of low circuit precision caused by the traditional etching method, which is conducive to the processing and manufacturing of FPC fine circuits (that is, it is conducive to compressing the line width / line spacing, hole diameter, etc.), thereby facilitating further compression of the area of ​​the FPC. In addition, in the above implementation, the manufacturing process of integrated wire and hole can also reduce the process complexity of the FPC and improve production efficiency.

[0007] In combination with the first aspect, in certain implementations of the first aspect, a photoresist is disposed on a surface of a substrate, the photoresist is exposed and developed, and a circuit pattern is formed in the surface area of ​​the substrate exposed after the exposure and development, including: a photoresist is disposed on two opposite surfaces of the substrate, the photoresist is exposed and developed, and two circuit patterns are formed in the surface areas of the substrate exposed after the exposure and development; a through hole is formed in the area of ​​the circuit pattern, including: a through hole is formed in the substrate, and the through hole passes through the area where the two circuit patterns are located.

[0008] Circuit patterns can be formed on both surfaces of the substrate, and the circuit patterns on the two surfaces can at least partially overlap, and through holes can be set in the overlapping area to connect the areas of the two circuit patterns. Through the above implementation, a double-layer FPC with a fine circuit structure and double-sided metal circuits and metal vias can be manufactured, wherein the metal vias can play an electrical connection role and connect the metal traces on different surfaces.

[0009] In combination with the first aspect, in certain implementations of the first aspect, the method further includes: forming at least one groove in the area of ​​the circuit pattern; forming a conductive dielectric layer in at least one groove; and forming a metal layer on the conductive dielectric layer in at least one groove.

[0010] Through the above implementation, the contact area between the substrate and the conductive medium layer can be increased, the bonding force between the substrate and the conductive medium layer can be improved, and the stability of the bonding between the substrate and the metal layer, or the metal circuit, can be improved, and the bending resistance of the FPC can be improved.

[0011] In combination with the first aspect, in certain implementations of the first aspect, a total cross-sectional area of ​​the at least one groove on the surface of the substrate is 10% to 30% of the area of ​​the circuit pattern.

[0012] In combination with the first aspect, in certain implementations of the first aspect, a plurality of grooves are formed in the circuit pattern region of the substrate, and the plurality of grooves are evenly distributed in the circuit pattern region.

[0013] Multiple grooves evenly distributed in the area of ​​the circuit pattern are conducive to uniform and stable combination of the substrate and the metal circuit, and can improve the bending resistance of the FPC.

[0014] In combination with the first aspect, in certain implementations of the first aspect, the cross-sectional shape of the groove on the surface of the substrate is a circle with a diameter of 1 um to 10 um, and / or the depth of the groove is 1 um to 8 um.

[0015] In combination with the first aspect, in some implementations of the first aspect, a diameter of the metal via is less than or equal to 0.10 mm.

[0016] In combination with the first aspect, in certain implementations of the first aspect, a minimum value of a line width and / or a line spacing of the metal line is less than 50 um.

[0017] The FPC with the above-mentioned fine metal circuit can compress the FPC area by about 25% to 55% when the circuit structure design is the same; when the FPC area is the same, it can accommodate more circuit structure designs and provide better performance support for electronic equipment.

[0018] In combination with the first aspect, in some implementations of the first aspect, forming a through hole in the area of ​​the circuit pattern includes: forming the through hole in the area of ​​the circuit pattern by a laser process.

[0019] The laser process has the advantages of high efficiency, precision, flexibility and environmental protection. Through the laser process, higher precision and smaller through-holes can be formed on the substrate, thereby supporting the compression of the FPC area.

[0020] In combination with the first aspect, in certain implementations of the first aspect, a conductive dielectric layer is formed on the surface of the circuit pattern in the substrate, the surface of the photoresist, and the inner wall of the through hole, including: forming a conductive dielectric layer on the surface of the circuit pattern in the substrate, the surface of the photoresist, and the inner wall of the through hole through an ion implantation process, wherein the material of the conductive dielectric layer includes a metal alloy.

[0021] The ion implantation process can form a doping structure at the contact portion between the substrate and the conductive medium layer. The doping structure has reliable and stable bonding performance, which can further improve the bonding stability between the substrate and the metal circuit, thereby improving the bending resistance of the FPC.

[0022] In a second aspect, an FPC is provided, comprising: a substrate provided with through holes; a conductive medium layer provided on the surface of the substrate and in the through holes; a metal layer correspondingly attached to the conductive medium layer to form metal circuits and metal vias; wherein the diameter of the metal vias is less than or equal to 0.10 mm, and / or the minimum value of the line width and / or line spacing of the metal circuit is less than 50 um.

[0023] The FPC with the above-mentioned fine metal circuit can reduce the area of ​​the FPC by about 25% to 55% under the same circuit structure design; or, under the same area, it can accommodate more circuit structure designs and provide better performance support for electronic equipment.

[0024] In combination with the second aspect, in certain implementations of the second aspect, the metal layer and the conductive medium layer are disposed on two opposite surfaces of the substrate to form metal circuits on the two surfaces, and the metal vias are connected to the metal circuits located on the two surfaces.

[0025] In the above-mentioned double-layer FPC with a fine circuit structure, the metal vias can play an electrical connection role to connect the metal traces located on different surfaces.

[0026] In combination with the second aspect, in certain implementations of the second aspect, at least one groove is further provided on the substrate, the at least one groove accommodates the conductive medium layer and the metal layer, and the at least one groove is provided corresponding to the metal circuit.

[0027] In conjunction with the second aspect, in certain implementations of the second aspect, a total cross-sectional area of ​​the at least one groove on the surface of the substrate is 10% to 30% of the area of ​​the metal line.

[0028] In combination with the second aspect, in some implementations of the second aspect, a plurality of grooves are provided on the substrate, and the plurality of grooves are evenly distributed in the area corresponding to the metal circuit in the substrate.

[0029] In combination with the second aspect, in certain implementations of the second aspect, the cross-sectional shape of the groove on the surface of the substrate is a circle with a diameter of 1 um to 10 um, and / or the depth of the groove is 1 um to 8 um.

[0030] In a third aspect, an electronic device is provided, comprising the FPC as in the second aspect or the implementations of the second aspect, or the FPC prepared by the method as in the first aspect or the implementations of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the forming process of the FPC local circuit provided in the embodiment of the present application.

[0032] Figure 2 It is a flow chart of the method for manufacturing an FPC provided in an embodiment of the present application.

[0033] Figure 3 It is a schematic top view of a local circuit of an FPC provided in an embodiment of the present application.

[0034] Figure 4 It is a schematic diagram of the process of manufacturing the FPC provided in an embodiment of the present application.

[0035] Figure 5 It is a schematic diagram of the process of manufacturing the FPC provided in an embodiment of the present application.

[0036] Figure 6 It is a schematic diagram of the process of manufacturing the FPC provided in an embodiment of the present application.

[0037] Figure 7 It is a flow chart of another method for manufacturing an FPC provided in an embodiment of the present application.

[0038] Figure 8 It is a top view schematic diagram of a local circuit of another FPC provided in an embodiment of the present application.

[0039] Fig. 9 yes Figure 8 Schematic diagram of the cross-section of the FPC local line in the BB′ direction.

[0040] Fig.10 yes Fig. 9 A schematic enlarged view of region C in the middle.

[0041] Fig.11 It is a schematic diagram of the process of another FPC manufacturing method provided in an embodiment of the present application.

[0042] Fig.12 It is a schematic diagram of the process of another FPC manufacturing method provided in an embodiment of the present application.

[0043] Fig.13 It is a cross-sectional schematic diagram of a local circuit of an FPC provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0045] In the description of this application, it should be noted that the terms "first", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0046] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly stipulated and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0047] The directional terms mentioned in the embodiments of the present application, such as "up", "down", "left", "right", "inside", "outside", etc., are only referenced to the directions of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application. In addition, unless otherwise specified in the present application, the "multiple" described in the present application refers to two or more. "Vertical" is not vertical in the strict sense, but is within the allowable error range. "Parallel" is not parallel in the strict sense, but is within the allowable error range.

[0048] In the description of the embodiments of the present application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0049] In the embodiments of the present application, "and / or" is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0050] The present application relates to an FPC and a method for manufacturing the same. The FPC can be applied to electronic devices that have high requirements for space utilization or bending performance, including mobile phones, tablet computers, tablet computer accessories, wearable devices, vehicle-mounted devices, augmented reality (AR) / virtual reality (VR) devices, laptop computers, ultra-mobile personal computers (UMPC), netbooks, personal digital assistants (PDA) and other mobile terminals, or professional shooting equipment such as digital cameras, SLR cameras / micro-single cameras, sports cameras, gimbal cameras, drones, etc.

[0051] As electronic devices continue to become thinner, smaller, foldable, and curled, the contradiction between the FPC area and the space of the device host has become increasingly prominent, and the demand for further compression of the FPC area has also continued to increase. It is understandable that by arranging more circuit designs within the unit area of ​​the FPC, that is, by compressing the FPC line width / line spacing, via diameter and other line design dimensions to increase its wiring density, the FPC area can be compressed. Among them, vias refer to metal holes on FPCs. However, the line width / line spacing dimensions of existing mass-produced FPCs are usually above 50um / 50um, making it difficult to compress the FPC area; the process technology that can achieve a line width / line spacing less than 50um / 50um usually has a poor process capability index CPK, which can also be called a process capability index, which refers to an indicator that enables the product to reach an acceptable level during mass production. Generally speaking, the smaller or worse the CPK, the lower the yield. Therefore, the existing process technology that can achieve line width / line spacing less than 50um / 50um has a low yield, the process capability cannot meet the product technical requirements, and cannot be put into mass production in actual applications.

[0052] In some possible FPC processes, flexible copper clad laminate (FCCL) is usually selected as the substrate, and circuits are formed through processes such as drilling, black holes or black shadows, copper plating, and photolithography. The photolithography process specifically includes processes such as coating, exposure, development, and etching. Figure 1 A schematic diagram of a forming process of a local circuit of an FPC provided in an embodiment of the present application, wherein the circuit of the FPC is formed through the above-mentioned process.

[0053] like Figure 1 As shown in (a), the FCCL substrate 1 used in the FPC is a multi-layer structure, which may include an insulating base film layer 11, an adhesive layer 12 and a copper foil layer 13. The material of the insulating base film layer 11 may be polyimide (PI) or polyester such as polyethylene terephthalate (PET).

[0054] The photoresist 2 is coated on the copper foil layer 13. After exposure and development, the photoresist 2 is left in the circuit area, and the copper foil in other areas is directly exposed.

[0055] like Figure 1As shown in (b), the etching process can remove the copper foil directly exposed in the copper foil layer 13 to obtain the circuit 131. However, the etching process has an unavoidable side corrosion problem, that is, the side wall of the copper circuit 131 is corroded, resulting in inconsistent cross-sectional width, and the cross-section is roughly trapezoidal or other shapes. Side corrosion will seriously affect the circuit accuracy, making it difficult to realize the processing and manufacturing of FPC fine circuits, and it is difficult to reduce the circuit dimensions such as line width / line spacing. In addition, the presence of the adhesive layer 12 and the copper foil layer 13 makes it difficult to compress the thickness of the FCCL substrate 1, which has an adverse effect on the accuracy of the drilling process, resulting in the metal via size of the FPC being difficult to reduce.

[0056] Based on the above factors, in some related technologies, the line width / line spacing of mass-produced FPC is usually above 50um / 50um, and the diameter of metal vias and their hole rings is usually 0.2mm / 0.25mm and above. The difficulty in compressing the line structure size makes it difficult to reduce the FPC area or increase the wiring density, which makes it difficult to meet the development requirements of lightweight and high-performance electronic equipment.

[0057] In addition, in the traditional FPC manufacturing process, the FPC circuit forming accuracy is low, the hole metallization method such as black hole or black shadow has high production cost and low efficiency. The metallization operation of the through hole and the forming of other circuit structures are usually completed in different processes, and the manufacturing process of FPC is relatively complicated.

[0058] The present application embodiment provides a method for manufacturing an FPC, such as Figure 2 As shown, the method may include the following steps:

[0059] 201, a photoresist is disposed on the surface of a substrate, and the photoresist is exposed and developed, and a circuit pattern is formed in the exposed surface area of ​​the substrate after the exposure and development.

[0060] 202, forming a through hole in the area of ​​the circuit pattern.

[0061] 203, forming a conductive dielectric layer on the surface of the circuit pattern in the substrate, the surface of the photoresist, and the inner wall of the through hole.

[0062] 204 , forming a metal layer on the conductive dielectric layer.

[0063] 205 , removing the photoresist, and the conductive dielectric layer and the metal layer on the surface of the photoresist to obtain the metal circuits and metal vias of the FPC.

[0064] The substrate material used in the FPC manufacturing method provided in the embodiment of the present application can be PI. In practical applications, other suitable substrate materials such as PET can also be selected according to FPC requirements.

[0065] Through the above-mentioned implementation, a circuit pattern can be formed on the surface of the substrate using a photoresist, and based on the circuit pattern, a metal circuit and a metal via can be directly formed on the surface of the substrate to realize a manufacturing process of line hole integration. The technical solution provided in the embodiment of the present application can solve the problem of low circuit precision caused by the traditional etching method, which is conducive to the processing and manufacturing of the fine circuit of the FPC (that is, it is conducive to compressing the line width / line spacing, hole diameter, etc.), thereby facilitating further compression of the area of ​​the FPC. In addition, through the above-mentioned implementation, the hole metallization operation of the through hole of the FPC and the forming of the surface circuit structure can be completed at the same time, that is, the metal circuit and the metal via of the FPC can be formed in an integrated manner, which can reduce the process complexity of the FPC and improve production efficiency. Furthermore, the presence of the conductive medium layer on the surface of the circuit pattern and the inner wall of the through hole can increase the bonding force between the substrate and the metal layer, that is, increase the bonding force between the substrate and the metal circuit, thereby improving the bending resistance of the FPC.

[0066] Through the FPC manufacturing method provided in the embodiment of the present application, it is possible to manufacture a single-layer FPC, a double-layer FPC, a single-layer soft board FPC, an outer layer circuit of a multi-layer soft board FPC, a single-layer soft and hard board FPC, or an outer layer circuit of a multi-layer soft and hard board FPC, etc. For example, a double-layer FPC with a fine circuit structure and double-sided metal circuits and metal vias formed in an integrated manner can be obtained by this method, wherein the metal vias can play an electrical connection role and conduct metal traces located on different surfaces.

[0067] Figure 3 FIG. 1 shows a schematic top view of a local circuit of an FPC provided in an embodiment of the present application. Optionally, the FPC may be Figure 2 The embodiment described in is manufactured.

[0068] like Figure 3 As shown, the FPC includes: a substrate, provided with through holes; a conductive medium layer, provided on the surface of the substrate and in the through holes; and a metal layer, correspondingly attached to the conductive medium layer to form metal circuits and metal vias. The metal circuit size and metal via size of the FPC can meet at least one of the following requirements: (1) the minimum value of the line width d8 of the metal circuit 51 is less than 50um; (2) the minimum value of the line spacing d9 of the metal circuit 51 is less than 50um; (3) the diameter d2 of the metal via 52 is less than or equal to 0.10mm.

[0069] For example, the minimum value of the line width d8 of the metal line 51 is less than or equal to 35 um, and / or the minimum value of the line spacing d9 of the metal line 51 is less than or equal to 35 um.

[0070] For another example, the minimum value of the line width d8 of the metal line 51 is less than or equal to 30 um, and / or the minimum value of the line spacing d9 of the metal line 51 is less than or equal to 30 um. Optionally, the diameter d2 of the metal via 52 may be between 0.03 mm and 0.10 mm.

[0071] In addition to metal routing, the metal circuit of the FPC may also include an annular ring of the metal via 52. The diameter d3 of the annular ring is related to the diameter d2 of the metal via 52. For example, the diameter d3 of the annular ring may be between 2 times d2 and 3 times d2.

[0072] Through the technical solution of the embodiment of the present application, it is possible to manufacture an FPC with a line width / line spacing of less than 50um / 50um and a hole diameter of less than or equal to 0.1mm through integrated molding. Furthermore, the solution can manufacture an FPC with a minimum line width / line spacing of 20um / 20um and a minimum hole diameter of 0.05mm. Compared with the FPC with a line width / line spacing greater than 50um / 50um and a hole diameter greater than 0.2mm in traditional technology, the line width, line spacing and hole diameter of the FPC provided in the embodiment of the present application are effectively compressed, and therefore, the FPC area can also be further compressed.

[0073] Under the same circuit structure design, the area of ​​the FPC with fine metal circuits provided in the embodiment of the present application is approximately Figure 1 In other words, under the same area, the FPC with fine metal circuits provided in the embodiment of the present application can accommodate more circuit structure designs. Therefore, the FPC with fine metal circuits provided in the embodiment of the present application can support the requirements of lightweight and high performance of electronic equipment.

[0074] In some embodiments, in addition to the above structure, the FPC may also include a covering layer or a protective layer. The covering layer may cover the metal circuit on the surface of the substrate to prevent the metal circuit from being oxidized and protect the metal circuit, thereby improving the electrical performance and service life of the FPC. As an example but not a limitation, the covering layer may be composed of an organic chemical plastic film and an adhesive. The covering layer material includes polyester resin, polyurethane, etc.

[0075] Optionally, in actual application, FPC may be provided with other related materials such as reinforcing sheets according to requirements, and the embodiment of the present application does not limit the specific structure thereof.

[0076] Figures 4 to 6 This is a schematic diagram of the process of the FPC manufacturing method provided in the embodiment of the present application. Figure 4 and Figure 5 . Figure 4 This is a schematic top view of a local circuit of the FPC provided by the present application after step 201 and step 202. Figure 5 For FPC local circuit Figure 4 Schematic diagram of the cross section along the AA′ direction.

[0077] Photoresist 2, also known as photoresist, is coated on a substrate 3. After exposure and development, a circuit pattern 31 is formed on the surface of the substrate 3. The circuit pattern 31 is not covered in the area, and the other areas are covered.

[0078] Optionally, step 201 may include providing photoresist 2 on two opposite surfaces of substrate 3, exposing and developing photoresist 2, and forming two circuit patterns 31 in the two substrate surface areas exposed after exposure and development. That is, the photoresist 2 may be coated on the upper and lower surfaces of substrate 3, so that circuit patterns 31 are formed on both surfaces of substrate 3, and the areas of circuit patterns 31 on the two surfaces may at least partially overlap, and the through holes 32 in subsequent steps may be provided in the overlapping areas.

[0079] In some embodiments, the coating thickness d4 of the photoresist 2 may be 6 um to 30 um.

[0080] In the embodiment of the present application, the substrate of the FPC is a single-layer structure. For example, the thickness d1 of the substrate 3 can be 8um to 50um. Compared with the multi-layer FCCL, the processing difficulty of drilling the through hole 32 in the area of ​​the circuit pattern 31 on the thinner single-layer substrate 3 is reduced, and the precision is improved, so that a through hole with a smaller diameter can be obtained, thereby realizing the fine metal circuit design of the FPC.

[0081] Optionally, step 202 may include forming a through hole 32 in the substrate 3 , wherein the through hole 32 passes through the areas where the two circuit patterns 31 are located.

[0082] The through hole 32 can be arranged in the overlapping area of ​​the circuit patterns 31 on the two surfaces of the substrate 3. In the subsequent steps, the through hole 32 forms a metal via to connect the metal circuits on the two surfaces of the substrate 3.

[0083] Optionally, step 202 may include forming a through hole in a region of the circuit pattern of the substrate by a laser process.

[0084] Laser drilling has the advantages of being efficient, precise, flexible, and environmentally friendly. Through the laser process, a through hole 32 with higher precision and smaller size can be formed on the substrate 3, which is beneficial to improving the overall process accuracy of the FPC.

[0085] refer to Figure 6 , Figure 6 for Figure 5Schematic diagram after steps 203 and 204. In step 203, a conductive dielectric layer 4 is formed on the substrate 3 having the circuit pattern and the through hole. For the area of ​​the circuit pattern and the inner wall of the through hole, the conductive dielectric layer 4 can directly contact the substrate 3 and play a transition role between the substrate 3 and the metal layer 5 formed in the subsequent steps, which can further improve the bonding force between the substrate 3 and the metal layer 5, thereby improving the bending resistance of the FPC. For the area covered by the photoresist 2, the conductive dielectric layer 4 is formed on the photoresist 2.

[0086] Optionally, step 203 may include forming a conductive dielectric layer on the surface of the circuit pattern in the substrate, the surface of the photoresist and the inner wall of the through hole by an ion implantation process. The material of the conductive dielectric layer may be a metal alloy, such as a copper-nickel alloy.

[0087] Through the ion implantation process, the implanted conductive ions can directly combine with the atoms or molecules on the surface of the substrate 3 to form a doping structure. The doping structure has reliable and stable bonding performance, which can further improve the bonding force between the substrate 3 and the metal layer 5, thereby improving the bending resistance of the FPC.

[0088] In step 204, a metal layer 5 is formed on the surface of the circuit pattern of the substrate 3 and the conductive medium layer 4 in the inner wall of the through hole 5. In other areas covered by the photoresist 2, the metal layer 5 is formed on the conductive medium layer 4 on the photoresist 2. The material of the metal layer 5 can be copper or other metals with good conductivity, and the formation method thereof can be, for example, electroplating.

[0089] In step 205, the photoresist is removed, that is, the photoresist on the substrate is removed using a degumming agent, etc. Accordingly, the conductive dielectric layer and the metal layer attached to the photoresist are removed together with the photoresist, and the remaining conductive dielectric layer and the metal layer on the surface of the substrate can form the metal circuit of the FPC, and the conductive dielectric layer and the metal layer on the inner wall of the through hole can form the metal via of the FPC, thereby obtaining the metal circuit and the metal via of the FPC. Among them, the metal circuit may include a routing, a pad, and an annular ring (hole disk) of the metal via, etc.

[0090] The debonding agents that can be used include alkaline debonding agents such as sodium hydroxide solution and potassium hydroxide solution, acidic debonding agents such as sulfuric acid of a certain concentration, solvent-based debonding agents such as dimethyl sulfoxide (DMSO) and N-ethylpyrrolidone (1-ethyl-2-pyrrolidone, NEP) solvent, etc.

[0091] Through the above implementation, the metal circuits and metal vias of the FPC can be formed in one piece, which reduces the complexity of the manufacturing process of the FPC and improves its production efficiency.

[0092] In some embodiments, when the conductive dielectric layer 4 is formed by an ion implantation process, the material of the conductive dielectric layer 4 may include a conductive material, such as an alloy, a conductive carbide, a conductive organic matter, etc. Optionally, when the material of the metal layer 5 is copper, the conductive dielectric layer 4 may use an alloy material with a strong bonding force with the substrate and copper, such as a copper-nickel alloy, a copper-zirconium alloy, a copper-titanium alloy, a copper-chromium alloy, etc. The conductive dielectric layer 4 can play a transitional role between the substrate 3 and the copper metal layer 5, so that the bonding force between the substrate and the copper plating is stronger, and the bending resistance of the FPC is further improved.

[0093] In some embodiments, Figure 6 As shown, the thickness d5 of the conductive medium layer 4 can be 100nm to 5um; the thickness of the metal layer 5 located on the surface of the substrate 3, or the thickness d6 of the metal line 51 can be 6um to 30um; the thickness of the metal layer 5 located on the inner wall of the through hole, or the thickness d7 of the inner wall of the metal via 52 can be 8um to 12um.

[0094] Optionally, the thickness d4 of the photoresist 2 and the thickness d6 of the metal line 51 may be the same.

[0095] In some embodiments, the manufacturing process of the FPC also includes pre-processing and post-processing. For example, before performing step 201, it may also include processes such as selecting and cutting the substrate according to design requirements. For another example, after performing step 205, it may also include processes such as cleaning and strengthening. The cleaning process refers to cleaning the formed FPC with deionized water, which can remove residual ionic impurities and contaminants on the FPC. The strengthening process refers to adding a covering layer and / or pressing a reinforcing sheet on the FPC. The material and function of the covering layer or the reinforcing sheet can refer to the relevant content mentioned above and will not be repeated here.

[0096] Figure 7 A schematic flowchart of another method for manufacturing an FPC provided in an embodiment of the present application is shown.

[0097] like Figure 7 As shown, the manufacturing method provided in the embodiment of the present application includes the following steps.

[0098] 701, a photoresist is disposed on the surface of a substrate, and the photoresist is exposed and developed, and a circuit pattern is formed in the exposed surface area of ​​the substrate after the exposure and development.

[0099] 702, forming a through hole and at least one groove in an area of ​​the circuit pattern.

[0100] 703, forming a conductive dielectric layer on the surface of the circuit pattern in the substrate, the surface of the photoresist, the inner wall of the through hole and at least one groove.

[0101] 704 , forming a metal layer on the conductive dielectric layer.

[0102] 705 , removing the photoresist, and the conductive dielectric layer and the metal layer on the surface of the photoresist to obtain the metal circuits and metal vias of the FPC.

[0103] In an embodiment of the present application, in addition to forming a through hole, at least one groove may be formed in the circuit pattern on the surface of the substrate. Furthermore, in the subsequent process of forming a conductive dielectric layer and a metal layer, a conductive dielectric layer and a metal layer may be simultaneously formed in the at least one groove.

[0104] The presence of the groove can increase the contact area between the substrate and the metal circuit in the FPC, thereby improving the bonding force between the substrate and the metal circuit and the bonding stability between the substrate and the metal circuit, and improving the bending resistance of the FPC.

[0105] Alternatively, in some embodiments, the groove may be formed by a laser process.

[0106] Optionally, in some embodiments, the number of the above-mentioned grooves can be multiple, and the size of each groove can be set smaller, and the multiple grooves can be evenly or unevenly distributed in the area of ​​the circuit pattern on the surface of the substrate, so that the multiple grooves can have a better embedding effect on the metal circuit, further improving the bending resistance of the FPC.

[0107] Figure 8 FIG. 7 is a top view of a local circuit of an FPC after the above step 701 . Fig. 9 for Figure 8 Schematic diagram of the cross-section of the local line of the FPC in the BB′ direction.

[0108] Alternatively, if Figure 8 As shown, the total cross-sectional area of ​​the plurality of grooves 33 on the substrate surface is 10% to 30% of the area of ​​the circuit pattern. Alternatively, in some alternative embodiments, the number of grooves 33 can also be set to one, and the total cross-sectional area of ​​the one groove on the substrate surface can also satisfy the above-mentioned proportional relationship.

[0109] Alternatively, if Figure 8 As shown, the plurality of grooves 33 may be randomly distributed in the area of ​​the circuit pattern 31 of the substrate, or the plurality of grooves 33 may be evenly distributed in the area of ​​the circuit pattern 31 .

[0110] When the plurality of grooves 33 are evenly distributed, the bonding force between the substrate and the conductive medium layer 4 is also more even. Furthermore, the bonding force between the substrate and the subsequently formed metal layer is also more even, and the bending resistance of the FPC can be further improved.

[0111] Alternatively, if Figure 8As shown, the cross-sectional shape of the groove on the surface of the substrate may be a circle with a diameter of 1 um to 10 um, and / or the depth of the groove may be 1 um to 8 um.

[0112] It should be noted that the cross-sectional shape of the above groove is not limited to it. According to actual needs, the cross-sectional shape of the groove can also be square, track-shaped, elliptical or any other possible shape, or one or more of the above shapes. When the cross-sectional shape of the groove is circular, the processing difficulty of the groove will be correspondingly lower than that of other shapes.

[0113] As an example, Fig.10 for Fig. 9 A schematic enlarged view of the C region in FIG. Fig. 9 As shown, the cross-sectional shape of the groove 33 on a plane perpendicular to the surface of the substrate 3 may be a trapezoid.

[0114] For example, the shorter upper bottom of the trapezoidal cross section may face the substrate 3, while the longer lower bottom of the trapezoidal cross section may face away from the substrate 3. In this case, compared with the groove with a rectangular cross section, the side wall area of ​​the groove 33 with the trapezoidal cross section is increased, and the contact area between the substrate 3 and the conductive medium layer 4 is increased, which can further enhance the bonding force between the two, thereby enhancing the bonding stability between the substrate 3 and the metal circuit 51, and improving the bending resistance of the FPC.

[0115] Alternatively, the shorter upper base of the trapezoidal cross section may be away from the substrate 3, and the longer lower base of the trapezoidal cross section may be toward the substrate 3. In this case, the groove 33 can form a more stable interlocking structure, thereby further enhancing the stability of the combination between the substrate 3 and the metal circuit 51, so as to improve the bending resistance of the FPC.

[0116] The embodiment of the present application does not limit the cross-sectional shape of the groove 33 on the plane perpendicular to the surface of the substrate 3. In practical applications, the cross-sectional shape can be any regular or irregular shape. In addition, the shapes and sizes of the multiple grooves 33 can be the same, or the shapes and sizes of the multiple grooves 33 can be different.

[0117] Fig.11 and Fig.12 They are Fig. 9 Schematic diagram of the FPC local line after the above steps 703 and 704. Fig.11 As shown, in step 703, the surface of the circuit pattern of the substrate 3, the inner wall of the through hole 32 and at least one groove 33 are all covered by the conductive dielectric layer 4. For the portion of the substrate 3 surface covered by the photoresist 2, the conductive dielectric layer 4 is formed on the photoresist 2.

[0118] like Fig.12As shown, in step 704, at least one groove 33 is filled with the metal layer 5 and can be flush with the metal layer 5 in the area of ​​the circuit pattern on the surface of the substrate 3. For the portion of the surface of the substrate 3 covered by the photoresist 2, the metal layer 5 is formed on the conductive medium layer 4 on the photoresist 2 and can be removed together with the photoresist 2 in step 705.

[0119] Fig.13 for Fig.12 A cross-sectional diagram of the FPC local circuit after undergoing the above step 705.

[0120] like Fig.13 As shown, after removing the photoresist and the conductive dielectric layer 4 and metal layer 5 on the surface, the remaining conductive dielectric layer 4 and metal layer 5 on the substrate together form the metal circuit 51 and metal via 52 of the FPC. Optionally, the metal layer 5 and the conductive dielectric layer 4 are arranged on two opposite surfaces of the substrate 3 to form the metal circuit 51 on the two surfaces, and the metal via 52 is connected to the metal circuit 51 located on the two surfaces.

[0121] Optionally, the FPC provided in the embodiment of the present application is further provided with at least one groove 33 on the substrate 3 , the at least one groove 33 accommodates the conductive medium layer 4 and the metal layer 5 , and the at least one groove is provided corresponding to the metal circuit 51 .

[0122] Through the above implementation, the contact area between the substrate 3 and the conductive medium layer 4 of the FPC provided in the embodiment of the present application is increased, which can improve the bonding force between the two, thereby improving the bonding stability between the substrate 3 and the metal circuit, and improving the bending resistance of the FPC.

[0123] The relevant parameter settings of the size, distribution, depth, cross-sectional shape and other related parameters of the grooves 33 can refer to the relevant settings described above, and for the sake of brevity, they will not be repeated here.

[0124] An embodiment of the present application further provides an electronic device, which may include the FPC in any of the above embodiments, or include the FPC prepared by the method in any of the above embodiments.

[0125] The electronic device may include but is not limited to the electronic device types mentioned above, which will not be described here for the sake of brevity.

[0126] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for manufacturing an FPC, characterized in that: include: Disposing a photoresist on the surface of the substrate, exposing and developing the photoresist, and forming a circuit pattern in the exposed surface area of ​​the substrate after the exposure and development; forming a through hole in the area of ​​the circuit pattern; forming a conductive dielectric layer on the surface of the circuit pattern in the substrate, the surface of the photoresist, and the inner wall of the through hole; forming a metal layer on the conductive dielectric layer; The photoresist, as well as the conductive medium layer and the metal layer on the surface of the photoresist are removed to obtain the metal lines and metal vias of the FPC.

2. The method according to claim 1, characterized in that: The method of disposing a photoresist on the surface of the substrate, exposing and developing the photoresist, and forming a circuit pattern in the exposed surface area of ​​the substrate after the exposure and development, comprises: The photoresist is disposed on two opposite surfaces of the substrate, and the photoresist is exposed and developed, so that the two exposed surface areas of the substrate after exposure and development form two circuit patterns; The forming of a through hole in the area of ​​the circuit pattern comprises: The through hole is formed in the substrate, and the through hole passes through the areas where the two circuit patterns are located.

3. The method according to claim 1 or 2, characterized in that: The method further comprises: forming at least one groove in the area of ​​the circuit pattern; forming the conductive dielectric layer in the at least one groove; The metal layer is formed on the conductive dielectric layer within the at least one groove.

4. The method according to claim 3, characterized in that The total cross-sectional area of ​​the at least one groove on the surface of the substrate is 10% to 30% of the area of ​​the circuit pattern.

5. The method according to claim 3, characterized in that: A plurality of the grooves are formed in the region of the circuit pattern, and the plurality of the grooves are evenly distributed in the region of the circuit pattern.

6. The method according to claim 3, characterized in that The cross-sectional shape of the groove on the surface of the substrate is a circle with a diameter of 1 um to 10 um, and / or the depth of the groove is 1 um to 8 um.

7. The method according to claim 1 or 2, characterized in that: The diameter of the metal via is less than or equal to 0.10 mm, and / or the minimum value of the line width and / or line spacing of the metal circuit is less than 50 um.

8. The method according to claim 1 or 2, characterized in that: Forming a through hole in the area of ​​the circuit pattern, comprising: The through hole is formed in the area of ​​the circuit pattern by a laser process.

9. The method according to claim 1 or 2, characterized in that: A conductive dielectric layer is formed on the surface of the circuit pattern in the substrate, the surface of the photoresist, and the inner wall of the through hole, including: The conductive medium layer is formed on the surface of the circuit pattern in the substrate, the surface of the photoresist and the inner wall of the through hole by an ion implantation process, and the material of the conductive medium layer includes a metal alloy.

10. An FPC, characterized in that: include: A substrate having a through hole; A conductive medium layer is disposed on the surface of the substrate and in the through hole; A metal layer, correspondingly attached to the conductive medium layer to form a metal circuit and a metal via; Wherein, the diameter of the metal via is less than or equal to 0.10 mm, and / or the minimum value of the line width and / or line spacing of the metal circuit is less than 50 um.

11. The FPC according to claim 10, characterized in that: The metal layer and the conductive medium layer are arranged on two opposite surfaces of the substrate to form the metal circuits on the two surfaces, and the metal vias are connected to the metal circuits on the two surfaces.

12. The FPC according to claim 10 or 11, characterized in that: At least one groove is also arranged on the substrate, and the at least one groove accommodates the conductive medium layer and the metal layer, and the at least one groove is arranged corresponding to the metal circuit.

13. The FPC according to claim 12, characterized in that: The total cross-sectional area of ​​the at least one groove on the surface of the substrate is 10% to 30% of the area of ​​the metal circuit; and / or, a plurality of the grooves are arranged on the substrate, and the plurality of the grooves are evenly distributed in the area corresponding to the metal circuit in the substrate.

14. The FPC according to claim 12, characterized in that: The cross-sectional shape of the groove on the surface of the substrate is a circle with a diameter of 1 um to 10 um, and / or the depth of the groove is 1 um to 8 um.

15. An electronic device, characterized in that: The invention comprises the FPC according to any one of claims 10 to 14, or the FPC prepared by the method according to any one of claims 1 to 9.

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