Structural support layer for protecting selective transfer layer during laser exposure of unbonded wafers

Abstract

Structural support layers for protecting selective transfer layers during laser exposure of unbonded wafers are disclosed herein. An embodiment discloses a method comprising: receiving a substrate, the substrate comprising a first layer, a second layer over the first layer, the second layer comprising at least one integrated circuit (IC) component, and a third layer over the second layer, the third layer comprising at least one dielectric material; and weakening the first layer using a laser, thereby promoting separation of the second layer from the substrate.

Description

Background Art

[0001] In semiconductor manufacturing, a layer is typically transferred from one substrate to another using layer transfer techniques on a wafer-level scale. This technique requires the entire layer to be transferred in its entirety, whether or not the entire layer is needed. Therefore, after the transfer, any unwanted portions of the transferred layer must be etched away, which increases cost and process complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1A-Figure 1I An exemplary process flow for selective layer transfer using selective release technology is shown.

[0003] Figure 2A-2I An exemplary process flow for selective layer transfer using blanket laser exposure is shown.

[0004] Figure 3A-Figure 3I An exemplary process flow for selective layer transfer from a singulated donor substrate is shown.

[0005] Figure 4A-4C An exemplary process flow for selective layer transfer from multiple donor substrates is shown.

[0006] Figure 5A-5F An exemplary process flow for forming an integrated circuit package using selective transfer of a passive interposer is shown.

[0007] Figure 6A-6B An example of selective layer transfer between wafers is shown.

[0008] Figure 7 A flow chart for performing a selective layer transfer is shown.

[0009] Figure 8A-8E An exemplary process flow for selective transfer using blanket wafer laser exposure is shown.

[0010] Figure 9A-9C Various laser debonding techniques for selective transfer are shown.

[0011] Figure 10A-10B A laser debonding technique is shown which would put the selectively transferred layer at risk of damage.

[0012] Fig.11 An exemplary structural support layer for protecting the selective transfer layer is shown.

[0013] Figures 12A-12D An exemplary process flow for selective layer transfer using a structural support layer is shown.

[0014] Figures 13A-13DAn exemplary process flow for selective layer transfer using a structural support layer comprising glass and a photo-release adhesive is shown.

[0015] Fig.14 An exemplary wafer chuck having a porous portion containing pores that are small relative to the laser spot size is shown.

[0016] Fig.15 A flow chart for performing selective layer transfer using a structural support layer is shown.

[0017] Fig.16 A debonded stack on a donor substrate is shown.

[0018] Fig.17 A protective debonded stack including a conversion layer on a donor substrate is shown.

[0019] Fig.18 A protective debonded stack including a compressive stress layer on a donor substrate is shown.

[0020] Fig.19 A protective debonding stack including a patterned layer on a donor substrate is shown.

[0021] Figure 20A-Figure 20E An exemplary patterned layer is shown.

[0022] Fig.21 A protective debonding stack including a reflector stack on a donor substrate is shown.

[0023] Fig. 22 A flow chart for performing selective layer transfer using a protective debonding stack is shown.

[0024] Fig.23 Shown are top views of wafers and dies that may be included in a microelectronic assembly.

[0025] Fig.24 A cross-sectional side view of an integrated circuit device that can be included in a microelectronic assembly is shown.

[0026] Figure 25A-Figure 25D Perspective views of exemplary planar transistors, FinFET transistors, gate-all-around transistors, and stacked gate-all-around transistors are shown.

[0027] Fig.26 A cross-sectional side view of an integrated circuit device assembly that may include a microelectronic assembly is shown.

[0028] Fig. 27 A block diagram of an exemplary electrical device that may include a microelectronic assembly is shown. DETAILED DESCRIPTION

[0029] Selective layer transfer

[0030] In semiconductor manufacturing, a layer is typically transferred from one substrate to another using a layer transfer technique on a wafer-level scale. Layer transfer contributes to a variety of applications in semiconductor manufacturing, including two-dimensional (2D) material fabrication, III-V semiconductors on complementary metal oxide semiconductors (CMOS), and traditional CMOS applications (e.g., metal-insulator-metal (MIM) devices and thin devices and / or interconnect layer transfer). However, current layer transfer techniques are limited to full-layer transfers, which may affect cost and performance when full layers are not required. For example, blanket layer transfer techniques (e.g., ion cutting and laser debonding layer transfers) require the entire layer to be transferred as a whole. As a result, after the transfer, any unwanted areas of the transferred layer must be etched away, which results in increased cost and process complexity.

[0031] Alternatively, pick-and-place techniques can be used to transfer specific dies or cores. For example, a core generally refers to an integrated circuit (IC) containing a subset of well-defined functions that is designed to be combined with other cores to form a single IC package. In order to transfer cores (e.g., for MIM core integration in a system on a chip (SoC)), a core device is made on a donor substrate (e.g., a wafer or panel), the donor substrate is singulated into cores, and then the cores are each attached to a receptor substrate (e.g., a SoC wafer or package) using a pick-and-place machine. Since additional processing is required to singulate the wafer and attach the corresponding core dies, this adds a lot of cost. For example, cores are generally manufactured on relatively thick substrates so that they can be handled without being damaged during singulation and attachment steps, and after the attachment step, additional processing is performed to thin the cores and / or remove the carrier substrate, which further increases cost and process complexity. Specifically, cores are typically fabricated on substrates over 700 micrometers (μm or microns) thick to provide structural and mechanical stability during fabrication, and after the singulation / attachment step, the cores can be thinned to approximately 20-100 μm by grinding the backside. However, grinding typically results in chipping along the edges of the core die. Furthermore, thinning the cores to less than 20 μm without creating defects can be challenging. Similarly, since pick and place assembly is difficult for substrates less than 1 square millimeter (mm 2 ) becomes very challenging for die with small size, so the die are typically singulated with die area on the millimeter scale.

[0032] Integrated circuits can also be manufactured monolithically, where all IC components and interconnections are fabricated in sequence on the same underlying substrate or wafer. However, monolithic ICs have various limitations, including design restrictions due to incompatible processes, lack of flexibility, and low yields.

[0033] Therefore, the present disclosure shows a selective layer transfer technology for selectively transferring portions of a layer between substrates, and a device and system formed using the technology. For example, the described technology enables the transfer of a selected area of ​​a donor substrate to a receptor substrate, which enables the donor substrate to be reused multiple times, while also solving the limitations of the blanket layer transfer and pick-and-place technology described above. Specifically, the described solution uses a selective release technology for a donor substrate (e.g., a wafer, a panel, or a die) in conjunction with a patterned bonding template on a receptor substrate (e.g., a wafer, a panel, or a die) to allow a selected area of ​​a layer on the donor substrate to be transferred to the receptor substrate. For the purposes of the present disclosure, the term "layer" can sometimes be used to refer to a single layer of a single material or multiple layers of one or more materials. For example, a selective transfer layer can be formed on a substrate and can be a single material layer, or a layer stack of layers that together form an IC component (e.g., a die, an interconnect, a bridge, a capacitor, and / or other semiconductor devices). The layer can also include stacked wafers, such as wafer-to-wafer bonding and stacked logic cells and / or memory wafers. As an example, a donor wafer may include layers of IC components (eg, IC dies), and selective layer transfer may be used to selectively and simultaneously transfer specific subsets of these IC components to a recipient wafer.

[0034] The described solution provides various advantages. For example, the described solution enables transfer of selected areas of a donor wafer, rather than an entire layer, which enables the donor wafer to be reused for multiple products, thus amortizing the cost of expensive devices (e.g., high-density MIM capacitors or high-density passive interposers) over multiple wafers. The solution also eliminates the need to etch away excess areas as required by a full-layer transfer (and thus, unlike the etched areas after the full-layer transfer, the selectively transferred areas may not have tapered edges resulting from the etching, or may have an inverted taper due to the etching used for singulation prior to the transfer).

[0035] Furthermore, in various examples, layers of IC components may be selectively transferred at any suitable level of granularity, including complete IC dies and packages, interconnects, transistors, resistors, capacitors, partial layers or layer stacks, and the like.

[0036] The solution also enables selective transfer of areas of ultra-thin layers without the increased processing and yield losses caused by the processing challenges brought by the core pick and place method (e.g., singulation, attaching each core individually, post-attachment thinning of the core). This helps to reduce the Z height of the product (e.g., due to form factor, thermal, and / or power delivery reasons) and the overall process complexity. For example, very thin IC dies or cores can be formed on any substrate and selectively transferred directly from the substrate. Therefore, selectively transferring the die not only eliminates the need for post-attachment thinning, but also enables the die to be much thinner than the die that is singulated, picked and placed, attached and subsequently thinned. For example, in some cases, the described solution can enable the transfer of dies with thicknesses ranging from 100 nanometers (nm) to 5μm or more. In addition, since post-attachment thinning is not required, unlike the cores that are thinned after attachment, the selectively transferred die may have no or minimal fragmentation on the die edge due to the lack of grinding.

[0037] Similarly, the described solutions support the selective transfer of very small areas on a donor substrate (e.g., very small dies or core particles) that are extremely challenging when using pick and place techniques. For example, in some cases, the described solutions can enable the transfer of very small areas with a size of less than 1 mm. 2 (e.g. 100 μm 2 (10×10μm), 10,000μm 2 (100×100μm), 810,000μm 2 (900 x 900 μm, etc.) (there is no limit to the maximum size of the area that can be selectively transferred).

[0038] The solution also supports the selective transfer of dies with non-standard shapes and designs that are difficult to handle using pick and place machines, such as dies with atypical, arbitrary, irregular or non-convex shapes (e.g., L-shape, U-shape, shapes with sharp angles), dies with high aspect ratios (e.g., aspect ratios of 8:1 or higher), dies with holes, etc.

[0039] Furthermore, the solution has very low topography and supports high surface cleanliness and planarization (eg, using chemical mechanical polishing (CMP) processing), which makes it compatible with hybrid bonding and fusion bonding processes. Additional advantages are described throughout this disclosure and will be apparent in the following description.

[0040] Thus, the solution enables the manufacture of complex IC packages and products by selectively transferring certain components (e.g., active circuit systems such as IC dies, passive circuit systems) rather than combining them using traditional processes (e.g.: (i) full-layer transfer with excess areas etched away; (ii) pick-and-place assembly of individual IC components; and / or (iii) monolithic IC fabrication).

[0041] Figure 1A-Figure 1I An exemplary process flow for selective layer transfer using a selective release technique is shown. In the example shown, a layer of an integrated circuit (IC) component is selectively transferred from a donor substrate 100 to an acceptor substrate 110, as described further below.

[0042] exist Figure 1A , a release layer 102 is formed on a carrier substrate, referred to as a donor substrate 100. The release layer 102 is a temporary bonding and debonding layer for the layer 104 to be selectively transferred. In some embodiments, the release layer 102 may include one or more layers and / or materials capable of providing adhesion to the donor substrate 100 and / or absorbing energy from a laser (e.g., a laser beam), such as (multiple) lossy dielectric and / or thin metal layers that provide adhesion and absorb / reflect infrared (IR) light, organic polymer layers (e.g., polyimide) that provide adhesion and absorb visible or ultraviolet (UV) light, and / or a patterned dielectric layer with anchors to provide residual adhesion (e.g., after the metal layer is ablated by an IR laser).

[0043] The selectively transferred layer 104 is formed on the release layer 102 on the donor substrate 100 (e.g., by directly fabricating the layer 104 (on the release layer 102) or blanket transferring the layer 104). The selectively transferred layer 104 may include one or more material layers, such as a single material layer, or a stack of layers that together form an IC component (e.g., a full IC die, a core particle, an interconnect, a bridge, a capacitor, a transistor, and / or other semiconductor device). For example, in some embodiments, the selectively transferred layer 104 may be a pre-fabricated semiconductor wafer containing unsingulated integrated circuit (IC) dies that is blanket transferred to the release layer 102 on the donor substrate 100.

[0044] exist Figure 1B In the process, the selective transfer layer 104 is cut over the donor substrate 100 without cutting through the donor substrate 100 using a technique such as etching, reactive ion etching (RIE), plasma cutting, mechanical sawing, etc., thereby partially singulating the IC components 106 in the layer 104. In some embodiments, the release layer 102 may also be singulated (e.g., cut or etched) together with the transfer layer 104.

[0045] exist Figure 1C In the embodiment of the present invention, a release layer 112 is optionally formed over another carrier substrate, referred to as an acceptor substrate 110. For example, if the selectively transferred IC component 106 will be subsequently debonded from the acceptor substrate 110 after transfer, the release layer 112 can be formed over the acceptor substrate 110. Otherwise, if the selectively transferred IC component 106 will remain on the acceptor substrate 110 after transfer, the release layer 112 on the acceptor substrate 110 can be omitted.

[0046] Next, a bonding template including bonding features 114 is formed on a surface of acceptor substrate 110 (e.g., over release layer 112, if included). The bonding template includes a pattern of bonding features 114 or bonding areas that can selectively transfer specific areas on donor substrate 100 to acceptor substrate 110. For example, the locations of bonding features 114 or bonding areas on acceptor substrate 110 correspond to areas on donor substrate 100 or IC components 106 that are to be transferred to acceptor substrate 110.

[0047] For example, in some embodiments, the bonding features 114 may include "islands" or "mesa" structures that are similar in size to the target area to be transferred from the donor substrate 100. For example, each island or mesa structure may be a raised structure located on the surface of the acceptor substrate 110 that has a similar footprint (e.g., shape / surface area) as the corresponding IC component 106 located on the donor substrate 100. In other embodiments, the bonding features 114 may be replaced by a surface treatment of photolithography or additive manufacturing that enhances adhesion in the target area of ​​the acceptor substrate 110 (e.g., the area showing the bonding features 114) and prevents adhesion in other areas, including but not limited to: surface topography changes, use of materials with high adhesion and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among other examples.

[0048] In various embodiments, these bonding features 114 may be made of a dielectric material, a conductive material (e.g., a metal), or both, depending on whether an electrical connection is desired between the bonded IC component 106 and the receptor substrate 110. For example, the bonding features 114 may be blanket dielectric structures with no electrical contacts, or if electrical connection across the bonding interface is desired, the bonding features 114 may be dielectric structures with electrical contacts therethrough (e.g., hybrid bond pads).

[0049] exist Figure 1DIn the process, the donor substrate 100 and the acceptor substrate 110 are brought into contact with each other with their top surfaces aligned face to face so that the target IC components 106 on the donor substrate 100 are aligned with the corresponding bonding features 114 on the acceptor substrate 110 .

[0050] exist Figure 1E , the donor substrate 100 and the acceptor substrate 110 are partially bonded together. For example, an area of ​​the acceptor substrate 110 having a raised surface feature or "mesa" 114 is bonded to a corresponding area on the donor substrate 100 having a target IC component 106, while other areas of the donor substrate 100 and the acceptor substrate 110 remain unbonded. For example, in some embodiments, this is controlled by the height of the bonding protrusions (e.g., bonding features 114) to prevent undesired contact between areas that will not be transferred. As previously mentioned, this can also be controlled by surface treatment of different areas to achieve good bonding in the target area (e.g., where the bonding features 114 are shown) and prevent or reduce bonding in other areas.

[0051] exist Figure 1F In the present invention, the IC component 106 bonded to the acceptor substrate 110 is selectively debonded from the donor substrate 100 using a selective release technique (e.g., IR debonding, selective visible or ultraviolet (UV) laser exposure, etc.). For example, a laser such as an IR or UV laser can be used to selectively remove or ablate the release layer 102 in the area 103 where the IC component 106 is bonded to the donor substrate 100, which forms a gap or void in the release layer 102 and causes the IC component 106 to be released from the donor substrate 100.

[0052] exist Figure 1G , the donor substrate 100 and the acceptor substrate 110 are mechanically separated from each other. At this point, the IC components 106 that were selectively bonded to the acceptor substrate 110 (e.g., via the bonding features 114) and debonded from the donor substrate 100 remain on the acceptor substrate 110 and are separated from the donor substrate 100. All other IC components 106 that are not bonded to the acceptor substrate 110 remain on the donor substrate 100.

[0053] exist Figure 1H , the receptor substrate 110 is now ready for continued processing, such as dielectric fill 116 around the transferred IC components 106, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attaching a structural substrate, debonding the receptor substrate (e.g., via an optional receptor release layer 112), and / or any other processing required for the finished product (e.g., an IC package).

[0054] exist Fig. 1I The donor substrate 100 is then reused to transfer the remaining IC components 106 (e.g., the remaining areas of the selectively transferred layer 104) to a new acceptor substrate 110'. The donor substrate 100 may continue to be reused in this manner until all IC components 106 or the entire layer 104 have been selectively transferred to any number of acceptor substrates 110.

[0055] It should be understood that the process flow shown for selective layer transfer is shown only as an example, and many other process variations are possible. For example, the donor substrate 100 and the acceptor substrate 110 can be wafers, panels, IC packages, cores, dies, or any combination thereof (e.g., for transfer from wafer to panel, transfer from core to wafer, etc.). In addition, each substrate 100, 110 can be made of a variety of materials, including but not limited to: inorganic materials (e.g., silicon, silicon on insulator (SOI), quartz, glass, and / or III-V materials), organic materials (e.g., IR or UV transparent epoxy resins), etc.

[0056] The materials used in the release layers 102, 112 may vary depending on the type of release or debonding technique used. For example, for infrared (IR) laser debonding, the release layers 102, 112 may include one or more materials capable of absorbing and / or reflecting infrared (IR) light, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For ultraviolet (UV) laser debonding, the release layers 102, 112 may include one or more materials capable of absorbing UV light (e.g., a variety of organic polymers, including but not limited to polyimide). In some embodiments, the release layers 102, 112 may additionally or alternatively include one or more layers of dielectric materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon carbon nitride (SiOCN), aluminum oxide (Al2O3), low-k dielectrics (e.g., carbon-doped oxide (CDO) or porous silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5)), which may be used to buffer laser ablation and thermal energy, control thin film interference or adhesion, and / or provide residual adhesion after other materials and / or layers in the release layers 102, 112 are weakened, removed and / or ablated by the laser.

[0057] The number of layers 104 on the donor substrate 100, the arrangement / structure of the layers 104, the materials in each layer 104, and the types of IC components 106 formed in the layers 104 may vary.

[0058] To control the level of adhesion in different areas, any suitable surface treatment or other technique may be used to form the bonding areas or joining features 114 on the acceptor substrate 110, including but not limited to: surface topography changes (e.g., terraces, depressions), use of materials with high adhesion and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among other examples. In addition, the joining features 114 or bonding areas on the acceptor substrate 110 may vary in size, shape, height, topography, pattern, and material. For example, inorganic dielectrics (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), and / or silicon carbon nitride (SiCN)), organic dielectrics (e.g., photoresists and adhesives), conductive materials (e.g., metals), and combinations thereof may be used to form the bonding features 114.

[0059] The donor substrate 100 and the acceptor substrate 110 may be (partially) joined using any suitable joining technique, including but not limited to hybrid joining, fusion joining, and adhesive joining. The donor substrate 100 and the acceptor substrate 110 may be debonded or released using any suitable debonding technique, including but not limited to IR and UV laser debonding. Furthermore, there may be additional cleaning steps before or after each selective layer transfer to the acceptor substrate 110, so that the donor substrate 100 can be reused.

[0060] In addition, in some embodiments, additional bonding and / or alignment features may be included at the wafer level and / or die level (e.g., on the donor die, donor wafer, acceptor wafer, and / or final product). For example, the donor and / or acceptor wafer may include ridges or cross structures for facilitating bonding, such as a single ridge (e.g., a line or strip of dielectric material) extending across and / or through the center of the wafer, or multiple orthogonal ridges forming a cross pattern. Alignment features for wafers, small dies, and / or die arrays may also be included to facilitate bonding with proper alignment. In addition, multiple dies may be connected by small (e.g., dielectric) bridges to facilitate their joint bonding and transfer together. For example, if some of the dies connected by the bridge are successfully bonded to the acceptor, the bridge may also facilitate bonding of other dies. Therefore, these inter-die bridges may exist on the donor before transfer and on the acceptor and final product after transfer.

[0061] Furthermore, in some cases the debonding process may cause some unique damage or delamination near the edge and / or on the backside of the die, which does not affect the process performance but may indicate that this solution is being used.

[0062] Figure 2A-2IAn exemplary process flow for selective layer transfer using blanket laser exposure is shown. In the example shown, layer 204 of integrated circuit (IC) component 206 is selectively transferred from donor substrate 200 to receptor substrate 210. However, prior to transfer, the entire release layer 202b on donor 200 is mechanically weakened (e.g., using IR laser, visible light laser, UV laser, chemical etching, and / or thermal techniques), which can also be referred to as partial release. In this way, after the target IC component 206 on donor 200 is bonded to receptor 210, the target IC component 206 can be completely released from donor 200 by mechanically separating donor 200 from receptor 210. In some cases, the target IC component 206 can be completely released from donor 200 by mechanically separating donor 200 from receptor 210. Figure 1A-Figure 1I This can result in a simplified and faster bonding / debonding process compared to the bonding / selective release / debonding process in . Other variations of this process are described in conjunction with other figures herein. Alternatively, rather than using blanket laser exposure, the corresponding materials used in the donor release layer 202 and the receptor bonding template 214 can be selected so that the bond to the donor 200 is weaker than the bond to the receptor 210 that is subsequently formed.

[0063] exist Figure 2A In the embodiment of the present invention, a release layer 202 is formed on a donor substrate 200. A selectively transferred layer 204 is formed on the release layer 202 (e.g., by directly fabricating the layer 204 (on the release layer 202) or blanket transferring the layer 204). In some embodiments, the selectively transferred layer 204 can be a layer of an IC component (e.g., an IC die, a core particle, an interconnect, a bridge, a capacitor, a transistor, and / or other semiconductor device).

[0064] exist Figure 2B In the embodiment of the present invention, the selective transfer layer 204 is cut above the donor substrate 200 without cutting through the entire donor substrate 200, thereby partially singulating the IC components 206 in the layer 204.

[0065] exist Figure 2C In the embodiment, before transfer, blanket laser exposure is performed on the donor release layer 202 to weaken the entire release layer 202. For example, in some embodiments, the blanket laser exposure can be performed using laser (e.g., IR or UV laser exposure), chemical and / or thermal techniques. In this way, the weakened release layer 202 has a lower bonding energy, which causes partial release of the IC component 206 bonded to the layer 202.

[0066] exist Figure 2DIn the embodiment of the present invention, release layer 212 is optionally formed over receptor substrate 210. For example, if selectively transferred IC component 206 will be subsequently debonded from receptor substrate 210 after transfer, release layer 212 may be formed over receptor 210; otherwise, release layer 212 on receptor 210 may be omitted.

[0067] Next, a bonding template 214 is formed on the surface of the acceptor substrate 210 (e.g., over the release layer 212, if included). The bonding template 214 includes a pattern of bonding features or bonding areas (e.g., mesas) that enable selective transfer of specific areas on the donor substrate 200 to the acceptor substrate 210. However, in various embodiments, any suitable surface treatment or other technique may be used to control the level of adhesion on different areas of the acceptor substrate 210 (e.g., to form bonding areas and non-bonding areas for selective transfer), including but not limited to: surface topography changes (e.g., mesas, depressions), use of materials with high adhesion and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among other examples.

[0068] exist Figure 2E In the process, the donor substrate 200 and the acceptor substrate 210 are brought into contact with each other with their top surfaces aligned face to face so that the target IC components 206 on the donor 200 are aligned with corresponding bonding features of the bonding template 214 on the acceptor 210 .

[0069] exist Figure 2F In FIG. 1 , a donor substrate 200 and an acceptor substrate 210 are partially bonded together, wherein a region of the donor 200 having a target IC component 206 is bonded to a region of the acceptor 210 having a bonding mesa of a bonding template 214 .

[0070] exist Figure 2G , the donor substrate 200 and the acceptor substrate 210 are mechanically separated from each other. At this point, the IC components 206 that were selectively bonded to the acceptor 210 (e.g., via the bonding mesas of the bonding template 214) remain on the acceptor 210 and are debonded / separated from the donor 200 due to the blanket weakening of the donor release layer 202. All other IC components 206 that are not bonded to the acceptor 210 remain on the donor 200.

[0071] Alternatively, in some embodiments, the respective materials used in the donor release layer 202 and the receptor engagement template 214 may be selected without performing Figure 2C Blanket laser exposure in Figure 2CThe target IC component 206 may be formed by a laser beam (except for blanket laser exposure in the embodiment of the present invention) so that the target IC component 206 will have a stronger bond with the receptor 210 than with the donor 200. In this way, when the donor 200 and the receptor 210 are mechanically separated, the target IC component 206 will be debonded from the donor 200 and remain on the receptor 210 due to the difference in bond strength.

[0072] exist Figure 2H , the receptor substrate 210 is ready for continued processing, such as dielectric fill 216 around the transferred IC component 206, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attachment of a structural substrate, debonding of the receptor substrate (e.g., via an optional receptor release layer 212), and / or any other processing required for the finished product (e.g., an IC package).

[0073] exist Fig.2I The donor substrate 200 is then reused to transfer the remaining IC components 206 (e.g., the remaining areas of the selectively transferred layer 204) to a new acceptor substrate 210'. The donor substrate 200 may continue to be reused in this manner until all IC components 206 or the entire layer 204 have been selectively transferred to any number of acceptor substrates 210.

[0074] Figure 2A-2I The elements marked with reference numerals in the Figure 1A-Figure 1I Furthermore, it should be understood that the illustrated process flow for selective layer transfer is presented as an example only, and that many other process variations are possible, including but not limited to those described throughout this disclosure.

[0075] Figure 3A-Figure 3I An exemplary process flow for selective layer transfer from a singulated donor substrate 300 is shown. For example, in some cases, if the percentage of integrated circuit (IC) components 306 transferred for each selective layer transfer is relatively small, it may be easier and more cost-effective to cut the donor substrate 300 and perform the transfer from singulated donor dies 301 containing a smaller subset of IC components 306 from the original donor substrate 300. Thus, in the example shown, the donor substrate 300 having a layer 304 of IC components 306 is cut, and the resulting layer of IC components 306 located on the singulated donor dies 301 is selectively transferred to an acceptor substrate 310. In this way, the transfer is performed at the donor die level rather than at the wafer level or panel level.

[0076] exist Figure 3A, a release layer 302 is formed on a donor substrate 300. A selectively transferred layer 304 is formed on the release layer 302 (e.g., by directly fabricating the layer 304 or blanket transferring the layer 304). In some embodiments, the selectively transferred layer 304 can be a layer of an IC component (e.g., an IC die, a chip, an interconnect, a bridge, a capacitor, a transistor, and / or other semiconductor device).

[0077] exist Figure 3B In the embodiment of the present invention, the selective transfer layer 304 is cut above the donor substrate 300 without cutting through the donor substrate 300, thereby partially singulating the IC components 306 in the layer 304. In some embodiments, the release layer 302 can also be singulated (e.g., cut or etched) together with the transfer layer including the IC components 306.

[0078] exist Figure 3C , a donor substrate 300 is cut into singulated donor dies 301, each of which contains a subset of IC components 306 from the original donor substrate 300. For example, each donor die 301 may include one or more IC components 306 from a layer 304 on the original donor substrate 300.

[0079] exist Figure 3D In the embodiment, blanket laser exposure (as shown) or selective laser release is performed on the donor release layer 302 prior to transfer (e.g., using IR / UV laser exposure or thermal techniques) to weaken the entire release layer 302, thereby partially releasing the IC component 306 from the donor die 301.

[0080] exist Figure 3E , a release layer 312 is optionally formed over the acceptor substrate 310 (e.g., in the case where the selectively transferred IC component 306 will subsequently be debonded from the acceptor substrate 310 after transfer). Next, a bonding template 314 is formed on the surface of the acceptor substrate 310 (e.g., over the release layer 312, if included). The bonding template 314 includes a pattern of bonding features or bonding areas (e.g., mesas) that enable specific areas of the donor die 301 to be selectively transferred to the acceptor substrate 310. However, in various embodiments, any suitable surface treatment or other technique may be used to control the level of adhesion on different areas of the acceptor substrate 310 (e.g., to form bonding areas and non-bonding areas for selective transfer), including but not limited to: surface topography changes (e.g., mesas, depressions), use of materials with high adhesion and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among other examples.

[0081] exist Figure 3F, a bond head 320 is used to pick up one of the donor dies 301 and place it face down on an acceptor substrate 310 such that a target IC component 306 located on the donor die 301 is aligned with a corresponding bonding surface of a bonding template 314 located on the acceptor substrate 310. The donor die 301 and the acceptor substrate 310 are then partially bonded together (e.g., die-to-wafer bonding), wherein the target IC component 306 is bonded to the acceptor bonding surface 314.

[0082] exist Figure 3G 3, the bond head 320 is raised and the donor die 301 is mechanically separated from the acceptor substrate 310. At this point, the IC components 306 that were selectively bonded to the acceptor 310 (e.g., via the bonding mesas of the bonding template 314) remain on the acceptor 310 and are debonded / separated from the donor die 301 (e.g., die-to-wafer debonding) due to the blanket weakening of the donor release layer 302. All other IC components 306 that are not bonded to the acceptor substrate 310 remain on the donor die 301.

[0083] Alternatively, in some embodiments, the target IC component 306 may be selectively released (e.g., as described with respect to Figure 1F ), instead of (or in addition to) executing Figure 3D Alternatively, the donor release layer 302 and the acceptor bonding template 314 may be formed using materials having different bonding strengths so that the target IC component 306 will have a stronger bond to the acceptor substrate 310 than to the donor die 301 .

[0084] exist Figure 3H and Fig. 3I In the process, the bonding head 320 translates and repeats the steps. For example, the bonding head 320 moves to a new position and repeats the steps respectively. Figure 3F and Figure 3G The process in to selectively transfer another set of IC components 306 from the donor die 301 to other areas of the acceptor substrate 310.

[0085] The process may be repeated in this manner until all IC components 306 on the donor die 301 have been transferred. At this point, the bond head 320 may pick up another donor die 301 and continue transferring the IC components 306 from the new donor die 301 to the same or a different receptor substrate 310.

[0086] After all transfers to the receptor substrate 310 are completed, the receptor 310 can be ready for continued processing, such as dielectric fill around the transferred IC components 306, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attaching a structural substrate, debonding the receptor substrate (e.g., via an optional receptor release layer 312), and / or any other processing required for the finished product (e.g., an IC package).

[0087] Figure 3A-Figure 3I The elements marked with reference numerals in the Figure 1A-Figure 1I Furthermore, it should be understood that the illustrated process flow for selective layer transfer is presented as an example only, and that many other process variations are possible, including but not limited to those described throughout this disclosure.

[0088] Figure 4A-4C An exemplary process flow for selective layer transfer from multiple donor substrates is shown. In the example shown, integrated circuit (IC) components 414, 434 are selectively transferred from multiple donor substrates 410, 430 to an acceptor substrate 450 using intermediate carrier substrates 420, 440. In some embodiments, the respective donors 410, 430 may have different types of IC components 414, 434, such as different types of IC dies or core particles. In this way, selective layer transfer can be used to transfer multiple types of IC components (e.g., different types of dies or core particles) to the same acceptor substrate 450. Although the example shown depicts selective transfer from two types of donor substrates 410, 430 (e.g., having two types of IC components 414, 434), any number of donor substrates having any type of IC die or other components (including having different die sizes) are possible.

[0089] exist Figure 4A4. In the process of selectively transferring IC components 414 from a first donor substrate 410 to an intermediate carrier substrate 420, a layer of IC components 414 is selectively transferred from a first donor substrate 410 to an intermediate carrier substrate 420 (e.g., using any of the selective transfer processes described throughout this disclosure). For example, a release layer 412 is formed on the donor substrate 410. Then, the selectively transferred layer 414 is formed on the release layer 412 (e.g., by directly fabricating the layer 414 or blanket transferring the layer 414 from a wafer to the donor carrier 410) and cut into partially singulated IC components 414. Separately, a release layer 422 is formed on the intermediate carrier / receiver substrate 420, and a bonding template 424 is formed on a surface of the intermediate carrier 420 (e.g., above the release layer 422). The donor 410 and the intermediate carrier 420 are then partially bonded together (e.g., the target IC component 414 located on the donor 410 is bonded to a bonding feature or bonding area 424 located on the intermediate carrier 420). The donor 410 and the intermediate carrier 420 are then debonded and separated from each other using any of the techniques described throughout this disclosure (e.g., selective release, blanket laser exposure, etc.). As a result, the target IC component 414 is debonded / separated from the donor 410 and remains on the intermediate carrier 420.

[0090] exist Figure 4B 4, another layer of IC components 434 is selectively transferred from a second donor substrate 430 to another intermediate carrier substrate 440 (e.g., using any of the selective transfer processes described throughout this disclosure). For example, a release layer 432 is formed on the donor substrate 430. Then, the selectively transferred layer 434 is formed on the release layer 432 (e.g., by directly fabricating the layer 434 or blanket transferring the layer 434 from the wafer to the donor carrier 430) and cut into partially singulated IC components 434. Separately, a release layer 442 is formed on the intermediate carrier / acceptor substrate 440, and a bonding template 444 is formed on the surface of the intermediate carrier 440 (e.g., above the release layer 442). The donor 430 and the intermediate carrier 440 are then partially bonded together (e.g., the target IC component 434 located on the donor 430 is bonded to a bonding feature or bonding area 444 located on the intermediate carrier 440). The donor 430 and the intermediate carrier 440 are then debonded and separated from each other using any of the techniques described throughout this disclosure (e.g., selective release, blanket laser exposure, etc.). As a result, the target IC component 434 is debonded / separated from the donor 430 and remains on the intermediate carrier 440.

[0091] exist Figure 4C, IC components 414, 434 located on both intermediate carriers 420, 440 are selectively transferred to an acceptor substrate 450 (e.g., using any selective transfer process described throughout this disclosure). For example, optionally, a release layer 452 is formed on the acceptor substrate 450 (e.g., in the case where the selectively transferred IC components 414, 434 will subsequently be debonded from the acceptor substrate 450 after transfer). Then, a bonding layer 454 (e.g., having bonding areas or bonding features) is formed on the surface of the acceptor 450 (e.g., above the release layer 452, if included). Next, the IC component 414 located on the first intermediate carrier 420 is selectively transferred to the acceptor substrate 450 (e.g., using any selective transfer process described throughout this disclosure). Finally, the IC component 434 located on the second intermediate carrier 440 is selectively transferred to the acceptor substrate 450 (e.g., using any selective transfer process described throughout this disclosure).

[0092] Additional processing may then be performed on the receptor substrate 450, such as cleaning steps (e.g., removing residual bonding structures 424, 444 from the transferred IC components 414, 434), dielectric fill around the transferred IC components 414, 434, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attaching a structural substrate, debonding the receptor substrate (e.g., via an optional receptor release layer 452), and / or any other processing required for the finished product (e.g., an IC package).

[0093] It should be understood that the illustrated process flow for selective layer transfer is presented by way of example only, and that numerous other process variations are possible, including but not limited to those described throughout this disclosure.

[0094] Figure 5A-5FAn exemplary process flow for forming an integrated circuit (IC) package 500 having a selectively transferred passive interposer 506 is shown. Selective transfer can be used for a variety of applications, including transfer of active components (e.g., IC die, transistors, diodes) and passive components (e.g., interconnects, metal-insulator-metal (MIM) cores, resistors, capacitors, inductors, transformers). In the example shown, the process flow is used to form an IC package 500 having a selectively transferred, low-cost passive interposer 506. For example, an interposer 506 having a high-density die-to-die (D2D) link 508 is created on a donor wafer 502 and then selectively transferred to a recipient wafer 512, which enables the same donor wafer 502 to be reused multiple times and the cost of the interconnect device to be amortized over multiple recipient wafers 512. In some embodiments, other components of the IC package 500, such as IC die 518a-518b, may also be selectively transferred. Selective transfer can also be used for other applications including, but not limited to, transfer of photonic / optical components, and localized transfer of III-V semiconductors for radio frequency (RF) and high power devices.

[0095] exist Figure 5A In the embodiment of the present invention, a repeating D2D interconnect pattern 506 is created on a release layer 504 of a donor substrate 502, and the resulting D2D interconnects are partially singulated (eg, cut to the donor substrate 502, but not through the donor substrate 502). The D2D interconnects 506 include high-density interconnect links 508 separated by dielectric layers 510.

[0096] exist Figure 5B , a transfer template 516 for selective transfer is created on a release layer 514 of an acceptor / carrier substrate 512. The transfer template 516 includes dielectric bonding protrusions 516 (referred to as mesas) located on the surface of the acceptor substrate 512. However, in various embodiments, any suitable surface treatment or other technique may be used to control the adhesion level on different areas of the acceptor substrate 512 (e.g., to form bonding areas and non-bonding areas for selective transfer), including but not limited to: surface topography changes (e.g., mesas, depressions), use of materials with high adhesion and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among other examples. In addition, in various embodiments, any number of buildup layers may be formed on the acceptor substrate 512 prior to forming the templated connection base or mesas 516 for selective transfer.

[0097] The bonding surface of the transfer template 516 is used to selectively transfer the D2D interconnect 506 from the donor 502 to the receptor 512 (e.g., using any selective transfer process described throughout the present disclosure). For example, the donor 502 and the receptor 512 are aligned face to face, stacked, and then partially bonded together so that one of the D2D interconnects 506 located on the donor 502 is bonded to the bonding surface of the transfer template 516 located on the receptor 512.

[0098] exist Figure 5C In the embodiment, the D2D interconnect 506 bonded to the receptor mesa of the transfer template 516 is debonded and / or released from the donor release layer 504 using any of the techniques described herein (e.g., selective release, blanket laser exposure, formation of bonds with intensity differentials), and the donor 502 and receptor 512 are mechanically separated. As a result, the transferred D2D interconnect 506 is separated from the donor 502 and remains on the receptor 512.

[0099] exist Figure 5D In the process, additional processing is performed to form the remaining interconnects, which additional processing includes dielectric (e.g., oxide) filling 510 and planarization, interconnect 508 patterning / metallization (e.g., forming through dielectric vias (TDVs), top metal contacts (e.g., hybrid bonding pads), dielectric layers), etc.

[0100] It is worth noting that since the D2D interposer 506 is selectively transferred and the surrounding dielectric layer 510 is directly fabricated on the receptor 512, Figure 5D As shown, there is a gap 511 between the transferred D2D interposer 506 and the surrounding layer 510. Generally speaking, since this type of gap or transition is not formed simultaneously with the surrounding layer, they may exist around any type of selectively transferred component.

[0101] exist Figure 5E In the embodiment, multiple IC dies 518a-518b are attached to a top metal pad 508 (e.g., via hybrid bonding), the area around the dies 518a-518b is filled with a dielectric material 510 (e.g., oxide) and planarized, and a structural substrate 520 (e.g., a structural silicon wafer) is attached.

[0102] The dies 518a-518b may be attached using standard assembly techniques (eg, pick and place) or using the selective transfer techniques described herein (eg, similar to the transferred D2D interconnect 506).

[0103] If the dies 518a-518b are attached using pick and place assembly, they are typically formed on a thick substrate for handling purposes and subsequently thinned after attachment.

[0104] However, if the die 518a-518b are selectively transferred, they can be formed on a very thin substrate and transferred directly from the very thin substrate. Therefore, selectively transferring the die 518a-518b not only eliminates the need for post-attachment thinning, but also enables the die 518a-518b to be much thinner than a die that is picked and placed for attachment and subsequently thinned. In addition, if the die 518a-518b are selectively transferred, there may be a gap 511 between the die 518a-518b and the portion of the layer 510 surrounding the die 518a-518b, similar to the gap 511 shown around the transferred D2D interconnect 506 as described above. In addition, since the die 518a-518b are selectively transferred, they can be different types of die, formed on separate substrate material sheets (e.g., separate wafers or panels) using separate processes, and then selectively transferred to the same layer of the IC device 500.

[0105] exist Fig. 5F In the process, receptor 512 is debonded and released from release layer 514 (eg, using any of the techniques described herein, such as IR or UV laser ablation).

[0106] At this point, IC package 500 may be completed, or alternatively, additional processing may be performed. For example, if processing is performed at the wafer level or panel level, the resulting IC package 500 on structural substrate 520 may be singulated.

[0107] Figure 6A-6B An example of selective layer transfer between a donor wafer 600 and an acceptor wafer 610 is shown. Specifically, Fig. 6A 600, 610 before transfer are shown, and Figure 6B Wafers 600, 610 are shown after transfer. In the example shown, non-contiguous regions of the donor wafer 600 are selectively transferred to non-contiguous locations on the acceptor wafer 610. However, in other embodiments, the target region on the donor 600 and the target region on the acceptor 610 may be partially or completely contiguous.

[0108] like Fig. 6AAs shown, prior to transfer, the donor wafer 600 includes a layer of integrated circuit (IC) components 602 (e.g., dies, core particles, interconnects, capacitors, transistors, etc.), which may be partially singulated (e.g., cut down to the underlying wafer 600, but not through the underlying wafer 600). The acceptor wafer 610 includes bonding areas 612 (also referred to as a bonding template) patterned in non-contiguous locations on the surface, which is where the target IC components 602 from the donor 600 will be transferred. For example, in some embodiments, the bonding areas 612 can be raised structures or protrusions (referred to as "mesas") patterned on the surface of the acceptor 612. In addition, in some embodiments, the bonding areas 612 on the acceptor 610 can have a similar footprint as the target IC components 602 on the donor 600. However, in various embodiments, any suitable surface treatment or other technique may be used to control the adhesion levels on different areas of the receptor substrate 610 (e.g., to form adhesion areas and non-adhesion areas for selective transfer), including but not limited to: surface topography changes (e.g., terraces, depressions), use of materials with high adhesion and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among other examples.

[0109] like Figure 6B As shown, after transfer, the target IC components 602 have been transferred from the donor wafer 600 to the acceptor wafer 610. Therefore, the donor wafer 600 includes a blank area 603 where the transferred IC components 602 are located, and the acceptor wafer 610 includes the transferred IC components 602 at locations where the bonding areas 612 are patterned. Specifically, the individual IC components 602 from the donor wafer 600 are now bonded to the individual bonding areas 612 on the acceptor wafer 610.

[0110] Although the illustrated example depicts selective transfer between two wafers, selective transfer may be performed between panels or other substrates of any shape or size, including substrates having non-matching shapes and sizes.

[0111] Figure 7A flow chart 700 for performing a selective layer transfer is shown. In accordance with the present disclosure, it will be understood that the process flow shown is only an exemplary method for performing a selective layer transfer. In addition, the steps of the process flow shown can be performed using any suitable semiconductor fabrication technology. For example, film deposition - such as depositing a layer, filling portions of a layer (e.g., removed portions), and filling via openings - can be performed using any suitable deposition technology (e.g., including chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and / or physical vapor deposition (PVD)). In addition, patterning and removal - such as interconnect patterning, forming via openings, and shaping - can be performed using any suitable technology (e.g., lithography-based patterning / masking and / or etching).

[0112] The flow chart begins at block 702 with receiving a first substrate having a layer of integrated circuit (IC) components, which may be referred to as a donor substrate. In some embodiments, the donor substrate may include a base substrate, a release layer located on the base substrate, and a (partially singulated) layer of IC components located on the release layer.

[0113] In some embodiments, a donor substrate can be formed by: receiving a base substrate; forming a release layer over the base substrate; forming layers of IC components over the release layer (e.g., by forming or transferring the layers of IC components onto the release layer); and partially singulating the layers of IC components (e.g., by cutting through the layers of IC components without cutting through the base substrate).

[0114] In various embodiments, a layer of an IC component may include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, transformers, optical components, and / or any other active or passive circuitry or components.

[0115] The base substrate can be made of one or more materials including elements such as silicon (Si), oxygen (O), carbon (C), hydrogen (H), and / or III-V group elements (e.g., aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb)), including but not limited to: silicon (Si), silicon dioxide (SiO2 or SiO2), silicon on insulator (SOI), quartz, glass, III-V group materials (e.g., gallium nitride (GaN), aluminum gallium nitride (GaN), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium phosphide (InP)), and epoxy resin / resin (e.g., IR or UV transparent epoxy resin).

[0116] The release layer may include one or more layers of different materials, depending on the type of release or debonding technique used. For example, for IR laser debonding, the release layer may include one or more layers of materials that can absorb and / or reflect infrared (IR) electromagnetic radiation, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For UV laser debonding, the release layer may include one or more layers of materials that can absorb ultraviolet (UV) electromagnetic radiation (e.g., an organic polymer such as polyimide). In some embodiments, the release layer may additionally or alternatively include one or more layers of dielectric materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon carbon nitride (SiOCN), aluminum oxide (Al2O3), low-k dielectrics (e.g., carbon-doped oxide (CDO) or porous silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5)) to buffer laser ablation and thermal energy, control thin film interference or adhesion, and / or provide residual adhesion after other materials and / or layers in the release layer are weakened, removed and / or ablated by the laser. Therefore, in some embodiments, the (multiple) release layers may be made of one or more materials including elements such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silicon (Si), oxygen (O), nitrogen (N), hydrogen (H) and carbon (C), including but not limited to any of the materials cited above.

[0117] The flow chart then proceeds to block 704 to receive a second substrate having one or more bonding areas, which may be referred to as an acceptor substrate. In some embodiments, the acceptor substrate may include a base substrate having one or more bonding areas patterned on a surface (e.g., a layer of raised bonding structures or "mesas" located above the base substrate). The acceptor substrate may also optionally include a release layer located above the base substrate (e.g., to enable subsequent debonding of the base substrate after transfer) and / or one or more additional buildup layers and / or IC components.

[0118] In some embodiments, the acceptor substrate can be formed by: receiving a base substrate; optionally forming a release layer on the base substrate; optionally forming additional buildup layers and / or IC components on the base substrate (e.g., on the optional release layer, if included); and forming bonding areas (e.g., bonding structures) on the surface of the acceptor substrate (e.g., on the layers cited above, if included). In some embodiments, the base substrate and optional release layer of the acceptor can be made of any of the materials cited above for the base substrate and release layer of the donor, respectively.

[0119] In some embodiments, the bonding area can include a mesa structure having a similar footprint as the corresponding IC component to be transferred from the donor (although in some cases, the mesa can be slightly larger or smaller than the IC component to accommodate alignment and manufacturing tolerances). The mesa structure can be made of different materials (e.g., dielectric materials, metals, or both), depending on the type of bonding and / or whether electrical connection through the bonding cross-section is required for the subsequently bonded IC component. For example, the mesa structure can include a blanket dielectric structure without conductive contacts (e.g., for dielectric-to-dielectric bonding), a dielectric structure with conductive contacts (e.g., for mixed dielectric and metal bonding), and / or itself includes conductive contacts (e.g., for metal-to-metal bonding). Therefore, in some embodiments, the mesa structure can be made of one or more materials, which include elements such as silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), including but not limited to: inorganic dielectrics (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), and / or silicon nitride carbon (SiCN)), organic dielectrics (e.g., photoresists and adhesives), and / or conductive materials (e.g., metals and alloys (e.g., any of the above-mentioned metal elements and / or their compounds / alloys)).

[0120] However, in various embodiments, any suitable technique(s) may be used to control the adhesion level on different regions of the receptor substrate. For example, various surface treatments (e.g., photolithography or additive manufacturing) may be used to enhance and / or reduce adhesion of selected regions of the receptor substrate, including, but not limited to: modifying the surface topography (e.g., raised regions versus recessed regions, smooth regions versus rough regions), using materials with high adhesion and / or low adhesion (e.g., forming a layer with adhesive material and non-adhesive material in the selected regions), using treatments with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques (e.g., plasma or wet activation), among other examples.

[0121] For example, the surface topography of the receptor substrate can be modified (e.g., using techniques such as deposition, lithography, etching, roughening) to form regions with different adhesion levels, such as raised (e.g., adhesion) regions and recessed (e.g., non-adhesion) regions, smooth (e.g., adhesion) regions and rough (e.g., non-adhesion) regions, etc.

[0122] As another example, the surface of the acceptor substrate can be patterned with a material having high adhesion and / or low adhesion in selected areas. For example, a layer patterned with adhesive materials and non-adhesive materials in different areas can be formed on the acceptor substrate. In some embodiments, the adhesive material can include: silicon dioxide (SiO2) or silicon nitride carbon (SiCN) to promote strong oxide melt bonding, silicon carbide (SiC) to provide lower thermal contact resistance than SiO2 or SiCN, and / or metal to form an electrical connection. In addition, in some embodiments, the non-adhesive material can include silicon nitride (Si3N4) to form a weak bond or no bond.

[0123] As another example, treatment with a hydrophobic material and / or a self-assembled monolayer (SAM) can be used to enhance and / or reduce adhesion in selected areas of a receptor substrate (e.g., using a SAM treatment to create a monolayer with high adhesion and / or low adhesion in selected areas). In some embodiments, the hydrophobic material can include a SAM material, such as an alkyl or fluoroalkyl silane (e.g., ODS, FDTS), a thiol (e.g., hexadecyl mercaptan), a phosphoric acid (e.g., octadecyl or perfluorooctane phosphoric acid), or an alkanoic acid (e.g., heptadecanoic acid). However, non-SAM based materials or membranes can also be used. In some embodiments, the hydrophobic material can include a polymer film, such as a siloxane (e.g., PDMS and derivatives, HMDSO), a silazane (HMDS), a polyolefin (e.g., PP), or a fluorinated polymer (e.g., PTFE, PFPE, PFDA, C4F8 plasma polymerized membrane, etc.). In other embodiments, other hydrophobic materials can be used.

[0124] As another example, surface activation techniques may be used to enhance and / or reduce adhesion in selected areas of the receptor substrate, including but not limited to plasma or wet activation.

[0125] The flow chart then proceeds to block 706 to partially bond the donor substrate (e.g., face-to-face) to the acceptor substrate such that one or more target IC components located on the donor substrate are selectively bonded to one or more bonding regions located on the acceptor substrate. The donor substrate and the acceptor substrate may be partially bonded using any suitable bonding technique, including, but not limited to, hybrid bonding, fusion bonding, and / or adhesive bonding.

[0126] The flow chart then proceeds to block 708 to release the target IC component from the donor substrate and separate the donor substrate from the acceptor substrate. In this way, when the donor substrate and the acceptor substrate are separated, the target IC component is separated from the donor substrate and remains on the acceptor substrate.

[0127] In some embodiments, the donor substrate and the acceptor substrate can be debonded / separated from each other by at least partially releasing the target IC component from the release layer of the donor substrate and then mechanically separating the donor substrate from the acceptor substrate. For example, in some embodiments, the target IC component can be completely released from the donor substrate by selectively debonding the target IC component from the donor release layer using a laser (e.g., an IR or UV laser); or alternatively, the target IC component can be partially released from the donor substrate by weakening the donor release layer using a laser (e.g., an IR or UV laser). After fully or partially releasing the target IC component from the donor, the donor substrate and the acceptor substrate are mechanically separated, and after separation, the target IC component remains bonded to the acceptor and is no longer located on the donor.

[0128] Alternatively or additionally, the donor release layer and receptor bonding structure can be formed of corresponding materials having different bonding strengths so that the target IC component has a stronger bond with the receptor than with the donor, so that when the donor and receptor are mechanically separated, the target IC component is debonded from the donor and remains on the receptor.

[0129] The flowchart then proceeds to box 710 to perform any remaining processing, such as dielectric fill and planarization, attaching additional IC dies or components (e.g., via selective transfer or pick and place assembly), forming interconnects (e.g., vias, traces), attaching the structure substrate, debonding the receptor base substrate (e.g., via an optional receptor release layer), and / or any other processing required for the completed product (e.g., IC package, device, system, etc.).

[0130] The finished product may include a variety of components and circuit systems (some of which may have been selectively transferred), including electrical components (e.g., electronic integrated circuits (EICs), processors, XPUs, controllers, memories), optical components (e.g., optical interfaces, photonic integrated circuits (PICs), optical connectors, optical fibers), and / or radio frequency (RF) or high voltage components (e.g., high voltage electrostatic discharge (ESD) devices, power amplifiers (PAs), low noise amplifiers (LNAs), voltage controlled oscillators (VCOs), surface acoustic wave (SAW) / bulk acoustic wave (BAW) devices or filters, bandpass filters (BPFs), intermediate frequency (IF) amplifiers, frequency synthesizers, mixers, RF digital-to-analog converters (DACs), RF analog-to-digital converters (ADCs), thick gate oxide devices, III-V devices / chiplets, passive RF devices (e.g., interconnects, antennas, and inductors)).

[0131] Furthermore, in some embodiments, the resulting IC package or product can be electrically coupled to a circuit board and / or incorporated into an electronic device or system (eg, with other electronic components).

[0132] At this point, the flow chart can be completed. However, in some embodiments, the flow chart can be restarted, and / or some boxes can be repeated. For example, in some embodiments, the flow chart can be restarted at box 702 to continue to perform selective transfer.

[0133] Blanket wafer laser exposure for rapid selective transfer

[0134] As discussed above, transferring selective areas or dies from a donor substrate to a recipient substrate can address one or more shortcomings of existing methods (e.g., full layer transfer, monolithic IC fabrication, die pick and place assembly) and can enable multiple reuse of the donor substrate. For example, full wafer layer transfer requires removal of unwanted areas after the transfer, which can result in higher costs and lower performance. In addition, pick and place die bonding has lower yields as dies become smaller and more dies are attached, and the ability to scale down die area and thickness is limited because pick and place cannot be used to attach dies / die with certain design parameters (e.g., high aspect ratio dies, sub-millimeter dies, thin dies / layers).

[0135] While selective transfer alleviates the aforementioned limitations of existing methods, it also faces its own unique challenges. For example, in some cases, especially when the transferred area is reduced in size (e.g., die size <1 mm 2), selective debonding (e.g., using laser debonding techniques to release only selective areas from the donor wafer) may be slow, and the percentage of donor wafer transferred to each acceptor wafer (%xfer) becomes lower.

[0136] Another challenge involves handling the wafers for selective debonding processing after bonding the donor and acceptor, which requires an in-plane offset between the wafers for all transfers after the first acceptor wafer. During transportation in a semiconductor factory, automated handling systems and the front opening wafer transfer box (Front Opening Unified Pod, FOUP) that holds the wafers cannot accept these non-circular offset bonded wafer pairs. In addition, existing equipment or tools cannot perform selective debonding on wafer pairs, and even if such equipment or tools are developed, it is impossible to transfer offset bonded wafer pairs between bonding tools and selective debonding tools. Solving the problem of offset bonded wafers requires integrating bonding, selective layer release and debonding into a single tool, which is complex and challenging, and also requires the development of new wafer handling robots to handle offset bonded wafers in the tool, which is even more challenging.

[0137] Thus, the present disclosure shows embodiments of rapid selective layer transfer using blanket wafer laser exposure, including processes, thin film architectures, and tools. For example, a thin structured film is made beneath the selectively transferred layer or die so that blanket laser exposure of the entire wafer is performed only once, after which a bonding / debonding process is used to selectively transfer regions from the donor wafer for each acceptor wafer. This eliminates the slow process of selectively debonding small regions of the wafer each time it is transferred to the acceptor wafer. In addition, the solution utilizes a novel bonding / debonding tool that eliminates any need to handle non-circular offset bonded wafer pairs.

[0138] The described solution (e.g., one or more of the embodiments described herein) provides various advantages. For example, the solution eliminates the slow process of selectively debonding small areas of the wafer each time it is transferred to a recipient wafer - instead, only a blanket laser exposure of each donor wafer using a standard laser debonding tool is required. The selective transfer from the donor to each recipient wafer is controlled by selective bonding to a patterned bonding area (e.g., a table or other bonding mechanism) on the recipient wafer, which is a fast full-wafer process. Because the recipient wafer can be bonded to a pre-exposed donor wafer and then immediately debonded using selective transfer in the same module, the bonding / debonding tool eliminates any need to handle non-circular offset-bonded wafer pairs. In addition, the thin film release layer architecture can be designed to protect the die edges and corners from shock wave damage.

[0139] Figure 8A-8E An exemplary process flow for selective transfer using blanket wafer laser exposure is shown. In the example shown, a blanket laser exposure of the donor wafer 800 is performed (e.g., in a standard laser debonding tool) to weaken the release layer 802, followed by selective bonding / debonding of the donor wafer 800 and the acceptor wafer 810.

[0140] exist Fig. 8A In the embodiment of the present invention, a donor wafer 800 is formed, wherein portions 804a-804b of the selective transfer layer are located on a release layer 802. The release layer 802 may include one or more thin film layers (e.g., a thin metal layer capable of absorbing infrared (IR) light) that enable laser debonding of the portions 804a-804b, and / or structured dielectric and metal layers. Figure 8A-8E , a continuous blanket release layer 802 is shown, but in other embodiments, the release layer 802 may include multiple dielectric and metal layers patterned with a "street pattern" etched through some or all of those layers located between the areas 804a-804b to be selectively transferred.

[0141] Portions 804a-804b of the selective transfer layer may include any combination of one or more layers to be selectively transferred. In the example shown, portions 804a-804b include multiple IC components, such as dies or core particles, and the multiple IC components will be transferred to two different receptor wafers 810a-810b by two selective transfers (e.g., %xfer=50% each transfer). Specifically, a first group of IC components (e.g., portion 804a) will be transferred to a first receptor 810a, and a second group of IC components (e.g., portion 804b) will be transferred to a second receptor 810b. For example, in some embodiments, the two groups of IC components (e.g., portions 804a-804b) can be the same type of die or different types of dies, transferred to different receptors 810a-810b by separate transfers.

[0142] exist Figure 8B In the embodiment, a laser debonding tool 820 is used to perform a blanket scan of the donor wafer 800 using laser exposure, which removes portions of the release layer 802 and / or weakens its structural integrity while still providing residual adhesion to the die / layers 804a-804b to be selectively transferred.

[0143] exist Figure 8C, a donor wafer 800 is partially or selectively bonded to a first acceptor wafer 810a (e.g., using a bonding / debonding tool) having templated bonding areas 812 on its surface. For example, a target IC component 804a for a first transfer from the donor 810a is bonded to the bonding area 812 on the acceptor 810a, while other IC components 804b remain unbonded. In the illustrated embodiment, the bonding area 812 is a raised bonding mesa. However, in other embodiments, the bonding area 812 can be formed using any suitable surface treatment or other technique to control the bonding level in different areas of the acceptor substrate 810a-810b, including but not limited to: surface topography changes (e.g., mesas, depressions), the use of materials with high and / or low adhesion, the use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments, and / or surface activation techniques, and other examples.

[0144] exist Fig.8D 8, the donor wafer 800 is mechanically separated and debonded from the acceptor wafer 810a. Specifically, due to the weakened release layer 802, when the donor wafer 800 and the acceptor wafer 810a are mechanically separated, the target IC component 804a is debonded from the donor 800 and remains on the acceptor 810a. This is because the bond with the acceptor 810a is stronger than the residual bond with the donor 800, because the bonding energy provided by the mesa 812 is greater than the residual bonding energy provided by the weakened release layer 802.

[0145] exist Fig. 8E In the process, the first acceptor wafer 810a is transferred away and the second acceptor wafer 810b is transferred in for the next selective transfer, and the process is repeated. Figure 8C and Fig.8D The steps in the above step can be repeated to transfer another set of IC components 804b to a new receptor 810b (e.g., by selectively bonding / debonding the donor 800 and the receptor 810b). This method can be repeated for any number of receptor wafers 810 as needed. Figure 8C and Fig.8D Steps in .

[0146] Figure 9A-9C Various laser release techniques for selective transfer are shown. Specifically, Fig.9A , Fig. 9B and Fig. 9C Cross-sectional views and plan views of a donor wafer 900 are depicted when performing selective scanning and laser exposure, blanket scanning and selective laser exposure, and blanket scanning and laser exposure techniques, respectively.

[0147] In the example shown, various laser release techniques are performed on a donor wafer 900 , wherein a layer of integrated circuit (IC) dies 904 a - 904 b is located above a release layer 902 .

[0148] exist Fig.9A In the method, laser release is performed using selective scanning and laser exposure techniques. As depicted by laser path 922, over the areas of the release layer 902 that are bonded to the target tube core 904a to be transferred, the donor wafer 900 is selectively scanned and exposed to the laser 920 (e.g., using a galvanometer), thereby removing or weakening these areas of the release layer 902 for subsequent transfer. Since the method has a very short scan length and each tube core 904a requires multiple changes in direction, the method is relatively slow, where each change in direction requires, for example, about 1 millisecond (ms), and there are multiple translations between the selective release areas. As a result, as the tube core 904a-904b becomes smaller, the average scan speed becomes slower. In addition, for each transfer to the recipient wafer, the selective release process must be repeated on the donor wafer 900. The method also requires complex integration of bonding, selective laser release, and transfer of wafer pairs that are debonded and offset bonded.

[0149] exist Fig. 9B In the embodiment of the present invention, laser release is performed using blanket scanning and selective laser exposure techniques. As depicted by laser path 922, the entire donor wafer 900 is blanket scanned, but only the area of ​​the release layer 902 bonded to the target die 904a is selectively exposed to the laser 920. For example, during the blanket scan, the laser 920 can be exposed when scanning over the target die 904a and turned off when scanning over the unselected die 904b. This method is more convenient than Fig.9A The method in is faster because fewer directional changes are required to scan the entire donor wafer 900. However, although the entire donor wafer 900 is scanned, only the target die 904a is released during the scan. Therefore, for each transfer to the recipient wafer, this method requires a full donor wafer scan. The transfer time per die of this method can be calculated as follows: Where "%xfer" represents the percentage of dies (or other selectively transferred components) on the donor wafer that are transferred to each recipient wafer. The transfer time per die increases as the transfer percentage (%xfer) decreases. For example, if only 1 die out of every 10 dies on the donor is transferred at a time, the transfer percentage (%xfer) is 10%, which increases the transfer time per die because more transfers are required. This method also requires complex integration of bonding, selective laser release, and debonding with the transfer of offset bonded wafer pairs.

[0150] exist Fig. 9C In the present invention, laser release is performed using a blanket scan and laser exposure technique. As depicted by laser path 922, the entire donor wafer 900 is blanket scanned and exposed to laser 920, thereby weakening the entire release layer 902 while still providing residual adhesion for the dies 904a-904b. In this way, each donor wafer 900 only needs to undergo a blanket wafer scan / exposure once. Therefore, this method is significantly faster than Figure 9A-9B As an example, for 1mm 2 For a die size of 1000nm, this method may take about 3.6ms per die. Laser release can be performed using a standard laser debonding tool, while subsequent bonding / debonding to a receptor wafer can be performed using a bonding / debonding tool, which provides a much simpler construction than other methods and does not require wafer handling for offset bonding.

[0151] Structural support layer for protecting the selective transfer layer during laser exposure of unbonded wafers

[0152] Figure 10A-10B Laser debonding techniques are shown that put the selectively transferred layer at risk of damage. Fig. 10A In the embodiment of the present invention, a donor substrate 1002 having a release layer 1004 and a selective transfer layer 1006 is placed in contact with a chuck 1010 of a laser debonding tool. The chuck 1010 includes a plurality of micro-pillars 1012 extending upward from the body of the chuck 1010 and having rounded edges to reduce the area of ​​contact between the chuck and the selective transfer layer 1006 during the laser debonding process. The vacuum chuck can serve to keep the wafer flat and stable, thereby allowing the laser 1008 to accurately focus its beam 1014.

[0153] During the laser exposure process, laser 1008 can apply a beam 1014 to release layer 1004 to weaken the layer prior to selectively transferring portions of selective transfer layer 1006. In certain areas, laser-induced ablation pressure and other stresses can crack or even blow holes in selective transfer layer 1006 due to insufficient support from chuck 1010 (e.g., in the area between adjacent micropillars).

[0154] Even for Fig. 10BIn the flat chuck design shown in FIG. 1 , which omits the micropillars, the millimeter (mm) scale (e.g., 1-3 mm wide) vacuum ports 1018 may result in unsupported areas of the selective transfer layer 1006 (due to the much smaller diameter of the laser spot, e.g., ~20-100 μm). Similarly, laser-induced ablation pressure and other stresses during the laser exposure process may cause cracking or more severe damage to the unsupported areas of the selective transfer layer. In addition, the vacuum of the laser debonding tool may also cause localized stresses.

[0155] Fig.11 An exemplary structural support layer 1108 is shown for protecting the selective transfer layer 1106. As depicted, the release layer 1104 is formed on the donor substrate 1102. The selective transfer layer 1106 is formed over (e.g., formed on) the release layer 1104, and the structural support layer 1108 is formed over (e.g., formed on) the selective transfer layer 1106.

[0156] Various embodiments of the present disclosure include adding structural support (e.g., structural support layer 1108) over a thin layer or die (e.g., of the selective transfer layer 1106) to protect the thin layer or die during laser exposure. The structural support layer 1108 can also provide surface protection when it contacts the chuck of the laser debonding tool to prevent the selective transfer layer 1106 from being contaminated by contact with metal or other contaminants of the chuck.

[0157] In some embodiments, the structural support layer 1108 is a temporary support layer on top of a donor substrate (e.g., a wafer) deposited over the selective transfer layer 1106. For example, the structural support layer 1108 can be removed after the laser exposure process is completed (e.g., by etching) and before the selective transfer layer 1106 is selectively transferred to one or more acceptor substrates. In other embodiments, the structural support layer 1108 can remain intact during the selective transfer to the acceptor substrate (e.g., vias can be formed through the structural support layer 1108 for desired connectivity) and subsequent processing.

[0158] In various embodiments, the structural support layer 1108 is thicker than the selective transfer layer 1106 to provide sufficient support to prevent the selective transfer layer 1106 from bending and breaking during laser exposure. In various examples, the structural support layer 1108 can be 1.5 times, 2 times, 3 times, or 5 times thicker than the selective transfer layer 1106. In some embodiments, the structural support layer 1108 has a thickness in the range of ˜1 micron to ˜100 microns, while the selective transfer layer 1106 has a thickness in the range of ˜100 nanometers to ˜1 micron (other suitable thicknesses are contemplated herein).

[0159] In some examples, the structural support layer 1108 is an inorganic film, such as a dielectric deposited (e.g., via plasma enhanced chemical vapor deposition (PECVD)) on the selective transfer layer 1106. For example, the structural support layer 1108 can include oxygen, silicon, carbon, and / or nitrogen. For example, the structural support layer 1108 can include an oxide (e.g., silicon dioxide (e.g., SiO2)) or a nitride (e.g., silicon nitride (e.g., SiNx), silicon carbon nitride (e.g., SiCN), silicon oxynitride (e.g., SiON), or silicon oxycarbon nitride (e.g., SiOCN)). In other examples, the structural support layer 1108 is a spin-on organic layer, such as a photoresist. In various examples, the photoresist can be positive or negative, single component (e.g., polymethyl methacrylate) or multi-component (e.g., phenol formaldehyde / diazo naphthoquinone), or any other photoresist formulation. The structural support layer 1108 can include other suitable spin-on organic layers, such as a silicon dioxide-filled spin-on dielectric or any other spin-on organic layer. In other embodiments, the structural support layer 1108 can include an adhesive (eg, a light-release adhesive) and a layer including glass. Other suitable organic or inorganic dielectrics can be used for the structural support layer 1108.

[0160] For purposes of this disclosure, the term "structural support layer" may be used to refer to one or more physical layers, such as a single material layer or a stack of multiple layers of one or more materials, formed on top of one or more other (e.g., thin) layers (e.g., a selective transfer layer).

[0161] In some embodiments, the structural support layer includes two different film layers. For example, the first film layer can be suitable for gap filling (e.g., to fill the space between discrete portions of the selective transfer layer 1106), or can be part of the fabrication of the selective transfer layer; and the second film layer placed on top of the first film layer can be suitable for structural support and / or device protection functions. In some embodiments, the second layer can be removed at a lower cost or more easily than the first layer, and thus the second layer can be easily applied in a larger volume than the first layer. Therefore, in some examples, the second layer can be thicker than the first layer.

[0162] In the depicted embodiment, the structural support layer 1108 completely fills the gaps (e.g., which may be created via singulation or other processes) between adjacent portions of the selective transfer layer 1106. In other examples, small voids may exist within the incompletely filled gaps, but such voids may be relatively small compared to the width of the gaps and / or the die thickness in order to maintain sufficient strength within the structural support layer 1108 to protect the selective transfer layer 1106.

[0163] Figures 12A-12DAn exemplary process flow for selective layer transfer using a structural support layer is shown.

[0164] Fig. 12A Depicted are a donor substrate 1202, a release layer 1204 formed on the donor substrate 1202, a selective transfer layer 1206 formed on the release layer 1204, and a structural support layer 1208 formed on the selective transfer layer 1206. The structural support layer can be formed on the release layer 1204 and between the discrete portions of the selective transfer layer in gaps between the discrete portions of the selective transfer layer 1206. In various embodiments, the structural support layer 1208 can be formed on the selective transfer layer 1206 using any suitable deposition technique.

[0165] Fig. 12B Laser exposure of a donor substrate 1202 in a laser debonding tool having a chuck 1212 is shown (eg, which may be combined with the above Figure 9A-9C 12). The structural support layer 1208 is placed in contact with the chuck 1212 (e.g., it can be placed on the micro-pillars of the chuck 1212). At this stage, the donor substrate 1202 is flipped over and placed in a laser debonding tool including a laser and chuck 1212. The laser 1210 applies a laser beam 1214 to various locations of the release layer 1204, thereby creating apertures 1216 (or at least weakened areas within the release layer 1204). During laser exposure, the structural support layer 1208 provides support to the selective transfer layer 1206 to prevent cracking and fissures caused by the laser exposure process.

[0166] exist Fig. 12C , the donor substrate 1202 is removed from the laser debonding tool, and the structural support layer 1208 is removed. For example, the structural support layer 1208 can be etched away (eg, via dry etching).

[0167] exist Fig.12D 12, portions of the selective transfer layer 1206 (portions that are now exposed after removing the structural support layer 1208) are transferred to the acceptor substrate 1220. For example, the transferred portions of the selective transfer layer 1206 can be placed in contact with the bonding features 1222 (e.g., templated mesas) formed on the acceptor substrate 1220. The selective transfer can be performed according to any suitable embodiment described herein.

[0168] Figures 13A-13D An exemplary process flow for selective layer transfer using a structural support layer comprising glass and a photo-release adhesive is shown.

[0169] exist Fig.13A1 , a release layer 1304 is formed on a donor substrate 1302. A selective transfer layer 1306 is formed over the release layer 1304. A structural support layer including an adhesive layer 1308 (e.g., a photo-releasing adhesive layer) and a glass layer 1310 (e.g., a layer primarily or substantially comprising glass) is formed over the selective transfer layer 1306.

[0170] Fig. 13B The result is shown after the donor substrate 1302 is flipped over, placed in a laser debonding tool, and exposed to the laser. The application of the laser creates apertures 1312 (or other weakened areas) in the release layer 1304. During the application of the laser, the adhesive layer 1308, in conjunction with the glass layer 1310, provides support to the selective transfer layer 1306 to prevent cracks and breaks in the layer.

[0171] Fig. 13C The result is shown after adhesive layer 1308 and glass layer 1310 have been removed. In one example, to remove adhesive layer 1308 and glass layer 1310, a light source (e.g., a broadband light source) can be applied to adhesive layer 1308 to weaken the bonding energy between adhesive layer 1308 and selective transfer layer 1306, and then, adhesive layer 1308 and glass layer 1310 are peeled off from selective transfer layer 1306. In various examples, before adhesive layer 1308 and glass layer 1310 are removed (e.g., after the light source is applied), the bonding energy at the interface between the adhesive layer and selective transfer layer 1306 is lower than the bonding energy at the interface between release layer 1304 and donor substrate 1302 (such that peeling of the adhesive layer does not impair the attachment of selective transfer layer 1306 to donor substrate 1302 before portions of selective transfer layer 1306 are selectively transferred to one or more receptor substrates).

[0172] exist Fig.13D 13, portions of selective transfer layer 1306 (portions that are now exposed after removing adhesive layer 1308 and glass layer 1310) are transferred to acceptor substrate 1314. For example, the transferred portions of selective transfer layer 1306 can be placed in contact with bonding features 1316 (e.g., templated mesas) formed on acceptor substrate 1314. The selective transfer can be performed according to any suitable embodiment described herein.

[0173] In some embodiments, after the selective transfer has been performed, trace amounts (or greater amounts if the structural support layer is permanent) of residue of the structural support layer may be present at or near the interface between the bonding feature 1316 and the selective transfer layer 1306. For example, portions of the structural support layer 1108 may be present at or near the interface. In some embodiments, the residue may include an organic material containing carbon (e.g., remaining from a layer including a photoresist or adhesive) or hydrogen. In other embodiments, the residue may include oxygen (e.g., remaining from a layer including an oxide) or nitrogen (e.g., remaining from a layer including a nitride). In some embodiments, the interface where the selective transfer layer contacts the bonding feature may be free of residue, but residue may be present on the sides of the portion of the selective transfer layer that is transferred to the recipient substrate (e.g., in regions corresponding to gaps between discrete portions of the selective transfer layer when the selective transfer layer is on a donor substrate).

[0174] Fig.14 An exemplary wafer chuck 1408 is shown having a porous portion 1410 having pores that are small relative to the laser spot size. In this embodiment, the porous portion 1410 interfaces with (e.g., may contact) the selective transfer layer 1406 formed on the donor substrate 1402 having the release layer 1404 and may provide structural support for the selective transfer layer 1406 during application of the laser 1416. In some embodiments, this may alleviate the need for a structural support layer above the selective transfer layer on the donor substrate.

[0175] Wafer chuck 1408 may also include a main portion 1412 and a vacuum port 1414. Although shown simply as a cavity, the cavity (e.g., a via) may extend to a manifold having a path to a vacuum line. Porous portion 1410 may be located above vacuum port 1414 so as not to leave a relatively large portion of selective transfer layer 1406 unsupported during laser debonding. Thus, stress on relatively thin selective transfer layer 1406 may be limited to compressive stress, thereby protecting selective transfer layer 1406 from cracking caused by the laser.

[0176] In some examples, chuck 1408 can be integrated with or attached to a laser debonding tool that also includes laser 1416. Porous portion 1410 and / or main portion 1412 can include any suitable material, such as a ceramic material, aluminum, glass, brass, bronze, stainless steel, or copper. Porous portion 1410 and / or main portion 1412 can be the same material, or can include different materials. In one embodiment, porous portion 1410 includes a ceramic material.

[0177] In various embodiments, the average pore size (e.g., average diameter of the pores) of the porous portion 1410 can be smaller (e.g., much smaller) than the diameter of the spot size of the laser 1416 (e.g., the width of the weakened area in the aperture 1420 or other cases within the release layer 1404 due to laser exposure). In some examples, the average pore size of the porous portion 1410 can be less than 1 / 10 of the spot size of the laser 1416, thereby providing sufficient support for the selective transfer layer 1406. In various examples, the spot size of the laser 1416 can be between 20 and 100 microns, while the average pore size of the porous portion 1410 can be less than 5 microns, less than 3 microns, less than 1 micron, etc.

[0178] The vacuum portion 1414, in conjunction with the porous portion 1410 (which, due to its porosity, may also allow vacuum suction to be applied), provides a suction force to hold the donor substrate 1402 stable while the laser is applied.

[0179] Fig.15 A flow chart for performing a selective layer transfer using a structural support layer is shown. In accordance with the present disclosure, it will be understood that the process flow shown is only one exemplary method for performing a selective layer transfer. In addition, the steps of the process flow shown can be performed using any suitable semiconductor fabrication technology (such as those described herein or other suitable technology).

[0180] The flow chart begins at block 1502, where a first substrate (e.g., a donor substrate) having a layer of integrated circuit (IC) components (e.g., a selective transfer layer), a release layer, and a structural support layer is received. In some embodiments, one or more layers may be formed on the donor substrate (e.g., a release layer on the donor substrate, a layer of IC components on the release layer, and a structural support layer on the layer of IC components).

[0181] In some embodiments, a donor substrate having layers of IC components can be formed by: receiving a donor substrate; forming a release layer over the donor substrate; forming layers of IC components over the release layer (e.g., by forming or transferring the layers of IC components onto the release layer); partially singulating the layers of IC components (e.g., by cutting through the layers of IC components without cutting through the donor substrate); and / or forming a structural support layer over the layers of IC components.

[0182] In various embodiments, a layer of IC components may include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, transformers, optical components, and / or any other active or passive circuitry or other components (e.g., as described herein).

[0183] The donor substrate and the layers of the donor substrate may be made of one or more materials (e.g., Figure 7 those materials described or other suitable materials).

[0184] The flow chart then proceeds to block 1504, where a laser is used to weaken the release layer. For example, any of the techniques described herein (e.g., in combination with Figure 9A-9C ) or other appropriate technique to apply laser exposure.

[0185] The flow chart then proceeds to block 1506, where the structural support layer is removed. The removal process may depend on the type of material included in the structural support layer. In one embodiment, the structural support layer is removed by applying one or more etching materials. In another embodiment (e.g., when the structural support layer includes an adhesive), the structural support layer is exposed to a light source (e.g., a broadband light source) to weaken its bonding strength, and then the adhesive and other materials (e.g., glass) of the structural support layer are stripped off. In other embodiments where the structural support layer will remain on the layer of the IC component during the selective transfer process, this operation may be omitted.

[0186] The flow chart then proceeds to block 1508 to receive a second substrate (which may be referred to as an acceptor substrate) having a layer of one or more bonding structures. In some embodiments, a layer of bonding structures (e.g., bonding areas) may be formed on a surface of the acceptor substrate, and / or the bonding structures may extend upward from the acceptor substrate. A release layer may optionally be formed on the acceptor substrate (e.g., to enable the acceptor substrate to be subsequently debonded after transfer) and / or one or more additional buildup layers and / or IC components.

[0187] In some embodiments, an acceptor substrate having a layer of bonding structure can be formed by: receiving an acceptor substrate; optionally forming a release layer over the acceptor substrate; optionally forming additional buildup layers and / or IC components over the acceptor substrate (e.g., over the optional release layer, if included); and forming a layer of bonding structure on a surface of the acceptor substrate (e.g., over the aforementioned layers, if included).

[0188] In some embodiments, the bonding structure may include a bonding area and / or a mesa structure having a similar footprint as the corresponding IC component to be transferred from the donor. The bonding structure may be made of a different material or have any suitable properties, such as those described herein (e.g., in combination with Figure 7 ) describes those characteristics.

[0189] In some embodiments, the acceptor substrate and the optional release layer located on the acceptor substrate can be made of any of the materials mentioned above (eg, for the donor substrate and the release layer).

[0190] The flow chart then proceeds to block 1510 to partially bond the donor substrate to the acceptor substrate (e.g., face-to-face) such that one or more target IC components located on the donor substrate are selectively bonded to one or more bonding structures located on the acceptor substrate. The donor substrate and the acceptor substrate may be partially bonded using any suitable bonding technique, including, but not limited to, hybrid bonding, fusion bonding, and / or adhesive bonding.

[0191] The flow chart then proceeds to block 1512 to release the target IC component from the donor substrate and separate the donor substrate from the acceptor substrate. When the donor substrate and the acceptor substrate are separated, the target IC component is separated from the donor substrate and remains on the acceptor substrate.

[0192] In some examples, the donor release layer and receptor bonding structure can be formed of corresponding materials having different bonding strengths so that the target IC component has a stronger bond with the receptor than the donor, thereby causing the target IC component to debond from the donor and remain on the receptor when the donor and receptor are mechanically separated.

[0193] The flowchart then proceeds to box 1514 to perform any remaining processing, such as dielectric fill and planarization, attaching additional IC dies or components (e.g., via selective transfer or pick and place assembly), forming interconnects (e.g., vias, traces), attaching a structural substrate, debonding a receptor substrate (e.g., via an optional receptor release layer), and / or any other processing required for a finished product (e.g., an IC package, device, system, etc.).

[0194] The finished product may include a variety of components and circuit systems (some of which may have been selectively transferred), including the above combined Figure 7 Any of the described components and circuitry or other suitable components and circuitry.

[0195] Furthermore, in some embodiments, the resulting IC package or product can be electrically coupled to a circuit board and / or incorporated into an electronic device or system (eg, with other electronic components).

[0196] At this point, the flowchart may be complete. However, in some embodiments, the flowchart may restart, and / or certain blocks may be repeated. For example, in some embodiments, the flowchart may restart at block 1502 to continue performing the selective transfer, or move to block 1520 for a different receptor substrate.

[0197] Protective debonding stack for selective transfer layer

[0198] Fig.16 A debonded stack is shown on a donor substrate 1600. In the depicted embodiment, a release layer 1606 and a selective transfer layer 1610 are formed on the donor substrate 1600.

[0199] During the selective transfer process, as part of the release process of the selective transfer layer 1610 from the donor substrate 1600, a light source (e.g., an infrared (IR) laser) can locally ablate the release layer 1606 to create a cleave plane to facilitate the release of one or more portions of the selective transfer layer 1610 onto the acceptor substrate. However, applying the light source carries the risk of damaging the selective transfer layer 1610 in areas that are not supported by bonding to the acceptor substrate. For example, local ablation may generate pressure or shock waves that may induce localized cracking of the selective transfer layer 1610 and induce mechanical damage.

[0200] Various embodiments of the present disclosure provide a protective debonding stack comprising one or more protective layers that prevent or inhibit cracks before they reach the selective transfer layer. Such a stack reduces the risk of mechanical damage to the selective transfer layer and improves the stability of the debonding process. In various embodiments, the protective layer can prevent the selective transfer layer from cracking during a blanket IR exposure process, wherein an unsupported film layer is present during the blanket IR exposure. In various embodiments, the protective layer(s) are placed between the release layer and the selective transfer layer.

[0201] The protective layer can take any of a variety of forms. In subsequent figures, the protective layer is shown in a variety of different configurations, including transition layers (e.g., Fig.17 in), compressive stress layers (e.g., in Fig.18 ), patterned layers (e.g., Fig.19 and Figure 20A-Figure 20E ), and reflector stacks (e.g., in Fig.21 ). Any of these layers can provide protection to the selective transfer layer from cracking due to attractive forces induced by the application of laser during ablation of the release layer 1606.

[0202] The release layer 1606 may include one or more layers of different materials, depending on the type of release or debonding technique used. For example, for IR laser debonding, the release layer may include one or more layers of materials that can absorb and / or reflect infrared (IR) electromagnetic radiation, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For UV laser debonding, the release layer may include one or more layers of materials that can absorb ultraviolet (UV) electromagnetic radiation (e.g., an organic polymer such as polyimide). In some embodiments, the release layer may additionally or alternatively include one or more layers of dielectric materials (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), aluminum oxide (Al2O3), low-k dielectrics (e.g., carbon-doped oxide (CDO) or porous silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5)) to buffer laser ablation and thermal energy, control thin film interference or adhesion, and / or other dielectric materials in the release layer. Other materials and / or layers are laser weakened, removed and / or ablated to provide residual adhesion. Thus, in some embodiments, the release layer(s) may be made of one or more materials including elements such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silicon (Si), oxygen (O), nitrogen (N), hydrogen (H), and carbon (C), including but not limited to any of the materials cited above. In various embodiments, release layer 1606 may include any of the materials described in the other release layers (e.g., 102, 112) described herein.

[0203] The selective transfer layer 1610 may be formed over the other layers. When the selective transfer layer 1610 is transferred to the acceptor substrate, one or more of the other layers of the donor substrate may also be transferred. Since the donor substrate may be flipped over and then placed on the acceptor substrate, the resulting stack may include a portion of the selective transfer layer 1610 located on the acceptor substrate and a protective layer located over the selective transfer layer. In some embodiments, the protective layer may then be removed (e.g., via etching), or the protective layer may be retained during subsequent processing.

[0204] In some embodiments, a tough layer can be formed within the release layer (e.g., above the metal layer absorbed by the laser). The tough layer can include a material with relatively high fracture toughness. In some embodiments, the tough layer can cause the entire debonded stack to have a fracture toughness greater than 0.9 megapascals times the square root of the distance in meters (MPa m^1 / 2) (e.g., greater than the fracture toughness of silicon dioxide or silicon). Adding a tough layer can increase the plastic region and can prevent cracking due to stress caused by the laser.

[0205] In various embodiments, the tough layer may primarily or substantially include a metal (e.g., tungsten (W), nickel (Ni), or titanium (Ti)) or a ceramic material (e.g., silicon nitride (SiN), silicon carbide (SiC), or aluminum oxide (Al2O3)). Other materials described above for the release layer may also be used as a tough layer to prevent cracking.

[0206] Fig.17 A protective debonding stack including a transition layer 1712 is shown formed on a donor substrate 1700. The stack includes a release layer 1706 formed on a donor substrate (e.g., over a base substrate), a transition layer 1712 formed over the release layer 1706, and a selective transfer layer 1710 formed over the transition layer 1712.

[0207] The transition layer 1712 can undergo a phase change in response to the application of stress (e.g., local stress caused by ablation pressure or crack extension caused by the application of laser). The phase change causes a local volume change (increasing the volume of the material within the transition layer 1712), which prevents rupture or prevents cracks from propagating from the release layer 1706 to the selective transfer layer 1710.

[0208] In various embodiments, the transition layer 1712 may include yttrium-doped zinc oxide (YZO), hafnium-doped zinc oxide (HZO), or other suitable phase change materials. In some embodiments, the transition layer may replace a dielectric layer within the release layer (e.g., above a metal layer that is absorbed by the laser).

[0209] Fig.18 A protective debonding stack including a compressive stress layer 1812 formed on a donor substrate 1800 is shown. The stack includes a release layer 1806 formed on a donor substrate (e.g., above a base substrate), a compressive stress layer 1812 formed on the release layer 1806, and a selective transfer layer 1810 formed on the compressive stress layer 1812.

[0210] The compressive stress layer 1812 can have a relatively high compressive stress. For example, in some embodiments, the compressive stress can be greater than the compressive stress of the selective transfer layer 1810 and / or the release layer 1806. In one example, the compressive stress of the material in the compressive stress layer 1812 can be greater than 500 MPa. The compressive stress layer 1812 can include one or more films that will produce localized compression around the crack tip, thereby effectively pushing back the crack and preventing the crack from opening further. In a specific embodiment, the compressive stress layer 1812 includes silicon nitride.

[0211] Fig.19 A protective debonding stack including a patterned layer 1912 formed on a donor substrate 1900 is shown. The stack includes a release layer 1906 formed on a donor substrate (e.g., over a base substrate), a patterned layer formed over the release layer 1906, and a selective transfer layer 1910 formed over the patterned layer 1912.

[0212] The patterned layer 1912 may include a first material and a second material different from the first material. In various embodiments, the first material may form a pattern (e.g., a strip, pad, column, or other suitable shape) within the patterned layer 1912, and the second material may fill the remaining volume of the patterned layer 1912 (or other portions of the patterned layer). Thus, the first material may form a plurality of inclusions, and these inclusions may be disconnected from one another (in other embodiments, one or more inclusions may be connected to one or more other inclusions). The patterned film with inclusions increases the fracture toughness of the entire stack and introduces a crack reversal mechanism in the stack.

[0213] In various embodiments, the first material or the second material may include an oxide, a nitride, a metal, or a metal alloy. In some examples, the first material includes an oxide and the second material includes a metal, or vice versa. In other examples, the first material includes an oxide and the second material includes a nitride, or vice versa. In some further examples, the first material includes a nitride and the second material includes a metal, or vice versa. In various embodiments, the patterned layer 1912 may include one or more shapes (e.g., which may be the first material or the second material) that include a metal, but the metal shape is not connected to any circuit system (e.g., of the selective transfer layer 1910) and does not carry current.

[0214] Figure 20A-Figure 20E An exemplary patterned layer is shown. Fig. 20A A cross-sectional view of an exemplary patterned layer is shown, which may correspond to a cross-sectional view through Fig. 20B or Fig. 20C A cross section taken along the dashed line of any of the plan views of the exemplary patterned layers depicted in FIG. Fig.20D A cross-sectional view of an exemplary patterned layer is shown, corresponding to a cross-sectional view through Fig.20E A cross section taken along the dashed line of a plan view of an exemplary patterned layer is depicted.

[0215] Fig. 20A Depicted is a first material 2002 patterned into vertical lines in a cross section and a second material 2004 occupying spaces not occupied by the first material. In some embodiments, the shapes formed by the first material can have a common spacing across the width and / or length of the patterned layer. In other embodiments, the distance between various pairs of adjacent shapes can be different.

[0216] Fig. 20B Depicts the corresponding Fig. 20A Plan view of the patterned layer in . Fig. 20A The vertical line formed by material 2002 shown in FIG. Fig. 20B 2004 extends as horizontal lines on the patterned layer shown in , with a second material 2004 formed between the lines.

[0217] Fig. 20C Another plan view of an exemplary patterned layer is depicted. In this embodiment, an additional set of horizontal lines orthogonal to the other horizontal lines are included to further improve the protection provided by the patterned layer.

[0218] Introduce lines containing (e.g. Figure 20A-20C A patterned layer of lines such as those shown in or other lines can cause crack bridging as a toughening mechanism for the stack. If a crack attempts to propagate toward the selective transfer layer, the line can act as a bridge connecting the two edges of the crack.

[0219] Fig.20D A first material 2002 is depicted patterned into vertical columns. Fig.20E A plan view of a vertical column is shown. In this embodiment, the vertical column has a square horizontal cross-section, although other embodiments may have a cross-section of any suitable shape. The respective column is surrounded by a second material 2004.

[0220] Fig.21 Protective debonding stacks including a reflector stack 2112 formed on a donor substrate 2100 are shown. Each exemplary stack includes a release layer 2106 formed on a donor substrate (e.g., over a base substrate), a reflector stack 2112 formed over the release layer 2106, and a selective transfer layer 2110 formed over the reflector stack 2112.

[0221] The reflector stack 2112 may include a Bragg reflector type structure having alternating layers of acoustically impedance mismatched materials that are capable of reflecting ablation-induced shock waves and reducing dynamic strains transferred to the selectively transferred layer 2110. The reflector stack 2112 may include different materials that are periodically repeated within the stack. For example, in the depicted embodiment, a layer of a first material 2114 is stacked on a layer of a second material 2116, which in turn is stacked on another layer of the first material 2114, which is stacked on another layer of the second material 2116, and so on. In some embodiments, the first material / second material pair may include W / SiO2, Mo / SiO2, Mo / AlN, W / AlN, W / Al, Mo / Al, or Mo / Ti, although other suitable pairs are contemplated by the present disclosure.

[0222] The combination is a pair of high acoustic impedance and low acoustic impedance. Although any combination of different materials is effective, the greater the difference, the more efficient it is. The thickness of each material can range between 100nm and 5μm.

[0223] Fig. 22 A flow chart 2200 for performing a selective layer transfer using a protective debonding stack is shown. In light of the present disclosure, it will be understood that the process flow shown is only one exemplary method for performing a selective layer transfer. Furthermore, the steps of the process flow shown may be performed using any suitable semiconductor fabrication techniques, such as those described herein or other suitable techniques.

[0224] The flowchart begins at block 2202 where a first substrate (eg, a donor substrate) having a layer of integrated circuit (IC) components (eg, a selective transfer layer), a release layer, and a protective layer is received. In some embodiments, one or more additional layers may be located on the donor substrate.

[0225] In some embodiments, a donor substrate having layers of IC components can be formed by: receiving a donor substrate; forming a release layer over the donor substrate; forming a protective layer over the release layer; and forming layers of IC components over the release layer (e.g., by forming or transferring the layers of IC components onto the release layer), and / or partially singulating the layers of IC components (e.g., by cutting through the layers of IC components without cutting through the donor substrate).

[0226] In various embodiments, a layer of IC components may include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, transformers, optical components, and / or any other active or passive circuitry or other components (e.g., as described herein).

[0227] The donor substrate and its various layers (e.g., release layer, protective layer, selective transfer layer) can be made of various materials (e.g., those described above (e.g., in combination with Figure 1A-Figure 7 or Figure 16-Figure 21 or elsewhere herein) or other suitable materials).

[0228] The flow chart then proceeds to block 2204, where a laser is applied to the release layer. For example, any of the techniques described herein (e.g., in combination with Figure 9A-9C ) or other suitable technique. The laser exposure can be applied before the donor substrate is placed in contact with the receptor substrate or after the donor substrate and the receptor substrate are at least partially engaged (e.g., when the donor substrate contacts the receptor substrate before completing the selective transfer).

[0229] The flow chart then proceeds to block 2206, where the target IC component is released from the donor substrate and the donor substrate and acceptor substrate (which may have any suitable characteristics of other acceptor substrates described herein) are separated. When the donor substrate and acceptor substrate are separated, the target IC component is separated from the donor substrate and remains on the acceptor substrate.

[0230] The flowchart then proceeds to box 2208 to perform any remaining processing, such as removing (e.g., etching away) protective layers or other underlying layers transferred from the donor substrate (although in some embodiments, the protective layer may remain intact in the final product), dielectric fill and planarization, attaching additional IC dies or components (e.g., via selective transfer or pick and place assembly), forming interconnects (e.g., vias, traces), attaching a structural substrate, debonding a receptor substrate (e.g., via an optional receptor release layer), and / or any other processing required for a finished product (e.g., an IC package, device, system, etc.).

[0231] The finished product may include a variety of components and circuit systems (some of which may have been selectively transferred), including the above combined Figure 7 Any of the described components and circuitry or other suitable components and circuitry.

[0232] Furthermore, in some embodiments, the resulting IC package or product can be electrically coupled to a circuit board and / or incorporated into an electronic device or system (eg, with other electronic components).

[0233] At this point, the flowchart may be complete. However, in some embodiments, the flowchart may restart, and / or certain blocks may be repeated. For example, in some embodiments, the flowchart may restart at block 2202 to continue performing the selective transfer, or move to block 2206 for a different receptor substrate.

[0234] Exemplary Embodiments

[0235] Fig.23 2302, wherein the individual dies may include dies selectively transferred from a donor wafer or dies integrated with such dies in a system as disclosed herein. Wafer 2300 may be composed of semiconductor material and may include one or more dies 2302 having integrated circuit structures formed on a surface of wafer 2300. A single die 2302 may be a repeating unit of an integrated circuit product including any suitable integrated circuit. After completion of the fabrication of the semiconductor product, wafer 2300 may undergo a singulation process in which the dies 2302 are separated from one another to provide discrete "chips" of an integrated circuit product. Die 2302 may include one or more transistors, supporting circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 2300 or die 2302 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 2302. For example, a memory array formed by multiple memory devices may be coupled to a processor unit (e.g., Fig. 27 The processor unit 2702 in the embodiment of the present invention or other logic units configured to store information in the memory device or execute instructions stored in the memory array are formed on the same die 2302. In some embodiments, individual microelectronic assemblies of the microelectronic assemblies disclosed herein can be manufactured using a die-to-wafer assembly technique in which some dies are attached to a wafer 2300 including other dies, and the wafer 2300 is subsequently singulated.

[0236] Fig.24 2302 ( Fig.23 ). The integrated circuit device 2400 may be formed on a die substrate 2402 (eg, Fig.23 2300) and may be included in a die (e.g., Fig.23The die substrate 2402 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). For example, the die substrate 2402 may include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 2402 may be formed using alternative materials that may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The die substrate 2402 may also be formed using other materials classified as II-VI, III-V, or IV groups. Although some examples of materials that may form the die substrate 2402 are described herein, any material that may serve as the basis for the integrated circuit device 2400 may be used. The die substrate 2402 may be a singulated die (e.g., Fig.23 2302 in the die) or wafer (e.g., Fig.23 A portion of wafer 2300).

[0237] The integrated circuit device 2400 may include one or more device layers 2404 disposed on a die substrate 2402. The device layer 2404 may include features of one or more transistors 2440 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 2402. The transistor 2440 may include, for example, one or more source and / or drain (S / D) regions 2420, a gate 2422 for controlling the flow of current between the S / D regions 2420, and one or more S / D contacts 2424 for routing electrical signals to / from the S / D regions 2420. The transistor 2440 may include additional features that are not depicted for clarity, such as device isolation regions, gate contacts, etc. The transistor 2440 is not limited to Fig.24 The types and configurations described in the drawings and may include a variety of other types and configurations (e.g., planar transistors, non-planar transistors, or a combination of both). Non-planar transistors may include FinFET transistors (e.g., dual-gate transistors or tri-gate transistors), and all-around gate transistors or all-around gate transistors (e.g., nanoribbon, nanosheet, or nanowire transistors).

[0238] Figure 25A-Figure 25D is a simplified perspective view of an exemplary planar transistor, a FinFET transistor, a gate-all-around transistor, and a stacked gate-all-around transistor. Figure 25A-Figure 25D The transistor shown in FIG. 25 is formed on a substrate 2516 having a surface 2508. An isolation region 2514 separates the source and drain regions of the transistor from other transistors and a body region 2518 of the substrate 2516.

[0239] Fig.25A is a perspective view of an exemplary planar transistor 2500 including a gate 2502 that controls current flow between a source region 2504 and a drain region 2506. Transistor 2500 is planar because source region 2504 and drain region 2506 are planar relative to substrate surface 2508.

[0240] Fig.25B is a perspective view of an exemplary FinFET transistor 2520 that includes a gate 2522 that controls current flow between a source region 2524 and a drain region 2526. Transistor 2520 is non-planar because source region 2524 and drain region 2526 include a "fin" that extends upward from a substrate surface 2528. Because gate 2522 surrounds three sides of the semiconductor fin extending from source region 2524 to drain region 2526, transistor 2520 can be considered a tri-gate transistor. Fig.25B One S / D fin is shown extending through the gate 2522 , but multiple S / D fins may extend through the gate of the FinFET transistor.

[0241] Fig.25C is a perspective view of a gate all around (GAA) transistor 2540 including a gate 2542 that controls current flow between a source region 2544 and a drain region 2546. Transistor 2540 is non-planar because source region 2544 and drain region 2546 are elevated from substrate surface 2528.

[0242] Fig.25D 2560 includes a gate 2562 that controls current flow between multiple elevated source regions 2564 and multiple elevated drain regions 2566. Transistor 2560 is a stacked GAA transistor because the gate controls current flow between multiple elevated S / D regions stacked on top of each other. Transistors 2540 and 2560 are considered to be all-around gate transistors because the gate surrounds all sides of the semiconductor portion extending from the source region to the drain region. Depending on the width of the semiconductor portion extending through the gate (e.g., widths 2548 and 2568 of transistors 2540 and 2560, respectively), transistors 2540 and 2560 may alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors.

[0243] Back to Fig.24, transistor 2440 may include a gate 2422 formed of at least two layers (i.e., a gate dielectric and a gate electrode). The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0244] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when a high-k material is used.

[0245] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 2440 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers or include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers may be included for other purposes, such as barrier layers.

[0246] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0247] In some embodiments, when viewed from a cross section of the transistor 2440 along the source-channel-drain direction, the gate electrode may consist of or include a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 2402 and two sidewall portions substantially perpendicular to the top surface of the die substrate 2402. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 2402 and does not include a sidewall portion substantially perpendicular to the top surface of the die substrate 2402. In other embodiments, the gate electrode may consist of a combination of a U-shaped structure and a planar non-U-shaped structure, or include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0248] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to sandwich the gate stack therebetween. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0249] The S / D region 2420 may be formed within the die substrate 2402 and adjacent to the gate 2422 of the single transistor 2440. The S / D region 2420 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 2402 to form the S / D region 2420. An annealing process may follow the ion implantation process, which activates the dopant and diffuses it further into the die substrate 2402. In the latter process, the die substrate 2402 may first be etched to form a recess at the location of the S / D region 2420. Then, an epitaxial deposition process may be performed to fill the recess with a material for making the S / D region 2420. In some embodiments, the S / D region 2420 may be made using a silicon alloy (e.g., silicon germanium or silicon carbide). In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials (eg, germanium or III-V materials or alloys) may be used to form the S / D region 2420. In further embodiments, the S / D region 2420 may be formed using one or more layers of metals and / or metal alloys.

[0250] The device layer 2404 may be provided with one or more interconnect layers (in Fig.24 2406-2410) to route electrical signals (e.g., power and / or input / output (I / O) signals) to and / or from devices (e.g., transistors 2440) of device layer 2404. For example, conductive features (e.g., gates 2422 and S / D contacts 2424) of device layer 2404 can be electrically coupled to interconnect structures 2428 of interconnect layers 2406-2410. One or more interconnect layers 2406-2410 can form a metallization stack (also referred to as an "ILD stack") 2419 of integrated circuit device 2400.

[0251] Interconnect structures 2428 (eg, wires) may be arranged within interconnect layers 2406-2410 to route electrical signals according to a variety of designs; in particular, the arrangement is not limited to Fig.24 The specific configuration of interconnect structure 2428 is depicted in FIG. Fig.24 A specific number of interconnect layers 2406 - 2410 are depicted in FIG. 2 , but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

[0252] In some embodiments, the interconnect structure 2428 may include a line 2428a and / or a via 2428b filled with a conductive material (e.g., metal). The line 2428a may be arranged to route electrical signals in a direction substantially parallel to a plane of the surface of the die substrate 2402 on which the device layer 2404 is formed. For example, the line 2428a may route electrical signals in a direction in and out of the page and / or in a direction across the page. The via 2428b may be arranged to route electrical signals in a direction substantially perpendicular to a plane of the surface of the die substrate 2402 on which the device layer 2404 is formed. In some embodiments, the via 2428b may electrically couple the lines 2428a of different interconnect layers 2406-2410 together.

[0253] like Fig.24As shown, the interconnect layers 2406-2410 may include a dielectric material 2426 disposed between interconnect structures 2428. In some embodiments, the dielectric material 2426 disposed between the interconnect structures 2428 in different ones of the interconnect layers 2406-2410 may have different compositions; in other embodiments, the composition of the dielectric material 2426 between different interconnect layers 2406-2410 may be the same. The device layer 2404 may also include a dielectric material 2426 disposed between the transistor 2440 and the bottom layer of the metallization stack. The dielectric material 2426 included in the device layer 2404 may have a different composition than the dielectric material 2426 included in the interconnect layers 2406-2410; in other embodiments, the composition of the dielectric material 2426 in the device layer 2404 may be the same as the dielectric material 2426 included in any one of the interconnect layers 2406-2410.

[0254] A first interconnect layer 2406 (referred to as metal 1 or "M1") can be formed directly on the device layer 2404. In some embodiments, as shown, the first interconnect layer 2406 can include lines 2428a and / or vias 2428b. The lines 2428a of the first interconnect layer 2406 can be coupled to contacts (e.g., S / D contacts 2424) of the device layer 2404. The vias 2428b of the first interconnect layer 2406 can be coupled to the lines 2428a of the second interconnect layer 2408.

[0255] A second interconnect layer 2408 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 2406. In some embodiments, the second interconnect layer 2408 may include vias 2428b to couple the wires 2428 of the second interconnect layer 2408 with the wires 2428a of the third interconnect layer 2410. Although the wires 2428a and the vias 2428b are structurally drawn with lines within a single interconnect layer for clarity, in some embodiments, the wires 2428a and the vias 2428b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0256] A third interconnect layer 2410 (referred to as metal 3 or "M3") (and additional interconnect layers, as needed) may be formed successively on the second interconnect layer 2408 according to similar techniques and constructions as described in connection with the second interconnect layer 2408 or the first interconnect layer 2406. In some embodiments, interconnect layers that are "higher up" (i.e., farther from the device layer 2404) in the metallization stack 2419 in the integrated circuit device 2400 may be thicker than interconnect layers lower in the metallization stack 2419, with lines 2428a and vias 2428b in higher interconnect layers being thicker than lines and vias in lower interconnect layers.

[0257] The integrated circuit device 2400 may include a solder resist material 2434 (eg, polyimide or similar material) formed on the interconnect layers 2406-2410 and one or more conductive contacts 2436. Fig.24 , the conductive contact 2436 is shown as taking the form of a bonding pad. The conductive contact 2436 can be electrically coupled to the interconnect structure 2428 and configured to route electrical signals of the transistor(s) 2440 to an external device. For example, a solder joint can be formed on one or more of the conductive contacts 2436 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 2400 to another component (e.g., a printed circuit board). The integrated circuit device 2400 may include additional or alternative structures to route electrical signals from the interconnect layers 2406-2410; for example, the conductive contacts 2436 may include other similar features (e.g., pillars) for routing electrical signals to external components.

[0258] In some embodiments where the integrated circuit device 2400 is a double-sided die, the integrated circuit device 2400 may include another metallization stack (not shown) on the opposite side of the device layer(s) 2404. The metallization stack may include a plurality of interconnect layers as discussed above with reference to the interconnect layers 2406-2410 to provide conductive paths (e.g., including conductive lines and vias) between the device layer(s) 2404 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 2400 from the conductive contacts 2436.

[0259] In other embodiments where the integrated circuit device 2400 is a double-sided die, the integrated circuit device 2400 may include one or more through silicon vias (TSVs) through the die substrate 2402; these TSVs may contact the device layer(s) 2404 and may provide a conductive path between the device layer(s) 2404 and additional conductive contacts (not shown) located on a side of the integrated circuit device 2400 opposite the conductive contacts 2436. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from conductive contacts located on a side of the integrated circuit device 2400 opposite the conductive contacts 2436 to the transistor 2440 and any other components integrated into the integrated circuit device (e.g., die) 2400, and the metallization stack 2419 may be used to route I / O signals from the conductive contacts 2436 to the transistor 2440 and any other components integrated into the integrated circuit device (e.g., die) 2400.

[0260] A plurality of integrated circuit devices 2400 may be stacked, wherein one or more TSVs in a single stacked device provide a connection between one device in the device and any device in the other devices in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies may be stacked on top of a substrate integrated circuit die, and the TSVs in the HBM die may provide a connection between a single HBM and the substrate integrated circuit die. The conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine pitch solder bumps (microbumps).

[0261] Fig.26 2600, which may include IC components (e.g., dies) selectively transferred from a donor wafer as disclosed herein. In some embodiments, the integrated circuit device assembly 2600 may be a microelectronic assembly. The integrated circuit device assembly 2600 includes a plurality of components disposed on a circuit board 2602 (which may be a motherboard, a system board, a mainboard, etc.). The integrated circuit device assembly 2600 includes components disposed on a first side 2640 of the circuit board 2602 and an opposing second side 2642 of the circuit board 2602; in general, the components may be disposed on one or both of the sides 2640 and 2642.

[0262] In some embodiments, circuit board 2602 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. A single metal layer includes conductive traces. Any one or more of the metal layers may be formed in accordance with a desired circuit pattern to route electrical signals between components coupled to circuit board 2602 (optionally, in conjunction with other metal layers). In other embodiments, circuit board 2602 may be a non-PCB substrate. Fig.26 The integrated circuit device assembly 2600 shown in FIG. 1 includes a package structure on an interposer 2636 coupled to a first side 2640 of a circuit board 2602 via a coupling component 2616. The coupling component 2616 can electrically and mechanically couple the package structure on the interposer 2636 to the circuit board 2602 and can include solder balls (e.g., Fig.26 as shown), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, a bottom fill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0263] Package-on-interposer structure 2636 may include integrated circuit component 2620 coupled to interposer 2604 via coupling component 2618. Coupling component 2618 may take any suitable form for the application, such as those discussed above with reference to coupling component 2616. Fig.26 A single integrated circuit component 2620 is shown in FIG. 2 , but multiple integrated circuit components may be coupled to interposer 2604; indeed, additional interposers may be coupled to interposer 2604. Interposer 2604 may provide an intervening substrate for bridging circuit board 2602 and integrated circuit component 2620.

[0264] Integrated circuit component 2620 may be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (eg, Fig.23 The tube core 2302, Fig.24 The integrated circuit device 2400 in the package includes one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit die and the packaging substrate are encapsulated in a housing material such as metal, plastic, glass or ceramic. In one example of an unpackaged integrated circuit component 2620, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 2604. The integrated circuit component 2620 may include one or more computing system components, such as one or more processor units (e.g., a system on a chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller. In some embodiments, the integrated circuit component 2620 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0265] In embodiments where integrated circuit component 2620 includes multiple integrated circuit dies, the dies may be of the same type (homogeneous multi-die integrated circuit component) or of two or more different types (heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0266] In addition to including one or more processor units, the integrated circuit component 2620 may also include additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where the integrated circuit component includes multiple integrated circuit dies, the integrated circuit dies may be formed by a packaging substrate, one or more silicon interposers, one or more silicon bridges (e.g., embedded in the packaging substrate), or a plurality of silicon interposers. Embedded multi-die interconnect bridge (EMIB)) or a combination thereof to provide interconnection between dies.

[0267] In general, interposer 2604 can extend connections to a wider pitch or reroute connections to different connections. For example, interposer 2604 can couple integrated circuit component 2620 to a set of ball grid array (BGA) conductive contacts of coupling component 2616 for coupling to circuit board 2602. Fig.26 In the embodiment shown in FIG, integrated circuit component 2620 and circuit board 2602 are attached to opposite sides of interposer 2604; in other embodiments, integrated circuit component 2620 and circuit board 2602 can be attached to the same side of interposer 2604. In some embodiments, three or more components can be interconnected through interposer 2604.

[0268] In some embodiments, the interposer 2604 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the interposer 2604 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polymer material such as polyimide. In some embodiments, the interposer 2604 may be formed of alternative rigid or flexible materials, which may include the same materials as those described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 2604 may include metal interconnects 2608 and vias 2610, including but not limited to through-hole vias 2610-1 (which extend from the first side 2650 of the interposer 2604 to the second side 2654 of the interposer 2604), blind vias 2610-2 (which extend from the first side 2650 or the second side 2654 of the interposer 2604 to the internal metal layer), and buried vias 2610-3 (which connect the internal metal layer).

[0269] In some embodiments, interposer 2604 may include a silicon interposer. Through silicon vias (TSVs) extending through the silicon interposer may connect connectors on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 2604 including a silicon interposer may further include one or more routing layers to route connectors on a first side of interposer 2604 to an opposite second side of interposer 2604.

[0270] Interposer 2604 may also include embedded devices 2614, which include both passive devices and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on interposer 2604. Interposer-on-package structure 2636 may take the form of any interposer-on-package structure known in the art.

[0271] The integrated circuit device assembly 2600 may include an integrated circuit component 2624 coupled to the first side 2640 of the circuit board 2602 via a coupling component 2622. The coupling component 2622 may take the form of any of the embodiments discussed above with reference to the coupling component 2616, and the integrated circuit component 2624 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 2620.

[0272] Fig.26 The integrated circuit device assembly 2600 shown in FIG. 26 includes a package-on-package structure 2634 coupled to the second side 2642 of the circuit board 2602 by a coupling component 2628. The package-on-package structure 2634 may include an integrated circuit component 2626 and an integrated circuit component 2632 coupled together by a coupling component 2630, such that the integrated circuit component 2626 is disposed between the circuit board 2602 and the integrated circuit component 2632. The coupling components 2628 and 2630 may take the form of any embodiment of the coupling component 2616 discussed above, and the integrated circuit components 2626 and 2632 may take the form of any embodiment of the integrated circuit component 2620 discussed above. The package-on-package structure 2634 may be constructed according to any package-on-package structure known in the art.

[0273] Fig. 272600, which may include IC components (e.g., dies) selectively transferred from a donor wafer as disclosed herein. For example, any suitable components of electrical device 2700 may include one or more of integrated circuit device assembly 2600, integrated circuit component 2620, integrated circuit device 2400, integrated circuit die 2302, or other components disclosed herein. Fig. 27 2700, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the electrical device 2700 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are fabricated on a single system-on-chip (SoC) die.

[0274] Additionally, in various embodiments, the electrical device 2700 may not include Fig. 27 , but the electrical device 2700 may include interface circuitry for coupling to one or more of the components. For example, the electrical device 2700 may not include the display device 2706, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 2706 may be coupled. In another set of examples, the electrical device 2700 may not include the audio input device 2724 or the audio output device 2708, but may include audio input or output device interface circuitry (e.g., connector and support circuitry) to which the audio input device 2724 or the audio output device 2708 may be coupled.

[0275] The electrical device 2700 may include one or more processor units 2702 (e.g., one or more processor units). As used herein, the term "processor unit", "processing unit" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 2702 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. In this way, the processor unit may be referred to as an XPU (or xPU).

[0276] The electrical device 2700 may include a memory 2704, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-voltage memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 2704 may include memory located on the same integrated circuit die as the processor unit 2702. The memory may be used as a cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0277] In some embodiments, the electrical device 2700 may include one or more processor units 2702 that are heterogeneous or asymmetric with another processor unit 2702 in the electrical device 2700. There may be a variety of differences between the processing units 2702 in the system in terms of a range of quality criteria including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences can effectively manifest themselves as asymmetry and heterogeneity between the processor units 2702 in the electrical device 2700.

[0278] In some embodiments, the electrical device 2700 may include a communication component 2712 (e.g., one or more communication components). For example, the communication component 2712 may manage wireless communications for transmitting data to and from the electrical device 2700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transmit data through a non-solid medium using modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain wires.

[0279] The communication component 2712 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) project and any revisions, updates and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed conformance and interoperability testing for the IEEE 802.16 standard. The communication component 2712 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 2712 can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 2712 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other embodiments, the communication component 2712 can operate according to other wireless protocols. The electrical device 2700 may include an antenna 2722 to facilitate wireless communications and / or receive other wireless communications (e.g., amplitude modulation (AM) or frequency modulation (FM) radio transmissions).

[0280] In some embodiments, the communication component 2712 can manage wired communications, such as electrical, optical, or any other appropriate communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 2712 can include multiple communication components. For example, the first communication component 2712 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication component 2712 can be dedicated to longer-range wireless communications, such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or other. In some embodiments, the first communication component 2712 can be dedicated to wireless communications, and the second communication component 2712 can be dedicated to wired communications.

[0281] The electrical device 2700 may include a battery / power circuit system 2714. The battery / power circuit system 2714 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the electrical device 2700 to an energy source separate from the electrical device 2700 (e.g., AC line power).

[0282] The electrical device 2700 may include a display device 2706 (or corresponding interface circuitry as discussed above). The display device 2706 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0283] The electrical device 2700 may include an audio output device 2708 (or corresponding interface circuitry as discussed above). The audio output device 2708 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0284] The electrical device 2700 may include an audio input device 2724 (or a corresponding interface circuit system as discussed above). The audio input device 2724 may include any embedded or wired or wirelessly connected device that produces a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a musical instrument digital interface (MIDI) output). The electrical device 2700 may include a global navigation satellite system (GNSS) device 2718 (or a corresponding interface circuit system as discussed above), such as a global positioning system (GPS) device. As is known in the art, the GNSS device 2718 can communicate with a satellite-based system and can determine the geographic location of the electrical device 2700 based on information received from one or more GNSS satellites.

[0285] The electrical device 2700 may include other output devices 2710 (or corresponding interface circuitry as discussed above). Examples of other output devices 2710 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0286] The electrical device 2700 may include other input devices 2720 (or corresponding interface circuit systems as discussed above). Examples of other input devices 2720 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device (e.g., a mouse, a stylus), a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0287] The electrical device 2700 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a fixed game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system as part of a vehicle, a smart home appliance, a consumer electronic product or device, a manufacturing device). In some embodiments, the electrical device 2700 may be any other electronic device that processes data. In some embodiments, the electrical device 2700 may include multiple discrete physical components. Considering the range of devices that the electrical device 2700 may appear in various embodiments, in some embodiments, the electrical device 2700 may be referred to as a computing device or a computing system.

[0288] Throughout the specification, multiple instances can implement the parts, operations or structures described as single instances. Although each operation of one or more methods is shown and described as a separate operation, one or more operations in each operation can be performed simultaneously, and the operation does not require to be performed in the order shown. The structure and function presented as a separate component in the exemplary configuration can be implemented with a combined structure or component. Similarly, the structure and function presented with a single component can be implemented with a separate component. These and other changes, modifications, increases and improvements fall within the scope of the subject matter herein.

[0289] It will also be understood that, although the terms "first", "second", etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish an element from another element, and are not intended to imply that the object described in this way must be in a given order in time, space, level or in any other way. For example, the first contact portion can be referred to as the second contact portion, and similarly, the second contact portion can be referred to as the first contact portion, without departing from the scope of this exemplary embodiment. The first contact portion and the second contact portion are both contacts, but they are not identical contacts.

[0290] As used in the description of the exemplary embodiments and the attached examples, the singular forms "a", "an" and "the" are intended to also include the plural forms unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. For example, the phrase "A and / or B" means (A), (B), or (A and B), while the phrase "A, B, and / or C" can mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0291] As used throughout the specification and in the claims, a list of items combined with the term "at least one of" or "one or more of" may mean any combination of the listed items.

[0292] It will also be understood that when used in this specification, the terms "include" and / or "comprising" specify the presence of the features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. In addition, as used with respect to the embodiments of the present disclosure, the terms "include", "comprising", "having", etc. are synonymous.

[0293] The description may use the phrases "in an embodiment," "according to some embodiments," "according to an embodiment," or "in embodiments," which may each refer to one or more of the same or different embodiments.

[0294] As used herein, the term "module" means being part of or including an ASIC, electronic circuit, system on chip, processor (shared, dedicated, or group), solid-state device, memory (shared, dedicated, or group) that executes one or more software or firmware programs, combinational logic circuit, and / or other appropriate components that provide the described functionality.

[0295] As used herein, in some examples, "conductive" may refer to a material having a conductivity greater than or equal to 10 at 20 degrees Celsius. 7 The characteristic of electrical conductivity is Siemens / meter (S / m). Examples of such materials include Cu, Ag, Al, Au, W, Zn, and Ni.

[0296] The term "signal" may refer to at least one current signal, a voltage signal, a magnetic signal, or a data / clock signal.

[0297] Throughout the specification and in the claims, the term "connected" means a direct connection, such as an electrical, mechanical or magnetic connection between connected elements without any intermediate devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical or magnetic connection between connected elements, or an indirect connection through one or more passive or active intermediate devices.

[0298] The description may use perspective-based descriptions, such as top / bottom, inside / outside, over / under, etc. Such descriptions are only used to facilitate discussion and are not intended to limit the application of the embodiments disclosed herein to any particular orientation.

[0299] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials (when such physical relationship is noteworthy). For example, in the context of materials, a material or layer that is above or below another material may be in direct contact or may have one or more intervening materials or layers. Additionally, a material that is between two materials or layers may be in direct contact with both materials / layers or may have one or more intervening materials / layers. Conversely, a first material or layer being "on" a second material or layer means that at least a portion of the first material or layer is in direct physical contact with at least a portion of the second material / layer. Similar distinctions are made in the context of component assemblies.

[0300] As used herein, “A is adjacent to B” means that at least a portion of A is in direct physical contact with at least a portion of B.

[0301] As used herein, “A is close to B” may mean that A is adjacent to B, or A is close to B.

[0302] Unless otherwise indicated in a particular context of use, the term "predominantly" means more than 50% or more than half. For example, an ingredient that is predominantly the first component means that more than half of the ingredient (by volume) is the first component (e.g., >50 at.%). The term "predominantly" means the most or largest portion. For example, an ingredient that is predominantly the first component means that the ingredient has more of the first component (e.g., by volume) than any other component. An ingredient that is predominantly the first component and the second component means that the ingredient has more of the first component and the second component than any other component. The term "substantially" means that only accidental variations exist. For example, an ingredient that is predominantly the first component means that the ingredient may also include <1% of any other component. An ingredient that is predominantly the first component and the second component means that the ingredient may also include <1% of any component that replaces the first component or the second component.

[0303] The terms "substantially," "close," "approximately," "close to," and "about" generally mean within + / - 10% of a target value (unless otherwise indicated).

[0304] Unless otherwise indicated in the explicit context in which it is used, the terms "substantially equal to", "approximately equal to" or "approximately equal to" indicate that only incidental variations exist between the two things so described. In the art, such variations are typically no greater than + / -10% of a predetermined target value.

[0305] In the corresponding accompanying drawings of the embodiments, signals, electric currents, electrical biases, or magnetic or electrical polarities can be represented by lines. Some lines are thicker, to indicate more constituent signal paths, and / or have arrows at one or more ends, to indicate the main information flow direction. Such indication is not intended to be restrictive. On the contrary, lines are used in combination with one or more exemplary embodiments to facilitate easier understanding of circuits or logic units. Any represented signal, polarity, electric current, voltage, etc., as specified by design needs or preferences, can actually include one or more signals that can propagate in either direction and can be implemented using any appropriate type of signal scheme.

[0306] The materials described herein are shown in the accompanying drawings by way of example and not by way of limitation. For simplicity and clarity of illustration, the elements shown in the accompanying drawings are not necessarily drawn to scale. For example, for clarity, the size of some elements may be exaggerated relative to other elements. In addition, where deemed appropriate, reference numerals have been reused in the accompanying drawings to indicate corresponding or similar elements.

[0307] Although the accompanying drawings may illustrate embodiments in which structures are substantially aligned with Cartesian axes (e.g., device structures with substantially vertical sidewalls), positive and negative (concave) tilted feature sidewalls are often present in practice. For example, manufacturing non-idealities may cause one or more structural features to have tilted sidewalls. Therefore, the properties shown are idealized only for the purpose of clearly describing the prominent features. It should be understood that when any structure described herein is examined using, for example, scanning electron microscope (SEM) images or transmission electron microscope (TEM) images, the schematic illustrations may not reflect real-life process limitations, which may cause features to appear not so "ideal". In such images of actual structures, possible processing defects may also be visible, such as imperfectly straight edges of material, tapered vias or other openings, inadvertent rounded corners or thickness variations of different material layers, accidental screw dislocations, edge dislocations or combined dislocations within a crystal region, and / or accidental dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but common in the field of device manufacturing.

[0308] The following provides illustrative examples of the techniques described throughout this disclosure. Embodiments of these techniques may include any one or more of the examples described below and any combination thereof. In some embodiments, at least one of the systems or components described in one or more of the drawings in the above-mentioned figures may be configured to perform one or more operations, techniques, processes, and / or methods described in the following examples.

[0309] Example 1 includes an electronic device, comprising: an integrated circuit (IC) die having a thickness of 5 microns or less; and a mesa structure, the mesa structure being located below the IC die, the mesa structure extending upward from a substrate, wherein the mesa structure has an occupied area substantially similar to an occupied area of ​​the IC die.

[0310] Example 2 includes the subject matter of Example 1, and further includes residual material in contact with a side of the IC die.

[0311] Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the residual material includes oxygen, carbon, or hydrogen.

[0312] Example 4 includes the subject matter of any of Examples 1-3, and wherein the residual material comprises a photoresist material.

[0313] Example 5 includes the subject matter of any of Examples 1-4, and wherein the residual material comprises an adhesive material.

[0314] Example 6 includes the subject matter of any of Examples 1-5, and further includes a dielectric material between the IC die and the mesa structure.

[0315] Example 7 includes the subject matter of any of Examples 1-6, and wherein the dielectric material comprises at least one of an oxide, a nitride, or a photoresist material.

[0316] Example 8 includes a method comprising: receiving a substrate comprising a first layer, a second layer located above the first layer, and a third layer located above the second layer, the second layer comprising at least one integrated circuit (IC) component, and the third layer comprising at least one dielectric material; and using a laser to weaken the first layer to facilitate separation of the second layer from the substrate.

[0317] Example 9 includes the subject matter of Example 8, and wherein the third layer comprises at least one of an oxide or a nitride.

[0318] Example 10 includes the subject matter of any of Examples 8 and 9, and wherein the third layer comprises a photoresist material.

[0319] Example 11 includes the subject matter of any of Examples 8-10, and wherein the third layer includes an adhesive and glass.

[0320] Example 12 includes the subject matter of any of Examples 8-11, and further includes removing the third layer.

[0321] Example 13 includes the subject matter of any of Examples 8-12, and wherein removing the third layer comprises applying an etch to the third layer.

[0322] Example 14 includes the subject matter of any of Examples 8-13, and wherein removing the third layer comprises applying a light source to the third layer.

[0323] Example 15 includes the subject matter of any of Examples 8-14, and further includes transferring a portion of the second layer from the substrate to a second substrate.

[0324] Example 16 includes the subject matter of any of Examples 8-15, and further includes transferring the second portion of the second layer from the substrate to a third substrate.

[0325] Example 17 includes a device comprising: a substrate; a first layer located above the substrate; a second layer located above the first layer, the second layer including an integrated circuit (IC) component; and a third layer located above the second layer, the third side including at least one dielectric material.

[0326] Example 18 includes the subject matter of Example 17, and wherein the third layer comprises at least one of an oxide or a nitride.

[0327] Example 19 includes the subject matter of any of Examples 17 and 18, and wherein the third layer comprises a photoresist material.

[0328] Example 20 includes the subject matter of any of Examples 17-19, and wherein the third layer comprises an adhesive and glass.

[0329] Example 21 includes an apparatus comprising a chuck comprising: a first portion, the first portion interfacing with a wafer, the first portion being porous; and a second portion coupled to the first portion, the second portion comprising at least one vacuum port.

[0330] Example 22 includes the subject matter of Example 21, and wherein the average pore size of the first portion is less than 5 microns.

[0331] Example 23 includes the subject matter of any of Examples 21-22, and wherein the first portion comprises a ceramic material.

[0332] Example 24 includes the subject matter of any of Examples 21-23, further comprising a laser for ablating the portion of the wafer, wherein a spot size of the laser has a diameter greater than 10 times an average aperture size of the first portion of the chuck.

[0333] The foregoing description has been described with reference to specific exemplary embodiments for purposes of explanation. However, the above illustrative discussion is not intended to be exhaustive or to limit the possible exemplary embodiments to the precise forms disclosed. In view of the above teachings, many modifications and variations are possible. The exemplary embodiments are selected and described in order to best explain the principles involved and their practical application, so that those skilled in the art can best utilize the various exemplary embodiments with various modifications suitable for the intended specific use.

Claims

1. An electronic device, comprising: An integrated circuit (IC) die having a thickness of 5 micrometers (μm) or less; as well as A mesa structure is disposed beneath the IC die, the mesa structure extending upward from the substrate, wherein the mesa structure has a footprint substantially similar to a footprint of the IC die.

2. The electronic device of claim 1 further comprising residual material in contact with a side of the IC die.

3. The electronic device according to claim 2, wherein: The residual material includes oxygen, carbon or hydrogen.

4. The electronic device according to claim 2, wherein: The residual material includes photoresist material.

5. The electronic device according to claim 2, wherein: The residual material includes adhesive material.

6. The electronic device of any one of claims 1-5, further comprising a dielectric material between the IC die and the mesa structure.

7. The electronic device according to claim 6, wherein: The dielectric material includes at least one of an oxide, a nitride or a photoresist material.

8. A method comprising: receiving a substrate comprising a first layer, a second layer located above the first layer, and a third layer located above the second layer, the second layer comprising at least one integrated circuit (IC) component, the third layer comprising at least one dielectric material; as well as A laser is used to weaken the first layer, thereby facilitating separation of the second layer from the substrate.

9. The method according to claim 8, wherein: The third layer includes at least one of oxide or nitride.

10. The method according to claim 8, wherein: The third layer includes a photoresist material.

11. The method according to claim 8, wherein: The third layer includes an adhesive and glass.

12. The method according to any one of claims 8 to 11, further comprising: After weakening the first layer using the laser, the third layer is removed.

13. The method according to claim 12, wherein: Removing the third layer includes: applying etching to the third layer.

14. The method according to claim 12, wherein: Removing the third layer includes applying a light source to the third layer.

15. The method according to any one of claims 8 to 11, further comprising: A portion of the second layer is transferred from the substrate to a second substrate.

16. The method according to claim 15, further comprising: A second portion of the second layer is transferred from the substrate to a third substrate.

17. A device comprising: substrate; a first layer located on the substrate; a second layer located above the first layer, the second layer comprising an integrated circuit (IC) component; as well as A third layer is located on the second layer, and the third layer includes at least one dielectric material.

18. The apparatus according to claim 17, wherein: The third layer includes at least one of oxide or nitride.

19. The apparatus according to claim 17, wherein: The third layer includes a photoresist material.

20. The apparatus of claim 17, wherein: The third layer includes an adhesive and glass.

21. A device comprising: A chuck, the chuck comprising: a first portion, the first portion being in contact with the wafer interface, the first portion being porous; and A second portion is coupled to the first portion, the second portion comprising at least one vacuum port.

22. The apparatus according to claim 21, wherein The first portion has an average pore size of less than 5 microns.

23. The apparatus of claim 21, wherein: The first portion includes a ceramic material.

24. The apparatus of any one of claims 21-23, further comprising a laser for ablating portions of the wafer, wherein The spot size of the laser has a diameter greater than 10 times the average pore size of the first portion of the chuck.

Images