Artificial intelligence processing device and weight coefficient writing method of artificial intelligence processing device

Abstract

An artificial intelligence processing device (200) is provided with: a substrate (60) or the like; a calculation circuit such as a product sum calculation circuit (215), which is mounted on a single substrate (60) or the like, and which includes a first resistance change type nonvolatile storage element (10) and a second resistance change type nonvolatile storage element (20), each of which holds conductivity and has the same structure as the first resistance change type nonvolatile storage element (10) and the second resistance change type nonvolatile storage element (20); and a write circuit (260) that, by applying a first voltage pulse having a first voltage to the first variable resistance non-volatile memory element (10), rewrites the conductance of the first variable resistance non-volatile memory element (10). A second voltage pulse having a second voltage different from the first voltage is applied to the second resistance change type non-volatile memory element (20), thereby rewriting the conductivity of the second resistance change type non-volatile memory element (20).

Description

Technical Field

[0001] The present invention relates to an artificial intelligence processing device and a method for writing weight coefficients thereof, and in particular to an artificial intelligence processing device using a resistance-varying non-volatile storage element whose resistance value changes according to a provided electrical signal. Background Art

[0002] With the development of information and communication technology, the advent of IoT (Internet of Things) technology connected to the Internet has attracted attention. In IoT technology, various electronic devices are connected to the Internet, and the performance of the devices is expected to be improved. However, as a technology to achieve further performance improvement, the research and development of artificial intelligence (AI) technology, which allows electronic devices to learn and judge by themselves, has been actively carried out in recent years.

[0003] In artificial intelligence technology, neural network technology is used to simulate human brain-type information processing in an engineering way, and research and development of semiconductor integrated circuits that can perform neural network operations at high speed and low power consumption are being actively carried out.

[0004] Patent document 1 discloses a conventional neural network operation circuit. A neural network is composed of basic elements called neurons (sometimes also called perceptrons) connected by couplings called synapses in which multiple inputs have different coupling weight coefficients. By connecting multiple neurons to each other, advanced operations such as image recognition and sound recognition can be performed. In neurons, a product-sum operation is performed to add all the values ​​after multiplying each input by each coupling weight coefficient. The product-sum operation circuit is composed of a memory circuit and a register circuit for storing inputs or coupling weight coefficients, a multiplication circuit for multiplying inputs by coupling weight coefficients, an accumulator circuit for accumulating and adding the multiplication results, and a control circuit for controlling the operation of these circuit blocks. All subsequent circuit blocks are composed of digital circuits.

[0005] Another example of a conventional neural network operation circuit is disclosed in Patent Document 2. A neural network operation circuit is constructed using a variable resistance nonvolatile memory capable of setting multiple levels of analog resistance values ​​or conductance as the reciprocal thereof (hereinafter referred to as "conductance" for short), a conductance equivalent to a coupling weight coefficient is stored in a nonvolatile storage element, a voltage value equivalent to the input is applied to the nonvolatile storage element, and the analog current value flowing through the nonvolatile storage element at this time is used. The product-sum operation performed by the neuron is performed in the following manner: a plurality of coupling weight coefficients are stored as conductances in a plurality of nonvolatile memory elements, a voltage value equivalent to the input is applied to a plurality of nonvolatile memory elements, and an analog current value obtained by adding the current values ​​flowing through the plurality of nonvolatile memory elements is obtained as a result of the product-sum operation. Here, as a writing method for writing conductance to a nonvolatile memory, the conductance to be written to each nonvolatile memory is calculated based on the coupling weight coefficient derived in advance, and the conductance is written to each nonvolatile memory.

[0006] Another example of a conventional neural network operation circuit is disclosed in non-patent document 1. Here, a resistance variable non-volatile memory capable of setting conductance is also used to form a neural network operation circuit, and the following aspects are the same: a conductance equivalent to a coupling weight coefficient is stored in a non-volatile storage element, an analog voltage value equivalent to an input is applied to the non-volatile storage element, and an analog current value flowing through the non-volatile storage element at this time is used. Here, as a writing method for writing conductance to the non-volatile memory, the change amount between the conductance at the time before writing and the conductance set after writing is first derived, and writing corresponding to the change amount of the conductance is performed on the non-volatile storage element.

[0007] That is, in the example of the neural network operation circuit such as Patent Document 2, the writing operation is generally performed based on the conductance itself written to the non-volatile memory, while in the neural network operation circuit such as Non-Patent Document 1, the writing operation is generally performed based on the change in conductance before and after writing to the non-volatile memory, which is different. The neural network operation circuits using non-volatile memory elements disclosed in Patent Document 2 and Non-Patent Document 1 can achieve low power consumption compared to the above-mentioned neural network operation circuits composed of digital circuits. In recent years, process development, equipment development, and circuit development of resistance variable non-volatile memories capable of setting conductance are popular.

[0008] Prior art literature

[0009] Patent Literature

[0010] Patent Document 1: Japanese Patent Application Publication No. 2001-188767

[0011] Patent Document 2: International Publication No. 2019 / 049741

[0012] Non-patent literature

[0013] Non-patent literature 1: M. Prezioso, et al., “Training and operation of an integrated neuromorphic network based on metal-ox i de memristors,” Nature, no.521, pp.61-64, 2015. Summary of the invention

[0014] Problems to be solved by the invention

[0015] However, the above-mentioned conventional neural network operation circuit has the following problems.

[0016] That is, the neural network operation circuit that performs writing based on the conductance itself written to the non-volatile memory uses the conductance itself derived in advance for writing, so the conductance can be written to the non-volatile memory element with high accuracy, and is therefore suitable for an "inference artificial intelligence processing device" that mainly processes only product-sum operations in a neural network after the product is shipped (i.e., after the artificial intelligence processing device such as the neural network operation circuit is shipped). However, in a neural network that is generally based on processing in software, the update of the coupling weight coefficient, that is, learning is performed based on the change in the coupling weight coefficient. Therefore, in a "learning artificial intelligence processing device" that frequently updates the conductance after the product is shipped, if a neural network operation circuit that performs writing based on the conductance itself is used, learning cannot be performed efficiently, which is a problem.

[0017] Figure 1A The process of learning in a neural network operation circuit that performs a write operation based on conductance itself is shown. In this process, the coupling weight coefficient of each non-volatile storage element is used to perform inference (S10), the difference between the inference result and the teacher label is confirmed (S11), the change amount when the coupling weight coefficient is updated is calculated for each non-volatile storage element (S12), the current coupling weight coefficient is read for each non-volatile storage element (S13), the updated coupling weight coefficient is calculated for each non-volatile storage element based on the read coupling weight coefficient (S14), and the calculated coupling weight coefficient is written to each non-volatile storage element (S15). That is, when writing the coupling weight coefficient itself, six steps are required.

[0018] Figure 1BThe process of learning in a neural network operation circuit that performs a write operation based on the change in conductance before and after writing is shown. In this process, the coupling weight coefficient of each non-volatile memory element is used to perform inference (S10), the difference between the inference result and the teacher label is confirmed (S11), the change in the coupling weight coefficient when updating is calculated for each non-volatile memory element (S12), and the coupling weight coefficient is updated in a manner that changes the current coupling weight coefficient by the calculated change in the coupling weight coefficient for each non-volatile memory element (S20). That is, in the case of writing the change in the coupling weight coefficient, four steps are sufficient. Figure 1B The learning process in can be implemented in the same way as the case of neural network calculation based on software. Figure 1A There is little learning process shown.

[0019] In addition, the neural network operation circuit that performs writing operation based on the change amount before and after writing of the conductance can perform writing operation based on the change amount. Figure 1B The learning process in the process of updating the conductance is suitable for "learning artificial intelligence processing devices" that frequently update the conductance after the product leaves the factory. Figure 1B In the neural network computing circuit of the learning process shown in the figure, the previously derived conductance itself cannot be used for writing during the "initial setting" before the product is shipped. It is necessary to continuously apply voltage pulses multiple times to change the conductance to the previously derived value. At this time, there is a problem that the writing characteristics are biased and the initial setting cannot be performed efficiently and accurately.

[0020] The present disclosure is completed in view of the above-mentioned problems, and provides an artificial intelligence processing device and a weight coefficient writing method thereof using a resistance variable non-volatile storage element that can take into account both the high-precision setting (initial setting) of the coupling weight coefficient when the product is shipped, etc. and the high-efficiency updating (learning) of the coupling weight coefficient after the product is shipped, etc.

[0021] Means for solving problems

[0022] An artificial intelligence processing device of one embodiment of the present invention comprises: a substrate; an operation circuit mounted on the one substrate, comprising a first resistance variable non-volatile memory element and a second resistance variable non-volatile memory element, each of which maintains conductance and has the same structure; and a write circuit, which rewrites the conductance of the first resistance variable non-volatile memory element by applying a first voltage pulse having a first voltage to the first resistance variable non-volatile memory element, and rewrites the conductance of the second resistance variable non-volatile memory element by applying a second voltage pulse having a second voltage different from the first voltage to the second resistance variable non-volatile memory element.

[0023] A weight coefficient writing method for an artificial intelligence processing device involved in one embodiment of the present invention is a weight coefficient writing method possessed by the artificial intelligence processing device, wherein the artificial intelligence processing device has a first resistance variable non-volatile storage element and a second resistance variable non-volatile storage element having the same structure and maintaining the weight coefficient in a product-sum operation as conductance, and the writing method comprises: a first rewriting step of rewriting the conductance of the first resistance variable non-volatile storage element by applying a first voltage pulse having a first voltage to the first resistance variable non-volatile storage element; and a second rewriting step of rewriting the conductance of the second resistance variable non-volatile storage element by applying a second voltage pulse having a second voltage different from the first voltage to the second resistance variable non-volatile storage element at least during a high resistance conversion process.

[0024] Effects of the Invention

[0025] According to the artificial intelligence processing device using a resistance variable non-volatile storage element and its weight coefficient writing method disclosed in the present invention, it is possible to take into account both the high-efficiency and high-precision setting of the coupling weight coefficient (initial setting) when the product is shipped, and the high-efficiency updating (learning) of the coupling weight coefficient after the product is shipped. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A This is a diagram showing the learning process in a neural network operation circuit that performs writing operations based on conductance itself.

[0027] Figure 1B This is a diagram showing the process of learning in a neural network operation circuit that performs a writing operation based on the change in conductance before and after writing.

[0028] Figure 2A This is a schematic cross-sectional view of a first variable resistance nonvolatile memory element according to an embodiment.

[0029] Figure 2B This is a schematic cross-sectional view of a second variable resistance nonvolatile memory element according to the embodiment.

[0030] Figure 3 This is a diagram showing changes in conductance when the resistance of the first variable resistance nonvolatile memory element according to the embodiment is changed by continuously applying a plurality of voltage pulses having the same polarity and the same voltage.

[0031] Figure 4 The diagram shows the change in conductance when the resistance of the second variable resistance nonvolatile memory element of the embodiment is changed by continuously applying a plurality of voltage pulses of the same polarity and the same voltage whose voltage magnitudes are different from those in the case of the first variable resistance nonvolatile memory element 10 .

[0032] Figure 5A A diagram for explaining the definition of a first variable resistance nonvolatile memory element and a second variable resistance nonvolatile memory element.

[0033] Figure 5B A diagram for explaining driving conditions of the first variable resistance nonvolatile memory element and the second variable resistance nonvolatile memory element.

[0034] Fig. 6A is a circuit diagram of a memory cell in the prior art.

[0035] Figure 6B is a cross-sectional view of a memory cell in the prior art.

[0036] Fig. 7A is a circuit diagram of a memory cell according to an embodiment.

[0037] Figure 7B It is a cross-sectional view showing an example of a memory cell according to the embodiment.

[0038] Figure 7C is a storage unit representing an embodiment and Figure 7B A cross-sectional view of a different example.

[0039] Fig. 8A is a circuit diagram of a memory cell according to another embodiment.

[0040] Figure 8B It means that it is equipped with Fig. 8A A diagram showing an example of a cross-sectional view of a memory cell of an artificial intelligence processing device having the first variable resistance nonvolatile memory element described above.

[0041] Figure 8C It means that it is equipped with Fig. 8A A diagram showing an example of a cross-sectional view of a memory cell of an artificial intelligence processing device including the second variable resistance nonvolatile memory element described above.

[0042] Fig.9A This is a block diagram showing a model of an artificial intelligence processing device according to an embodiment.

[0043] Fig. 9B Yes means Fig.9A Diagram of the function of the neuron shown.

[0044] Fig. 10A It shows the realization Fig. 9B Diagram of an example circuit of a neuron shown.

[0045] Fig. 10B It shows the realization Fig. 9B A diagram of another circuit example of a neuron is shown.

[0046] Fig.11 It means by Fig. 10A A block diagram of the overall structure of an artificial intelligence processing device composed of neurons is shown.

[0047] Fig. 12A Yes Fig. 10A The diagram shows an example of voltages applied through the word line WL, bit lines BL1 and BL2, and source line SL when writing and reading are performed in the memory cell.

[0048] Fig. 12B Yes Fig. 10B The diagram shows an example of voltages applied through word lines WL1 and WL2, bit line BL, and source line SL when writing and reading are performed in the memory cell shown.

[0049] Fig.13 Yes means Fig.11 Flowchart of an operation example of the control circuit shown. DETAILED DESCRIPTION

[0050] Hereinafter, the embodiments of the present disclosure will be described with reference to the accompanying drawings. In addition, the embodiments described below all represent a specific example of implementation. Therefore, the numerical values, shapes, materials, components, configuration positions and connection forms of components, steps, and the order of steps shown in the following embodiments are only examples and are not intended to limit the present disclosure. The present disclosure is limited only by the claims.

[0051] Among the components in the following embodiments, components that are not recited in the independent claims representing the most general concept of the present disclosure are described as modes that are not necessarily required to achieve the subject matter of the present disclosure but can be adopted.

[0052] The inventors of the present invention conducted in-depth research to improve the efficiency of setting high-precision coupling weight coefficients (initial settings) when products are shipped, and updating (learning) high-efficiency coupling weight coefficients after products are shipped, in artificial intelligence processing devices using resistance variable non-volatile memory elements, and obtained the following insights.

[0053] The inventors of the present invention have discovered that in an artificial intelligence processing device using a variable resistance non-volatile memory element, two variable resistance non-volatile memory elements of the same structure are mounted on a substrate, and by applying continuous voltage pulses of the same polarity and the same voltage based on different driving conditions (specifically, voltages of different magnitudes) to the two variable resistance non-volatile memory elements, the conductance of one non-volatile memory element changes little by little, while the conductance of the other non-volatile memory element changes significantly by the application of the first voltage pulse, and the amount of conductance change caused by the application of the second and subsequent voltage pulses is smaller. This makes it possible to take into account both the high-precision setting (initial setting) of the coupling weight coefficient at the time of product shipment, which has been a previous issue, and the high-efficiency updating (learning) of the coupling weight coefficient after product shipment.

[0054] It should be noted that "same structure" means that the materials are substantially the same and the structure is substantially the same, and even if the content of trace material components such as impurities is different, or there are differences caused by dimensional deviations produced in the same manufacturing process, they are also included in the "same structure". Typically, the same structure is formed by the same manufacturing process.

[0055] The details of this finding will be described below together with the embodiments as appropriate.

[0056] (Implementation Method)

[0057] [Structure of variable resistance nonvolatile memory element]

[0058] First, one of the variable resistance nonvolatile memory elements to be subjected to conductance change under two different driving conditions of the embodiment is referred to as a "first variable resistance nonvolatile memory element", and the other is referred to as a "second variable resistance nonvolatile memory element", and an example of the configuration of the first variable resistance nonvolatile memory element and the second variable resistance nonvolatile memory element is described. As described above, the first variable resistance nonvolatile memory element and the second variable resistance nonvolatile memory element are driven under different driving conditions, but have the same structure.

[0059] The phrase “the first variable resistance nonvolatile memory element and the second variable resistance nonvolatile memory element are driven under different driving conditions” does not necessarily apply to all driving conditions, but applies at least to the high resistance process in the present embodiment.

[0060] Figure 2A1 is a schematic diagram showing a configuration example of a first variable resistance nonvolatile memory element 10 of an embodiment. The first variable resistance nonvolatile memory element 10 is a variable resistance nonvolatile memory element used for setting (initial setting) a coupling weight coefficient with high precision when a product is shipped, etc., which is determined by the driving conditions described later.

[0061] like Figure 2A As shown, the first variable resistance nonvolatile memory element 10 includes a substrate 1, a first electrode 2 formed on the substrate 1, a variable resistance layer 3 formed as a metal oxide layer on the first electrode 2, and a second electrode 4 formed on the variable resistance layer 3. The first electrode 2 and the second electrode 4 are electrically connected to the variable resistance layer 3. That is, the first variable resistance nonvolatile memory element 10 includes the first electrode 2, the second electrode 4, and the variable resistance layer 3 between the first electrode 2 and the second electrode 4.

[0062] The first electrode 2 may have the same size as the second electrode 4 , and the first electrode 2 , the second electrode 4 , and the variable resistance layer 3 may be arranged upside down or in a lateral direction.

[0063] The substrate 1 is composed of, for example, a silicon substrate on which circuit elements such as transistors are formed. In addition, at least one of the first electrode 2 and the second electrode 4 is composed of a metal that is a noble metal, such as Au (gold), Pt (platinum), Ir (iridium), Pd (palladium), Ru (ruthenium), etc. For example, the second electrode 4 in contact with the second tantalum oxide layer 3b is composed of a noble metal, and the first electrode 2 is composed of a noble metal or a non-noble metal. Due to the characteristics of such electrodes, the first variable resistance nonvolatile memory element 10 has the following characteristics. Figure 3 The resistance change characteristics are shown.

[0064] The resistance (in other words, conductance) of the resistance variable layer 3 changes according to the voltage pulse applied between the first electrode 2 and the second electrode 4. The resistance variable layer 3 is composed of a metal oxide and is composed of a first tantalum oxide layer 3a and a second tantalum oxide layer 3b stacked together. Here, the oxygen content of the second tantalum oxide layer 3b is higher than the oxygen content of the first tantalum oxide layer 3a.

[0065] When the composition of the first tantalum oxide layer 3 a is TaOx, 0<x<2.5, and when the composition of the second tantalum oxide layer 3 b is TaOy, x<y.

[0066] Figure 2B1 is a schematic diagram showing a configuration example of the second variable resistance nonvolatile memory element 20 of the embodiment. The second variable resistance nonvolatile memory element 20 is a variable resistance nonvolatile memory element used for updating (learning) a coupling weight coefficient efficiently after a product is shipped, etc., for a purpose determined by a driving condition described later.

[0067] like Figure 2B As shown, the second variable resistance nonvolatile memory element 20 has the same structure as the first variable resistance nonvolatile memory element 10, and includes a substrate 11, a first electrode 12 formed on the substrate 11, a variable resistance layer 13 formed as a metal oxide layer on the first electrode 12, and a second electrode 14 formed on the variable resistance layer 13. The variable resistance layer 13 is formed of a metal oxide, and is formed by stacking a first tantalum oxide layer 13a and a second tantalum oxide layer 13b.

[0068] The substrate 11 , the first electrode 12 , the variable resistance layer 13 , the second electrode 14 , the first tantalum oxide layer 13 a , and the second tantalum oxide layer 13 b are respectively made of the same materials as the corresponding components of the first variable resistance nonvolatile memory element 10 .

[0069] [Method for manufacturing variable resistance nonvolatile memory element]

[0070] Next, an example of a method for manufacturing the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 will be described. Since these manufacturing methods are the same, the case of using the method for manufacturing the first variable resistance nonvolatile memory element 10 will be described.

[0071] First, the first electrode 2 is formed on the substrate 1 by sputtering. Then, a tantalum oxide layer is formed on the first electrode 2 by a so-called reactive sputtering method in which a Ta target is sputtered in argon and oxygen. Here, the oxygen content in the tantalum oxide layer can be easily adjusted by changing the flow rate ratio of oxygen to argon. In addition, the substrate temperature can be set to room temperature without special heating.

[0072] Next, the surface of the tantalum oxide layer formed as described above is modified by oxidizing the outermost surface thereof. Alternatively, a tantalum oxide target (e.g., Ta2O5) having a high oxygen content is used to form a layer having a higher oxygen content by sputtering. Thus, a region (second region) having a higher oxygen content than the unoxidized region (first region) of the tantalum oxide layer formed previously is formed on the surface of the tantalum oxide layer.

[0073] The first region and the second region correspond to the first tantalum oxide layer 3 a and the second tantalum oxide layer 3 b , respectively. The first tantalum oxide layer 3 a and the second tantalum oxide layer 3 b formed in this way constitute the variable resistance layer 3 .

[0074] Next, the second electrode 4 is formed on the variable resistance layer 3 formed as described above by a sputtering method.

[0075] Finally, in order to form the first resistance variable non-volatile memory element 10, the first electrode 2, the oxygen-deficient first tantalum oxide layer 3a, the second tantalum oxide layer 3b and the second electrode 4 are patterned using a desired mask, thereby forming the first resistance variable non-volatile memory element 10 in which the resistance variable layer 3 is sandwiched between the first electrode 2 and the second electrode 4.

[0076] In the formation of the first variable resistance nonvolatile memory element 10 , patterning is performed collectively using the same mask in this step, but patterning may be performed separately in each step.

[0077] The size and shape of the first electrode 2, the second electrode 4, and the variable resistance layer 3 can be adjusted by photomasking and photolithography. In this embodiment, the size of the second electrode 4 and the variable resistance layer 3 is set to 0.1 μm×0.1 μm (area 0.01 μm 2 ), the size of the portion where the first electrode 2 and the variable resistance layer 3 are in contact is also set to 0.1 μm×0.1 μm (area 0.01 μm 2 ), but is not limited to this size and shape and can be appropriately changed according to the layout design.

[0078] [Operation Method and Resistance Change Characteristics of Resistance Variable Nonvolatile Memory Element]

[0079] Next, operations of the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 obtained by the above-described manufacturing method will be described.

[0080] Hereinafter, the case where the resistance value of the resistance variable layer 3 is at a specified high value (for example, 300 kΩ) is referred to as a high resistance state, and similarly, the case where it is at a specified low value (for example, 12 kΩ) is referred to as a low resistance state. By continuously applying a plurality of voltage pulses of the same polarity and the same voltage of different sizes to the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20, respectively (for example, a first voltage pulse having a first voltage to the first resistance variable nonvolatile memory element 10, and a second voltage pulse having a second voltage different from the first voltage to the second resistance variable nonvolatile memory element 20), the conductance of the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20 changes during this period.

[0081] Furthermore, in the process of reducing the resistance, it is not necessarily necessary to continuously apply a plurality of voltage pulses of the same polarity and the same voltage but of different magnitudes to the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20. That is, in the process of reducing the resistance, a plurality of voltage pulses of the same polarity and the same voltage but of the same magnitude may be continuously applied to the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20.

[0082] In addition, hereinafter, the process of increasing the conductance of the resistance variable layer 3 and changing the resistance variable layer 3 from a high resistance state to a low resistance state by applying a negative write voltage pulse between the first electrode 2 and the second electrode 4 of the first resistance variable nonvolatile memory element 10 or the second resistance variable nonvolatile memory element 20 is referred to as low resistance (or also referred to as "setting"), and the process of decreasing the conductance of the resistance variable layer 3 and changing the resistance variable layer 3 from a low resistance state to a high resistance state by applying a positive write voltage pulse between the first electrode 2 and the second electrode 4 is referred to as high resistance (or also referred to as "resetting"). In addition, the low resistance and high resistance of the resistance variable nonvolatile memory element are also referred to as "writing" or "rewriting" of the conductance or resistance value.

[0083] By repeating such writing, the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 operate as nonvolatile memory elements.

[0084] Here, the initialization process is described. In this embodiment, before the first writing, the initialization process is usually performed only once. The initialization process is a preparatory process for achieving a stable resistance change action in the subsequent low resistance and high resistance, and is also called "disconnection" or "forming".

[0085] Typically, the first resistance change type nonvolatile memory element 10 and the second resistance change type nonvolatile memory element 20 just after manufacture have an initial resistance value higher than the high resistance state during normal resistance change, and in this state, even if a low resistance voltage pulse or a high resistance voltage pulse is applied during normal operation, no resistance change will be caused.

[0086] Therefore, in the initial process, an initial voltage pulse is applied between the first electrode 2 and the second electrode 4 .

[0087] Thereafter, the magnitude of the voltage applied to the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20 (i.e., driving conditions) is different, but by continuously applying multiple voltage pulses of the same polarity and the same voltage during high resistance or low resistance conversion, the conductance of the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20 changes between a high resistance state and a low resistance state.

[0088] That is, the initial process is a process performed on the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 in an initial state where no voltage is applied after the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 are manufactured.

[0089] By going through the above-described initial process, a local region called a filament having a higher degree of oxygen deficiency than the surrounding area is formed in the resistance variable layer 3 .

[0090] It should be noted that in this embodiment, the filament is formed through an initial process, but it is not necessarily necessary to form the filament through the initial process. It can also be replaced by providing an oxide layer with an oxygen deficiency sufficiently greater than 0% when forming a variable resistance nonvolatile memory element.

[0091] Next, the manner in which the conductance of the first variable resistance nonvolatile memory element 10 of this embodiment changes will be described. Figure 3 The first variable resistance nonvolatile memory element 10 of the present embodiment is characterized by the resistance change when the conductance of the first variable resistance nonvolatile memory element 10 is changed to a high resistance state or a low resistance state by continuously applying a plurality of voltage pulses of the same polarity and the same voltage (i.e., the first voltage pulse). The horizontal axis represents the number of times the voltage pulse is applied, and the vertical axis represents the conductance. Figure 3 As shown in FIG. 1 , when a plurality of voltage pulses of the same polarity and the same voltage are continuously applied to the first variable resistance nonvolatile memory element 10 to reduce the resistance, as shown in FIG. Figure 3 As shown in the curve of the black circle on the upper side of the rectangular waveform in FIG, the change in conductance under the first voltage pulse is large, and the conductance increases from a high resistance state to a state close to a low resistance state by the first voltage pulse. After that, even if the second and third pulses are applied continuously, the change in conductance remains very small compared to the change in conductance under the first voltage pulse. Similarly, when a plurality of voltage pulses of the same polarity and the same voltage are applied continuously to the first variable resistance nonvolatile memory element 10 to increase resistance, as shown in FIG. Figure 3As shown by the curve of the black circle below the rectangular waveform in , the change amount of conductance under the first voltage pulse is large, and the conductance is reduced from a low resistance state to a state close to a high resistance state by the first voltage pulse. After that, even if the second and third pulses are applied continuously, the change amount of conductance remains very small compared to the change amount of conductance under the first voltage pulse. In other words, the first variable resistance nonvolatile memory element 10 has the following characteristics: the conductance changes discontinuously (or nonlinearly) by the continuous application of the first voltage pulse having a voltage of a different magnitude from that of the second variable resistance nonvolatile memory element 20.

[0092] In the first variable resistance nonvolatile memory element 10 exhibiting such a variable resistance characteristic, the conductance itself in the low resistance state (in other words, the multi-level simulated resistance value) can be adjusted by a current limiting circuit connected to the element. That is, the first variable resistance nonvolatile memory element 10 has the following characteristics: the conductance changes greatly due to the first voltage pulse in the application of continuous voltage pulses, and the change amount is small in the subsequent voltage pulses. Therefore, the first variable resistance nonvolatile memory element 10 can be said to be a variable resistance nonvolatile memory element suitable for setting (initial setting) of a high-precision coupling weight coefficient when a product is shipped. That is, by using the first variable resistance nonvolatile memory element 10 and the current limiting circuit, in an artificial intelligence processing device using the variable resistance nonvolatile memory element, when the coupling weight coefficient is not sufficiently updated during firmware updates, learning model updates, regular maintenance, and changes in the conductance of the second variable resistance nonvolatile memory element 20 before and after product shipment, the conductance setting value of each element can be obtained in advance and written into each element.

[0093] Next, the manner in which the conductance of the second variable resistance nonvolatile memory element 20 of this embodiment changes will be described. Figure 4 The resistance change characteristic is when the conductance of the second variable resistance nonvolatile memory element 20 of the present embodiment is changed to a high resistance state or a low resistance state by continuously applying a plurality of voltage pulses (i.e., second voltage pulses) of the same polarity and the same voltage whose voltage magnitude is different from that of the first variable resistance nonvolatile memory element 10. The horizontal axis represents the number of times the voltage pulses are applied, and the vertical axis represents the conductance.

[0094] like Figure 4 As shown in FIG. 1 , when a plurality of voltage pulses of the same polarity and the same voltage are continuously applied to the second variable resistance nonvolatile memory element 20 to reduce the resistance, as shown in FIG. Figure 4As shown by the curve of the black circle in the rising waveform in FIG, the change ratio of the conductance under the first voltage pulse is smaller than the change ratio of the conductance under the first voltage pulse in the first variable resistance nonvolatile memory element 10. After that, when the second and third pulses are applied successively, the conductance continues to change in the direction of low resistance. Similarly, when a plurality of voltage pulses of the same polarity and the same voltage are applied successively to the second variable resistance nonvolatile memory element 20 to increase resistance, as shown in FIG. Figure 4 As shown by the curve of the black circle in the falling waveform in , the change ratio of the conductance under the first voltage pulse is smaller than the change ratio of the conductance under the first voltage pulse in the first variable resistance nonvolatile memory element 10. Afterwards, when the second and third pulses are applied successively, the change of conductance toward the high resistance direction continues.

[0095] In the second variable resistance nonvolatile memory element 20 showing such a variable resistance characteristic, regardless of the conductance before the pulse application, by applying a voltage pulse with a polarity in the direction of low resistance or a voltage pulse with a polarity in the direction of high resistance, a certain amount of conductance increase (low resistance) or conductance decrease (high resistance) can be generated. That is, the second variable resistance nonvolatile memory element 20 has the characteristic that the conductance gradually changes due to continuous voltage pulses. Therefore, the second variable resistance nonvolatile memory element 20 can be said to be a variable resistance nonvolatile memory element suitable for efficient updating (learning) of coupling weight coefficients after the product leaves the factory. That is, by using the second variable resistance nonvolatile memory element 20, in an artificial intelligence processing device using a variable resistance nonvolatile memory element, when updating the coupling weight coefficient for learning after the product leaves the factory, it is possible to directly write a certain amount of conductance increase or decrease to each element. When voltage pulses of the same polarity and the same voltage are applied multiple times in succession, the ratio of the change in conductance in the second voltage pulse to the change in conductance in the first voltage pulse in the second variable resistance nonvolatile memory element 20 is greater than the ratio of the change in conductance in the second voltage pulse to the change in conductance in the first voltage pulse in the first variable resistance nonvolatile memory element 10. In other words, the second variable resistance nonvolatile memory element 20 has a feature that the conductance changes continuously (or linearly) by the continuous application of the second voltage pulse having a voltage of a different magnitude from that of the first variable resistance nonvolatile memory element 10.

[0096] As described above, although the difference is caused by the difference in driving conditions (i.e., the size of the applied voltage pulse), if the first variable resistance nonvolatile memory element 10 that roughly reaches the set conductance by a single voltage pulse is compared with the second variable resistance nonvolatile memory element 20 that gradually changes conductance by continuous application of multiple voltage pulses of the same polarity and the same voltage, it is considered that the first variable resistance nonvolatile memory element 10 that can set conductance by a single voltage pulse can more firmly maintain a specific resistance state, and therefore it is considered that the retention characteristics after writing (i.e., storage tolerance) are high. On the other hand, the second variable resistance nonvolatile memory element 20 that gradually changes conductance by continuous application of multiple voltage pulses of the same polarity and the same voltage has a small degree of element degradation caused by writing itself, and has a high durability characteristic (i.e., writing characteristic).

[0097] [Driving Conditions of the Resistance Variable Nonvolatile Memory Element]

[0098] Next, we will refer to Figure 5A and Figure 5B The driving conditions of the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 are described in detail.

[0099] Figure 5A 1 Super-Cycle ( FIG. 1 ) is a diagram for explaining the definition of the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20. Here, a voltage pulse of the same polarity and the same voltage is applied 20 times in a low resistance process, and then a voltage pulse of the opposite polarity and the same voltage is applied 20 times in a high resistance process. Figure 5A The relationship between the number of voltage pulses (horizontal axis) and the conductance (vertical axis) when the drive is repeated 50 times ("nth_Cycle" in FIG. 5 ).

[0100] exist Figure 5A Medium, 0 th _LR, 1 th _LR and Max_LR respectively represent the conductance after the 0th voltage pulse application (i.e., as the initial value) in the process of reducing resistance under 1 Super-Cycle, the conductance after the 1st voltage pulse application, and the maximum conductance. th _HR, 1 th _HR and Min_HR respectively represent the conductance after the 0th voltage pulse application (ie, as the initial value) in the resistance increasing process of 1 Super-Cycle, the conductance after the 1st voltage pulse application, and the minimum conductance.

[0101] Here, the rate of change in conductance due to the first voltage pulse in the process of reducing resistance is referred to as Ratio_LR, and Ratio_LR is defined as the following formula 1.

[0102] Ratio_LR=(1 th _LR-0 th _LR) / (Max_LR-0 th _LR)(Formula 1)

[0103] In addition, the rate of change of conductance due to the first voltage pulse in the process of increasing resistance is referred to as Ratio_HR, and Ratio_HR is defined as the following formula 2.

[0104] Ratio_HR=(1 th _HR-0 th _HR) / (Min_HR-0 th _HR)(Formula 2)

[0105] In addition, Ratio_LR and Ratio_HR are collectively referred to as Ratio (rate of change).

[0106] Using the above definition, in this application specification, the resistance variable nonvolatile memory element driven under the driving condition of Ratio>0.7 is referred to as the "first resistance variable nonvolatile memory element" or digital RAND (Resistive Analog Neuro Device). In addition, the resistance variable nonvolatile memory element driven under the driving condition of Ratio<0.4 is referred to as the "second resistance variable nonvolatile memory element" or analog RAND.

[0107] In addition, strictly speaking, the "second resistance change non-volatile memory element" or analog RAND does not necessarily need to be driven under the same driving conditions (i.e., Ratio_LR<0.4 and Ratio_HR<0.4) in both the low resistance process and the high resistance process, and can also be driven under driving conditions that satisfy at least one of Ratio_LR<0.4 and Ratio_HR<0.4.

[0108] Figure 5BThis is a diagram for explaining the driving conditions of the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20. Here, the voltage of the voltage pulse used to make the variable resistance nonvolatile memory element high resistance as a digital RAND is set to 1.0, the voltage ratio of the actually applied voltage pulse (HR-pulse_Voltage_Ratio) is set as the horizontal axis, and the Ratio obtained by the voltage pulse is set as the vertical axis, and the results obtained by the experiment are plotted. The circular graph represents the results obtained in the low resistance process, and the square graph represents the results obtained in the high resistance process.

[0109] exist Figure 5B In the embodiment, the region satisfying "Ratio>0.7" is recorded as "digital operation", which is a region where the variable resistance nonvolatile memory element operates as the first variable resistance nonvolatile memory element 10 or the digital RAND. In addition, the region satisfying "Ratio<0.4" is recorded as "analog operation", which is a region where the variable resistance nonvolatile memory element operates as the second variable resistance nonvolatile memory element 20 or the analog RAND.

[0110] In addition, in obtaining Figure 5B In the experiment of the characteristics shown, the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 were driven under the same driving conditions during the process of reducing the resistance.

[0111] according to Figure 5B It can be seen that by applying the following driving condition of Formula 3 to the resistance variable non-volatile memory element, that is, by applying a voltage pulse with a voltage smaller than 0.71 times the voltage of the voltage pulse that makes the resistance variable non-volatile memory element high-resistance as a digital RAND to the resistance variable non-volatile memory element, the resistance variable non-volatile memory element can be caused to operate as the second resistance variable non-volatile memory element 20 or the analog RAND.

[0112] HR-pulse_Voltage_Ratio<0.71(Formula 3)

[0113] [Configuration of resistance variable nonvolatile memory element]

[0114] Fig. 6A and Figure 6B A circuit diagram and a cross-sectional view of a variable resistance nonvolatile memory element in the prior art.

[0115] Fig. 6AThis is a circuit diagram showing a memory cell of an artificial intelligence processing device equipped with a conventional variable resistance nonvolatile memory element. The memory cell MC is composed of a series connection of a variable resistance nonvolatile memory element RP and a cell transistor T0, and is a "1T1R" type memory cell composed of a cell transistor T0 and a variable resistance nonvolatile memory element RP. The word line WL of the memory cell MC is connected to the gate terminal of the cell transistor T0, the bit line BL is connected to the variable resistance nonvolatile memory element RP, and the source line SL is connected to the source terminal of the cell transistor T0.

[0116] Figure 6B A cross-sectional view of a memory cell of an artificial intelligence processing device equipped with a conventional variable resistance nonvolatile memory element RP is shown. Diffusion regions 61a and 61b are formed on a substrate 60, and the diffusion region 61a functions as a source terminal of a cell transistor T0, and the diffusion region 61b functions as a drain terminal of the cell transistor. The region between the diffusion regions 61a and 61b functions as a channel region of the cell transistor T0, and an oxide film 62 and a gate electrode 63 formed of polysilicon are formed on the channel region, and the cell transistor T0 operates. The diffusion region 61a, which is the source terminal of the cell transistor T0, is connected to the source line SL, which is the first wiring layer 65a, via a through hole 64a. The diffusion region 61b, which is the drain terminal of the cell transistor T0, is connected to the first wiring layer 65b via a through hole 64b. In addition, the first wiring layer 65b is connected to the second wiring layer 67 via a through hole 66, and the second wiring layer 67 is connected to the variable resistance nonvolatile memory element RP via a through hole 68a. The variable resistance nonvolatile memory element RP includes a first electrode 2, a variable resistance layer 3, and a second electrode 4. The variable resistance nonvolatile memory element RP is connected to a bit line BL as a third wiring layer 69 via a through hole 68b.

[0117] In this structure, as the variable resistance nonvolatile memory element RP, only the first variable resistance nonvolatile memory element 10 of the embodiment that approximately reaches the set conductance by a single voltage pulse is mounted on the artificial intelligence processing device. Therefore, it is difficult to achieve both high-efficiency and high-precision setting of the coupling weight coefficient (initial setting) when the product is shipped and high-efficiency updating (learning) of the coupling weight coefficient after the product is shipped.

[0118] Figure 7A to Figure 7C It is a diagram showing an example of a circuit diagram and a cross-sectional view of a variable resistance nonvolatile memory element according to an embodiment.

[0119] Fig. 7AA circuit diagram showing a memory cell of an artificial intelligence processing device equipped with both a first variable resistance nonvolatile memory element 10 and a second variable resistance nonvolatile memory element 20. The memory cell MC is formed by connecting the first variable resistance nonvolatile memory element 10 capable of setting conductance by a single voltage pulse, the second variable resistance nonvolatile memory element 20 capable of gradually changing conductance by continuously applying a plurality of voltage pulses of the same polarity and the same voltage satisfying the above formula 3, and a cell transistor T0, and is a "1T2R" type memory cell consisting of one cell transistor T0 and two variable resistance nonvolatile memory elements. The word line WL of the memory cell MC is connected to the gate terminal of the cell transistor T0, the bit line BL1 is connected to the first variable resistance nonvolatile memory element 10, the bit line BL2 is connected to the second variable resistance nonvolatile memory element 20, and the source line SL is connected to the source terminal of the cell transistor T0.

[0120] Figure 7B Indicates that it is equipped with Fig. 7A An example of a cross-sectional view of a memory cell of an artificial intelligence processing device showing both a first variable resistance nonvolatile memory element 10 and a second variable resistance nonvolatile memory element 20. Here, a structural example is shown in which the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 are arranged on a first layer sandwiched by two wiring layers and a second layer different from the first layer sandwiched by two wiring layers, respectively.

[0121] Diffusion regions 71a and 71b are formed on a semiconductor substrate 70. The diffusion region 71a functions as a source terminal of the cell transistor T0, and the diffusion region 71b functions as a drain terminal of the cell transistor. The region between the diffusion regions 71a and 71b functions as a channel region of the cell transistor T0. An oxide film 72 and a gate electrode 73 formed of polysilicon are formed on the channel region, and the cell transistor T0 operates. The diffusion region 71a, which functions as a source terminal of the cell transistor T0, is connected to a source line SL, which functions as a first wiring layer 75a, via a through hole 74a. The diffusion region 71b, which functions as a drain terminal of the cell transistor T0, is connected to the first wiring layer 75b via a through hole 74b.

[0122] Furthermore, the first wiring layer 75b is connected to the second wiring layer 77 via the through hole 76a, and the second wiring layer 77 is connected to the first variable resistance nonvolatile memory element 10 via the through hole 78a. The first variable resistance nonvolatile memory element 10 includes a first electrode 2, a variable resistance layer 3, and a second electrode 4. The first variable resistance nonvolatile memory element 10 is connected to the bit line BL1 as the third wiring layer 79 via the through hole 78b.

[0123] In addition, at the same time, the second wiring layer 77 is connected to the second variable resistance nonvolatile memory element 20 via the through hole 76c. The second variable resistance nonvolatile memory element 20 includes the first electrode 12, the variable resistance layer 13, and the second electrode 14. The second variable resistance nonvolatile memory element 20 is connected to the bit line BL2 as the first wiring layer 75c via the through hole 76b. In this configuration, when viewed from a direction perpendicular to the substrate plane, the center of the first variable resistance nonvolatile memory element 10 and the center of the second variable resistance nonvolatile memory element 20 are aligned.

[0124] Figure 7C Indicates that it is equipped with Fig. 7A The cross-sectional view of the memory cell of the artificial intelligence processing device including the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 is similar to the previous one (ie, Figure 7B Here, a structural example in which the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 are arranged in the same layer sandwiched between two wiring layers is illustrated.

[0125] Diffusion regions 81a and 81b are formed on a semiconductor substrate 80. Diffusion region 81a functions as a source terminal of a cell transistor T0, and diffusion region 81b functions as a drain terminal of the cell transistor. The region between diffusion regions 81a and 81b functions as a channel region of the cell transistor T0. An oxide film 82 and a gate electrode 83 formed of polysilicon are formed on the channel region, and the cell transistor T0 operates. Diffusion region 81a, which functions as a source terminal of the cell transistor T0, is connected to a source line SL, which functions as a first wiring layer 85a, via a through hole 84a. Diffusion region 81b, which functions as a drain terminal of the cell transistor T0, is connected to a first wiring layer 85b via a through hole 84b.

[0126] Furthermore, the first wiring layer 85b is connected to the second wiring layer 87b via the through hole 86c, and the second wiring layer 87b is connected to the first variable resistance nonvolatile memory element 10 via the through hole 88a. The first variable resistance nonvolatile memory element 10 includes a first electrode 2, a variable resistance layer 3, and a second electrode 4. The first variable resistance nonvolatile memory element 10 is connected to the bit line BL1 as the third wiring layer 89b via the through hole 88b.

[0127] In addition, at the same time, the first wiring layer 85b is connected to the second wiring layer 87a via the through hole 86a, and the second wiring layer 87a is connected to the second variable resistance nonvolatile memory element 20 via the through hole 88c. The second variable resistance nonvolatile memory element 20 includes the first electrode 12, the variable resistance layer 13, and the second electrode 14. The second variable resistance nonvolatile memory element 20 is connected to the bit line BL2 as the third wiring layer 89a via the through hole 88d. In this configuration, when viewed from a direction perpendicular to the substrate plane, the center of the first variable resistance nonvolatile memory element 10 and the center of the second variable resistance nonvolatile memory element 20 do not coincide.

[0128] In addition, Figure 7B In the present invention, the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20 are arranged between different wiring layers between the first wiring layer and the third wiring layer, but the same effect can be obtained even if they are arranged between other wiring layers, for example, between the second wiring layer and the fourth wiring layer.

[0129] In addition, Figure 7C In the present invention, the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20 are arranged in a layer sandwiched by the second wiring layer and the third wiring layer, but the same effect can be obtained even if they are arranged between other wiring layers, for example, in a layer sandwiched by the first wiring layer and the second wiring layer.

[0130] In the case of existing Fig. 6A In the embodiment, the current flowing in the bit line BL or the source line SL, that is, the current flowing in the variable resistance nonvolatile memory element RP is defined as the current flowing in the memory cell MC. Fig. 7A In the example, the current flowing in the memory cell MC is defined as the sum of the currents flowing in the bit line BL1 and the bit line BL2, or the current flowing in the source line SL, that is, the sum of the currents flowing in the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20.

[0131] exist Figure 7A to Figure 7C In the memory cell MC shown, the signal in the word line WL is equivalent to an input signal input to a neuron, the sum of the conductances of the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 is equivalent to a coupling weight coefficient corresponding to the input signal, and the sum of the currents flowing through the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 (i.e., the sum of the currents flowing through the bit line BL1 and the bit line BL2, or the current flowing through the source line SL) is equivalent to the product of the input signal and the coupling weight coefficient.

[0132] Figure 8A to Figure 8C It is a diagram showing an example of a circuit diagram and a cross-sectional view of a variable resistance nonvolatile memory element according to another embodiment.

[0133] Fig. 8A A circuit diagram showing a memory cell of an artificial intelligence processing device equipped with both a first variable resistance nonvolatile memory element 10 and a second variable resistance nonvolatile memory element 20. The memory cell MC1 is composed of a first variable resistance nonvolatile memory element 10 whose conductance can be set by a single voltage pulse and a cell transistor T1 connected together, and the memory cell MC2 is composed of a second variable resistance nonvolatile memory element 20 whose conductance gradually changes by continuous application of a plurality of voltage pulses of the same polarity and the same voltage satisfying the above formula 3 and a cell transistor T2 connected together, and is a "2T2R" type memory cell composed of two cell transistors T1 and T2 and two variable resistance nonvolatile memory elements. The word line WL1 of the memory cell MC1 is connected to the gate terminal of the cell transistor T1, the word line WL2 of the memory cell MC2 is connected to the gate terminal of the cell transistor T2, the bit line BL is connected to the first resistance variable non-volatile memory element 10 and the second resistance variable non-volatile memory element 20, and the source line SL is connected to the source terminals of the cell transistors T1 and T2.

[0134] Figure 8B express Fig. 8A An example of a cross-sectional view of a memory cell MC1 of an artificial intelligence processing device equipped with a first variable resistance nonvolatile memory element 10 is described. Diffusion regions 91a and 91b are formed on a semiconductor substrate 90, and the diffusion region 91a functions as a source terminal of the cell transistor T1, and the diffusion region 91b functions as a drain terminal of the cell transistor T1. The area between the diffusion regions 91a and 91b functions as a channel region of the cell transistor T1, and an oxide film 92 and a gate electrode 93 formed of polysilicon are formed on the channel region, so that the cell transistor T1 operates. The diffusion region 91a, which is the source terminal of the cell transistor T1, is connected to the source line SL, which is the first wiring layer 95a, via a through hole 94a. The diffusion region 91b, which is the drain terminal of the cell transistor T1, is connected to the first wiring layer 95b via a through hole 94b.

[0135] Furthermore, the first wiring layer 95b is connected to the second wiring layer 97 via the through hole 96, and the second wiring layer 97 is connected to the first variable resistance nonvolatile memory element 10 via the through hole 98a. The first variable resistance nonvolatile memory element 10 includes a first electrode 2, a variable resistance layer 3, and a second electrode 4. The first variable resistance nonvolatile memory element 10 is connected to the bit line BL as the third wiring layer 99 via the through hole 98b.

[0136] Figure 8C express Fig. 8A An example of a cross-sectional view of a memory cell MC2 of an artificial intelligence processing device having a second variable resistance nonvolatile memory element 20 mounted thereon. Figure 8B Diffusion regions 101a and 101b are formed on the common substrate 90. Diffusion region 101a functions as a source terminal of the cell transistor T2, and diffusion region 101b functions as a drain terminal of the cell transistor T2. The area between diffusion regions 101a and 101b functions as a channel region of the cell transistor T2. An oxide film 102 and a gate electrode 103 formed of polysilicon are formed on the channel region, and the cell transistor T2 functions as the cell transistor T2. Diffusion region 101a, which functions as a source terminal of the cell transistor T2, is connected to the cell transistor T2 via a through hole 104a. Figure 8B The common source line SL of the first wiring layer 95a and the diffusion region 101b serving as the drain terminal of the cell transistor T2 are connected to the first wiring layer 105 via a through hole 104b.

[0137] Furthermore, the first wiring layer 105 is connected to the second wiring layer 107 via the through hole 106, and the second wiring layer 107 is connected to the second variable resistance nonvolatile memory element 20 via the through hole 108a. The second variable resistance nonvolatile memory element 20 includes the first electrode 12, the variable resistance layer 13, and the second electrode 14. The second variable resistance nonvolatile memory element 20 is connected to the second variable resistance nonvolatile memory element 20 via the through hole 108b. Figure 8B The common third wiring layer 99 is the bit line BL.

[0138] In addition, Figure 8B and Figure 8C In the present invention, the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20 are arranged in a layer sandwiched by the second wiring layer and the third wiring layer, but the same effect can be obtained even if they are arranged between other wiring layers, for example, between the first wiring layer and the second wiring layer.

[0139] Furthermore, even if the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 are arranged between different wiring layers, the same effect can be obtained.

[0140] In the case of existing Fig. 6A In the embodiment, the current flowing in the bit line BL or the source line SL, that is, the current flowing in the variable resistance nonvolatile memory element RP is defined as the current flowing in the memory cell MC. Fig. 8A, the current flowing in the bit line BL or the source line SL is defined as the sum of the current flowing in the memory cell MC1 and the current flowing in the memory cell MC2, that is, the sum of the current flowing in the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20.

[0141] If we focus on Figure 8A to Figure 8C In the memory cell shown as a combination of memory cell MC1 and memory cell MC2, the signal flowing in word lines WL1 and WL2 together is equivalent to an input signal input to a neuron, the sum of the conductances of the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 is equivalent to a coupling weight coefficient corresponding to the input signal, and the sum of the currents flowing through the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 (i.e., the current flowing through the bit line BL, or the current flowing through the source line SL) is equivalent to the product of the input signal and the coupling weight coefficient.

[0142] like Figure 7A to Figure 7C and Figure 8A to Figure 8C As shown, in an artificial intelligence processing device of an embodiment equipped with a first variable resistance nonvolatile memory element 10 that approximately reaches a set conductance by a single voltage pulse, and a second variable resistance nonvolatile memory element 20 that gradually changes conductance by continuously applying multiple voltage pulses of the same polarity and the same voltage that satisfy the above-mentioned formula 3, since two elements can be used, the first variable resistance nonvolatile memory element 10 changes conductance when the coupling weight coefficient is not sufficiently updated during firmware updates, learning model updates, and regular maintenance before and after product shipment, and in changes in conductance of the second variable resistance nonvolatile memory element 20. The second variable resistance nonvolatile memory element 20 adopts a method of using the second variable resistance nonvolatile memory element 20 such that the conductance is changed when the coupling weight coefficient for learning is updated after product shipment. This allows for both efficient and high-precision setting (initial setting) of the coupling weight coefficient before and after product shipment and efficient updating (learning) of the coupling weight coefficient after product shipment. That is, when changing (i.e., writing) the coupling weight coefficient, the conductance of only one of the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20 is changed according to the current purpose, and when using the artificial intelligence processing device to make inferences (i.e., reading the coupling weight coefficient), the total value of the current flowing in both the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20 is used.

[0143] In addition, in an artificial intelligence processing device, when there is a first neural network region that directly uses the coupling weight coefficient setting of an existing neural network and a second neural network region that is newly learned, transfer learning or reinforcement learning can be efficiently performed by changing the conductance of the first variable resistance nonvolatile memory element 10 in the setting of the coupling weight coefficient of the first neural network region and changing the conductance of the second variable resistance nonvolatile memory element 20 in the setting of the coupling weight coefficient of the second neural network region.

[0144] [Example]

[0145] Next, an embodiment of the artificial intelligence processing device disclosed in the present invention is described.

[0146] Fig.9A 1 is a block diagram showing a model of an artificial intelligence processing device 200 according to an embodiment. The artificial intelligence processing device 200 is a neural network composed of an input layer 201, a plurality of hidden layers 202, and an output layer 203. Each layer (input layer 201, hidden layer 202, output layer 203) is composed of a plurality of neurons 210. Output data from the neurons 210 constituting the previous layer is input to each neuron 210 via a synapse 211.

[0147] Fig. 9B Yes means Fig.9A The neuron 210 performs the following product-sum operation (Σw i ·x i ): receiving the output data from the neuron 210 constituting the previous layer via the synapse 211 as the input data x i , for all input data x i , the received input data x i Multiply by the coupling weight coefficient w corresponding to the synapse 211 i The obtained product (w i ·x i ) are added. Then, neuron 210 adds the internal bias b to the result of the product-sum operation and obtains the result (Σw i ·x i +b) is input to an activation function f such as a step function inside, thereby generating output data y, and outputting it to each neuron 210 constituting the next layer.

[0148] Fig. 10A It shows the realization Fig. 9B FIG. 2 is a diagram showing an example of a circuit of a neuron 210 shown in FIG. 2. In this figure, a memory cell MCij (i=0 to m, j=0 to n) arranged two-dimensionally is shown. Fig. 7A The circuit example of the 1T2R type memory cell MC is shown in FIG. The neuron 210 is composed of a product-sum operation circuit 215, a word line selection circuit 230, a determination circuit 250, and a column gate (transistors YTi1, YTi2, transistor DTi).

[0149] The product-sum operation circuit 215 is a circuit that performs product-sum operation in the neuron 210, and a plurality of Fig. 7A The 1T2R type memory cell shown in FIG. 1 is connected so that the bit lines BLi1 and BLi2 and the source line SLi are shared. The current output from each memory cell corresponds to the input data x i and the coupling weight coefficient w i The product (w i ·x i ), these currents merge, and the current flowing in the source line SLi (or the sum of the currents flowing in the bit lines BLi1 and BLi2) is equivalent to the product-sum operation result Σw i ·x i In the product-sum operation circuit 215, the input data x i is "1" or "0", the coupling weight coefficient w i Corresponds to the total of the conductances of the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 .

[0150] Note that in this figure, Fig.9A The plurality of product-sum operation circuits 215 corresponding to all neurons 210 shown are arranged side by side in the row direction, and one of the product-sum operation circuits 215 performs a product-sum operation in one neuron 210 .

[0151] The word line selection circuit 230 is a circuit that supplies input data x0 to xn for selecting or not selecting memory cells in row units to gate terminals of transistors Ti included in memory cells MCi0 to MCin constituting the product-sum operation circuit 215 via word lines WL0 to WLn.

[0152] The determination circuit 250 is a circuit for executing the activation function f of the neuron 210, and for determining the current flowing through the source line SLi or the sum of the currents flowing through the bit lines BLi1 and BLi2 (Σw i ·x i ) plus the internal bias b (Σw i ·x i +b) is compared with a prescribed threshold value and outputted. The determination circuit 250 can perform processing in parallel on a plurality of product-sum operation circuits 215 arranged in the row direction.

[0153] The transistors YTi1 and YTi2 constituting the column gate connect or disconnect the bit lines BLi1 and BLi2 of the memory cells MCi0 to MCin to a predetermined power supply voltage, respectively, according to the signal input to the gate terminal when writing to or reading from the memory cells MCi0 to MCin. In addition, the transistor DTi connects or disconnects the source line SLi to a predetermined power supply voltage, according to the signal input to the gate terminal when writing to or reading from the memory cells MCi0 to MCin.

[0154] Fig. 10B It shows the realization Fig. 9B FIG. 2 is a diagram of another circuit example (neuron 210a) of the neuron 210 shown in FIG. In this figure, a plurality of memory cells MCij (i=0 to m, j=0 to n) are arranged in the column direction. Fig. 8A The 2T2R memory cell MC shown in the figure is connected in a manner that the bit line BLi and the source line SLi are shared. The neuron 210a is composed of a product-sum operation circuit 215a, a word line selection circuit 230a, a determination circuit 250a and a column gate (transistor YTi, transistor DTi).

[0155] The basic function of the neuron 210a is Fig. 10A The neuron 210 shown is identical to the one formed by the memory cell MCij of the 1T2R type. Fig. 10A The neuron 210 is different from the one of the 2T2R type memory cell MCij. The word line selection circuit 230a outputs two word lines WLj1 and WLj2 to the memory cells MCi0 to MCin respectively. The determination circuit 250a determines the value of the word line by combining the internal bias b with the current (Σw i ·x i ) is added to obtain the value (Σw i ·x i +b) is compared with a predetermined threshold value and the comparison result is output. The bit line BLi or source line SLi indicates the result of the product-sum operation output from the product-sum operation circuit 215a. As for the column gate, a transistor YTi is provided for each bit line BLi to switch between connection and non-connection with a prescribed power supply voltage.

[0156] Fig.11 It means by Fig. 10A The block diagram of the overall structure of the artificial intelligence processing device 200 is shown as a neuron 210. The artificial intelligence processing device 200 is composed of a memory cell array 220, a word line selection circuit 230, a column gate 240, a determination circuit 250, a write circuit 260 and a control circuit 270.

[0157] The memory cell array 220 is equivalent to Fig. 10A The memory cell MCij (i=0-m, j=0-n) shown in FIG. 2 is a memory cell MCij (i=0-m, j=0-n). The word line selection circuit 230, the column gate 240, the determination circuit 250 and the Fig. 10A Same as described in .

[0158] The write circuit 260 is provided in Fig. 10A The circuit for providing a predetermined power supply voltage described in the above description has a current limiting circuit for writing a desired conductance (in other words, a multi-level analog resistance value) to the memory cell MCij.

[0159] More specifically, under the control of the control circuit 270, the write circuit 260 applies a first voltage pulse having a first voltage to the first variable resistance nonvolatile memory element 10 to rewrite the conductance of the first variable resistance nonvolatile memory element 10, and applies a second voltage pulse having a second voltage different from the first voltage to the second variable resistance nonvolatile memory element 20 to rewrite the conductance of the second variable resistance nonvolatile memory element 20. The second voltage in the high resistance process is 0.71 times or less of the first voltage in the high resistance process, for example, a voltage designated from a plurality of voltages of 0.7 times, 0.5 times, 0.3 times, or 0.71 times or less.

[0160] The control circuit 270 is a circuit for controlling writing and reading to the memory cell MCij by controlling the entire artificial intelligence processing device 200, and is composed of, for example, a memory storing a program and a processor. More specifically, when changing the coupling weight coefficient of the artificial intelligence processing device 200 (i.e., writing), the control circuit 270 controls the artificial intelligence processing device 200 in a manner that changes the conductance of only one of the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 constituting each memory cell MCij, depending on whether the purpose is to set the coupling weight coefficient with high accuracy (initial setting) at the time of product shipment or to update (learn) the coupling weight coefficient with high efficiency after product shipment. In addition, when the control circuit 270 uses the artificial intelligence processing device 200 (i.e., uses the coupling weight coefficient) for inference, the control circuit 270 controls the artificial intelligence processing device 200 in a manner that uses the total value of the current flowing in the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 constituting each memory cell MCij.

[0161] in addition, Fig.11 It means by Fig. 10A The block diagram of the overall structure of the artificial intelligence processing device 200 composed of neurons 210 shown in FIG. Fig. 10BThe block diagram of the overall structure of the artificial intelligence processing device 200 composed of the neuron 210a shown in FIG. Fig.11 The same, therefore, the illustration and description are omitted.

[0162] Fig. 12A Yes Fig. 10A The diagram shows an example of voltage applied via the word line WL, bit lines BL1, BL2 and source line SL when writing and reading from the memory cell MCij shown. Here, examples of voltage applied when resetting (high resistance) the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 constituting the memory cell MCij of the i-th column, setting (low resistance) and reading from the memory cell MCij are shown. Fig. 12A In the embodiment, “mode 1” indicates writing conductance to the first variable resistance nonvolatile memory element 10 (first rewriting step), and “mode 2” indicates writing conductance to the second variable resistance nonvolatile memory element 20 (second rewriting step). In addition, “writing to the memory cell MCij” means setting or changing the coupling weight coefficient to the memory cell MCij, and “reading from the memory cell MCij” means measuring the current flowing through the memory cell MCij.

[0163] (1) Writing to the memory cell MCij (setting or changing the coupling weight coefficient)

[0164] In the present embodiment, when resetting (“turning to high resistance”) the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 , writing is performed under different driving conditions.

[0165] That is, when resetting (“turning to high resistance”) the first variable resistance nonvolatile memory element 10 (“mode 1”), a pulse voltage V for turning on the transistor Ti is supplied to the gate terminal via the word line WL. g_on (e.g. 2V), a reset voltage V is applied to the bit line BL1 H1 (e.g. 2V), a reference voltage V is applied to the bit line BL2 ss (e.g. 0V), a reference voltage V is applied to the source line SL ss (e.g., 0 V). Thus, only for the first variable resistance nonvolatile memory element 10, a positive voltage is applied to the upper terminal with reference to the lower terminal of the first variable resistance nonvolatile memory element 10, and the resistance is increased to a resistance value corresponding to the limiting current of the current limiting circuit built into the write circuit 260.

[0166] When resetting (“turning to high resistance”) the second variable resistance nonvolatile memory element 20 (“mode 2”), a pulse voltage V for turning on the transistor Ti is supplied to the gate terminal via the word line WL. g_on (e.g. 2V), a reference voltage V is applied to the bit line BL1 ss (e.g. 0V), a reset voltage V is applied to the bit line BL2 H2 (For example, 1.4V (i.e. V H1 0.7 times of the reference voltage V is applied to the source line SL ss (e.g., 0 V). Thus, only for the second variable resistance nonvolatile memory element 20, a positive voltage is applied to the upper terminal with the lower terminal of the second variable resistance nonvolatile memory element 20 as a reference, and the resistance is increased to a resistance value corresponding to the limiting current of the current limiting circuit built into the write circuit 260.

[0167] On the other hand, when the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 are set ("low resistance"), in this embodiment, writing based on different driving conditions is not performed (that is, writing based on the same driving conditions is performed).

[0168] That is, when the first variable resistance nonvolatile memory element 10 is set (“low resistance”) (“mode 1”), a pulse voltage V for turning on the transistor Ti is supplied to the gate terminal via the word line WL. g_on (e.g. 2V), a reference voltage V is applied to the bit line BL1 ss (e.g. 0V), a set voltage V is applied to the bit line BL2 set (e.g. 2V), a set voltage V is applied to the source line SL set (For example, 2 V.) Thus, a negative voltage is applied to the upper terminal of only the first variable resistance nonvolatile memory element 10 with the lower terminal of the first variable resistance nonvolatile memory element 10 as a reference, thereby lowering the resistance to a resistance value corresponding to the limiting current of the current limiting circuit built into the write circuit 260.

[0169] When the second variable resistance nonvolatile memory element 20 is set (“low resistance”) (“mode 2”), a pulse voltage V for turning on the transistor Ti is supplied to the gate terminal via the word line WL. g_on (e.g. 2V), a set voltage V is applied to the bit line BL1 set (e.g. 2V), a reference voltage V is applied to the bit line BL2 ss (e.g. 0V), a set voltage V is applied to the source line SL set(For example, 2V). Thus, a negative voltage is applied to the upper terminal of the second variable resistance nonvolatile memory element 20 with the lower terminal of the second variable resistance nonvolatile memory element 20 as a reference, thereby lowering the resistance to a resistance value corresponding to the limiting current of the current limiting circuit built into the write circuit 260.

[0170] (2) Reading from memory cell MCij (inference step)

[0171] When measuring the total current flowing through the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 (“reading”), a read voltage V for turning on the transistor Ti is supplied to the gate terminal via the word line WL. g_read (e.g., 1V), and a read voltage V is applied to the bit lines BL1 and BL2. read (e.g. 0.4V), a reference voltage V is applied to the source line SL ss As a result, the read voltage V is applied to the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20. read The total current (i.e., a product (w i ·x i )). Thus, the current output from all memory cells MCij constituting the product-sum operation circuit 215 flows to the source line SL (also the sum of the currents flowing to the bit lines BL1 and BL2), and the product-sum operation result (Σw i ·x i ), measured by the decision circuit 250.

[0172] Fig. 12B Yes Fig. 10B 1 and 2 are diagrams showing examples of voltages applied via word lines WL1, WL2, bit lines BL, and source lines SL when writing and reading are performed on memory cell MCij. Here, examples of voltages applied when resetting (making the resistance higher) and setting (making the resistance lower) the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 constituting the memory cell MCij of the i-th column and reading from the memory cell MCij are shown.

[0173] (1) Writing to the memory cell MCij (setting or changing the coupling weight coefficient)

[0174] In the present embodiment, when resetting (“turning to high resistance”) the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 , writing is performed under different driving conditions.

[0175] That is, when resetting (“turning to high resistance”) the first variable resistance nonvolatile memory element 10 (“mode 1”), a pulse voltage V for turning on the transistor Ti1 is supplied to the gate terminal via the word line WL1. g_on (e.g., 2 V), a pulse voltage V that turns off transistor Ti2 is supplied to the gate terminal via word line WL2. g_off (e.g. 0V), a reset voltage V is applied to the bit line BL H1 (e.g. 2V), a reference voltage V is applied to the source line SL ss (e.g., 0 V). Thus, only for the first variable resistance nonvolatile memory element 10, a positive voltage is applied to the upper terminal with reference to the lower terminal of the first variable resistance nonvolatile memory element 10, and the resistance is increased to a resistance value corresponding to the limiting current of the current limiting circuit built into the write circuit 260.

[0176] When resetting (“turning to high resistance”) the second variable resistance nonvolatile memory element 20 (“mode 2”), a pulse voltage V1 that turns off the transistor Ti1 is supplied to the gate terminal via the word line WL1. g_off (e.g., 0 V), a pulse voltage V that turns on transistor Ti2 is supplied to the gate terminal via word line WL2. g_on (e.g. 2V), a reset voltage V is applied to the bit line BL H2 (For example, 1.4V (i.e., V H1 0.7 times of the reference voltage V is applied to the source line SL ss (e.g., 0 V). Thus, only for the second variable resistance nonvolatile memory element 20, a positive voltage is applied to the upper terminal with the lower terminal of the second variable resistance nonvolatile memory element 20 as a reference, and the resistance is increased to a resistance value corresponding to the limiting current of the current limiting circuit built into the write circuit 260.

[0177] On the other hand, when the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 are set ("low resistance"), in this embodiment, writing based on different driving conditions is not performed (that is, writing based on the same driving conditions is performed).

[0178] When the first variable resistance nonvolatile memory element 10 is set (“low resistance”) (“mode 1”), a pulse voltage V for turning on the transistor Ti1 is supplied to the gate terminal via the word line WL1. g_on (e.g., 2V), a pulse voltage V is supplied to the gate terminal via the word line WL2 to turn off the transistor Ti2. g_off (e.g. 0V), a reference voltage V is applied to the bit line BL ss(e.g. 0V), a set voltage V is applied to the source line SL set (For example, 2 V.) Thus, a negative voltage is applied to the upper terminal of only the first variable resistance nonvolatile memory element 10 with the lower terminal of the first variable resistance nonvolatile memory element 10 as a reference, thereby lowering the resistance to a resistance value corresponding to the limiting current of the current limiting circuit built into the write circuit 260.

[0179] When the second variable resistance nonvolatile memory element 20 is set (“low resistance”) (“mode 2”), a pulse voltage V for turning off the transistor Ti1 is supplied to the gate terminal via the word line WL1. g_off (e.g., 0 V), a pulse voltage V that turns on transistor Ti2 is supplied to the gate terminal via word line WL2. g_on (e.g. 2V), a reference voltage V is applied to the bit line BL ss (e.g. 0V), a set voltage V is applied to the source line SL set (For example, 2V). Thus, a negative voltage is applied to the upper terminal of the second variable resistance nonvolatile memory element 20 with the lower terminal of the second variable resistance nonvolatile memory element 20 as a reference, thereby lowering the resistance to a resistance value corresponding to the limiting current of the current limiting circuit built into the write circuit 260.

[0180] (2) Reading from memory cell MCij (inference step)

[0181] When the total current flowing through the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 is measured (“reading”), a read voltage V for turning on the transistors Ti1 and Ti2 is supplied to the gate terminals via the word lines WL1 and WL2. g_read (e.g. 1V), a read voltage V is applied to the bit line BL read (e.g. 0.4V), a reference voltage V is applied to the source line SL ss As a result, the read voltage V is applied to the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20. read The current flowing through the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 is output from the memory cell MCij (the total of which corresponds to a product (w i ·x i )). Thus, the current output from all the memory cells MCij constituting the product-sum operation circuit 215 flows to the source line SL and the bit line BL, and the product-sum operation result (Σw i ·x i ), measured by the decision circuit 250.

[0182] Fig.13 Yes means Fig.11 Flowchart of an operation example of the control circuit 270 shown.

[0183] The control circuit 270 determines whether the setting process of the coupling weight coefficient to be performed from now on is the first case of changing the coupling weight coefficient for initial setting or the second case of changing the coupling weight coefficient during learning (S30). In addition, the first case includes at least one of firmware update before and after the artificial intelligence processing device 200 is shipped, update of the learning model, regular maintenance, and change of the conductance of the second variable resistance non-volatile memory element 20 when the update of the coupling weight coefficient is insufficient, and the second case includes the update of the coupling weight coefficient for learning after the artificial intelligence processing device 200 is shipped.

[0184] As a result, when it is determined that the setting process of the coupling weight coefficient is the initial setting (i.e., the first instance) (“initial setting” in S30), the control circuit 270 selects the first variable resistance non-volatile memory element 10 for each memory cell MCij by controlling the column gate 240 or the word line selection circuit 230 and the write circuit 260 (S31), and performs a coupling operation with the selected first variable resistance non-volatile memory element 10. Fig. 12A or Fig. 12B In other words, the control circuit 270 writes the conductance derived in advance to the first variable resistance nonvolatile memory element 10 (i.e., "mode 1") for each memory cell MCij (first rewriting step).

[0185] On the other hand, in step S30, when it is determined that the setting process of the coupling weight coefficient is an update of the coupling weight coefficient based on learning (i.e., the second case) ("update of the coupling weight coefficient based on learning" in S30), the control circuit 270 uses the coupling weight coefficient currently stored in the memory cell array 220 to perform inference (S35), and after confirming the difference between the inference result and the teacher label (S36), the change amount of the coupling weight coefficient during the update is calculated for each memory cell MCij (S37). Then, the control circuit 270 selects the second variable resistance nonvolatile memory element 20 for each memory cell MCij by controlling the column gate 240 or the word line selection circuit 230 (S38), and performs the inference on the selected second variable resistance nonvolatile memory element 20 based on the teacher label. Fig. 12A or Fig. 12BThe drive condition corresponding to the mode 2 shown in FIG. 1 is written, thereby updating the coupling weight coefficient so that the current coupling weight coefficient changes by the calculated change amount of the coupling weight coefficient (S39). That is, the control circuit 270 updates the conductance of the second variable resistance nonvolatile memory element 20 (i.e., "mode 2") for each memory cell MCij by the change amount (second rewriting step).

[0186] Therefore, depending on whether the purpose is initial setting or learning, only the first resistance variable non-volatile storage element 10 or the second resistance variable non-volatile storage element 20 suitable for the purpose is written, thereby achieving a balance between high-precision setting of the coupling weight coefficient when the product is shipped (initial setting) and high-efficiency updating (learning) of the coupling weight coefficient after the product is shipped.

[0187] It should be noted that in Fig.13 In the embodiment, each step is executed by the control circuit 270, but some or all of the steps may also be executed by a control circuit such as another processor placed outside the artificial intelligence processing device 200.

[0188] As described above, the artificial intelligence processing device 200 of the present disclosure includes: a substrate 60, etc.; a processing circuit such as a product-sum processing circuit 215 mounted on the substrate 60, etc., including a first variable resistance nonvolatile memory element 10 and a second variable resistance nonvolatile memory element 20 having the same structure and each maintaining conductance; and a writing circuit 260 for rewriting the conductance of the first variable resistance nonvolatile memory element 10 by applying a first voltage pulse having a first voltage to the first variable resistance nonvolatile memory element 10, and rewriting the conductance of the second variable resistance nonvolatile memory element 20 by applying a second voltage pulse having a second voltage different from the first voltage to the second variable resistance nonvolatile memory element 20. As an example, the second voltage in the high resistance process is 0.71 times or less of the first voltage in the high resistance process.

[0189] Thus, by writing voltage pulses based on different voltages (i.e., different driving conditions) to two variable resistance nonvolatile memory elements having the same structure, the conductance of the first variable resistance nonvolatile memory element 10 can be changed discontinuously when the first voltage pulse is repeatedly applied, and the conductance of the second variable resistance nonvolatile memory element 20 can be changed continuously when the second voltage pulse is repeatedly applied.

[0190] Therefore, the first variable resistance nonvolatile memory element 10 having the following characteristics can be used to set the coupling weight coefficient (initial setting): the conductance changes significantly due to the first voltage pulse in the application of continuous voltage pulses, and the change amount is small in the subsequent voltage pulses. On the other hand, the second variable resistance nonvolatile memory element 20 having the following characteristics can be used to update (learn) the coupling weight coefficient: the conductance changes gradually due to the continuous voltage pulses. As a result, an artificial intelligence processing device using a variable resistance nonvolatile memory element that can take into account both the setting (initial setting) of the coupling weight coefficient with high accuracy at the time of product shipment and the updating (learning) of the coupling weight coefficient with high efficiency after the product shipment is realized.

[0191] In addition, based on the difference in the change forms of the conductance of the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20, the first resistance variable nonvolatile memory element 10 has better storage tolerance than the second resistance variable nonvolatile memory element 20, and the second resistance variable nonvolatile memory element 20 has better rewrite characteristics than the first resistance variable nonvolatile memory element 10.

[0192] Here, the operation circuit is a product-sum operation circuit 215 that performs a product-sum operation using a composite value of the conductance of the first variable resistance nonvolatile memory element 10 and the conductance of the second variable resistance nonvolatile memory element 20 as a weight coefficient. More specifically, the operation circuit performs a product-sum operation using the sum of the current flowing through the first variable resistance nonvolatile memory element 10 and the current flowing through the second variable resistance nonvolatile memory element 20 as a product.

[0193] Thus, a coupling weight coefficient is formed by the conductance of the first variable resistance nonvolatile memory element 10 and the conductance of the second variable resistance nonvolatile memory element 20, which enables the storage unit including the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 to correspond to a neuron.

[0194] In addition, the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 may be arranged in the same layer sandwiched by two wiring layers. Thus, the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 are arranged in parallel in structure, so that the manufacturing process is simplified compared with the case where they are arranged in different layers.

[0195] In addition, the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 may be respectively arranged on a first layer sandwiched by two wiring layers and a second layer sandwiched by two wiring layers that is different from the first layer. Thus, in a plan view of the substrate, the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 can be arranged in an overlapping manner, so that the chip size of the artificial intelligence processing device 200 is reduced compared to the case where they are arranged on the same layer.

[0196] In addition, each of the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 may include first electrodes 2 and 12, second electrodes 4 and 14, and variable resistance layers 3 and 13 sandwiched between the first electrodes 2 and 12 and the second electrodes 4 and 14. In this case, the first electrodes 2 and 12 of the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 may be noble metal electrodes. Specifically, the first electrodes 2 and 12 of the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 may include either Ir or Pt.

[0197] Thus, by writing voltage pulses based on different voltages (i.e., different driving conditions) to two resistance variable nonvolatile memory elements having the same structure, it is possible to achieve a situation in which the conductance of the first resistance variable nonvolatile memory element 10 changes discontinuously when the first voltage pulse is repeatedly applied, and a situation in which the conductance of the second resistance variable nonvolatile memory element 20 changes continuously when the second voltage pulse is repeatedly applied.

[0198] In addition, the weight coefficient writing method of the artificial intelligence processing device 200 of the present disclosure is a weight coefficient writing method of the artificial intelligence processing device 200, the artificial intelligence processing device 200 has a first variable resistance nonvolatile memory element 10 and a second variable resistance nonvolatile memory element 20 having the same structure and maintaining the weight coefficient in the product-sum operation as conductance, and the writing method includes: a first rewriting step (S31-S32) of rewriting the conductance of the first variable resistance nonvolatile memory element 10 by applying a first voltage pulse having a first voltage to the first variable resistance nonvolatile memory element 10; and a second rewriting step (S38-S39) of rewriting the conductance of the second variable resistance nonvolatile memory element 20 by applying a second voltage pulse having a second voltage different from the first voltage to the second variable resistance nonvolatile memory element 20 at least in a high resistance process. As an example, the second voltage in the high resistance process is 0.71 times or less of the first voltage in the high resistance process.

[0199] Thus, by writing voltage pulses based on different voltages (i.e., different driving conditions) to two variable resistance nonvolatile memory elements having the same structure, the conductance of the first variable resistance nonvolatile memory element 10 can be changed discontinuously when the first voltage pulse is repeatedly applied, and the conductance of the second variable resistance nonvolatile memory element 20 can be changed continuously when the second voltage pulse is repeatedly applied.

[0200] Therefore, the first variable resistance nonvolatile memory element 10 having the following characteristics can be used to set the coupling weight coefficient (initial setting): the conductance changes significantly due to the first voltage pulse in the application of continuous voltage pulses, and the change amount is small in the subsequent voltage pulses. On the other hand, the second variable resistance nonvolatile memory element 20 having the following characteristics can be used to update (learn) the coupling weight coefficient: the conductance gradually changes due to the continuous voltage pulses. As a result, the first rewriting step can be performed when the weight coefficient is initially set for the artificial intelligence processing device 200, and the second rewriting step can be performed when the weight coefficient is updated by making the artificial intelligence processing device 200 learn.

[0201] In addition, the first variable resistance nonvolatile memory element 10 constitutes a first artificial intelligence region for directly using the weight coefficients of an existing artificial intelligence process in transfer learning or reinforcement learning, and the second variable resistance nonvolatile memory element 20 constitutes a second artificial intelligence region for updating the weight coefficients by performing new learning in transfer learning or reinforcement learning. Thus, the first rewrite step can be performed when writing the weight coefficients to the first artificial intelligence region, and the second rewrite step can be performed when updating the weight coefficients to the second artificial intelligence region.

[0202] The above is an explanation of the artificial intelligence processing device and the weight coefficient writing method involved in the present disclosure based on the implementation mode, but the present disclosure is not limited to the implementation mode. As long as it does not deviate from the main purpose of the present disclosure, the implementation mode obtained by various deformations thought of by those skilled in the art and other methods constructed by combining some of the constituent elements in the implementation mode are also included in the scope of the present disclosure.

[0203] For example, in the above embodiment, the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 have a variable resistance layer composed of tantalum oxide, but the variable resistance layer is not limited to such a material and may be composed of a transition metal such as hafnium or an oxide of aluminum.

[0204] In addition, in the above embodiment, the resistance variable layer of the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20 is composed of a stacked structure of a first tantalum oxide layer and a second tantalum oxide layer, but is not limited to such a stacked structure, and can also be composed of a single layer such as a tantalum oxide layer.

[0205] In addition, in the above embodiment, a neuron is composed of a first variable resistance nonvolatile memory element 10 and a second variable resistance nonvolatile memory element 20, but as long as there are at least one first variable resistance nonvolatile memory element 10 and at least one second variable resistance nonvolatile memory element 20, there may be more than two first variable resistance nonvolatile memory elements 10 or more than two second variable resistance nonvolatile memory elements 20.

[0206] In addition, in the above-mentioned embodiment, the artificial intelligence processing device 200 is a Fig.9A The neural network has the structure shown, but is not limited to this structure, and may also be a neural network consisting of a desired number of layers, each layer consisting of a desired number of neurons.

[0207] In the above-described embodiment, the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 are used as weight coefficients in the product-sum operation circuit 215, but their use is not limited to the product-sum operation circuit. For example, the first variable resistance nonvolatile memory element 10 and the second variable resistance nonvolatile memory element 20 may be used in an operation circuit that holds a variable value corresponding to conductance and performs various operations such as four arithmetic operations using the variable value.

[0208] In addition, in the embodiment, Fig. 12A and Fig. 12B As shown, writing under different driving conditions is performed only when the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20 are reset ("high resistance"), but writing under different driving conditions can also be performed when the first resistance variable nonvolatile memory element 10 and the second resistance variable nonvolatile memory element 20 are set ("low resistance").

[0209] [Industrial Applicability]

[0210] An artificial intelligence processing device using the resistance variable non-volatile memory element disclosed in the present invention is capable of taking into account both high-efficiency, high-precision setting of coupling weight coefficients (initial setting) when the product is shipped, and high-efficiency updating (learning) of coupling weight coefficients after the product is shipped, and is particularly useful as an edge AI processing device for IoT.

[0211] Explanation of symbols

[0212] 1, 11, 60, 70, 80, 90 substrate

[0213] 12 first electrode;

[0214] 13 Resistance variable layer

[0215] 3a, 13a 1st tantalum oxide layer

[0216] 3b, 13b Second tantalum oxide layer

[0217] 14. Second electrode

[0218] 10First resistance variable nonvolatile memory element

[0219] 20Second resistance variable nonvolatile memory element

[0220] 61a, 61b, 71a, 71b, 81a, 81b, 91a, 91b, 101a, 101b diffusion region 62, 72, 82, 92, 102 oxide film

[0221] 63, 73, 83, 93, 103 gate electrodes (word lines)

[0222] 64a, 64b, 66, 68a, 68b, 74a, 74b, 76a, 76b, 76c, 78a, 78b, 84a, 84b, 86a, 86c, 88a, 88b, 88c, 88d, 94a, 94b, 96, 98a, 98b, 104a, 104b, 106, 108a, 108b through hole

[0223] 65a, 65b, 75a, 75b, 75c, 85a, 85b, 95a, 95b, 105: 1st wiring layer

[0224] 67, 77, 87a, 87b, 97, 107 2nd wiring layer

[0225] 69, 79, 89a, 89b, 99 3rd wiring layer

[0226] 200 Artificial Intelligence Processing Device

[0227] 201 Input layer

[0228] 202 hidden layers

[0229] 203 output layer

[0230] 210, 210a neurons

[0231] 211 Synapse

[0232] 215, 215a Product-sum operation circuit

[0233] 220 memory cell array

[0234] 230, 230a word line selection circuit

[0235] 240 grid columns

[0236] 250, 250a determination circuit

[0237] 260 Write Circuit

[0238] 270 control circuit

[0239] MC, MC1, MC2, MCij storage units

[0240] T0, T1, T2 unit transistors

[0241] WL, WL1, WL2 word lines

[0242] BL, BL1, BL2, BLi1, BLi2 bit lines

[0243] SL, SLi source line

Claims

1. An artificial intelligence processing device, comprising: a substrate; an arithmetic circuit mounted on the one substrate, comprising a first variable resistance nonvolatile memory element and a second variable resistance nonvolatile memory element each maintaining electrical conductance and having the same structure; and A write circuit rewrites the conductance of the first resistance variable nonvolatile memory element by applying a first voltage pulse having a first voltage to the first resistance variable nonvolatile memory element, and rewrites the conductance of the second resistance variable nonvolatile memory element by applying a second voltage pulse having a second voltage different from the first voltage to the second resistance variable nonvolatile memory element.

2. The artificial intelligence processing device according to claim 1, The operation circuit is a product-sum operation circuit that performs a product-sum operation using a combined value of the conductance of the first variable resistance nonvolatile memory element and the conductance of the second variable resistance nonvolatile memory element as one weight coefficient.

3. The artificial intelligence processing device according to claim 2, The arithmetic circuit performs the product-sum operation by taking a total of a current flowing through the first variable resistance nonvolatile memory element and a current flowing through the second variable resistance nonvolatile memory element as one product.

4. The artificial intelligence processing device according to any one of claims 1 to 3, The conductance of the first variable resistance nonvolatile memory element changes discontinuously when the first voltage pulse is repeatedly applied. The conductance of the second variable resistance nonvolatile memory element changes continuously when the second voltage pulse is repeatedly applied.

5. The artificial intelligence processing device according to any one of claims 1 to 4, The first variable resistance nonvolatile memory element has better storage tolerance than the second variable resistance nonvolatile memory element. The second variable resistance nonvolatile memory element has a better rewrite characteristic than the first variable resistance nonvolatile memory element.

6. The artificial intelligence processing device according to any one of claims 1 to 5, The second voltage during the process of increasing the resistance is 0.71 times or less of the first voltage during the process of increasing the resistance.

7. The artificial intelligence processing device according to any one of claims 1 to 6, The first variable resistance nonvolatile memory element and the second variable resistance nonvolatile memory element are arranged in the same layer sandwiched between two wiring layers.

8. The artificial intelligence processing device according to any one of claims 1 to 6, The first variable resistance nonvolatile memory element and the second variable resistance nonvolatile memory element are respectively arranged on a first layer sandwiched between two wiring layers and a second layer different from the first layer sandwiched between two wiring layers.

9. The artificial intelligence processing device according to any one of claims 1 to 6, Each of the first variable resistance nonvolatile memory element and the second variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer interposed between the first electrode and the second electrode.

10. The artificial intelligence processing device according to claim 9, The first electrodes of the first variable resistance nonvolatile memory element and the second variable resistance nonvolatile memory element are noble metal electrodes.

11. The artificial intelligence processing device according to claim 10, The first electrodes of the first variable resistance nonvolatile memory element and the second variable resistance nonvolatile memory element include one of Ir and Pt.

12. A method for writing weight coefficients, It is a method for writing weight coefficients in artificial intelligence processing devices. The artificial intelligence processing device includes a first variable resistance nonvolatile memory element and a second variable resistance nonvolatile memory element having the same structure and maintaining a weight coefficient in a product-sum operation as conductance. The writing method comprises: a first rewriting step of rewriting the conductance of the first variable resistance nonvolatile memory element by applying a first voltage pulse having a first voltage to the first variable resistance nonvolatile memory element; as well as, The second rewriting step rewrites the conductance of the second variable resistance nonvolatile memory element by applying a second voltage pulse having a second voltage different from the first voltage at least in a high resistance process to the second variable resistance nonvolatile memory element.

13. The weight coefficient writing method according to claim 12, The first rewriting step is performed when the weight coefficient is initially set for the artificial intelligence processing device. The second rewriting step is performed when the weight coefficient is updated by causing the artificial intelligence processing device to learn.

14. The weight coefficient writing method according to claim 12, The first variable resistance nonvolatile memory element constitutes a first artificial intelligence region for directly using the weight coefficient of the existing artificial intelligence processing in transfer learning or reinforcement learning. The second variable resistance nonvolatile memory element constitutes a second artificial intelligence region for performing new learning and updating weight coefficients in transfer learning or reinforcement learning. The first rewriting step is performed when writing the weight coefficient to the first artificial intelligence area. The second rewriting step is performed when the weight coefficient is updated for the second artificial intelligence area.

15. The weight coefficient writing method according to any one of claims 12 to 14, The second voltage during the process of increasing the resistance is equal to or less than 0.71 times the first voltage during the process of increasing the resistance.

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