Laminated chip mixed signal boundary scanning test structure

Abstract

The invention relates to the field of boundary scanning test of laminated chips, in particular to a laminated chip boundary scanning test structure combining IEEE 1838 and IEEE 1149.4 standards, and mainly relates to fault and defect detection of TSV (Through Silicon Via) of a laminated chip connecting part. Chip package registers (DWR) are embedded into the two ends of a through silicon via (TSV) connected with the laminated chip in the laminated chip, a simulation test bus and a corresponding interface circuit are added into the chip to form a scanning chain, and the mixed signal boundary scanning test structure of the laminated chip is formed. When the chip works normally, the test structure does not influence the logic function of the chip; in the testing process, the testing upper computer sends different control instructions, and full-coverage online fault and defect detection of the connectivity of the laminated chips is achieved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and in particular to a stacked chip testing structure combining IEEE 1838 standard and IEEE 1149.4 standard. Background Art

[0002] In recent years, stacked chip packaging has gradually become the mainstream of technological development. Stacked chip packaging technology, referred to as 3D packaging, refers to the packaging technology of stacking two or more chips in the same package in the vertical direction without changing the size of the package. It originated from the stacking packaging of flash memory (NOR / NAND) and SDRAM. There are many types of 3D packaging based on stacking methods, mainly including: on-chip 3D integration based on the functional layer in the chip and built-in connection layer by layer, 3D stacked packaging formed by chip-to-chip (die-to-die) stacking, or 3D stacked packaging formed by package-to-package stacking, and 3D ICs that realize die-to-die interconnection through through-silicon vias (TSV). Among all 3-D packaging technologies, TSV can achieve the shortest and richest z-direction interconnection.

[0003] In the production and use of 3D stacked chips, the chip testability index cannot be ignored, which directly affects the production efficiency and production cost of the chip. Traditional testability design (DFT, Design For Test), such as boundary scan test, built-in self-test and other methods, mostly focus on planar 2D packaged chips, and can only provide single die test methods, which is difficult to meet the testing requirements of stacked chips for multiple cores, especially for the fault and defect detection problems of inter-chip connectivity. There is a lack of effective and convenient methods.

[0004] IEEE 1149.4, the full name of which is Standard for a Mixed-Signal Test Bus, was developed after IEEE 1149.1 (JTAG) and is specifically designed to support circuit testing of mixed signals (including analog and digital signals). This standard expands the original JTAG boundary scan standard and introduces new pins and structures, making it applicable not only to digital signals but also to test and diagnose analog signal channels.

[0005] The mixed signal boundary scan structure in the IEEE 1149.4 standard IC consists of a boundary scan test interface (TAP, ATAP), a boundary scan test control unit, a test bus interface circuit (TBIC) and a boundary scan test unit (including DBM and ABM). The boundary scan interface provides a channel for the device to interact with the test system when it is in the test state. It mainly consists of 6 mandatory pins (TCK, TMS, TDI, TDO, AT1, AT2) and 3 optional pins (TRST, ATN1, ATN2). Among them, TCK, TMS, TDI, TDO and TRST are 5 pins compatible with the JTAG standard; AT1 and AT2 and the optional ATN1 and ATN2 pins constitute the analog test interface, which provides a channel for applying and obtaining analog stimuli. The analog test signal is input into the chip through the AT1 port and applied to the specified device pins via the internal test bus (AB1) under the control of the TBIC. The analog test response on the analog pin is output from the AT2 pin through the internal test bus (AB2) under the control of the TBIC and is received and processed by the analog test response processing device.

[0006] The boundary scan test control unit of the IEEE 1149.4 standard is mainly composed of a TAP controller, an instruction register, an instruction decoder, etc. Its functions are fully compatible with the IEEE 1149.1 standard. The TBIC consists of two parts: a logic control part and a switch matrix. The TBIC logic control part mainly consists of three parts: a control register, an update register, and a control logic. Through a 4-bit test code and a 2-bit mode selection signal, the control of 10 conceptual switches is realized.

[0007] The switch matrix of TBIC includes 10 conceptual switches, among which S1~S4 are used to realize the interconnection test function; S5~S8 realize parameter test and function test by controlling the connection between ATAP and internal bus; S9~S10 controls whether the internal neutral lines AB1 and AB2 are connected to V clamp Connect the internal bus to V clamp The connection is used to ensure that a continuous value is maintained when the internal bus is not in use, avoiding interference caused by the internal bus being suspended during testing.

[0008] The boundary scan unit of the IEEE 1149.4 standard consists of ABM and DBM, which are connected in series with TBIC to form the boundary scan register chain of the mixed signal device. The DBM in the IEEE 1149.4 standard is compatible with the DBM in the IEEE 1149.1 standard; the ABM is a mixed analog circuit unit, which consists of two parts: control logic and switch matrix. The control logic is a control register composed of digital logic, which is used to control the mixed signal flow of analog function pins and the action of the switch matrix, and controls 6 conceptual switches through 4-bit update register signals and 2-bit mode selection signals.

[0009] The switch matrix of ABM is a series of conceptual switches connected to the analog function pins, mainly including 6 conceptual switches, among which the SD switch controls the connection or isolation of the analog function pins with the core. During the test, the function pins are separated from the core to ensure that the analog core does not interfere with the test signal; the SH, SL and SG switches respectively control the analog function pin value to be high V H , set V low L or with reference level V G For simple interconnection testing, V H and V L The logic level is used to represent the logic 0 and logic 1 on the logic pin. At this time, the interconnection test of the analog pin is carried out just like the interconnection test of the digital pin. The SB1 and SB2 switches respectively control the analog function pins to be connected to the internal buses AB1 and AB2. SB1 and SB2 make the analog bus used as a "virtual probe", so that AT1 and AT2 can be directly connected to any analog function pin without a physical probe.

[0010] PTAP, TBIC, ABM and internal analog test data bus constitute the mixed signal boundary scan structure, providing the hardware foundation for mixed signal boundary scan test and stacked chip connectivity test.

[0011] The IEEE 1838 standard provides a unified architecture and method for 3D stacked chip testing: each chip contains a test access port PTAP (Primary Test Access Port) connected to the closest circuit board or package interface, where the interface includes five test interfaces TCK, TMS, TDI, TDO and TRSTN and is driven by control logic compatible with the JTAG standard; the IEEE 1838 standard adds an auxiliary test access port STAP (Secondary Test Access Port) and related control logic to enable the test signal to be effectively transmitted to the target chip required for testing through the PTAP-STAP channel; the IEEE 1838 standard also includes a flexible parallel port FPP (Flexible Parallel Port), which provides a more efficient data transmission method for stacked chip testing and improves test efficiency. The IEEE 1838 standard is applicable to both pre-binding testing of chip production and multi-situation testing such as during and after binding. Summary of the invention

[0012] The present invention provides a mixed signal boundary scan test structure for stacked chips, which is used to solve the online test problem of the connectivity between layers of stacked chips, and realizes full coverage defect and fault detection of TSV between layers of stacked chips through digital / analog mixed signal detection.

[0013] In order to solve the above technical problems, the present invention provides a boundary scan test structure, the structure comprising:

[0014] On the basis of the primary interface specified by the IEEE 1838 standard for each chiplet, the TBIC, analog test interfaces AT1, AT2 and internal analog test bus ABx specified by the IEEE 1149.4 standard are introduced to form PTAP, where the internal analog test bus ABx is connected to the analog test interface through TBIC. In the secondary interface of the chiplet, the corresponding interface corresponding to the analog test function pin is introduced to form STAP and control logic STAP Controller.

[0015] A mixed signal boundary scan unit DWR is added between the TSV in the primary interface and secondary interface of each chip and the connection between the internal logic pins of the chip. The DWR and TBIC are connected to the PTAP and STAP through digital signal lines and analog test internal buses AB1 and AB2 to form a boundary scan chain. At the same time, PTAP and STAP in the same chip are also directly connected by TDI, TDO, AB1 and AB2. By selecting different test modes and test positions, a certain middle-layer chip can be bypassed, and the test data can be directly received from PTAP and sent to the back-layer chip at STAP, reducing the transmission time of test data in the boundary scan link.

[0016] Design an ABM module, which consists of two parts: a switch matrix and a control logic. The switch matrix contains 6 analog switches. Different switches are turned on to realize different test functions. For example, when switches SB1 and SB2 are closed, the corresponding analog function pins will be connected to the internal analog test bus for analog testing; switches SH, SL, and SG connect various levels of different sizes to realize the conversion of analog signals to digital signals. The control logic contains four control signals D, C, B1, and B2 and two mode selection signals M1 and M2 to jointly control the 6 analog switches to realize different test functions. The mode selection signal is obtained by decoding different test instructions input into the instruction register; the 4-bit control signal is essentially the digital test data input during the test, which is input into the control logic through the control register.

[0017] The TBIC module is designed, which consists of two parts: the switch matrix and the control logic. By controlling the switch matrix, the internal test bus is connected to the corresponding external analog pins to form a complete test channel. The switch matrix includes 10 analog switches in total. Some analog switches are mainly used for interconnection testing; the other part ensures that the analog test interface is connected to the internal test bus to achieve effective transmission of analog signals in the test channel. The control logic contains four control signals Ca, Co, D1, and D2 and two mode selection signals M1 and M2 to jointly control the analog switches to achieve different test functions. The control signal and mode selection signal acquisition are the same as the control signal of the ABM module.

[0018] By combining ABM to design a mixed-signal boundary scan test unit DWR, different test modes can be selected through the controller, and test paths that meet different test requirements can be constructed to achieve efficient testing.

[0019] A TAP controller is designed. Under the action of clock signal TCK and mode selection signal TMS, the TAP controller generates six control signals, namely Update-DR, Pause-DR, Shift-DR, Update-IR, Pause-IR and Shift-IR. Among them, Update-DR, Pause-DR and Shift-DR act on the control registers in ABM and TBIC; Update-IR, Pause-IR and Shift-IR act on the instruction registers in the scan link. The controllability design of the test process is realized through a finite state machine.

[0020] During the TSV analog signal test, the conduction of the ABM internal analog switch between two adjacent layers of chips is controlled by the TAP controller to separate all the TSVs inside the chip from the chip core one by one and connect them between the internal analog test buses AB1 and AB2. At this time, the analog stimulus can be input from the external test interface AT1 and output and analyzed from the external test interface AT2 through the transmission path of AT1-TBIC-AB1-a DWR in a certain layer-TSV-the corresponding DWR in the adjacent layer-AB2-TBIC-AT2, so as to achieve more complete defect and fault detection of TSV.

[0021] The test methods involved in the test structure of the present invention mainly include integrity test, interconnection test, extended interconnection test, and kernel function test. The specific test methods are as follows:

[0022] The integrity test is to ensure that the test structure itself functions properly before the boundary scan test. The test objects include the instruction register, the control register in the DWR and TBIC, the corresponding switch matrix, and the TSV as the test data channel. Only when the integrity test passes can other subsequent tests be carried out.

[0023] The test object of the interconnection test is the specific connection status between the interconnected circuits. The common faults mainly involved include fixed faults, short circuit faults, open circuit faults, etc. At the same time, the fault point and fault condition can be accurately located after the test.

[0024] The extended interconnect test mainly focuses on the analog measurement of TSV electrical parameters. By analyzing the measurement results, it is determined whether there are defects or faults in the TSV connecting the chips.

[0025] Core functional testing refers to testing the core logic of the chip. By controlling the stimulus input and analyzing the test response, it is determined whether the chip core has a fault. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The finite state machine state transition diagram of the PTAP controller is

[0027] Figure 2 Schematic diagram of the STAP controller structure

[0028] Figure 3 3DCR structure diagram

[0029] Figure 4 TBIC structure diagram

[0030] Figure 5 ABM structure diagram

[0031] Figure 6 DWR structure diagram

[0032] Figure 7 Configuration register structure diagram for DWR

[0033] Figure 8 Multi-layer test structure diagram DETAILED DESCRIPTION

[0034] The present invention is further described below in conjunction with the accompanying drawings.

[0035] exist Figure 8 In the structure shown, an internal analog test bus and TBIC are added on the basis of the IEEE 1838 standard test structure, and a DWR structure is modified on all external pins of the chip logic circuit.

[0036] The PTAP control logic is as follows: Figure 1The controller controls the flow path of TDI and TDO in the test structure by changing the TMS signal, thus controlling the entire test process. When the controller selects the instruction register IR, IR is connected to the test channel between TDI and TDO. At this time, the input to TDI is the test instruction. IR decodes the test instruction, generates a control signal, and performs a series of control actions on the test structure. When the controller selects the data register DR, according to the instruction decoded by IR, the test structure connects the specified data register between TDI and TDO and performs the corresponding operation.

[0037] STAP controller Figure 2 As shown in the figure, AT1, AT2, TCK and TRSTN will be directly transmitted to the next level through STAP; only when a certain STAP is selected, the TMS, TDI and TDO signals for the next core grain will be used, so there are some combinational circuits in the STAP control logic to realize signal selection. The enable signal Enable in the STAP control logic comes from the result of the instruction register output according to the test data to achieve the bypass effect; the selection signal Select_Sn and the parking state signal RTL_or_TLR_Sn both come from Figure 3 The configuration register 3DCR designed according to the IEEE 1838 standard is shown. When Select_Sn is 0, it means that the STAP is not selected, and the TMS signal of the back-end PTAP is the value of RTL_or_TLR_Sn, thereby controlling the next-level chip to be in a reset or test parking state.

[0038] The structure of TBIC is as follows Figure 4 As shown in the figure, different on-off relationships of the ten internal analog switches can realize different circuit functions. For example, when the TAP controller is in a non-test or waiting state, only S9 and S 10 This not only disconnects the external test interface from the internal test bus, but also Clamp Prevent the internal test bus from generating noise that affects the normal operation of the core logic. The control logic of TBIC includes 2-bit mode selection signals M1 and M2 from the decoded output of the instruction register, control register and update register structure. The control register includes 4-bit control signals Ca, Co, D1 and D2. When the TAP controller is in the Capture-DR state, D1 and D2 respectively collect the digital results of the AT1 and AT2 pin voltages on the rising edge of TCK. When the TAP controller is in the Update-DR state, the 4-bit update register collects the corresponding control register state on the falling edge of TCK to meet the shift operation needs of the boundary scan chain.

[0039] ABM structure Figure 5As shown in the figure, the analog boundary scan cell is a mixed signal cell, which includes a switch matrix and corresponding control logic that connects the TSV micro-pad to the core structure of the chip. The core disconnect switch consists of a pair of analog switches that are not turned on or off at the same time, one of which connects the chip core and TSV, and the other connects the core to ground after the TSV is disconnected from the core. The three switches SH, SL, and SG are not turned on at the same time. The ABM control logic is similar to TBIC, consisting of a total of 6 control signals, namely, M1 and M2 signals from the instruction register decode and D, C, B1, and B2 from the boundary scan chain output.

[0040] The schematic diagram of DWR structure is shown in Figure 6. Its essence is a chain composed of a series of register units. Each register unit includes functional input and output ports CFI and CFO connected to the external interface and core pins, test input and output ports CTI and CTO connected in a daisy chain form, and a series of control signals including clock signals. The present invention designs a DWR unit with optional test mode to meet various test requirements. Figure 6 Model_TEST is the test selection signal. When not in test mode, CFI is directly connected to CFO, which does not affect the normal logic function of the chip. Mode_Select is the mode selection signal obtained by decoding the instruction register, which consists of M0, M1 and M2. When not in test mode, SD is closed, other switches are disconnected, and the signal from TSV input CFI goes directly to CFO through the multiplexer, which does not affect the normal operation of the chip. When in digital signal test mode, SD is closed, other switches are disconnected, and the CTI to CTO path is connected to a DBC. The signal from TSV input CFI passes through the DBC and is output by CFO through the multiplexer after the rising edge of the Update signal arrives. When performing analog interconnection testing, SD is disconnected, and the CTI to CTO path is connected to 5 DBCs, of which the first 4 bits are D, C, B1, B2 control signals, and the last bit is the digitization of the signal sampled by TSV, as the CFO output.

[0041] Figure 7 Figure 1 is a schematic diagram of the DWR configuration register. Since the connectivity test of TSV involves two adjacent chips, the boundary scan chain is divided into two parts, DWR_TOP at the top and DWR_TOP at the bottom, which are selectively activated through the DWR configuration register output.

Claims

1. A stacked chip mixed signal boundary scan test structure, characterized in that: The structure includes the following parts: adding a stacked chip boundary scan test structure based on the IEEE 1838 standard and a mixed signal boundary scan unit, an analog test bus and an analog test interface structure based on the IEEE1149.4 standard inside the stacked chip to realize a mixed signal boundary scan test on the stacked chip.

2. In the structure described in claim 1, each layer of chip should have two structures: primary interface and secondary interface. For the bottom layer chip, the primary interface is the interface with the external I / O, and for other layer chips, the primary interface includes the interface with the previous layer structure; for non-top layer chips, the secondary interface includes the interface with the next layer structure.

3. In the structure described in claims 1 and 2, the primary interface of the bottom layer chip in the test structure includes the Primary Test Access Port (PTAP) and PTAP controller structure connected to the outside world and the analog test interface circuit TBIC, and the primary interface of the other layer chips includes the PTAP and PTAP controller structure and TBIC connected to the previous layer chip; the secondary interface of the chip except the top layer includes the Secondary Test Access Port (STAP) and STAP controller structure. The PTAP controller has the functions of parsing commands, controlling the internal registers of the chip and the on and off of the analog switch, and the STAP controller controls the backward transmission of the test data.

4. In the structures described in claims 1, 2, and 3, the external I / O interface of the test structure should include TDI, TMS, TCK, TRSTN, and TDO compatible with the IEEE 1149.1 standard, and two analog signal ports AT1 and AT2 specified in the IEEE 1149.4 standard. TDI and TDO are the input and output interfaces of digital boundary scan test data, respectively; TMS is the test mode selection input interface; TCK is the test clock input interface; TRSTN is the optional test reset signal input interface, and the five interfaces are connected to the PTAP structure of the underlying chip. According to the test requirements, the AT1 and AT2 ports use one end as the signal input port and the other end as the signal output port, and the two ports are connected to the TBIC of the underlying chip.

5. In the structures described in claims 1, 2, and 3, the interconnection between the front-end chip A and the back-end chip B should include five test data transmission channels, namely TDI, TMS, TCK, TRSTN, and TDO, in a TAP controller compatible with the IEEE1149.1 standard, and two analog test internal bus interfaces AB1 and AB2. The five data transmission channels, namely TDI, TMS, TCK, TRSTN, and TDO, are connected to the PTAP of the back-end chip via an external I / O interface or the STAP of the front-end chip; and AB1 and AB2 are connected to the TBIC structure of the back-end by the TBIC structure of the front-end.

6. In the structure described in claim 1, the test process is to select a test mode, locate the chip to be tested, form a corresponding scan chain, input test data, output a test response, and analyze the test results. In the structure described in claim 1 and the test process described in claim 6, the test method is that after the PTAP controller receives a digital signal test command such as an internal logic test, the boundary scan unit separates itself and the analog test bus from the chip digital signal test link through an analog switch. The test performed at this time is the same as the test process specified in the IEEE 1149.1 standard; when the PTAP controller receives an analog signal test instruction, the PTAP controller of the chip to be tested controls the boundary scan unit to separate the circuit to be tested from the chip core and connect it to the analog test bus, and inputs stimulus and outputs response through the analog test port.

Images