A high order bandgap reference source circuit with base compensation

Abstract

The application claims a high-order bandgap reference source circuit with base compensation, comprising a biasing circuit with start-up, a base-compensated bandgap reference core circuit and a high-order temperature compensation circuit. The application adopts NPN transistor base series resistance technology to suppress the influence of NPN transistor base current on the output voltage of the bandgap reference source circuit, adopts two high-order temperature compensation currents realized by two NMOS tubes working in the sub-threshold region and the difference between the gate-source voltages and the negative temperature coefficient current generated by the NPN transistor base-emitter voltage on the resistor to compensate the high-order nonlinearity of the temperature of the output voltage of the bandgap reference source circuit, and then obtain a high-order temperature-compensated bandgap reference voltage, so as to realize a high-order bandgap reference source circuit with base compensation.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a high-order bandgap reference source circuit with base compensation. Background Art

[0002] With the development of integrated circuit technology, the number of integrated circuit chip systems integrating more and more functional modules has increased, and these functional modules require high-performance reference circuits. Bandgap reference circuits provide output voltages with low temperature drift characteristics and are widely used to provide high-performance bias for integrated circuit chip systems.

[0003] Figure 1 This is a traditional bandgap reference source circuit, in which the PMOS tube M1 and the PMOS tube M2 are exactly the same, the resistors R1, R2 and R3 are made of the same material, and the emitter area of ​​the PNP transistor Q1 is m times that of the PNP transistor Q2. Then the voltage V REF for Where V EB2 is the emitter-base voltage of the PNP transistor Q2, R1 is the resistance value of the resistor R1, R3 is the resistance value of the resistor R3, k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge. By optimizing the resistance values ​​of the resistors R1 and R3, a reference voltage V with zero temperature characteristics can be obtained within a certain temperature range. REF In any case, the reference voltage V REF It is a first-order bandgap reference voltage with a high temperature drift characteristic, which restricts the application of bandgap reference source circuits in high-performance integrated circuit chip systems. Summary of the Invention

[0004] The present invention aims to solve the above problems of the prior art and proposes a high-order bandgap reference source circuit with base compensation. The technical solution of the present invention is as follows:

[0005] A high-order bandgap reference source circuit with base compensation comprises: a bias circuit with startup, a bandgap reference core circuit with base compensation, and a high-order temperature compensation circuit, wherein the signal output end of the bias circuit with startup is respectively connected to the signal input end of the bandgap reference core circuit with base compensation and the signal input end of the high-order temperature compensation circuit; the signal output end of the bandgap reference core circuit with base compensation is respectively connected to the signal input end of the bias circuit with startup and the signal input end of the high-order temperature compensation circuit; and the signal output end of the high-order temperature compensation circuit is connected to the signal input end of the bandgap reference core circuit with base compensation.

[0006] Furthermore, the bias circuit with startup includes: a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, a PMOS tube M5, a PMOS tube M6, an NMOS tube M7, an MMOS tube M8, a PMOS tube M9, a PMOS tube M10, a PMOS tube M11, a PMOS tube M12, an NMOS tube M13, an NMOS tube M14, an NPN transistor Q1, an NPN transistor Q2, a resistor R1, and a resistor R2, wherein the source of the PMOS tube M1 is respectively connected to the source of the PMOS tube M5, the source of the PMOS tube M6, the source of the PMOS tube M9, the source of the PMOS tube M10, and the external power supply VDD. The gate of the PMOS transistor M1 is connected to the drain of the PMOS transistor M1 and the source of the PMOS transistor M2 respectively. The gate of the PMOS transistor M2 is connected to the drain of the PMOS transistor M2, the drain of the NMOS transistor M4 and the gate of the NMOS transistor M3 respectively. The source of the NMOS transistor M4 is connected to the source of the NMOS transistor M3, the source of the NMOS transistor M7, the source of the NMOS transistor M8, the source of the NMOS transistor M13, the source of the NMOS transistor M14 and the external ground GND respectively. The drain of the PMOS transistor M5 is connected to the collector of the NPN transistor Q1, the base of the NPN transistor Q1 and the base of the NPN transistor Q2 respectively. The drain of the PMOS transistor M6 is connected to the collector of the NPN transistor Q1, the base of the NPN transistor Q1 and the base of the NPN transistor Q2 respectively. The MOSFETs 1 and 2 are connected to the gate of the PMOS transistor M5, the gate of the PMOS transistor M6, the drain of the NMOS transistor M3, and the collector of the NPN transistor Q2. The emitter of the NPN transistor Q2 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the emitter of the NPN transistor Q1, the gate of the NMOS transistor M62, the gate of the NMOS transistor M63, the drain of the NMOS transistor M7, the gate of the NMOS transistor M7, and the gate of the NMOS transistor M8. The drain of the PMOS transistor M9 is connected to the source of the PMOS transistor M11. The drain of the PMOS transistor M11 is connected to the gate of the PMOS transistor M9, the gate of the PMOS transistor M10, the gate of the PMOS transistor M30, and the gate of the PMOS transistor M8. The gate of the MOS transistor M36, the gate of the PMOS transistor M44, the gate of the PMOS transistor M45, the gate of the PMOS transistor M49, the gate of the PMOS transistor M55, the gate of the PMOS transistor M60, the gate of the PMOS transistor M61, and one end of the resistor R2 are connected. The other end of the resistor R2 is respectively connected to the gate of the PMOS transistor M11, the gate of the PMOS transistor M12, and the drain of the NMOS transistor M8. The drain of the PMOS transistor M10 is connected to the source of the PMOS transistor M12. The drain of the PMOS transistor M12 is respectively connected to the gate of the NMOS transistor M13, the drain of the NMOS transistor M13, the gate of the NMOS transistor M14, and the drain of the NMOS transistor M24.

[0007] Furthermore, the base-compensated bandgap reference core circuit includes: PMOS tube M15, PMOS tube M16, PMOS tube M17, PMOS tube M18, PMOS tube M19, PMOS tube M20, NMOS tube M21, NMOS tube M22, NMOS tube M23, NMOS tube M24, PMOS tube M25, PMOS tube M26, PMOS tube M27, PMOS tube M28, NPN transistor Q3, NPN transistor Q4, NPN transistor Q5, resistor R3, resistor R4, resistor R5, resistor R6 and resistor R7, wherein the source of PMOS tube M15 is connected to the source of PMOS tube M16, the source of PMOS tube M17, and the source of PMOS tube M28 respectively. The source of the OS transistor M25, the source of the PMOS transistor M26 and the external power supply VDD are connected. The gate of the PMOS transistor M15 is respectively connected to the gate of the PMOS transistor M16, the gate of the PMOS transistor M17, the drain of the PMOS transistor M16 and the source of the PMOS transistor M19. The drain of the PMOS transistor M15 is respectively connected to the gate of the PMOS transistor M25, the gate of the PMOS transistor M26 and the source of the PMOS transistor M18. The gate of the PMOS transistor M18 is respectively connected to the drain of the PMOS transistor M18, the drain of the NMOS transistor M14 and the drain of the NMOS transistor M21. The source of the NMOS transistor M21 is connected to the collector of the NPN transistor Q3. The base of the NPN transistor Q3 is respectively connected to the drain of the PMOS transistor M25, the gate of the PMOS transistor M26 and the source of the PMOS transistor M18. The gate of the NMOS tube M21 and one end of the resistor R4 are connected. The other end of the resistor R4 is respectively connected to one end of the resistor R3 and the collector of the NPN transistor Q4. The emitter of the NPN transistor Q3 is respectively connected to the emitter of the NPN transistor Q4, the emitter of the NPN transistor Q5, the source of the NMOS tube M23, the source of the NMOS tube M24, one end of the resistor R6, one end of the resistor R7 and the external ground GND. The gate of the PMOS tube M19 is respectively connected to the gate of the PMOS tube M20, the drain of the PMOS tube M19 and the drain of the NMOS tube M22. The source of the NMOS tube M22 is connected to the collector of the NPN transistor Q5. The drain of the PMOS tube M17 is connected to the PMOS tube M20. The source of the OS transistor M20 is connected, the drain of the PMOS transistor M20 is respectively connected to the drain of the NMOS transistor M23, the gate of the NMOS transistor M23, and the gate of the NMOS transistor M24. The drain of the PMOS transistor M25 is connected to the source of the PMOS transistor M27. The drain of the PMOS transistor M27 is respectively connected to the gate of the NMOS transistor M4, the other end of the resistor R3, the base of the NPN transistor Q4, the gate of the NMOS transistor M22, the base of the NPN transistor Q5, and one end of the resistor R5. The other end of the resistor R5 is respectively connected to the gate of the PMOS transistor M27, the gate of the PMOS transistor M28, and the other end of the resistor R6. The drain of the PMOS transistor M26 is connected to the source of the PMOS transistor M28.The drain of the PMOS transistor M28 is respectively connected to the drain of the PMOS transistor M30, the drain of the NMOS transistor M31, the drain of the PMOS transistor M55, the drain of the NMOS transistor M56, the other end of the resistor R7 and the circuit output terminal VREF.

[0008] Furthermore, the high-order temperature compensation circuit includes: PMOS tube M29, PMOS tube M30, NMOS tube M31, NMOS tube M32, NMOS tube M33, NMOS tube M34, PMOS tube M35, PMOS tube M36, NMOS tube M37, NMOS tube M38, PMOS tube M39, NMOS tube M40, NMOS tube M41, PMOS tube M42, PMOS tube M43, PMOS tube M44, PMOS tube M45, NMOS tube M46, NMOS tube M47, PMOS tube M48, PMOS tube M49, NMOS tube M50, NMOS tube M51, NMOS tube M52, NMOS tube M53, PMOS tube OS transistor M54, PMOS transistor M55, NMOS transistor M56, NMOS transistor M57, PMOS transistor M58, PMOS transistor M59, PMOS transistor M60, PMOS transistor M61, NMOS transistor M62, NMOS transistor M63, NMOS transistor M64, NMOS transistor M65, NPN transistor Q6, resistor R8 and resistor R9, wherein the source of PMOS transistor M29 is respectively connected to the source of PMOS transistor M35, the source of PMOS transistor M39, the source of PMOS transistor M42, the source of PMOS transistor M43, the source of PMOS transistor M48, the source of PMOS transistor M54, the source of PMOS transistor M58, the source of PMOS transistor M59 and the external power supply VD D is connected to each other, the drain of the PMOS tube M29 is connected to the source of the PMOS tube M30, the source of the NMOS tube M31 is connected to the drain of the NMOS tube M33, the source of the NMOS tube M33 is respectively connected to the source of the NMOS tube M34, the source of the NMOS tube M38, the source of the NMOS tube M41, one end of the resistor R8, the emitter of the NPN transistor Q6, the source of the NMOS tube M51, the source of the NMOS tube M53, the source of the NMOS tube M57, one end of the resistor R9, the source of the NMOS tube M65 and the external ground GND, the drain of the PMOS tube M35 is connected to the source of the PMOS tube M36, the drain of the PMOS tube M36 is respectively connected to the gate of the NMOS tube M31, The gate of the NMOS transistor M32, the drain of the NMOS transistor M32, and the drain of the NMOS transistor M37 are connected. The source of the NMOS transistor M32 is respectively connected to the drain of the NMOS transistor M34, the gate of the NMOS transistor M34, and the gate of the NMOS transistor M33. The source of the NMOS transistor M37 is connected to the drain of the NMOS transistor M38. The drain of the PMOS transistor M39 is respectively connected to the gate of the NMOS transistor M37, the gate of the NMOS transistor M38, the gate of the NMOS transistor M40, the gate of the NMOS transistor M41, the drain of the NMOS transistor M40, the gate of the NMOS transistor M50, and the gate of the NMOS transistor M51. The source of the NMOS transistor M40 is connected to the drain of the NMOS transistor M41.The drain of the PMOS tube M42 is connected to the gate of the PMOS tube M42, the gate of the PMOS tube M43, the gate of the PMOS tube M39, and the source of the PMOS tube M44 respectively. The drain of the PMOS tube M44 is connected to the drain of the NMOS tube M46. The source of the NMOS tube M46 is connected to the other end of the resistor R8. The drain of the PMOS tube M43 is connected to the source of the PMOS tube M45. The drain of the PMOS tube M45 is connected to the gate of the NMOS tube M46, the gate of the NMOS tube M47, and the source of the NMOS tube M48 respectively. The drain of the PMOS tube M48 is connected to the source of the PMOS tube M49. The drain of the PMOS tube M49 is connected to the drain of the NMOS tube M50, the drain of the NMOS tube M52, the gate of the NMOS tube M52 and the gate of the NMOS tube M56. The source of the NMOS tube M52 is connected to the drain of the NMOS tube M53, the drain of the NMOS tube M54 and the gate of the NMOS tube M55. The gate of the transistor M53 is connected to the gate of the NMOS transistor M57, the drain of the PMOS transistor M54 is connected to the source of the PMOS transistor M55, the source of the NMOS transistor M56 is connected to the drain of the NMOS transistor M57, the drain of the PMOS transistor M58 is connected to the source of the PMOS transistor M60, and the drain of the PMOS transistor M60 is respectively connected to the drain of the NMOS transistor M62, the gate of the PMOS transistor M59, the gate of the PMOS transistor M58, the gate of the PMOS transistor M54, the gate of the PMOS transistor M48, and the gate of the PMOS transistor M60. The gate of the S transistor M35 is connected to the gate of the PMOS transistor M29, the source of the NMOS transistor M62 is connected to the drain of the NMOS transistor M64, the source of the NMOS transistor M64 is connected to the other end of the resistor R9, the drain of the PMOS transistor M59 is connected to the source of the PMOS transistor M61, the drain of the PMOS transistor M61 is connected to the drain of the NMOS transistor M63, the gate of the NMOS transistor M64, and the gate of the NMOS transistor M65, respectively, and the source of the NMOS transistor M63 is connected to the drain of the NMOS transistor M65.

[0009] Furthermore, in the bias circuit with startup, after the circuit is powered on and started, the NMOS tube M14 works in the cutoff region, the PMOS tube M5 is identical to the PMOS tube M6, the emitter area of ​​the NPN transistor Q2 is m times that of the NPN transistor Q1, and the NMOS tube M7 is identical to the NMOS tube M8, then the current I flowing through the PMOS tube M11 11 have Where V T is the thermal voltage, and R1 is the resistance value of resistor R1.

[0010] Further, in the base-compensated bandgap reference core circuit, the base of the NPN transistor Q3 is connected in series with the resistor R3 and the resistor R4 to eliminate the influence of the base current of the NPN transistor on the output voltage of the circuit. The PMOS transistor M15 is identical to the PMOS transistor M16, the channel width-length ratio of the PMOS transistor M17 is 2 times that of the PMOS transistor M16, the NMOS transistor M21 is identical to the NMOS transistor M22, the NPN transistor Q4 is identical to the NPN transistor Q5, the emitter area of the NPN transistor Q3 is K1 times that of the NPN transistor Q4, and the channel width-length ratio of the NMOS transistor M24 is K2 times that of the NMOS transistor M23. At the same time, after the circuit is normally powered on, the NMOS transistor M24 makes the NMOS transistor M14 work in the cut-off region. The PMOS transistor M25 is identical to the PMOS transistor M26, and the PMOS transistor M27 is identical to the PMOS transistor M28. Therefore, the signal provided by the base-compensated bandgap reference core circuit provides a voltage VREF at the circuit output end REF1 For where i b3 is the base current of the NPN transistor Q3, R3 is the resistance value of the resistor R3, R4 is the resistance value of the resistor R4, i b5 is the base current of the NPN transistor Q5, V BE5 is the base-emitter voltage of the NPN transistor Q5, R5 is the resistance value of the resistor R5, R6 is the resistance value of the resistor R6, and R7 is the resistance value of the resistor R7. By optimizing the circuit, the base current of the NPN transistor is eliminated, and the base-compensated bandgap reference voltage V is obtained. REF1

[0011] Further, in the high-order temperature compensation circuit, the PMOS transistor M58 is identical to the PMOS transistor M59, the PMOS transistor M60 is identical to the PMOS transistor M61, the NMOS transistor M62 is identical to the NMOS transistor M63, the channel width-length ratio of the NMOS transistor M64 is a times that of the NMOS transistor M65, and the NMOS transistor M64 and the NMOS transistor M65 work in the sub-threshold region. Therefore, the current I 58 of the PMOS transistor M58 is and is a current that increases with the increase of temperature, where n is a process-related parameter, and R9 is the resistance value of the resistor R9. The PMOS transistor M42 is identical to the PMOS transistor M43, the PMOS transistor M44 is identical to the PMOS transistor M45, the NMOS transistor M46 is identical to the NMOS transistor M47, and the PMOS transistor M39 is identical to the PMOS transistor M39. Therefore, the drain current I 39 of the PMOS transistor M39 is where R8 is the resistance value of the resistor R8, and V BE6 ​is the base-emitter voltage of NPN transistor Q6, so the current I 39 Has negative temperature characteristics.

[0012] Furthermore, in the high-order temperature compensation circuit, the channel width-to-length ratio of the NMOS tube M37 is K3 times that of the NMOS tube M40, the channel width-to-length ratio of the NMOS tube M38 is K3 times that of the NMOS tube M41, the channel width-to-length ratio of the PMOS tube M35 is K4 times that of the PMOS tube M58, the channel width-to-length ratio of the PMOS tube M36 is K4 times that of the PMOS tube M60, the NMOS tube M31 is exactly the same as the NMOS tube M32, and the NMOS tube M33 is exactly the same as the NMOS tube M34. By optimizing the channel width-to-length ratios of the relevant MOS tubes, the current I 31 for Where T is the absolute temperature and T1 is the reference temperature. The channel width-to-length ratio of NMOS tube M50 is K5 times that of NMOS tube M40, the channel width-to-length ratio of NMOS tube M51 is K5 times that of NMOS tube M41, the channel width-to-length ratio of PMOS tube M48 is K6 times that of PMOS tube M58, the channel width-to-length ratio of PMOS tube M49 is K6 times that of PMOS tube M60, NMOS tube M56 is exactly the same as NMOS tube M52, and NMOS tube M57 is exactly the same as NMOS tube M53. By optimizing the channel width-to-length ratios of the relevant MOS tubes, the current I 56 for Wherein, T2 is the reference temperature, and T2>T1.

[0013] Furthermore, in the high-order temperature compensation circuit, the channel width-to-length ratio of the PMOS tube M29 is K7 times that of the PMOS tube M58, the channel width-to-length ratio of the PMOS tube M30 is K7 times that of the PMOS tube M60, the channel width-to-length ratio of the PMOS tube M54 is K8 times that of the PMOS tube M58, and the channel width-to-length ratio of the PMOS tube M55 is K8 times that of the PMOS tube M60. Then, the current provided by the high-order temperature compensation circuit generates a voltage in the resistor R7 and provides a reference voltage V to the bandgap reference core circuit for base compensation. REF1 Perform high-order temperature compensation so that the output voltage V provided by the high-order bandgap reference circuit with base compensation is REF have The output voltage V of the high-order bandgap reference circuit with base compensation REF Contains V REF1 、 as well as Equal factors, where factors and factors V REF1 The temperature high-order nonlinearity is compensated to obtain the high-order compensated bandgap reference voltage VREF .

[0014] The advantages and beneficial effects of the present invention are as follows:

[0015] The present invention provides a high-order bandgap reference source circuit with base compensation, adopts an NPN transistor base series resistor technology to suppress the influence of the NPN transistor base current on the output voltage of the bandgap reference source circuit, and adopts two high-order temperature compensation currents realized by technologies such as a positive temperature coefficient current generated by the gate-source voltage difference of two NMOS transistors operating in a subthreshold region and a negative temperature coefficient current generated on a resistor by the base-emitter voltage of the NPN transistor to compensate for the high-order temperature nonlinearity of the output voltage of the bandgap reference source circuit, thereby obtaining a high-order temperature compensated bandgap reference voltage, thereby realizing a high-order bandgap reference source circuit with base compensation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is the schematic diagram of the traditional bandgap reference source circuit;

[0017] Figure 2 A schematic diagram of a high-order bandgap reference source circuit with base compensation is provided for a preferred embodiment of the present invention;

[0018] Figure 3 The present invention provides a simulation diagram of output voltage and temperature of a high-order bandgap reference source circuit with base compensation according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will describe the technical solutions in the embodiments of the present invention in detail with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of the present invention.

[0020] The technical solution of the present invention to solve the above technical problems is:

[0021] In the embodiment of the present application, NPN transistor base series resistor technology is used to suppress the influence of NPN transistor base current on the output voltage of the bandgap reference source circuit, and two high-order temperature compensation currents are realized by using technologies such as a positive temperature coefficient current generated by the difference in gate-source voltage of two NMOS tubes operating in the subthreshold region and a negative temperature coefficient current generated by the base-emitter voltage of the NPN transistor on the resistor to compensate for the high-order temperature nonlinearity of the output voltage of the bandgap reference source circuit, thereby obtaining a high-order temperature compensated bandgap reference voltage, thereby realizing a high-order bandgap reference source circuit with base compensation.

[0022] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0023] Example

[0024] A high-order bandgap reference source circuit with base compensation, such as Figure 2 As shown, it includes a bias circuit 1 with startup, a base-compensated bandgap reference core circuit 2 and a high-order temperature compensation circuit 3; wherein, the signal output end of the bias circuit 1 with startup is respectively connected to the signal input end of the base-compensated bandgap reference core circuit 2 and the signal input end of the high-order temperature compensation circuit 3, the signal output end of the base-compensated bandgap reference core circuit 2 is respectively connected to the signal input end of the bias circuit 1 with startup and the signal input end of the high-order temperature compensation circuit 3, and the signal output end of the high-order temperature compensation circuit 3 is connected to the signal input end of the base-compensated bandgap reference core circuit 2.

[0025] As a preferred technical solution, Figure 2As shown, the bias circuit 1 with startup includes: a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, a PMOS transistor M5, a PMOS transistor M6, an NMOS transistor M7, an MMOS transistor M8, a PMOS transistor M9, a PMOS transistor M10, a PMOS transistor M11, a PMOS transistor M12, an NMOS transistor M13, an NMOS transistor M14, an NPN transistor Q1, an NPN transistor Q2, a resistor R1, and a resistor R2, wherein the source of the PMOS transistor M1 is connected to the source of the PMOS transistor M5, the source of the PMOS transistor M6, the source of the PMOS transistor M9, the source of the PMOS transistor M10, and the external power supply VDD, respectively. The gate of the PMOS tube M1 is connected to the drain of the PMOS tube M1 and the source of the PMOS tube M2 respectively. The gate of the PMOS tube M2 is connected to the drain of the PMOS tube M2, the drain of the NMOS tube M4 and the gate of the NMOS tube M3 respectively. The source of the NMOS tube M4 is connected to the source of the NMOS tube M3, the source of the NMOS tube M7, the source of the NMOS tube M8, the source of the NMOS tube M13, the source of the NMOS tube M14 and the external ground GND respectively. The drain of the PMOS tube M5 is connected to the collector of the NPN transistor Q1, the base of the NPN transistor Q1 and the base of the NPN transistor Q2 respectively. The drain of the PMOS tube M6 is connected to the collector of the NPN transistor Q1, the base of the NPN transistor Q1 and the base of the NPN transistor Q2 respectively. The gate of the PMOS tube M5 is connected to the gate of the PMOS tube M6, the drain of the NMOS tube M3 and the collector of the NPN transistor Q2. The emitter of the NPN transistor Q2 is connected to one end of the resistor R1. The other end of the resistor R1 is respectively connected to the emitter of the NPN transistor Q1, the gate of the NMOS tube M62, the gate of the NMOS tube M63, the drain of the NMOS tube M7, the gate of the NMOS tube M7 and the gate of the NMOS tube M8. The drain of the PMOS tube M9 is connected to the source of the PMOS tube M11. The drain of the PMOS tube M11 is respectively connected to the gate of the PMOS tube M9, the gate of the PMOS tube M10, the gate of the PMOS tube M30, the gate of the PMOS tube M8. The gate of the OS transistor M36, the gate of the PMOS transistor M44, the gate of the PMOS transistor M45, the gate of the PMOS transistor M49, the gate of the PMOS transistor M55, the gate of the PMOS transistor M60, the gate of the PMOS transistor M61, and one end of the resistor R2 are connected. The other end of the resistor R2 is respectively connected to the gate of the PMOS transistor M11, the gate of the PMOS transistor M12, and the drain of the NMOS transistor M8. The drain of the PMOS transistor M10 is connected to the source of the PMOS transistor M12. The drain of the PMOS transistor M12 is respectively connected to the gate of the NMOS transistor M13, the drain of the NMOS transistor M13, the gate of the NMOS transistor M14, and the drain of the NMOS transistor M24.

[0026] The base compensation bandgap reference core circuit 2 comprises PMOS M15, PMOS M16, PMOS M17, PMOS M18, PMOS M19, PMOS M20, NMOS M21, NMOS M22, NMOS M23, NMOS M24, PMOS M25, PMOS M26, PMOS M27, PMOS M28, NPN triode Q3, NPN triode Q4, NPN triode Q5, resistor R3, resistor R4, resistor R5, resistor R6 and resistor R7, wherein the source of PMOS M15 is connected with the source of PMOS M16, the source of PMOS M17, the source of PMOS M25, the source of PMOS M26 and external power supply VDD respectively, the gate of PMOS M15 is connected with the gate of PMOS M16, the gate of PMOS M17, the drain of PMOS M16 and the source of PMOS M19 respectively, the drain of PMOS M15 is connected with the gate of PMOS M25, the gate of PMOS M26 and the source of PMOS M18 respectively, the gate of PMOS M18 is connected with the drain of PMOS M18, the drain of NMOS M14 and the drain of NMOS M21 respectively, the source of NMOS M21 is connected with the collector of NPN triode Q3, the base of NPN triode Q3 is connected with the gate of NMOS M21 and one end of resistor R4 respectively, the other end of resistor R4 is connected with one end of resistor R3 and the collector of NPN triode Q4 respectively, the emitter of NPN triode Q3 is connected with the emitter of NPN triode Q4, the emitter of NPN triode Q5, the source of NMOS M23, the source of NMOS M24, one end of resistor R6, one end of resistor R7 and external ground GND respectively, the gate of PMOS M19 is connected with the gate of PMOS M20, the drain of PMOS M19 and the drain of NMOS M22 respectively, the source of NMOS M22 is connected with the collector of NPN triode Q5, the drain of PMOS M17 is connected with the source of PMOS M20, the drain of PMOS M20 is connected with the drain of NMOS M23, the gate of NMOS M23 and the gate of NMOS M24 respectively, the drain of PMOS M25 is connected with the source of PMOS M27, the drain of PMOS M27 is connected with the gate of NMOS M4, the other end of resistor R3, the base of NPN triode Q4, the gate of NMOS M22, the base of NPN triode Q5 and one end of resistor R5 respectively, the other end of resistor R5 is connected with the gate of PMOS M27, the gate of PMOS M28 and the other end of resistor R6 respectively, the drain of PMOS M26 is connected with the source of PMOS M28.The drain of the PMOS transistor M28 is respectively connected to the drain of the PMOS transistor M30, the drain of the NMOS transistor M31, the drain of the PMOS transistor M55, the drain of the NMOS transistor M56, the other end of the resistor R7 and the circuit output terminal VREF.

[0027] The high-order temperature compensation circuit 3 comprises a PMOS tube M29, a PMOS tube M30, an NMOS tube M31, an NMOS tube M32, an NMOS tube M33, an NMOS tube M34, a PMOS tube M35, a PMOS tube M36, an NMOS tube M37, an NMOS tube M38, a PMOS tube M39, an NMOS tube M40, an NMOS tube M41, a PMOS tube M42, a PMOS tube M43, a PMOS tube M44, a PMOS tube M45, an NMOS tube M46, an NMOS tube M47, a PMOS tube M48, a PMOS tube M49, an NMOS tube M50, an NMOS tube M51, an NMOS tube M52, an NMOS tube M53, a PMOS tube M54, a PMOS tube M55, an NMOS tube M56, an NMOS tube M57, a PMOS tube M58, a PMOS tube M59, a PMOS tube M60, an NMOS tube M62, an NMOS tube M63, an NMOS tube M64, an NMOS tube M65, an NPN triode Q6, a resistor R8 and a resistor R9, wherein the source of the PMOS tube M29 is connected with the source of the PMOS tube M35, the source of the PMOS tube M39, the source of the PMOS tube M42, the source of the PMOS tube M43, the source of the PMOS tube M48, the source of the PMOS tube M54, the source of the PMOS tube M58, the source of the PMOS tube M59 and an external power supply VDD respectively, the drain of the PMOS tube M29 is connected with the source of the PMOS tube M30, the source of the NMOS tube M31 is connected with the drain of the NMOS tube M33, the source of the NMOS tube M33 is connected with the source of the NMOS tube M34, the source of the NMOS tube M38, the source of the NMOS tube M41, one end of the resistor R8, the emitter of the NPN triode Q6, the source of the NMOS tube M51, the source of the NMOS tube M53, the source of the NMOS tube M57, one end of the resistor R9, the source of the NMOS tube M65 and an external ground GND respectively, the drain of the PMOS tube M35 is connected with the source of the PMOS tube M36, the drain of the PMOS tube M36 is connected with the gate of the NMOS tube M31, the gate of the NMOS tube M32, the drain of the NMOS tube M32 and the drain of the NMOS tube M37 respectively, the source of the NMOS tube M32 is connected with the drain of the NMOS tube M34, the gate of the NMOS tube M34 and the gate of the NMOS tube M33 respectively, the source of the NMOS tube M37 is connected with the drain of the NMOS tube M38, the drain of the PMOS tube M39 is connected with the gate of the NMOS tube M37, the gate of the NMOS tube M38, the gate of the NMOS tube M40, the gate of the NMOS tube M41, the drain of the NMOS tube M40, the gate of the NMOS tube M50 and the gate of the NMOS tube M51 respectively, the source of the NMOS tube M40 is connected with the drain of the NMOS tube M41, and so on.The drain of the PMOS tube M42 is connected to the gate of the PMOS tube M42, the gate of the PMOS tube M43, the gate of the PMOS tube M39, and the source of the PMOS tube M44 respectively. The drain of the PMOS tube M44 is connected to the drain of the NMOS tube M46. The source of the NMOS tube M46 is connected to the other end of the resistor R8. The drain of the PMOS tube M43 is connected to the source of the PMOS tube M45. The drain of the PMOS tube M45 is connected to the gate of the NMOS tube M46, the gate of the NMOS tube M47, and the source of the NMOS tube M48 respectively. The drain of the PMOS tube M48 is connected to the source of the PMOS tube M49. The drain of the PMOS tube M49 is connected to the drain of the NMOS tube M50, the drain of the NMOS tube M52, the gate of the NMOS tube M52 and the gate of the NMOS tube M56. The source of the NMOS tube M52 is connected to the drain of the NMOS tube M53, the drain of the NMOS tube M54 and the gate of the NMOS tube M55. The gate of the transistor M53 is connected to the gate of the NMOS transistor M57, the drain of the PMOS transistor M54 is connected to the source of the PMOS transistor M55, the source of the NMOS transistor M56 is connected to the drain of the NMOS transistor M57, the drain of the PMOS transistor M58 is connected to the source of the PMOS transistor M60, and the drain of the PMOS transistor M60 is respectively connected to the drain of the NMOS transistor M62, the gate of the PMOS transistor M59, the gate of the PMOS transistor M58, the gate of the PMOS transistor M54, the gate of the PMOS transistor M48, and the gate of the PMOS transistor M60. The gate of the S transistor M35 is connected to the gate of the PMOS transistor M29, the source of the NMOS transistor M62 is connected to the drain of the NMOS transistor M64, the source of the NMOS transistor M64 is connected to the other end of the resistor R9, the drain of the PMOS transistor M59 is connected to the source of the PMOS transistor M61, the drain of the PMOS transistor M61 is connected to the drain of the NMOS transistor M63, the gate of the NMOS transistor M64, and the gate of the NMOS transistor M65, respectively, and the source of the NMOS transistor M63 is connected to the drain of the NMOS transistor M65.

[0028] In the bias circuit 1 with startup, the PMOS tube M5 is identical to the PMOS tube M6, the emitter area of ​​the NPN transistor Q2 is m times that of the NPN transistor Q1, and the NMOS tube M7 is identical to the NMOS tube M8. Then the current I flowing through the PMOS tube M11 is 11 have

[0029]

[0030] Where V T is the thermal voltage, R1 is the resistance of resistor R1. From formula (1), we can know that the current I flowing through the PMOS tube M11 is 11 Has positive temperature characteristics.

[0031] In the base-compensated bandgap reference core circuit 2, the PMOS transistor M15 is identical to the PMOS transistor M16, the channel width-to-length ratio of the PMOS transistor M17 is twice that of the PMOS transistor M16, the NMOS transistor M21 is identical to the NMOS transistor M22, the NPN transistor Q4 is identical to the NPN transistor Q5, the emitter area of ​​the NPN transistor Q3 is K1 times that of the NPN transistor Q4, and the channel width-to-length ratio of the NMOS transistor M24 is K2 times that of the NMOS transistor M23. At the same time, after the circuit is powered on and operating normally, the NMOS transistor M24 causes the NMOS transistor M14 to operate in the cutoff region. Therefore, the collector current I c4 for

[0032]

[0033] Where i b3 is the base current of NPN transistor Q3, R3 is the resistance value of resistor R3, and R4 is the resistance value of resistor R4. PMOS transistor M25 is identical to PMOS transistor M26, and PMOS transistor M27 is identical to PMOS transistor M28. The signal provided by the base-compensated bandgap reference core circuit 2 provides a voltage V at the circuit output terminal VREF. REF1 for

[0034]

[0035] Where i b5 is the base current of NPN transistor Q5, V BE5 is the base-emitter voltage of NPN transistor Q5, R5 is the resistance value of resistor R5, R6 is the resistance value of resistor R6, and R7 is the resistance value of resistor R7. By optimizing the circuit, This eliminates the influence of the NPN transistor base current on the circuit output voltage, thereby obtaining the base-compensated bandgap reference voltage V REF1 .

[0036] In the high-order temperature compensation circuit 3, the PMOS transistor M58 is identical to the PMOS transistor M59, the PMOS transistor M60 is identical to the PMOS transistor M61, the NMOS transistor M62 is identical to the NMOS transistor M63, the channel width-to-length ratio of the NMOS transistor M64 is α times that of the NMOS transistor M65, and the NMOS transistors M64 and M65 operate in the subthreshold region. The difference ΔV between the gate-source voltage of the NMOS transistor M64 and the gate-source voltage of the NMOS transistor M65 is GS for

[0037]

[0038] Where n is a process-related parameter. Then the current I of the PMOS tube M58 is58 for

[0039]

[0040] In the formula, R9 is the resistance value of resistor R9. From formula (5), we can know that the current I 58 It is a current that increases with increasing temperature. PMOS tube M42 is exactly the same as PMOS tube M43, PMOS tube M44 is exactly the same as PMOS tube M45, NMOS tube M46 is exactly the same as NMOS tube M47, and PMOS tube M39 is exactly the same as PMOS tube M39. Then the drain current I of PMOS tube M39 is 39 for

[0041]

[0042] Where R8 is the resistance of resistor R8, V BE6 is the base-emitter voltage of NPN transistor Q6, so the current I 39 It has negative temperature characteristics. The channel width-to-length ratio of the NMOS tube M37 is K3 times that of the NMOS tube M40, the channel width-to-length ratio of the NMOS tube M38 is K3 times that of the NMOS tube M41, and the current I 37 for

[0043]

[0044] The channel width-to-length ratio of the PMOS tube M35 is K4 times that of the PMOS tube M58, the channel width-to-length ratio of the PMOS tube M36 is K4 times that of the PMOS tube M60, the NMOS tube M31 is exactly the same as the NMOS tube M32, and the NMOS tube M33 is exactly the same as the NMOS tube M34. By optimizing the channel width-to-length ratios of the relevant MOS tubes, the current I 31 for

[0045]

[0046] Where T is the absolute temperature and T1 is the reference temperature. The channel width-to-length ratio of NMOS tube M50 is K5 times that of NMOS tube M40, the channel width-to-length ratio of NMOS tube M51 is K5 times that of NMOS tube M41, the channel width-to-length ratio of PMOS tube M48 is K6 times that of PMOS tube M58, and the channel width-to-length ratio of PMOS tube M49 is K6 times that of PMOS tube M60. NMOS tube M56 is exactly the same as NMOS tube M52, and NMOS tube M57 is exactly the same as NMOS tube M53. By optimizing the channel width-to-length ratios of the relevant MOS tubes, the current I 56 for

[0047]

[0048] Wherein, T2 is the reference temperature, and T2>T1. The channel width-to-length ratio of the PMOS transistor M29 is K7 times that of the PMOS transistor M58, the channel width-to-length ratio of the PMOS transistor M30 is K7 times that of the PMOS transistor M60, the channel width-to-length ratio of the PMOS transistor M54 is K8 times that of the PMOS transistor M58, and the channel width-to-length ratio of the PMOS transistor M55 is K8 times that of the PMOS transistor M60. The current provided by the high-order temperature compensation circuit 3 generates a voltage in the resistor R7 and provides a reference voltage V provided by the bandgap reference core circuit 2 for base compensation. REF1 Perform high-order temperature compensation so that the output voltage V provided by the high-order bandgap reference circuit with base compensation is REF have

[0049]

[0050] From formula (10), we can know that the output voltage V of the high-order bandgap reference source circuit with base compensation is REF Contains V REF1 、 as well as Equal factors, where factors and factors V REF1 The temperature high-order nonlinearity is compensated to obtain the high-order compensated bandgap reference voltage V REF .

[0051] Figure 3 The output voltage V of a high-order bandgap reference source circuit with base compensation according to the present invention is REF The temperature characteristic simulation curve of the high-order bandgap reference circuit with base compensation is shown in the figure, where the horizontal axis is temperature and the vertical axis is output voltage. The simulation results show that in the temperature range of -40℃ to 120℃, the output voltage V REF The temperature coefficient is 2.85ppm / ℃.

[0052] In the above-mentioned embodiment of the present application, a high-order bandgap reference source circuit with base compensation includes a bias circuit with startup, a bandgap reference core circuit with base compensation, and a high-order temperature compensation circuit. The embodiment of the present application adopts the technology of connecting the base of an NPN transistor in series with a resistor to suppress the influence of the base current of the NPN transistor on the output voltage of the bandgap reference source circuit, and adopts two high-order temperature compensation currents realized by technologies such as a positive temperature coefficient current generated by the difference between the gate-source voltages of two NMOS transistors operating in the subthreshold region and a negative temperature coefficient current generated on the resistor by the base-emitter voltage of the NPN transistor to compensate for the high-order temperature nonlinearity of the output voltage of the bandgap reference source circuit, thereby obtaining a high-order temperature compensated bandgap reference voltage, thereby realizing a high-order bandgap reference source circuit with base compensation.

[0053] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0054] The above embodiments should be understood as merely illustrating the present invention and not as limiting the scope of protection of the present invention. After reading the contents of the present invention, technicians may make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A high-order bandgap reference source circuit with base compensation, characterized in that: include: A bias circuit with startup (1), a base-compensated bandgap reference core circuit (2) and a high-order temperature compensation circuit (3), wherein the signal output end of the bias circuit with startup (1) is respectively connected to the signal input end of the base-compensated bandgap reference core circuit (2) and the signal input end of the high-order temperature compensation circuit (3), the signal output end of the base-compensated bandgap reference core circuit (2) is respectively connected to the signal input end of the bias circuit with startup (1) and the signal input end of the high-order temperature compensation circuit (3), and the signal output end of the high-order temperature compensation circuit (3) is connected to the signal input end of the base-compensated bandgap reference core circuit (2); the base-compensated bandgap reference core circuit ( 2) including: PMOS transistor M15, PMOS transistor M16, PMOS transistor M17, PMOS transistor M18, PMOS transistor M19, PMOS transistor M20, NMOS transistor M21, NMOS transistor M22, NMOS transistor M23, NMOS transistor M24, PMOS transistor M25, PMOS transistor M26, PMOS transistor M27, PMOS transistor M28, NPN transistor Q3, NPN transistor Q4, NPN transistor Q5, resistor R3, resistor R4, resistor R5, resistor R6 and resistor R7, wherein the source of PMOS transistor M15 is connected to the source of PMOS transistor M16, the source of PMOS transistor M17, the source of PMOS transistor M25, the source of PMOS transistor M26, the source of PMOS transistor M27, the source of PMOS transistor M28, the source of PMOS transistor M29, the source of PMOS transistor M30, the source of PMOS transistor M31, the source of PMOS transistor M32, the source of PMOS transistor M33, the source of PMOS transistor M34, the source of PMOS transistor M35, the source of PMOS transistor M36, the source of PMOS transistor M37, the source of PMOS transistor M38, the source of PMOS transistor M39, the source of PMOS transistor M40, the source of PMOS transistor M41, the source of PMOS transistor M42, the source of PMOS transistor M43, the source of PMOS transistor M44, the source of PMOS transistor M45, the source of PMOS transistor M46, the source of PMOS transistor M47, the source of PMOS transistor M48, the source of PMOS transistor M49, the source of PMOS transistor M50, the source of PMOS transistor M51, the source of PMOS transistor M52 The source of the PMOS transistor M26 is connected to the external power supply VDD, the gate of the PMOS transistor M15 is connected to the gate of the PMOS transistor M16, the gate of the PMOS transistor M17, the drain of the PMOS transistor M16 and the source of the PMOS transistor M19 respectively, the drain of the PMOS transistor M15 is connected to the gate of the PMOS transistor M25, the gate of the PMOS transistor M26 and the source of the PMOS transistor M18 respectively, the gate of the PMOS transistor M18 is connected to the drain of the PMOS transistor M18, the drain of the NMOS transistor M14 and the drain of the NMOS transistor M21 respectively, the source of the NMOS transistor M21 is connected to the collector of the NPN transistor Q3, the base of the NPN transistor Q3 is connected to the gate of the NMOS transistor M21 and the drain of the NMOS transistor M21 respectively. One end of the resistor R4 is connected, and the other end of the resistor R4 is respectively connected to one end of the resistor R3 and the collector of the NPN transistor Q4. The emitter of the NPN transistor Q3 is respectively connected to the emitter of the NPN transistor Q4, the emitter of the NPN transistor Q5, the source of the NMOS transistor M23, the source of the NMOS transistor M24, one end of the resistor R6, one end of the resistor R7, and the external ground GND. The gate of the PMOS transistor M19 is respectively connected to the gate of the PMOS transistor M20, the drain of the PMOS transistor M19, and the drain of the NMOS transistor M22. The source of the NMOS transistor M22 is connected to the collector of the NPN transistor Q5. The drain of the PMOS transistor M17 is connected to the source of the PMOS transistor M20.The drain of the PMOS transistor M20 is connected to the drain of the NMOS transistor M23, the gate of the NMOS transistor M23, and the gate of the NMOS transistor M24. The drain of the PMOS transistor M25 is connected to the source of the PMOS transistor M27. The drain of the PMOS transistor M27 is connected to the gate of the NMOS transistor M4, the other end of the resistor R3, the base of the NPN transistor Q4, the gate of the NMOS transistor M22, the base of the NPN transistor Q5, and one end of the resistor R5. The other end of the resistor R5 is connected to the gate of the PMOS transistor M27, the gate of the PMOS transistor M28, and the other end of the resistor R6. The drain of the PMOS transistor M26 is connected to the source of the PMOS transistor M28. The drain of the PMOS transistor M28 is connected to the drain of the PMOS transistor M30, the drain of the NMOS transistor M31, the drain of the PMOS transistor M55, the drain of the NMOS transistor M56, the other end of the resistor R7, and the circuit output terminal VREF.

2. The high-order bandgap reference source circuit with base compensation according to claim 1, characterized in that: The bias circuit (1) with startup comprises: a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, a PMOS tube M5, a PMOS tube M6, an NMOS tube M7, an MMOS tube M8, a PMOS tube M9, a PMOS tube M10, a PMOS tube M11, a PMOS tube M12, an NMOS tube M13, an NMOS tube M14, an NPN transistor Q1, an NPN transistor Q2, a resistor R1 and a resistor R2, wherein the source of the PMOS tube M1 is respectively connected to the source of the PMOS tube M5, the source of the PMOS tube M6, the source of the PMOS tube M9, the source of the PMOS tube M10 and an external power supply VDD. The gate of the PMOS tube M1 is connected to the drain of the PMOS tube M1 and the source of the PMOS tube M2 respectively. The gate of the PMOS tube M2 is connected to the drain of the PMOS tube M2, the drain of the NMOS tube M4 and the gate of the NMOS tube M3 respectively. The source of the NMOS tube M4 is connected to the source of the NMOS tube M3, the source of the NMOS tube M7, the source of the NMOS tube M8, the source of the NMOS tube M13, the source of the NMOS tube M14 and the external ground GND respectively. The drain of the PMOS tube M5 is connected to the collector of the NPN transistor Q1, the base of the NPN transistor Q1 and the base of the NPN transistor Q2 respectively. The drain of the PMOS tube M6 is connected to the collector of the NPN transistor Q1, the base of the NPN transistor Q1 and the base of the NPN transistor Q2 respectively. The gate of the PMOS tube M5 is connected to the gate of the PMOS tube M6, the drain of the NMOS tube M3 and the collector of the NPN transistor Q2. The emitter of the NPN transistor Q2 is connected to one end of the resistor R1. The other end of the resistor R1 is respectively connected to the emitter of the NPN transistor Q1, the gate of the NMOS tube M62, the gate of the NMOS tube M63, the drain of the NMOS tube M7, the gate of the NMOS tube M7 and the gate of the NMOS tube M8. The drain of the PMOS tube M9 is connected to the source of the PMOS tube M11. The drain of the PMOS tube M11 is respectively connected to the gate of the PMOS tube M9, the gate of the PMOS tube M10, the gate of the PMOS tube M30, the gate of the PMOS tube M8. The gate of the OS transistor M36, the gate of the PMOS transistor M44, the gate of the PMOS transistor M45, the gate of the PMOS transistor M49, the gate of the PMOS transistor M55, the gate of the PMOS transistor M60, the gate of the PMOS transistor M61, and one end of the resistor R2 are connected. The other end of the resistor R2 is respectively connected to the gate of the PMOS transistor M11, the gate of the PMOS transistor M12, and the drain of the NMOS transistor M8. The drain of the PMOS transistor M10 is connected to the source of the PMOS transistor M12. The drain of the PMOS transistor M12 is respectively connected to the gate of the NMOS transistor M13, the drain of the NMOS transistor M13, the gate of the NMOS transistor M14, and the drain of the NMOS transistor M24.

3. The high-order bandgap reference source circuit with base compensation according to claim 1, characterized in that: The high-order temperature compensation circuit (3) includes: a PMOS tube M29, a PMOS tube M30, an NMOS tube M31, an NMOS tube M32, an NMOS tube M33, an NMOS tube M34, a PMOS tube M35, a PMOS tube M36, an NMOS tube M37, an NMOS tube M38, a PMOS tube M39, an NMOS tube M40, an NMOS tube M41, a PMOS tube M42, a PMOS tube M43, a PMOS tube M44, a PMOS tube M45, an NMOS tube M46, an NMOS tube M47, a PMOS tube M48, a PMOS tube M49, an NMOS tube M50, an NMOS tube M51, an NMOS tube M52, an NMOS tube M53, a PMOS tube S transistor M54, PMOS transistor M55, NMOS transistor M56, NMOS transistor M57, PMOS transistor M58, PMOS transistor M59, PMOS transistor M60, PMOS transistor M61, NMOS transistor M62, NMOS transistor M63, NMOS transistor M64, NMOS transistor M65, NPN transistor Q6, resistor R8 and resistor R9, wherein the source of PMOS transistor M29 is respectively connected to the source of PMOS transistor M35, the source of PMOS transistor M39, the source of PMOS transistor M42, the source of PMOS transistor M43, the source of PMOS transistor M48, the source of PMOS transistor M54, the source of PMOS transistor M58, the source of PMOS transistor M59 and the external power supply VDD The drain of the PMOS tube M29 is connected to the source of the PMOS tube M30, the source of the NMOS tube M31 is connected to the drain of the NMOS tube M33, the source of the NMOS tube M33 is respectively connected to the source of the NMOS tube M34, the source of the NMOS tube M38, the source of the NMOS tube M41, one end of the resistor R8, the emitter of the NPN transistor Q6, the source of the NMOS tube M51, the source of the NMOS tube M53, the source of the NMOS tube M57, one end of the resistor R9, the source of the NMOS tube M65 and the external ground GND, the drain of the PMOS tube M35 is connected to the source of the PMOS tube M36, and the drain of the PMOS tube M36 is respectively connected to the gate of the NMOS tube M31, The gate of the NMOS transistor M32, the drain of the NMOS transistor M32, and the drain of the NMOS transistor M37 are connected. The source of the NMOS transistor M32 is respectively connected to the drain of the NMOS transistor M34, the gate of the NMOS transistor M34, and the gate of the NMOS transistor M33. The source of the NMOS transistor M37 is connected to the drain of the NMOS transistor M38. The drain of the PMOS transistor M39 is respectively connected to the gate of the NMOS transistor M37, the gate of the NMOS transistor M38, the gate of the NMOS transistor M40, the gate of the NMOS transistor M41, the drain of the NMOS transistor M40, the gate of the NMOS transistor M50, and the gate of the NMOS transistor M51. The source of the NMOS transistor M40 is connected to the drain of the NMOS transistor M41.The drain of the PMOS tube M42 is connected to the gate of the PMOS tube M42, the gate of the PMOS tube M43, the gate of the PMOS tube M39, and the source of the PMOS tube M44 respectively. The drain of the PMOS tube M44 is connected to the drain of the NMOS tube M46. The source of the NMOS tube M46 is connected to the other end of the resistor R8. The drain of the PMOS tube M43 is connected to the source of the PMOS tube M45. The drain of the PMOS tube M45 is connected to the gate of the NMOS tube M46, the gate of the NMOS tube M47, and the source of the NMOS tube M48 respectively. The drain of the PMOS tube M48 is connected to the source of the PMOS tube M49. The drain of the PMOS tube M49 is connected to the drain of the NMOS tube M50, the drain of the NMOS tube M52, the gate of the NMOS tube M52 and the gate of the NMOS tube M56. The source of the NMOS tube M52 is connected to the drain of the NMOS tube M53, the drain of the NMOS tube M54 and the gate of the NMOS tube M55. The gate of the transistor M53 is connected to the gate of the NMOS transistor M57, the drain of the PMOS transistor M54 is connected to the source of the PMOS transistor M55, the source of the NMOS transistor M56 is connected to the drain of the NMOS transistor M57, the drain of the PMOS transistor M58 is connected to the source of the PMOS transistor M60, and the drain of the PMOS transistor M60 is respectively connected to the drain of the NMOS transistor M62, the gate of the PMOS transistor M59, the gate of the PMOS transistor M58, the gate of the PMOS transistor M54, the gate of the PMOS transistor M48, and the gate of the PMOS transistor M60. The gate of the S transistor M35 is connected to the gate of the PMOS transistor M29, the source of the NMOS transistor M62 is connected to the drain of the NMOS transistor M64, the source of the NMOS transistor M64 is connected to the other end of the resistor R9, the drain of the PMOS transistor M59 is connected to the source of the PMOS transistor M61, the drain of the PMOS transistor M61 is connected to the drain of the NMOS transistor M63, the gate of the NMOS transistor M64, and the gate of the NMOS transistor M65, respectively, and the source of the NMOS transistor M63 is connected to the drain of the NMOS transistor M65.

4. The high-order bandgap reference source circuit with base compensation according to claim 2, characterized in that: In the bias circuit (1) with startup, after the circuit is powered on and started, the NMOS tube M14 works in the cutoff region, the PMOS tube M5 is identical to the PMOS tube M6, the emitter area of ​​the NPN transistor Q2 is m times that of the NPN transistor Q1, and the NMOS tube M7 is identical to the NMOS tube M8, then the current I flowing through the PMOS tube M11 is 11 have Then, a bias signal is generated to provide the high-order temperature compensation circuit (3), wherein V T is the thermal voltage, and R1 is the resistance value of resistor R1.

5. The high-order bandgap reference source circuit with base compensation according to claim 1, characterized in that: In the base-compensated bandgap reference core circuit (2), the base of the NPN transistor Q3 is connected in series with the resistor R3 and the resistor R4 to eliminate the influence of the base current of the NPN transistor on the circuit output voltage. The PMOS transistor M15 is identical to the PMOS transistor M16. The channel width-to-length ratio of the PMOS transistor M17 is twice that of the PMOS transistor M16. The NMOS transistor M21 is identical to the NMOS transistor M22. The NPN transistor Q4 is identical to the NPN transistor Q5. The emitter area of ​​the NPN transistor Q3 is K1 times that of the NPN transistor Q4. The channel width-to-length ratio of the NMOS transistor M24 is K2 times that of the NMOS transistor M23. After the circuit is powered on and operates normally, the NMOS transistor M24 causes the NMOS transistor M14 to operate in the cutoff region. The PMOS transistor M25 is identical to the PMOS transistor M26. The PMOS transistor M27 is identical to the PMOS transistor M28. Then, the voltage V provided by the signal provided by the base-compensated bandgap reference core circuit at the circuit output terminal VREF is REF1 for Where V T is the thermal voltage, R1 is the resistance value of resistor R1, i b3 is the base current of NPN transistor Q3, R3 is the resistance value of resistor R3, R4 is the resistance value of resistor R4, i b5 is the base current of NPN transistor Q5, V BE5 is the base-emitter voltage of NPN transistor Q5, R5 is the resistance value of resistor R5, R6 is the resistance value of resistor R6, and R7 is the resistance value of resistor R7. By optimizing the circuit, It can eliminate the influence of the NPN transistor base current on the circuit output voltage, thereby obtaining the base-compensated bandgap reference voltage V REF1 .

6. The high-order bandgap reference source circuit with base compensation according to claim 3, characterized in that: In the high-order temperature compensation circuit (3), the PMOS tube M58 is identical to the PMOS tube M59, the PMOS tube M60 is identical to the PMOS tube M61, the NMOS tube M62 is identical to the NMOS tube M63, the channel width-to-length ratio of the NMOS tube M64 is α times that of the NMOS tube M65, and the NMOS tube M64 and the NMOS tube M65 operate in the subthreshold region, so the current I of the PMOS tube M58 is 58 for It is a current that increases with temperature, where n is a process-related parameter, V T is the thermal voltage, R9 is the resistance of resistor R9, PMOS tube M42 is exactly the same as PMOS tube M43, PMOS tube M44 is exactly the same as PMOS tube M45, NMOS tube M46 is exactly the same as NMOS tube M47, and PMOS tube M39 is exactly the same as PMOS tube M42. Then the drain current I 39 for Where R8 is the resistance value of resistor R8, V BE6 is the base-emitter voltage of NPN transistor Q6, so the current I 39 Has negative temperature characteristics.

7. The high-order bandgap reference source circuit with base compensation according to claim 6, characterized in that: In the high-order temperature compensation circuit (3), the channel width-to-length ratio of the NMOS tube M37 is K3 times that of the NMOS tube M40, the channel width-to-length ratio of the NMOS tube M38 is K3 times that of the NMOS tube M41, the channel width-to-length ratio of the PMOS tube M35 is K4 times that of the PMOS tube M58, the channel width-to-length ratio of the PMOS tube M36 is K4 times that of the PMOS tube M60, the NMOS tube M31 is identical to the NMOS tube M32, and the NMOS tube M33 is identical to the NMOS tube M34. By optimizing the channel width-to-length ratios of the relevant MOS tubes, the current I 31 for Wherein, T is the absolute temperature, T1 is the reference temperature, α is the ratio of the channel width to length ratio of the NMOS tube M64 to the NMOS tube M65, n is a process-related parameter, V T is the thermal voltage, R9 is the resistance value of resistor R9, V BE6 is the base-emitter voltage of the NPN transistor Q6, R8 is the resistance value of the resistor R8, the channel width-to-length ratio of the NMOS transistor M50 is K5 times that of the NMOS transistor M40, the channel width-to-length ratio of the NMOS transistor M51 is K5 times that of the NMOS transistor M41, the channel width-to-length ratio of the PMOS transistor M48 is K6 times that of the PMOS transistor M58, the channel width-to-length ratio of the PMOS transistor M49 is K6 times that of the PMOS transistor M60, the NMOS transistor M56 is exactly the same as the NMOS transistor M52, and the NMOS transistor M57 is exactly the same as the NMOS transistor M53. By optimizing the channel width-to-length ratios of the relevant MOS transistors, the current I 56 for Wherein, T2 is the reference temperature, and T2>T1.

8. A high-order bandgap reference source circuit with base compensation according to any one of claims 5 to 7, characterized in that: The channel width-to-length ratio of the PMOS tube M29 is K7 times that of the PMOS tube M58, the channel width-to-length ratio of the PMOS tube M30 is K7 times that of the PMOS tube M60, the channel width-to-length ratio of the PMOS tube M54 is K8 times that of the PMOS tube M58, and the channel width-to-length ratio of the PMOS tube M55 is K8 times that of the PMOS tube M60. Then, the current provided by the high-order temperature compensation circuit (3) generates a voltage in the resistor R7 and provides a reference voltage V to the bandgap reference core circuit (2) for base compensation. REF1 Perform high-order temperature compensation so that the output voltage V provided by the high-order bandgap reference circuit with base compensation is REF have Where n is a process-related parameter, V T is the thermal voltage, R9 is the resistance of the resistor R9, α is the ratio of the channel width to length ratio of the NMOS tube M64 and the NMOS tube M65, I 31 is the current of NMOS tube M31, R7 is the resistance value of resistor R7, I 56 is the current of NMOS tube M56, and the output voltage V REF Contains V REF1 、 as well as Among them, the factor and factors V REF1 The temperature high-order nonlinearity is compensated to obtain the high-order compensated bandgap reference voltage V REF .

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