Strr / dtr mode implementation method for flash controller

Abstract

The invention discloses a strir / dtr mode implementation method for a flash controller. The strir / dtr mode implementation method comprises the steps that the clock frequency of a frequency doubling clock is set to serve as a reference clock; the register taking the frequency doubling clock as the clock signal outputs a Flash clock signal and outputs the Flash clock signal to the Flash chip; setting a clock gating signal of the reference clock and obtaining an application clock; an application clock is adopted to control a chip selection signal and a data signal of the Flash chip; in the str mode, a clock gating signal is set to be overturned according to the upper and lower edges of a reference clock; setting a clock gating signal to be effective in the dtr mode, and ensuring that an application clock and a reference clock have the same frequency through the clock gating signal; and repeating the steps to complete the realization of the str / dtr mode for the flash controller. According to the invention, the strr / dtr mode of the flash controller can be realized, the development period is short, the power consumption is low, the occupied resources are less, the reliability is high, and the accuracy is good.

Description

Technical Field

[0001] The invention belongs to the field of digital signal processing, and in particular relates to a STR / DTR mode implementation method for a flash controller. Background Art

[0002] In many large-scale integrated circuits (such as satellite positioning, artificial intelligence computer vision, etc.), there are SoC (system on chip) parts. SoC work usually requires storing part of the operating system and business firmware in the off-chip NVM (non-volatile) memory. Among the commonly used NVM memories, QSPI (4-wire synchronous serial interface) type Nor flash has become the most commonly used choice of NVM memory today because of its fast reading speed, stable data storage, simple interface, and xip (immediate execution) capabilities.

[0003] The read data rate of QSPI flash is crucial to system performance; especially during the system boot phase, the read data rate of QSPI flash plays a decisive role in the fast operation of the system.

[0004] The previous QSPI interface flash is in STR (single cycle transfer rate) mode, that is, every rising edge of the SCCLK pin aligns the center position of the data signal (including command, address, and data). Both read (flash to chip) and write (chip to flash) operations use STR mode.

[0005] In order to improve the performance of the system, a new flash device has emerged in recent years. In addition to supporting the traditional STR mode, it also supports the DTR (double transfer rate) transmission mode. In the process of reading data, the command code is the same as the STR mode. The command signal jumps on the falling edge of sclk, and the rising edge of sclk is aligned to the center position of the effective level of the command signal. However, the address signal sent jumps once on each rising edge of sclk and each falling edge of sclk. The read data returned from the flash also jumps once on each rising edge and each falling edge of sclk. The DTR mode is reflected in the read address sent by the chip's flash controller and the read data returned by the flash, which is twice as fast as the previous STR mode signal rate.

[0006] Flash controllers that support DTR must still support traditional STR operations because, except for the operations of reading data and setting DLP (data learning mode), which can choose to use STR or DTR, all other operations, such as writing data and reading status registers, are still STR operations.

[0007] In order to make flash compatible with both str and dtr modes, the commonly used implementation methods include:

[0008] 1) Divide into 2 functional modules: Divide into 2 functional modules, one is the str function, which works on the same frequency clock as sclk; the other is the dtr function, which works on the 2 times frequency clock of sclk. However, this method has the defects of occupying more resources and high power consumption; in addition, the port signal of this method has 2 clocks, and when calculating the timing of the path, both clocks must be calculated;

[0009] 2) Both work at the sclk frequency clock, and use dual-edge clock registers at the port: Under this method, some FPGA versions have dual-edge clock registers, oddr and iddr; an oddr has two data input ports and one data output port. The oddr clock rising edge samples the signal from one data input port, and the oddr clock falling edge samples the signal from the other data input port. Originally, the two data input signals were signals of a single clock edge for the entire cycle, but after a parallel-to-serial conversion, they became dual-clock edges at the data output port, with a double-rate signal that jumps once every half a cycle. The iddr is the opposite, with a dual-clock edge, double-rate signal at one data input port, after a serial-to-parallel conversion, it becomes two single-clock edges, with a single-rate signal that jumps once every cycle, and is output from the two data output ports. However, this method requires the process to support the corresponding devices, but there are generally no devices such as oddr and iddr in the asic process.

[0010] 3) All operate at 2x frequency clock of sclk, and the signal update is controlled by the synchronization enable signal: the whole module is synchronized with the rising edge of 2x frequency clock (qspi_clk_2x) of sclk. The sclk port signal is always output with 2x frequency clock. It is controlled by the synchronization signal sclk_tglen (sclk_flip enable). When flipping is required, sclk_tglen flips once on the rising edge of each 2x frequency clock. When flipping is not required, it stays at high level or low level according to the mode selection; this method increases the logic operation of the data path, increases the logic resources, and the timing path is also longer; in addition, the dynamic power consumption of this method is also large. Summary of the invention

[0011] The object of the present invention is to provide a method for realizing the STR / DTR mode for a flash controller which has high reliability, good accuracy and is simple and convenient to implement.

[0012] The str / dtr mode implementation method for a flash controller provided by the present invention comprises the following steps:

[0013] S1. Set the clock frequency of the double frequency clock and use the set double frequency clock as the reference clock;

[0014] S2. The register with the double frequency clock as the clock signal outputs the Flash clock signal and outputs it to the corresponding pin of the Flash chip;

[0015] S3 sets the clock gating signal of the reference clock, and controls the reference clock through the clock gating signal, and obtains the application clock;

[0016] S4. The chip select signal and data signal of the Flash chip are controlled by the application clock obtained in step S4;

[0017] S5. In str mode, set the clock gating signal to flip according to the rising and falling edges of the reference clock to ensure that the application clock is the reference clock divided by two;

[0018] S6. In the DTR mode, set the clock gating signal to be valid, and ensure that the application clock and the reference clock are in the same frequency through the clock gating signal;

[0019] S7. Repeat steps S1 to S6 to complete the str / dtr mode implementation for the flash controller.

[0020] The step S5 is specifically to set the clock gating signal qspi_clk_en to flip once at the rising edge of each reference clock qspi_clk_2x in the str mode, so as to ensure that the application clock qspi_clk is a half-frequency of the reference clock; in the str mode, the data signal of the Flash chip corresponds to one beat of data in each Flash clock signal cycle.

[0021] The step S6 is specifically to set the clock gating signal qspi_clk_en to be continuously valid in the dtr mode, at which time the application clock qspi_clk and the reference clock qspi_clk_2x have the same frequency; in the dtr mode, all signals of the circuit are synchronized with the rising edge of the application clock qspi_clk.

[0022] The STR / DTR mode implementation method for a flash controller provided by the present invention can implement the STR / DTR mode of a flash controller through simple algorithm design and innovative use of a gated enable signal, and has a short development cycle, low power consumption, less resource occupation, high reliability and good accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The figure is a schematic diagram of the method flow of the present invention.

[0024] Figure 2 It is a timing diagram of the method of the present invention. DETAILED DESCRIPTION

[0025] like Figure 1 The method flow diagram of the method of the present invention is shown as follows: the str / dtr mode implementation method for the flash controller provided by the present invention comprises the following steps:

[0026] S1. Set the clock frequency of the double frequency clock qspi_clk_2x, and use the set double frequency clock as the reference clock;

[0027] S2. The register outputs the Flash clock signal sclk using the double frequency clock qspi_clk_2x as the clock signal, and outputs it to the corresponding pin of the Flash chip;

[0028] S3. Set the clock gating signal qspi_clk_en of the reference clock, and control the reference clock through the clock gating signal to obtain the application clock qspi_clk;

[0029] S4. The application clock qspi_clk obtained in step S4 is used to control the chip select signal scs and the data signal data of the Flash chip;

[0030] S5. In str mode, the clock gating signal is set to flip according to the rising and falling edges of the reference clock to ensure that the application clock is the reference clock divided by two; specifically, in str mode, the clock gating signal qspi_clk_en is set to flip once at the rising edge of each reference clock qspi_clk_2x, thereby ensuring that the application clock is the reference clock divided by two; in str mode, the data signal of the Flash chip corresponds to one data beat in each Flash clock signal cycle

[0031] S6. In dtr mode, set the clock gating signal to be valid, and ensure that the application clock and the reference clock are in the same frequency through the clock gating signal; specifically, in dtr mode, set the clock gating signal qspi_clk_en to be continuously valid in dtr mode, at which time the application clock qspi_clk and the reference clock qspi_clk_2x are in the same frequency; in dtr mode, all signals of the circuit are synchronized with the rising edge of the application clock qspi_clk;

[0032] S7. Repeat steps S1 to S6 to complete the str / dtr mode implementation for the flash controller.

[0033] like Figure 2 The timing diagram of the method of the present invention is shown as follows: Figure 2It can be seen that the clock frequency of the double-frequency clock qspi_clk_2x is set; the register output Flash clock signal sclk with the double-frequency clock qspi_clk_2x as the clock signal, sclk flips once at the rising edge of the double-frequency clock qspi_clk_2x, so sclk is the frequency divided by two of qspi_clk_2x;

[0034] Set the clock gating signal qspi_clk_en of the reference clock, and control the reference clock through the clock gating signal to obtain the application clock qspi_clk;

[0035] In the specific implementation, in the str model (at this time, the dtr signal is at a low level), the clock gating signal qspi_clk_en is set to flip once at the rising edge of each reference clock qspi_clk_2x. At this time, the waveform of the application clock is as follows: Figure 2 As shown in qspi_clk in; in this case, the data pin data[3:0] transmits data once in each cycle of sclk;

[0036] In DTR mode, the clock gating signal qspi_clk_en is set to be continuously valid in DTR mode (DTR signal is continuously high level). At this time, the application clock qspi_clk and the reference clock qspi_clk_2x are at the same frequency. In this case, the data pin data[3:0] transmits data twice in each cycle of sclk.

[0037] The switch between sdr and dtr will only occur in one case when the command is sent at the beginning, and it is necessary to switch from str to dtr when the command is sent and the time to send the read address is switched. In other cases, there will be no switch between str and dtr mode during the operation.

[0038] Therefore, qspi_clk_en is the register output triggered by the rising edge of the qspi_clk_2x clock. In addition to the str and dtr modes, when switching from str to dtr is required, the switch from str to dtr can be achieved by controlling qspi_clk_en from jumping every 1 beat to always being high.

[0039] In the method of the present invention, when the setup and hold timing requirements are met, the signal jumps of the synchronization circuit all follow the clock. If clock gating is used to select the entire module, it works at the original frequency and half the frequency, and the dynamic change of the synchronization circuit frequency can be achieved.

[0040] Although the frequency of qspi_clk may be 2 times the frequency of qspi_clk_2x, that is, it is used at half the frequency, but because it has the same frequency as qspi_clk_2x, it is still set to the same frequency as qspi_clk_2x. In this way, if the high-frequency timing is met, there is no problem with using it at a reduced frequency in str mode.

[0041] In addition, because the dtr mode is introduced, the 2x frequency clock qspi_clk_2x of sclk is used to output the dtr data. sclk does not need to be gated clock, but is output by the register qspi_clk_2x like scs and data. In this way, the path constraints of the sclk, scs, and data registers output to the pins are simple and clear, which is convenient for the timing balance of the output path.

[0042] The digital circuit design of chips has a history of several decades of development, and synchronous design has gradually become the mainstream, which is easy to implement with automated tools. The most common and stable solution for synchronous circuits is to use a clock solution: this clock jumps twice per cycle, once rising and once falling, and all functions follow this clock; generally, all registers flip or not flip on the rising edge of the clock according to the calculation results.

[0043] However, the solution of the present invention breaks this convention, and judges whether the signal of a certain function needs to be changed in a certain period of time or in a certain clock cycle according to the functional needs. If it does not need to be changed, the clock can be decisively stopped at this time stage, or even accurately at the clock cycle when the signal does not need to be changed.

[0044] The way to stop the clock from flipping is to gate the clock. In low-power design, gated clock is a common method, which is generally used to turn on or off the clock to determine whether the circuit is working.

[0045] However, it is very difficult to dynamically and accurately control the opening and closing of the clock of a certain circuit:

[0046] Difficulty 1: Feasibility; after seeing the solution of the present invention, many design experts who have worked in the chip industry for more than ten years said that the solution of the present invention is not a regular practice and no one dares to do it. At the same time, there are also questions: How to ensure that there are no problems with the phase relationship between dynamic clock enable and the original clock and the clock after gating; How to ensure that there are no problems when transmitting data between circuits that use dynamic gating based on functions and circuits that do not use gated clocks but original clocks, or circuits that use dynamic gating of other functions.

[0047] Difficulty 2: Risk and cost; The chip R&D cycle is long, the investment cost is high, and the risk is very high. Each step of the process must be executed to ensure that it is foolproof and impeccable. For a new design method, there are processes such as RTL pre-simulation, netlist post-simulation, static timing analysis, formal verification, and FPGA version testing. However, such an unused circuit implementation method that many people only have is still under tremendous pressure.

[0048] However, the solution of the present invention finally achieved the expected function successfully. The method of the present invention is further described below in conjunction with an embodiment:

[0049] The solution of the present invention has been applied to more than a hundred Xilinx FPGA board tests. During the test process, each board is very stable, tested for full functions, and passed the performance test. Three chips have been taped out using SMIC28nm and other processes. After comprehensive sample testing, the performance is superior and commercially available.

[0050] The test results and statistical results of the method of the present invention are shown in Table 1 below:

[0051] Table 1 Test and statistical results

[0052] Version Conventional methods Method of the present invention Improved results Development cycle 221 days 85 days Reduced to 38.46% resource <![CDATA[72532um 2 ]]> <![CDATA[48418um 2 ]]> Reduced to 66.75% of the previous performance 47.5MHz 133MHz Increased to 2.8 times the previous Power consumption 11mW 3mW Reduced to 27.27%

[0053] It can be seen from Table 1 that the solution of the present invention has a short development cycle, low power consumption, less resource occupation, high reliability and good accuracy.

[0054] The advantages of the method of the present invention are:

[0055] Short development cycle: The operation requirements of the device must be based on the traditional STR mode; and the function of STR, except for the SCCLK signal, is a single clock, and there is no rate change during the operation. Therefore, the implementation process is the same as that of ordinary synchronous circuits, and there is no need to consider too many factors; based on the fact that STR has been implemented, fully verified and tested, it is relatively easy to modify; the key is to take the STR and DTR modes into consideration, and then determine the time point of whether qspi_clk_en jumps according to the stage of operation execution, so as to achieve compatibility between STR and DTR.

[0056] Low power consumption: The circuits that require fast and slow adjustable rates account for a large proportion, more than 98%. Because the present invention adopts a gated clock method, the clock frequency is reduced by half when it is necessary to work at full rate, and the dynamic power consumption is also reduced accordingly. According to theoretical analysis and test statistics, a large part of the dynamic power consumption of the circuit is occupied by the flipping of the clock tree. By turning off the clock at the root of the clock tree and stopping the flipping of the signals of each device in the entire clock tree, the dynamic power consumption of the clock tree can be significantly reduced, especially when the circuit scale is large and the operating frequency is high.

[0057] Less resource occupation: If the entire design uses a fast clock globally, synchronous logic is used to control the circuit register in a mode that requires a speed reduction, and the data is flipped once every two clock cycles, while the register level in the other clock cycle remains the same as the previous clock cycle. In this case, a logic control of flipping or jumping will be added to the data input end of each register, thereby increasing logic resources; precisely because of the use of a gated clock method, the circuit globally uses a fast clock that can be dynamically turned on or off, and only one gate device needs to be added to delete the synchronous control logic of each register, thereby realizing the function of the present invention;

[0058] Convenient timing constraint: using a 2x frequency clock and synchronous logic to control whether to jump also increases the amount of logical operations, and the synchronization path becomes slightly complicated; in contrast, the present invention is implemented by gated clock, which transfers the signal hold or jump from the data path to the opening and closing of the clock, which is more conducive to the timing convergence of the synchronous data path; on the other hand, the output signal paths of sclk, scs, and data need to be balanced to the same delay of the pins; in the str method of the prior art, scs and data are ordinary data paths, and sclk is output with a gated clock, which is not conducive to timing constraints; the sclk of the present invention is also uniformly changed to qspi_clk_2x output, the same as scs and data, which is convenient for timing constraints.

Claims

1. A method for implementing the str / dtr mode for a flash controller, characterized in that The steps include: S1. Set the clock frequency of the double frequency clock and use the set double frequency clock as the reference clock; S2. The register with the double frequency clock as the clock signal outputs the Flash clock signal and outputs it to the corresponding pin of the Flash chip; S3 sets the clock gating signal of the reference clock, and controls the reference clock through the clock gating signal, and obtains the application clock; S4. The chip select signal and data signal of the Flash chip are controlled by the application clock obtained in step S4; S5. In str mode, set the clock gating signal to flip according to the rising and falling edges of the reference clock to ensure that the application clock is the reference clock divided by two; S6. In the DTR mode, set the clock gating signal to be valid, and ensure that the application clock and the reference clock are in the same frequency through the clock gating signal; S7. Repeat steps S1 to S6 to complete the str / dtr mode implementation for the flash controller.

2. The method for implementing the str / dtr mode for a flash controller according to claim 1, characterized in that The step S5 is specifically to set the clock gating signal qspi_clk_en to flip once at the rising edge of each reference clock qspi_clk_2x in the str mode, so as to ensure that the application clock qspi_clk is a half-frequency of the reference clock; in the str mode, the data signal of the Flash chip corresponds to one beat of data in each Flash clock signal cycle.

3. The method for implementing the str / dtr mode for a flash controller according to claim 2, characterized in that The step S6 is specifically to set the clock gating signal qspi_clk_en to be continuously valid in the dtr mode, at which time the application clock qspi_clk and the reference clock qspi_clk_2x have the same frequency; in the dtr mode, all signals of the circuit are synchronized with the rising edge of the application clock qspi_clk.

Images