I / O acceleration method and device, computer equipment and chip system

Abstract

The invention discloses an I / O acceleration method and device, computer equipment and a chip system, and relates to the technical field of computers. The method comprises the steps that after an application source code is obtained, I / O information contained in the application source code is determined according to structural characteristics of the application source code, and the structural characteristics can be used for indicating the execution sequence of a plurality of code segments in the application source code; and generating an I / O optimization suggestion according to the I / O information to realize I / O acceleration. The application source code comprises a plurality of code segments, and the code segments are associated in the structure of the application source code. Compared with the mode of independently analyzing the lexical and grammar of the application source code one by one to obtain the I / O information, the method has the advantages that the I / O information is obtained in combination with the multiple code segments in the application source code, the execution sequence of the multiple code segments in time is analyzed, the relation among the multiple code segments can be established, and the implementation efficiency is improved. The execution process of the application source code is reflected more meticulously, so that the efficiency and accuracy of obtaining the I / O information are improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an I / O acceleration method, device, computer equipment and chip system. Background Art

[0002] I / O (input / output) optimization may refer to an I / O acceleration technology that improves I / O operation efficiency and reduces I / O waiting time by analyzing the I / O information of the source code. In order to achieve I / O acceleration, it is necessary to obtain the I / O information of the source code. Usually, the I / O information is obtained during the source code running stage, but it is necessary to wait until the source code is finished running before the I / O information can be counted, resulting in a long waiting time for obtaining the I / O information. Alternatively, during the source code compilation stage, the I / O information contained in the source code is obtained by analyzing the lexical and grammar of the source code, but the I / O information in the entire source code is analyzed line by line, resulting in low efficiency and accuracy in obtaining the I / O information, thereby affecting the efficiency and accuracy of I / O acceleration. Summary of the invention

[0003] The present application provides an I / O acceleration method, apparatus, computer device and chip system, which solve the problem of low efficiency and accuracy in obtaining I / O information.

[0004] In a first aspect, the present application provides an I / O acceleration method, which is executed by a computer device, and includes: after obtaining the application source code, first determining the I / O information contained in the application source code according to the structural features of the application source code, where the structural features can be used to indicate the execution order of multiple code segments in the application source code. Then, generating I / O optimization suggestions according to the I / O information to achieve I / O acceleration.

[0005] The application source code includes multiple code segments, and the multiple code segments are related in the structure of the application source code. Compared with obtaining I / O information by analyzing the lexical and grammatical structure of the application source code line by line, this application obtains I / O information by combining multiple code segments in the application source code, analyzes the time sequence of execution of multiple code segments, and can establish the connection between multiple code segments, reflecting the execution process of the application source code in more detail, thus improving the efficiency and accuracy of obtaining I / O information, so as to ensure the efficiency and accuracy of I / O acceleration.

[0006] In a possible implementation, I / O information contained in the application source code is determined based on structural features of the application source code, including: determining a logical relationship between execution of multiple code segments based on an execution order of multiple code segments in the application source code; and determining the I / O information based on the logical relationship between execution of the multiple code segments.

[0007] The logical relationship between multiple code segments can reflect the execution process and data flow of the application source code. The I / O information is obtained by analyzing the logical relationship between multiple code segments. Compared with analyzing the statements of the application source code line by line to obtain I / O information, the analysis process is more comprehensive and specific, ensuring the accuracy of the I / O information.

[0008] In another possible implementation, the logical relationship of execution between the multiple code segments is determined according to the execution order of the multiple code segments in the application source code, including: determining a state flow graph according to the execution order of the multiple code segments in the application source code, the state flow graph including multiple I / O nodes and edges for connecting the I / O nodes, the I / O nodes corresponding to the code segments, the I / O nodes including state transfer conditions, the state flow graph being used to indicate the execution flow of the multiple I / O nodes under the state transfer conditions; determining the logical relationship of execution between the multiple code segments according to the state flow graph.

[0009] The state flow diagram shows the execution process of the application source code in the form of a topological structure graph, making the execution logic of the application source code clear and helpful for better understanding the logical relationship between multiple code segments (such as conditional statements, judgment statements, loop structures, etc.). In addition, the use of state flow diagrams improves the readability and maintainability of the application source code.

[0010] In another possible implementation, the I / O node further includes a state transfer instruction, where the state transfer instruction is used to provide a state transfer prompt for the I / O node when running the application source code.

[0011] During the compilation phase of the application source code, the compiler can insert a state transfer instruction (such as a Hint instruction) after the key I / O node position, thus marking the key I / O position in the application source code. During the running phase of the application source code, whenever the application source code runs to the state transfer instruction position, it indicates that there is a key I / O node here. Hinting the position of the I / O node in the application source code helps improve the efficiency of obtaining I / O information.

[0012] In another possible implementation, a state flow graph is determined according to the execution order of multiple code segments in the application source code, including: determining at least one of a control flow graph and a data flow graph of the application source code according to the execution order of multiple code segments in the application source code; and determining a state flow graph according to at least one of the control flow graph and the data flow graph.

[0013] In this way, the state flow graph is determined based on the control flow graph and the data flow graph. The state flow graph can be used as an overall view of the running state of the application source code. Compared with analyzing the lexical and grammatical aspects of the application source code line by line, the application analyzes and understands the execution flow of the application source code in a visual view, establishes the connection between program execution and data processing, and improves the efficiency and accuracy of obtaining I / O information, so as to ensure the efficiency and accuracy of I / O acceleration.

[0014] In another possible implementation, the I / O information includes I / O statistical information and I / O access behavior information, the I / O statistical information includes I / O size and I / O location, and the I / O access behavior information includes file read operations and file write operations.

[0015] I / O information can be used as data information related to I / O operations during the execution of application source code. I / O statistics information focuses on quantitative description of I / O-related statistical data, while I / O access behavior information focuses on qualitative analysis of I / O-related access operations. Combining I / O statistics information and I / O access behavior information, the two together serve as the basis for generating I / O optimization suggestions for achieving I / O acceleration to ensure the accuracy of I / O acceleration.

[0016] In another possible implementation, the method further includes: storing the state flow diagram and I / O information in a database.

[0017] During the compilation phase of the application source code, the state flow diagram and I / O information are stored in a database, so that during the running phase of the application source code, the controller can quickly query the state flow diagram and I / O information by searching the content stored in the database. In this way, there is no need to regenerate the state flow diagram and reacquire the I / O information. The controller directly analyzes the I / O information to generate I / O optimization suggestions for achieving I / O acceleration, thereby improving the efficiency of I / O acceleration.

[0018] In a second aspect, the present application provides an I / O acceleration device, which includes an acquisition module and an acceleration module. The acquisition module is used to determine the I / O information contained in the application source code according to the structural characteristics of the application source code, and the structural characteristics are used to indicate the execution order of multiple code segments in the application source code; the acceleration module is used to generate I / O optimization suggestions according to the I / O information.

[0019] In a possible implementation, when the acquisition module determines the I / O information contained in the application source code based on the structural characteristics of the application source code, it is specifically used to: determine the logical relationship of execution between multiple code segments based on the execution order of multiple code segments in the application source code; determine the I / O information based on the logical relationship of execution between multiple code segments.

[0020] In another possible implementation, when the acquisition module determines the logical relationship of execution between multiple code segments according to the execution order of multiple code segments in the application source code, it is specifically used to: determine a state flow graph according to the execution order of multiple code segments in the application source code, the state flow graph includes multiple I / O nodes and edges for connecting the I / O nodes, the I / O nodes correspond to the code segments, the I / O nodes include state transfer conditions, and the state flow graph is used to indicate the execution process of multiple I / O nodes under the state transfer conditions; determine the logical relationship of execution between multiple code segments according to the state flow graph.

[0021] In another possible implementation, the I / O node further includes a state transfer instruction, where the state transfer instruction is used to provide a state transfer prompt for the I / O node when running the application source code.

[0022] In another possible implementation, when the acquisition module determines the state flow graph according to the execution order of multiple code segments in the application source code, it is specifically used to: determine at least one of the control flow graph and the data flow graph of the application source code according to the execution order of multiple code segments in the application source code; determine the state flow graph according to at least one of the control flow graph and the data flow graph.

[0023] In another possible implementation, the I / O information includes I / O statistical information and I / O access behavior information, the I / O statistical information includes I / O size and I / O location, and the I / O access behavior information includes file read operations and file write operations.

[0024] In another possible implementation, the above device further includes: a storage module, used to store the state flow diagram and I / O information in a database.

[0025] In a third aspect, the present application provides a computer device comprising a memory and a processor, the memory being used to store a set of computer instructions; when the processor executes the set of computer instructions as an execution device in the first aspect or any possible implementation of the first aspect, the operating steps of the I / O acceleration method in the first aspect or any possible implementation of the first aspect are executed.

[0026] In a fourth aspect, the present application provides a chip system, the chip system includes a logic circuit and a power supply circuit, the power supply circuit supplies power to the logic circuit, and the logic circuit is used to execute the operation steps of the I / O acceleration method in the first aspect or any possible implementation of the first aspect. In a possible design, the chip system also includes a memory for storing program instructions and / or data.

[0027] In a fifth aspect, the present application provides a computer-readable storage medium, comprising: computer software instructions; when the computer software instructions are executed in a computing device, the computer device executes the operating steps of the I / O acceleration method in the first aspect or any possible implementation of the first aspect.

[0028] In a sixth aspect, the present application provides a computer program product, which, when executed on a computer, enables the computer device to execute the operating steps of the I / O acceleration method in the first aspect or any possible implementation of the first aspect.

[0029] The technical effects brought about by any design method in the second to sixth aspects can refer to the technical effects brought about by the first aspect or different design methods in the first aspect.

[0030] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of a process for obtaining I / O information by statically analyzing application source code provided in the prior art;

[0032] Figure 2 A schematic diagram of the structure of an I / O acceleration device provided in this application;

[0033] Figure 3 A flowchart of an I / O acceleration method provided in this application;

[0034] Figure 4 A schematic diagram of the structure of an interval tree provided for this application;

[0035] Figure 5 A schematic diagram of a control flow graph provided for this application;

[0036] Figure 6 A schematic diagram of a state flow diagram provided for this application;

[0037] Figure 7 A schematic diagram of storing state flow diagram and I / O information in a database provided by the present application;

[0038] Figure 8 A schematic diagram of I / O optimization suggestions in a storage-level affinity scheduling scenario provided for this application;

[0039] Fig. 9 A schematic diagram of an I / O acceleration method provided in this application;

[0040] Fig.10 A schematic diagram of the structure of an I / O acceleration device provided in this application;

[0041] Fig.11 A schematic diagram of the structure of a computer device provided in this application. DETAILED DESCRIPTION

[0042] In order to make the description of the following embodiments clear and concise, the terms involved in this application are first briefly introduced:

[0043] I / O acceleration (input / output acceleration) refers to a technology used to improve the input performance and output performance of computer devices. The application of this acceleration technology can improve data transmission efficiency, reduce data transmission latency, and speed up the response of computer devices to applications, thereby ensuring good performance of computer devices. I / O acceleration technology plays a key role in the field of high performance computing (HPC), and can meet the needs of HPC for large-scale data processing and high-speed computing.

[0044] Before implementing I / O acceleration, computer devices need to obtain I / O information contained in the application source code so that I / O optimization suggestions that help achieve I / O acceleration can be generated by analyzing the I / O information. Usually, I / O information is obtained during the application source code running stage, but it is necessary to wait until the application source code is finished running before the I / O information can be counted, resulting in a long waiting time for obtaining I / O information.

[0045] Alternatively, during the application source code compilation phase, without running the application source code, the lexical structure and syntax of the application source code are statically analyzed to obtain the I / O information contained in the application source code. Figure 1 A schematic diagram of a process for obtaining I / O information by statically analyzing application source code is provided in the prior art. Figure 1 As shown, first, the application source code is scanned line by line during the compilation phase (step 110). Then, the lexical and grammatical information contained in each line of the application source code is analyzed (step 120). Finally, I / O information is obtained according to the lexical and grammatical structure (step 130).

[0046] However, line-by-line analysis of the lexical and grammatical contents contained in the overall application source code takes a long time to obtain I / O information, resulting in low efficiency in obtaining I / O information. In addition, line-by-line analysis cannot associate multiple code segments containing I / O information in the overall application source code, severing the connection between multiple code segments, resulting in low accuracy in obtaining I / O information. Since the efficiency and accuracy of obtaining I / O information are low, the efficiency and accuracy of I / O acceleration will be affected.

[0047] In order to solve the problem that the efficiency and accuracy of obtaining I / O information are low, which affects the efficiency and accuracy of I / O acceleration, the present application provides an I / O acceleration method, which is executed by a computer device, and includes: after obtaining the application source code, first determine the I / O information contained in the application source code according to the structural features of the application source code, where the structural features can be used to indicate the execution order of multiple code segments in the application source code. Then generate I / O optimization suggestions based on the I / O information to achieve I / O acceleration.

[0048] The application source code includes multiple code segments, and the multiple code segments are related in the structure of the application source code. Compared with obtaining I / O information by analyzing the lexical and grammatical structure of the application source code line by line, this application obtains I / O information by combining multiple code segments in the application source code, analyzes the time sequence of execution of multiple code segments, and can establish the connection between multiple code segments, reflecting the execution process of the application source code in more detail, thus improving the efficiency and accuracy of obtaining I / O information, so as to ensure the efficiency and accuracy of I / O acceleration.

[0049] The I / O acceleration method provided by the present application is described in detail below with reference to the accompanying drawings.

[0050] Figure 2 This is a schematic diagram of the structure of an I / O acceleration device provided in this application. Figure 2 As shown, the I / O acceleration device 200 includes a compiler 210, a controller 220, and an I / O accelerator 230. The I / O acceleration device 200 here may be a computer device for accelerating I / O operations, and the compiler 210, the controller 220, and the I / O accelerator 230 may be run in the computer device.

[0051] Among them, the compiler 210 can convert the application source code written in a high-level programming language into a lower-level machine code or bytecode that can be executed by the computer. In the compilation stage, the compiler 210 converts the application source code into an intermediate code by performing lexical analysis, syntax analysis, and semantic analysis on the application source code, and performs code optimization on the intermediate code to convert the optimized code into an executable machine code or bytecode. After the application source code is compiled, the generated executable code enters the running stage. The controller 220 can be an execution program that runs the executable code, which is used to generate I / O optimization suggestions based on I / O information. The I / O accelerator 230 can be a driver running on a computer device, which is used to implement I / O acceleration and improve I / O performance by optimizing I / O operations such as reading and writing data to storage devices.

[0052] In the compilation phase of the application source code, the compiler 210 can determine a state flow diagram according to the execution order of multiple code segments in the application source code, determine the logical relationship between the multiple code segments according to the state flow diagram, and determine the I / O information according to the logical relationship between the multiple code segments. In the running phase of the application source code, the controller 220 can generate I / O optimization suggestions based on the I / O information. The specific implementation method can refer to the description in the following embodiment steps.

[0053] Next, combine Figures 3 to 9 , the I / O acceleration method provided in this application is described in detail. Figure 3 A flowchart of an I / O acceleration method provided in this application. Here, a computer device is used as Figure 2 Taking the I / O acceleration device in the example, the computer device determines the I / O information required to implement I / O acceleration according to the structural characteristics of the application source code. Figure 3 As shown, the method may include the following steps.

[0054] Step 310: Determine the I / O information included in the application source code according to the structural characteristics of the application source code.

[0055] Source code can be a readable text file written in accordance with the specifications of a programming language (such as C language, C++ language, fortran language, etc.). The computer device needs to first convert the source code into executable code (binary instructions) that the computer can execute. This process can be called compilation. Then the compiled executable code is run and the running results are output. This process can be called running. The application source code first goes through the compilation stage and then the running stage to realize the functions provided by the application.

[0056] The application source code may include multiple code segments, and the structural features of the application source code may be used to indicate the execution order of the multiple code segments in the application source code. The execution order may be the order in which the multiple code segments are executed in time. The computer device may convert the application source code into executable code according to the execution order during the compilation stage.

[0057] The application source code can include I / O information, such as Figure 3 In the application source code shown in the example, when the execution conditions of code block 3 and code block 4 are met, the compiler executes the contents of code block 3 and code block 4. Both code block 3 (code block 3) and code block 4 (code block 4) contain I / O information.

[0058] The computer device determines the I / O information contained in the application source code according to the structural characteristics of the application source code. The method of obtaining the I / O information is described by the following steps 311 to 312.

[0059] Step 311: Determine the logical relationship between the execution of the multiple code segments according to the execution order of the multiple code segments in the application source code.

[0060] Multiple code segments in the application source code can be executed according to the program execution structure (such as sequence structure, selection structure or loop structure, etc.). The execution order of multiple code segments will be affected by the execution structure. Different execution structures will result in different execution orders. Based on the execution order, the execution logic relationship between multiple code segments can be determined. Clarifying the execution logic relationship between multiple code segments helps to structure the application source code and improve the readability and maintainability of the application source code.

[0061] In some embodiments, the computer device may first determine a state flow diagram according to the execution order of multiple code segments in the application source code, and then determine the logical relationship between the execution of the multiple code segments according to the state flow diagram. For specific implementation methods, refer to the description in the following content.

[0062] In a possible implementation, the computer device can determine at least one of a control flow graph and a data flow graph of the application source code according to the execution order of multiple code segments in the application source code. The control flow graph can represent all paths traversed by the application source code during the execution process, reflecting the possible flow directions of the execution of multiple code segments during the execution process. The data flow graph can represent the flow direction and transformation process of data in the application source code.

[0063] Exemplarily, during the compilation phase of the application source code, first, an interval tree of the application source code may be generated based on the execution order of multiple code segments in the application source code. The interval tree may include branch intervals, continuous intervals, simple intervals, loop intervals, and empty intervals. Figure 4 A schematic diagram of the structure of an interval tree provided for this application, such as Figure 4 As shown, the application source code includes an if conditional statement code segment and a while loop statement code segment. The if conditional statement code segment may correspond to branch interval 1 in the interval tree, and the while loop statement code segment may correspond to loop interval 4 in the interval tree. Code block 3 in the if conditional statement and code block 4 in the while loop statement may correspond to simple intervals in the interval tree.

[0064] Based on the interval tree of the application source code, the control flow graph or data flow graph of the application source code can be sorted out. Here, the control flow graph of the application source code is taken as an example. Figure 5 A schematic diagram of a control flow graph provided for this application, such as Figure 5As shown in the figure, the application source code can be divided into five related nodes from node 1 to node 5, and each node can correspond to each code segment in the application source code. The application source code starts to execute from node 1. When the execution condition condition1 is not met, the execution order flows from node 1 to node 3; when the execution condition condition1 is met, the execution order flows from node 1 to node 2; when the execution condition condition2 is met, the execution order flows from node 3 to node 4; when the execution condition condition2 is not met, the execution order flows from node 3 to node 5. This control flow graph contains the conditions of the branch interval (condition1) and the conditions of the loop interval (condition2). Nodes 3 and 4 can be used as key I / O nodes, and their corresponding code segments contain I / O operations.

[0065] Based on the control flow graph, it is possible to sort out the situation where the current node flows to the subsequent node and the I / O information is included in the state transition condition. In an example, the corresponding relationship between the state transition condition and whether the I / O information is included can be presented in the form of a table, as shown in Table 1.

[0066] Table 1

[0067]

[0068]

[0069] As can be seen from Table 1, in the initial status (init status), I / O information is not included. When status 1 (status1) satisfies the execution condition condition1 (condition1==true), I / O information is not included when node 1 flows to node 2. When status 2 (status2) does not satisfy the execution condition condition1 (condition1==false), I / O information is included when node 1 flows to node 3. When status 3 (status3) satisfies the execution condition condition2 (condition2==true), I / O information is included when node 3 flows to node 4. When status 4 (status4) does not satisfy the execution condition condition2 (condition2==false), I / O information is not included when node 3 flows to node 5.

[0070] According to the control flow graph of the application source code, a state flow graph of the application source code can be determined. The state flow graph can reflect the association relationship between multiple I / O nodes in execution logic. Figure 6 A schematic diagram of a state flow diagram provided for this application, such as Figure 6As shown, the state flow graph has a topological structure and may include multiple I / O nodes and edges for connecting the I / O nodes. The I / O nodes here may correspond to code segments, and one I / O node may serve as a code segment. The I / O node may include state transition conditions, and the state flow graph may be used to indicate the execution flow of multiple I / O nodes under state transition conditions. For example, when condition1 == false, state 2 may transfer to state 3 or to state 4. Specifically, when condition2 == true, state 2 transfers to state 3, and the execution flow is from node 3 to node 4. When condition2 == false, state 2 transfers to state 4, and the execution flow is from node 3 to node 5.

[0071] In some embodiments, the I / O node may also include a state transfer instruction, which is used to provide a state transfer hint for the I / O node when running the application source code. Exemplarily, the state transfer instruction may be a Hint instruction automatically generated by the compiler. Figure 6 It can be seen that except for the initial state, reaching other states is conditional, and the achievement of these conditions can be used as the basis for state transition prompts.

[0072] Hint instructions may include location, code logic, and content. Among them, Hint instructions may be inserted after the location of key I / O nodes. Hint instructions may be inserted manually by the user or automatically by the compiler. The code logic of the Hint instruction may be that the controller calls the state transfer interface provided for it when running the application source code. After the application source code runs to the Hint instruction location and calls the state transfer interface using the Hint instruction, the controller may perform operations such as query, graph search of the state flow diagram, and call the algorithm library, so that the controller outputs I / O optimization suggestions for the I / O node corresponding to the Hint instruction. The content of the Hint instruction may be embodied in the form of parameters, which include the basis for the state transfer prompt, such as whether the preconditions are met.

[0073] Step 312: Determine I / O information according to the logical relationship between the multiple code segments.

[0074] After the computer device determines the logical relationship between the execution of multiple code segments, the I / O information contained in the application source code can be determined according to the logical relationship between the execution of the multiple code segments. The I / O information here may include I / O statistical information and I / O access behavior information, the I / O statistical information includes I / O size and I / O location, etc., and the I / O access behavior information includes file reading operations and file writing operations, etc. For example, when the processor of the computer device accesses a file stored in a storage device (such as a memory), the I / O access behavior information may include reading data in the file and writing data to the file.

[0075] Multiple I / O nodes in the state flow diagram can correspond to multiple code segments in the application source code one by one. The interface calls of the code segments to I / O standards such as portable operating system interface (POSIX) and message passing interface (MPI) are fixed in the compilation stage. Based on the logical order of execution between multiple code segments in the compilation stage, all interfaces are called in sequence, and I / O information is matched according to the name of the called interface to obtain the corresponding I / O access behavior information (including read file operations, write file operations, open file operations, etc.) and corresponding I / O statistical information (including location, size, access times, etc.).

[0076] In an example, the names of relevant interfaces under the I / O standards that can be obtained are presented in a table, as shown in Table 2. The I / O standards in the table may include but are not limited to POSIX and MPI.

[0077] Table 2

[0078] I / O Standards The name of the relevant interface POSIX open,read,write,dup,fopen,create,fdopen,freopen,opendir,fdopendir, etc. MPI MPI_File_write,MPI_File_read,MPI_File_open MPI_File_close, etc.

[0079] As can be seen from Table 2, when the I / O standard is POSIX, the related interfaces may include but are not limited to open, read, write, copy, create, open file (fopen), open file descriptor (fdopen), file redirection (freopen), open directory (opendir), open file descriptor to access directory (fdopendir), etc. When the I / O standard is MPI, the related interfaces may include but are not limited to write file (MPI_File_write), read file (MPI_File_read), open file (MPI_File_open), close file (MPI_File_close), etc.

[0080] It should be noted that the above Tables 1 and 2 only illustrate the storage form of the corresponding relationship in the storage device in the form of a table, and are not limitations on the storage form of the corresponding relationship in the storage device. Of course, the storage form of the corresponding relationship in the storage device can also be stored in other forms, and this embodiment does not limit this.

[0081] In some embodiments, the state flow diagram determined according to the above method and the obtained I / O information can be stored in a database, so that during the running phase of the application source code, the controller can quickly query the state flow diagram and I / O information by searching the content stored in the database.

[0082] Figure 7 A schematic diagram of storing state flow diagram and I / O information in a database provided by the present application, such as Figure 7 As shown in (a), it is the topological structure information of the state flow graph. The topological structure information can reflect the execution flow between multiple I / O nodes under the state transition conditions. For example, when condition 1 is met, the execution flow is from node 1 to node 2; when condition 1 is not met, the execution flow is from node 1 to node 3; when condition 2 is met, the execution flow is from node 3 to node 4; when condition 2 is not met, the execution flow is from node 3 to node 5. Figure 7 As shown in (b), it is the node information of the I / O node in the state flow diagram. The node information includes the state transition condition number (condition ID) of the node and the I / O information of the node. The I / O information includes I / O statistical information and I / O access behavior information.

[0083] It should be noted that the present application is not limited to using a database to store state flow graphs and I / O information. In practical applications, a temporary storage file or a temporary memory buffer may also be used to temporarily store state flow graphs and I / O information.

[0084] Step 320: Generate I / O optimization suggestions based on the I / O information.

[0085] After the computer device obtains the I / O information, it can generate an I / O optimization suggestion according to the I / O information, so that the I / O accelerator can implement I / O acceleration based on the I / O optimization suggestion, thereby improving the I / O operation efficiency and reducing the I / O waiting time.

[0086] In some embodiments, since the Hint instruction is inserted after the key I / O node position during the compilation phase of the application source code, in this way, during the running phase of the application source code, whenever the application source code runs to the Hint instruction position, it indicates that there is a key I / O node there. The controller can query the state flow diagram stored in the database and the I / O information of multiple I / O nodes to generate I / O optimization suggestions.

[0087] Exemplarily, I / O optimization suggestions can be applied in storage-level affinity scheduling scenarios. In the storage level of a distributed storage system, various types of storage media are included. The read and write speeds and capacities of storage media are generally inversely proportional, that is, the faster the read and write speeds of storage media in the high-speed storage level, the smaller the capacity of the storage media, such as a solid state drive (SSD). The slower the read and write speeds of storage media in the low-speed storage level, the larger the capacity of the storage media, such as a hard disk drive (HHD). Based on the I / O optimization suggestions, the I / O accelerator can schedule I / O information to the appropriate storage level in order to leverage the advantages of different storage media, maintain overall load balancing of the storage system, and achieve the purpose of optimizing and improving storage performance.

[0088] Figure 8 A schematic diagram of I / O optimization suggestions in a storage-level affinity scheduling scenario provided for this application is shown in FIG. Figure 8 As shown, the content of I / O optimization suggestions can be divided into two parts, including completed suggestions and pre-taken suggestions. Among them, the completed suggestions can be to store the I / O information of the I / O nodes that have executed the I / O process in the state flow diagram in the low-speed storage layer, and the pre-taken suggestions can be to store the I / O information of the I / O nodes that have not executed the I / O process in the state flow diagram in the high-speed storage layer. In this way, based on the above optimization suggestions, the I / O accelerator efficiently uses different storage layers to dynamically store I / O information to achieve I / O acceleration.

[0089] The above I / O acceleration method is understood below in conjunction with the accompanying drawings. Fig. 9 A schematic diagram of the process of an I / O acceleration method provided in this application is shown as follows: Fig. 9 As shown, after the computer device obtains the application source code, it executes the compilation process of the application source code. In the compilation stage of the application source code, a state flow diagram, I / O information and executable code are generated.

[0090] The state flow graph generation module includes an analysis module and a Hint instruction insertion module. The analysis module determines the state flow graph by analyzing the order in which multiple code segments are executed in time. The nodes in the state flow graph correspond to the code segments of the application source code. Each I / O node has a state transfer condition, and the Hint instruction is inserted after the key I / O node position. Based on the state flow graph, the connection between multiple code segments can be established, and the logical relationship between the execution of multiple code segments can be determined. According to the logical relationship between the execution of multiple code segments, the I / O information can be determined. After the compiler completes the compilation, it generates executable code of the application source code with Hint instructions.

[0091] During the running phase of the application source code, the executable code runs when the controller is started. During the running of the executable code, the inserted Hint instruction will pass the I / O information of the key I / O nodes to the controller process by calling the Hint interface, so as to connect the I / O information required by the subsequent I / O accelerator. The controller queries the state flow diagram and I / O information stored in the database, obtains the subsequent I / O information that may be related based on the I / O information algorithm library, and transmits this I / O information to the subsequent I / O accelerator in a timely manner. The I / O accelerator generates I / O optimization suggestions in real time based on the I / O information.

[0092] According to the I / O acceleration method described in the above steps, the application source code includes multiple code segments, and the multiple code segments are related in the structure of the application source code. Compared with obtaining I / O information by analyzing the lexical and grammatical structure of the application source code line by line, this application combines multiple code segments in the application source code to obtain I / O information, analyzes the order in which multiple code segments are executed in time, and can establish connections between multiple code segments, reflecting the execution process of the application source code in more detail. In this way, the efficiency and accuracy of obtaining I / O information are improved, so as to ensure the efficiency and accuracy of I / O acceleration.

[0093] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the method. It is understandable that in order to achieve the above functions, the computer device includes a hardware structure and / or software module corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the algorithm steps of each example described in the embodiment disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application.

[0094] Combined with the above Figures 3 to 9 , describes in detail the I / O acceleration method provided according to the embodiment of the present application, and will be combined with Fig.10 , describing an I / O acceleration device provided according to an embodiment of the present application.

[0095] Fig.10 This is a schematic diagram of the structure of an I / O acceleration device provided by the present application. These I / O acceleration devices can be used to implement the functions of the computer device in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0096] like Fig.10As shown, the I / O acceleration device 1000 includes an acquisition module 1010 , an acceleration module 1020 and a storage module 1030 .

[0097] The acquisition module 1010 is used to determine the I / O information contained in the application source code according to the structural characteristics of the application source code, and the structural characteristics are used to indicate the execution order of multiple code segments in the application source code. Figure 3 Step 310.

[0098] The acceleration module 1020 is used to generate I / O optimization suggestions based on the I / O information. For example, the acceleration module 1020 is used to perform Figure 3 Step 320.

[0099] Optionally, the acquisition module 1010 is used to determine the logical relationship between the execution of multiple code segments according to the execution order of multiple code segments in the application source code. Figure 3 Step 311.

[0100] Optionally, the acquisition module 1010 is used to determine the I / O information according to the logical relationship between the multiple code segments. Figure 3 Step 312.

[0101] Optionally, acquisition module 1010 is used to determine a state flow graph according to the execution order of multiple code segments in the application source code, the state flow graph includes multiple I / O nodes and edges for connecting the I / O nodes, the I / O nodes correspond to the code segments, the I / O nodes include state transfer conditions, and the state flow graph is used to indicate the execution flow of multiple I / O nodes under the state transfer conditions; the logical relationship between the execution of multiple code segments is determined according to the state flow graph.

[0102] Optionally, the acquisition module 1010 is used to determine at least one of a control flow graph and a data flow graph of the application source code according to the execution order of multiple code segments in the application source code; and determine a state flow graph according to at least one of the control flow graph and the data flow graph.

[0103] Optionally, the I / O acceleration device 1000 also includes a storage module 1030 .

[0104] The storage module 1030 may correspond to the method embodiments described above and be used to store state flow diagrams, I / O information, and I / O optimization suggestions, etc.

[0105] It should be understood that the I / O acceleration device 1000 according to the embodiment of the present application may correspond to the method described in the embodiment of the present application, and the above and other operations and / or functions of each unit in the I / O acceleration device 1000 are respectively to achieve Figure 3For the sake of brevity, the corresponding processes of each method in are not repeated here.

[0106] Fig.11 A schematic diagram of the structure of a computer device provided in this embodiment. Fig.11 As shown, the computer device 1100 includes a processor 1110, a bus 1120, a memory 1130, a memory unit 1150 (also referred to as a main memory unit), and a communication interface 1140. The processor 1110, the memory 1130, the memory unit 1150, and the communication interface 1140 are connected via the bus 1120.

[0107] It should be understood that in this embodiment, the processor 1110 may be a CPU, and the processor 1110 may also be other general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0108] The communication interface 1140 is used to implement communication between the computer device 1100 and an external device or component. In this embodiment, the communication interface 1140 can be used to exchange data with other computer devices.

[0109] The bus 1120 may include a path for transmitting information between the above components (such as the processor 1110, the memory unit 1150, and the memory 1130). In addition to the data bus, the bus 1120 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are labeled as bus 1120 in the figure. The bus 1120 may be a Peripheral Component Interconnect Express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc.

[0110] As an example, the computer device 1100 may include multiple processors. The processor may be a multi-core (multi-CPU) processor. The processor here may refer to one or more devices, circuits, and / or computing units for processing data (e.g., computer program instructions). The processor 1110 may be used to determine the I / O information contained in the application source code according to the structural features of the application source code, and the structural features are used to indicate the execution order of multiple code segments in the application source code; generate I / O optimization suggestions according to the I / O information.

[0111] It is worth mentioning that Fig.11 In the example, a computer device 1100 including one processor 1110 and one memory 1130 is taken as an example. Here, the processor 1110 and the memory 1130 are respectively used to indicate a type of device or equipment. In a specific embodiment, the number of each type of device or equipment can be determined according to business requirements.

[0112] The memory unit 1150 may correspond to the above method embodiment for storing state flow diagrams and I / O information. The memory unit 1150 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0113] The memory 1130 is used to store state flow diagrams, I / O information, and I / O optimization suggestions, and may be a solid-state drive or a mechanical hard disk.

[0114] It should be understood that the computer device 1100 according to this embodiment may correspond to the I / O acceleration device 1000 in this embodiment, and may correspond to the computer device 1100 executing the I / O acceleration device 1000 according to the embodiment. Figure 3 The above and other operations and / or functions of each module in the I / O acceleration device 1000 are respectively implemented Figure 3 For the sake of brevity, the corresponding process in will not be repeated here.

[0115] The method steps in this embodiment can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a computer device. Of course, the processor and the storage medium can also exist as discrete components in a network device or a terminal device.

[0116] The present application also provides a chip system, which includes a processor for implementing the functions of the data processing unit in the above method. In one possible design, the chip system also includes a memory for storing program instructions and / or data. The chip system can be composed of a chip, or can include a chip and other discrete devices.

[0117] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device or other programmable device. The computer program or instruction may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instruction may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, for example, a floppy disk, a hard disk, a tape; it may also be an optical medium, for example, a digital video disc (DVD); it may also be a semiconductor medium, for example, a solid state drive (SSD).

[0118] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An I / O acceleration method, characterized in that: include: Determining I / O information contained in the application source code according to a structural feature of the application source code, wherein the structural feature is used to indicate an execution order of multiple code segments in the application source code; An I / O optimization suggestion is generated according to the I / O information.

2. The method according to claim 1, characterized in that Determining I / O information contained in the application source code according to the structural characteristics of the application source code includes: Determining the logical relationship between the execution of the multiple code segments according to the execution order of the multiple code segments in the application source code; The I / O information is determined according to a logical relationship executed between the plurality of code segments.

3. The method according to claim 2, characterized in that Determining the logical relationship between the execution of the multiple code segments according to the execution order of the multiple code segments in the application source code includes: Determine a state flow graph according to the execution order of the plurality of code segments in the application source code, the state flow graph comprising a plurality of I / O nodes and edges for connecting the I / O nodes, the I / O nodes corresponding to the code segments, the I / O nodes comprising state transition conditions, and the state flow graph indicating the execution flow of the plurality of I / O nodes under the state transition conditions; The logical relationship between the execution of the plurality of code segments is determined according to the state flow diagram.

4. The method according to claim 3, characterized in that The I / O node also includes a state transfer instruction, and the state transfer instruction is used to provide a state transfer prompt for the I / O node when running the application source code.

5. The method according to claim 3 or 4, characterized in that: Determining a state flow diagram according to the execution order of multiple code segments in the application source code includes: Determine at least one of a control flow graph and a data flow graph of the application source code according to an execution order of multiple code segments in the application source code; The state flow graph is determined according to at least one of the control flow graph and the data flow graph.

6. The method according to any one of claims 1 to 5, characterized in that The I / O information includes I / O statistical information and I / O access behavior information. The I / O statistical information includes I / O size and I / O position. The I / O access behavior information includes file read operations and file write operations.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: The state flow diagram and the I / O information are stored in a database.

8. An I / O acceleration device, characterized in that: The I / O acceleration device comprises: an acquisition module, configured to determine the I / O information contained in the application source code according to a structural feature of the application source code, wherein the structural feature is used to indicate an execution order of multiple code segments in the application source code; The acceleration module is used to generate I / O optimization suggestions according to the I / O information.

9. A computer device, characterized in that: The computer device includes a memory and a processor, wherein the memory is used to store a set of computer instructions; when the processor executes the set of computer instructions, the operation steps of the method described in any one of claims 1 to 7 are performed.

10. A chip system, characterized in that: The chip system includes a memory and a processor, wherein the memory is used to store a set of computer instructions; when the processor executes the set of computer instructions, the operation steps of the method described in any one of claims 1 to 7 are performed.

Images